[llvm] ce811aa - [X86] pr53842.ll - add test coverage for ICMP_SGT/SLT cases (#202906)

[via llvm-commits]

Author: Simon Pilgrim
Date: 2026-06-10T10:13:20Z
New Revision: ce811aacef9a35c0765aa39381340993459fbd33

URL: https://github.com/llvm/llvm-project/commit/ce811aacef9a35c0765aa39381340993459fbd33
DIFF: https://github.com/llvm/llvm-project/commit/ce811aacef9a35c0765aa39381340993459fbd33.diff

LOG: [X86] pr53842.ll - add test coverage for ICMP_SGT/SLT cases (#202906)

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/pr53842.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/pr53842.ll b/llvm/test/CodeGen/X86/pr53842.ll
index a962a9b3ddf2f..28f3af8202a20 100644
--- a/llvm/test/CodeGen/X86/pr53842.ll
+++ b/llvm/test/CodeGen/X86/pr53842.ll
@@ -4,8 +4,8 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512dq | FileCheck %s
 
-define void @PR53842() {
-; CHECK-LABEL: PR53842:
+define void @PR53842_eq() {
+; CHECK-LABEL: PR53842_eq:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
 ; CHECK-NEXT:    vpmovzxbq {{.*#+}} zmm1 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero,zero,zero,zero,mem[2],zero,zero,zero,zero,zero,zero,zero,mem[3],zero,zero,zero,zero,zero,zero,zero,mem[4],zero,zero,zero,zero,zero,zero,zero,mem[5],zero,zero,zero,zero,zero,zero,zero,mem[6],zero,zero,zero,zero,zero,zero,zero,mem[7],zero,zero,zero,zero,zero,zero,zero
@@ -36,3 +36,66 @@ middle.block:
   unreachable
 }
 
+define void @PR53842_sgt() {
+; CHECK-LABEL: PR53842_sgt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vpmovsxbq (%rax), %zmm1
+; CHECK-NEXT:    vextracti64x4 $1, %zmm1, %ymm2
+; CHECK-NEXT:    vpxor %xmm3, %xmm3, %xmm3
+; CHECK-NEXT:    vpcmpgtq %ymm2, %ymm3, %ymm2
+; CHECK-NEXT:    vpcmpgtq %ymm1, %ymm3, %ymm1
+; CHECK-NEXT:    vinserti64x4 $1, %ymm2, %zmm1, %zmm1
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB1_1: # %vector.body
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    vpsubq %zmm1, %zmm0, %zmm0
+; CHECK-NEXT:    jmp .LBB1_1
+entry:
+  br label %vector.body
+
+vector.body:
+  %index = phi i64 [ 0, %entry ], [ 0, %vector.body ]
+  %vec.phi = phi <8 x i64> [ zeroinitializer, %entry ], [ %i2, %vector.body ]
+  %wide.load23 = load <8 x i8>, ptr undef, align 1
+  %i = icmp sgt <8 x i8> zeroinitializer, %wide.load23
+  %i1 = zext <8 x i1> %i to <8 x i64>
+  %i2 = add <8 x i64> %vec.phi, %i1
+  br i1 false, label %middle.block, label %vector.body
+
+middle.block:
+  %bin.rdx = add <8 x i64> undef, %i2
+  unreachable
+}
+
+define void @PR53842_slt() {
+; CHECK-LABEL: PR53842_slt:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vpmovsxbq (%rax), %zmm1
+; CHECK-NEXT:    vextracti64x4 $1, %zmm1, %ymm2
+; CHECK-NEXT:    vpxor %xmm3, %xmm3, %xmm3
+; CHECK-NEXT:    vpcmpgtq %ymm3, %ymm2, %ymm2
+; CHECK-NEXT:    vpcmpgtq %ymm3, %ymm1, %ymm1
+; CHECK-NEXT:    vinserti64x4 $1, %ymm2, %zmm1, %zmm1
+; CHECK-NEXT:    .p2align 4
+; CHECK-NEXT:  .LBB2_1: # %vector.body
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    vpsubq %zmm1, %zmm0, %zmm0
+; CHECK-NEXT:    jmp .LBB2_1
+entry:
+  br label %vector.body
+
+vector.body:
+  %index = phi i64 [ 0, %entry ], [ 0, %vector.body ]
+  %vec.phi = phi <8 x i64> [ zeroinitializer, %entry ], [ %i2, %vector.body ]
+  %wide.load23 = load <8 x i8>, ptr undef, align 1
+  %i = icmp slt <8 x i8> zeroinitializer, %wide.load23
+  %i1 = zext <8 x i1> %i to <8 x i64>
+  %i2 = add <8 x i64> %vec.phi, %i1
+  br i1 false, label %middle.block, label %vector.body
+
+middle.block:
+  %bin.rdx = add <8 x i64> undef, %i2
+  unreachable
+}