[llvm] [AArch64][SVE] Enable known bits for predicated shifts (PR #200347)

[Harry Ramsey via llvm-commits]

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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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Harry-Ramsey wrote:

Sorry, these tests were for fixed vectors when SVE is available. I have updated the test now to ensure that we use SVE.

The behaviour is as expected for fixed vectors, this patch primarily targets scalable vectors.

https://github.com/llvm/llvm-project/pull/200347