[llvm] 78d4900 - AMDGPU/GlobalISel: Implement RegBankLegalize rules for SALUFloat variants of G_INTRINSIC_TRUNC, G_FFLOOR and G_FCEIL. (#187679)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 10 02:21:06 PDT 2026
Author: anjenner
Date: 2026-06-10T10:21:02+01:00
New Revision: 78d49002ce6595237f7702999c8f30b00d7a4302
URL: https://github.com/llvm/llvm-project/commit/78d49002ce6595237f7702999c8f30b00d7a4302
DIFF: https://github.com/llvm/llvm-project/commit/78d49002ce6595237f7702999c8f30b00d7a4302.diff
LOG: AMDGPU/GlobalISel: Implement RegBankLegalize rules for SALUFloat variants of G_INTRINSIC_TRUNC, G_FFLOOR and G_FCEIL. (#187679)
As requested on PR #179954.
Added:
llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
Modified:
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index b82561455167d..f23524ee1fc6b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1591,12 +1591,20 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{UniS1, _, S64}, {{UniInVcc}, {None, Vgpr64, Vgpr64}}})
.Any({{DivS1, _, S64}, {{Vcc}, {None, Vgpr64, Vgpr64}}});
- addRulesForGOpcs({G_INTRINSIC_TRUNC, G_INTRINSIC_ROUNDEVEN, G_FFLOOR, G_FCEIL,
- G_FEXP2, G_FLOG2},
- Standard)
+ addRulesForGOpcs({G_INTRINSIC_ROUNDEVEN, G_FEXP2, G_FLOG2}, Standard)
+ .Uni(S16, {{UniInVgprS16}, {Vgpr16}})
+ .Div(S16, {{Vgpr16}, {Vgpr16}})
+ .Uni(S32, {{UniInVgprS32}, {Vgpr32}})
+ .Div(S32, {{Vgpr32}, {Vgpr32}})
+ .Uni(S64, {{UniInVgprS64}, {Vgpr64}})
+ .Div(S64, {{Vgpr64}, {Vgpr64}});
+
+ addRulesForGOpcs({G_INTRINSIC_TRUNC, G_FFLOOR, G_FCEIL}, Standard)
.Uni(S16, {{UniInVgprS16}, {Vgpr16}})
+ .Uni(S16, {{Sgpr16}, {Sgpr16}}, hasSALUFloat)
.Div(S16, {{Vgpr16}, {Vgpr16}})
.Uni(S32, {{UniInVgprS32}, {Vgpr32}})
+ .Uni(S32, {{Sgpr32}, {Sgpr32}}, hasSALUFloat)
.Div(S32, {{Vgpr32}, {Vgpr32}})
.Uni(S64, {{UniInVgprS64}, {Vgpr64}})
.Div(S64, {{Vgpr64}, {Vgpr64}});
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
new file mode 100644
index 0000000000000..f040d702df605
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
@@ -0,0 +1,134 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=fiji -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=FIJI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX12 %s
+
+define float @fceil_s(float inreg %val) {
+; FIJI-LABEL: fceil_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_ceil_f32_e32 v0, s16
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fceil_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_ceil_f32 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call float @llvm.ceil.f32(float %val)
+ ret float %result
+}
+
+define float @fceil_v(float %val) {
+; FIJI-LABEL: fceil_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_ceil_f32_e32 v0, v0
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fceil_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_ceil_f32_e32 v0, v0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call float @llvm.ceil.f32(float %val)
+ ret float %result
+}
+
+define half @fceil_s16_s(half inreg %val) {
+; FIJI-LABEL: fceil_s16_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_ceil_f16_e32 v0, s16
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fceil_s16_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_ceil_f16 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call half @llvm.ceil.f16(half %val)
+ ret half %result
+}
+
+define half @fceil_s16_v(half %val) {
+; FIJI-LABEL: fceil_s16_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_ceil_f16_e32 v0, v0
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fceil_s16_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_ceil_f16_e32 v0.l, v0.l
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call half @llvm.ceil.f16(half %val)
+ ret half %result
+}
+
+define double @fceil_s64_v(double %val) {
+; FIJI-LABEL: fceil_s64_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_ceil_f64_e32 v[0:1], v[0:1]
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fceil_s64_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_ceil_f64_e32 v[0:1], v[0:1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call double @llvm.ceil.f64(double %val)
+ ret double %result
+}
+
+
+define double @fceil_s64_s(double inreg %val) {
+; FIJI-LABEL: fceil_s64_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_ceil_f64_e32 v[0:1], s[16:17]
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fceil_s64_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_ceil_f64_e32 v[0:1], s[0:1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call double @llvm.ceil.f64(double %val)
+ ret double %result
+}
+
+declare float @llvm.ceil.f32(float)
+declare half @llvm.ceil.f16(half)
+declare double @llvm.ceil.f64(double)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
new file mode 100644
index 0000000000000..382c3eb9f54c5
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
@@ -0,0 +1,133 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=fiji -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=FIJI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX12 %s
+
+define float @ffloor_s(float inreg %val) {
+; FIJI-LABEL: ffloor_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_floor_f32_e32 v0, s16
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: ffloor_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_floor_f32 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call float @llvm.floor.f32(float %val)
+ ret float %result
+}
+
+define float @ffloor_v(float %val) {
+; FIJI-LABEL: ffloor_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_floor_f32_e32 v0, v0
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: ffloor_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_floor_f32_e32 v0, v0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call float @llvm.floor.f32(float %val)
+ ret float %result
+}
+
+define half @ffloor_s16_s(half inreg %val) {
+; FIJI-LABEL: ffloor_s16_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_floor_f16_e32 v0, s16
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: ffloor_s16_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_floor_f16 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call half @llvm.floor.f16(half %val)
+ ret half %result
+}
+
+define half @ffloor_s16_v(half %val) {
+; FIJI-LABEL: ffloor_s16_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_floor_f16_e32 v0, v0
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: ffloor_s16_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_floor_f16_e32 v0.l, v0.l
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call half @llvm.floor.f16(half %val)
+ ret half %result
+}
+
+define double @ffloor_s64_v(double %val) {
+; FIJI-LABEL: ffloor_s64_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_floor_f64_e32 v[0:1], v[0:1]
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: ffloor_s64_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_floor_f64_e32 v[0:1], v[0:1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call double @llvm.floor.f64(double %val)
+ ret double %result
+}
+
+define double @ffloor_s64_s(double inreg %val) {
+; FIJI-LABEL: ffloor_s64_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_floor_f64_e32 v[0:1], s[16:17]
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: ffloor_s64_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_floor_f64_e32 v[0:1], s[0:1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call double @llvm.floor.f64(double %val)
+ ret double %result
+}
+
+declare float @llvm.floor.f32(float)
+declare half @llvm.floor.f16(half)
+declare double @llvm.floor.f64(double)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
new file mode 100644
index 0000000000000..53e2fb384410c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
@@ -0,0 +1,133 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=fiji -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=FIJI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX12 %s
+
+define float @intrinsic_trunc_s(float inreg %val) {
+; FIJI-LABEL: intrinsic_trunc_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_trunc_f32_e32 v0, s16
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: intrinsic_trunc_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_trunc_f32 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call float @llvm.trunc.f32(float %val)
+ ret float %result
+}
+
+define float @intrinsic_trunc_v(float %val) {
+; FIJI-LABEL: intrinsic_trunc_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_trunc_f32_e32 v0, v0
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: intrinsic_trunc_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_trunc_f32_e32 v0, v0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call float @llvm.trunc.f32(float %val)
+ ret float %result
+}
+
+define half @intrinsic_trunc_s16_s(half inreg %val) {
+; FIJI-LABEL: intrinsic_trunc_s16_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_trunc_f16_e32 v0, s16
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: intrinsic_trunc_s16_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_trunc_f16 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call half @llvm.trunc.f16(half %val)
+ ret half %result
+}
+
+define half @intrinsic_trunc_s16_v(half %val) {
+; FIJI-LABEL: intrinsic_trunc_s16_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_trunc_f16_e32 v0, v0
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: intrinsic_trunc_s16_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_trunc_f16_e32 v0.l, v0.l
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call half @llvm.trunc.f16(half %val)
+ ret half %result
+}
+
+define double @intrinsic_trunc_s64_v(double %val) {
+; FIJI-LABEL: intrinsic_trunc_s64_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: intrinsic_trunc_s64_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call double @llvm.trunc.f64(double %val)
+ ret double %result
+}
+
+define double @intrinsic_trunc_s64_s(double inreg %val) {
+; FIJI-LABEL: intrinsic_trunc_s64_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_trunc_f64_e32 v[0:1], s[16:17]
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: intrinsic_trunc_s64_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_trunc_f64_e32 v[0:1], s[0:1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call double @llvm.trunc.f64(double %val)
+ ret double %result
+}
+
+declare float @llvm.trunc.f32(float)
+declare half @llvm.trunc.f16(half)
+declare double @llvm.trunc.f64(double)
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
index 12e7211355080..92cad3f0f4bf3 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
@@ -838,21 +838,21 @@ define i64 @test_s_signed_i64_f32(float inreg %f) nounwind {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: v_trunc_f32_e32 v0, s0
+; GFX12-GI-NEXT: s_trunc_f32 s1, s0
; GFX12-GI-NEXT: s_mov_b32 s6, 0
; GFX12-GI-NEXT: s_brev_b32 s7, 1
-; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_bitset0_b32 s1, 31
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_mul_f32 s2, s1, 0x2f800000
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: v_floor_f32_e32 v0, s2
+; GFX12-GI-NEXT: s_floor_f32 s3, s2
; GFX12-GI-NEXT: s_ashr_i32 s2, s0, 31
-; GFX12-GI-NEXT: v_readfirstlane_b32 s3, v0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_fmac_f32 s1, s3, 0xcf800000
; GFX12-GI-NEXT: s_cvt_u32_f32 s5, s3
-; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_mov_b32 s3, s2
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_cvt_u32_f32 s4, s1
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_xor_b64 s[4:5], s[4:5], s[2:3]
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
index b064ce6cec7a8..2b02c54f780ac 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
@@ -575,13 +575,13 @@ define i64 @test_s_unsigned_i64_f32(float inreg %f) nounwind {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: v_trunc_f32_e32 v0, s0
+; GFX12-GI-NEXT: s_trunc_f32 s1, s0
; GFX12-GI-NEXT: s_cmp_nge_f32 s0, 0
-; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_mul_f32 s2, s1, 0x2f800000
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: v_floor_f32_e32 v0, s2
-; GFX12-GI-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GI-NEXT: s_floor_f32 s2, s2
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_fmac_f32 s1, s2, 0xcf800000
; GFX12-GI-NEXT: s_cvt_u32_f32 s3, s2
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
diff --git a/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll b/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
index 76d58e0e46dd1..ea1cf34010607 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
@@ -97,64 +97,34 @@ define amdgpu_vs half @fptrunc_f32_to_f16(float inreg %val) {
}
define amdgpu_vs float @fceil_f32(float inreg %val) {
-; SDAG-LABEL: fceil_f32:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_ceil_f32 s0, s0
-; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; SDAG-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX11-LABEL: fceil_f32:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_ceil_f32_e32 v0, s0
-; GISEL-GFX11-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX12-LABEL: fceil_f32:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: v_ceil_f32_e32 v0, s0
-; GISEL-GFX12-NEXT: ; return to shader part epilog
+; CHECK-LABEL: fceil_f32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_ceil_f32 s0, s0
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: ; return to shader part epilog
%res = call float @llvm.ceil.f32(float %val)
ret float %res
}
define amdgpu_vs float @ffloor_f32(float inreg %val) {
-; SDAG-LABEL: ffloor_f32:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_floor_f32 s0, s0
-; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; SDAG-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX11-LABEL: ffloor_f32:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_floor_f32_e32 v0, s0
-; GISEL-GFX11-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX12-LABEL: ffloor_f32:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: v_floor_f32_e32 v0, s0
-; GISEL-GFX12-NEXT: ; return to shader part epilog
+; CHECK-LABEL: ffloor_f32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_floor_f32 s0, s0
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: ; return to shader part epilog
%res = call float @llvm.floor.f32(float %val)
ret float %res
}
define amdgpu_vs float @ftrunc_f32(float inreg %val) {
-; SDAG-LABEL: ftrunc_f32:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_trunc_f32 s0, s0
-; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; SDAG-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX11-LABEL: ftrunc_f32:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_trunc_f32_e32 v0, s0
-; GISEL-GFX11-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX12-LABEL: ftrunc_f32:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: v_trunc_f32_e32 v0, s0
-; GISEL-GFX12-NEXT: ; return to shader part epilog
+; CHECK-LABEL: ftrunc_f32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_trunc_f32 s0, s0
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: ; return to shader part epilog
%res = call float @llvm.trunc.f32(float %val)
ret float %res
}
@@ -181,64 +151,34 @@ define amdgpu_vs float @frint_f32(float inreg %val) {
}
define amdgpu_vs half @fceil_f16(half inreg %val) {
-; SDAG-LABEL: fceil_f16:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_ceil_f16 s0, s0
-; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; SDAG-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX11-LABEL: fceil_f16:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_ceil_f16_e32 v0.l, s0
-; GISEL-GFX11-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX12-LABEL: fceil_f16:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: v_ceil_f16_e32 v0.l, s0
-; GISEL-GFX12-NEXT: ; return to shader part epilog
+; CHECK-LABEL: fceil_f16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_ceil_f16 s0, s0
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: ; return to shader part epilog
%res = call half @llvm.ceil.f16(half %val)
ret half %res
}
define amdgpu_vs half @ffloor_f16(half inreg %val) {
-; SDAG-LABEL: ffloor_f16:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_floor_f16 s0, s0
-; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; SDAG-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX11-LABEL: ffloor_f16:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_floor_f16_e32 v0.l, s0
-; GISEL-GFX11-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX12-LABEL: ffloor_f16:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: v_floor_f16_e32 v0.l, s0
-; GISEL-GFX12-NEXT: ; return to shader part epilog
+; CHECK-LABEL: ffloor_f16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_floor_f16 s0, s0
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: ; return to shader part epilog
%res = call half @llvm.floor.f16(half %val)
ret half %res
}
define amdgpu_vs half @ftrunc_f16(half inreg %val) {
-; SDAG-LABEL: ftrunc_f16:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_trunc_f16 s0, s0
-; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; SDAG-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX11-LABEL: ftrunc_f16:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_trunc_f16_e32 v0.l, s0
-; GISEL-GFX11-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX12-LABEL: ftrunc_f16:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: v_trunc_f16_e32 v0.l, s0
-; GISEL-GFX12-NEXT: ; return to shader part epilog
+; CHECK-LABEL: ftrunc_f16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_trunc_f16 s0, s0
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: ; return to shader part epilog
%res = call half @llvm.trunc.f16(half %val)
ret half %res
}
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