[llvm] [Xtensa] Implement support of the ESP32S2 target. (PR #200130)

[Matt Arsenault via llvm-commits]

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@@ -606,4 +610,16 @@ XtensaMCCodeEmitter::getImm7_22OpValue(const MCInst &MI, unsigned OpNo,
 
   return res;
 }
+
+uint8_t
+XtensaMCCodeEmitter::getSelect_256OpValue(const MCInst &MI, unsigned OpNo,
+                                          SmallVectorImpl<MCFixup> &Fixups,
+                                          const MCSubtargetInfo &STI) const {
+  const MCOperand &MO = MI.getOperand(OpNo);
+  uint8_t Res = static_cast<uint8_t>(MO.getImm());
+
+  assert(((Res >= 0) && (Res <= 255)) && "Unexpected operand value!");
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arsenm wrote:

isUInt<8>

https://github.com/llvm/llvm-project/pull/200130