[llvm] [AArch64][SVE] Use ADD/ADR instead of MUL/MLA for x*N (PR #198566)

[Tomas Matheson via llvm-commits]

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@@ -20579,10 +20618,169 @@ static bool isOnlyUsedAsMemoryAddress(SDNode *N) {
   return true;
 }
 
+/// Build an all-active SVE left shift by a constant element value.
+static SDValue buildSVEShiftLeftImmediate(SDValue Op, unsigned Shift,
+                                          SelectionDAG &DAG, SDLoc DL) {
+  EVT VT = Op.getValueType();
+  assert(VT.isScalableVector() && "Expected scalable vector type");
+
+  EVT ScalarVT = VT.getScalarType();
+  SDValue ShiftSplat = DAG.getNode(ISD::SPLAT_VECTOR, DL, VT,
+                                   DAG.getConstant(Shift, DL, ScalarVT));
+  return DAG.getNode(AArch64ISD::SHL_PRED, DL, VT,
+                     getPredicateForVector(DAG, DL, VT), Op, ShiftSplat);
+}
+
+static bool isSupportedSVEMulByConstantVT(EVT VT) {
+  return VT.isScalableVector() &&
+         (VT.getScalarType() == MVT::i32 || VT.getScalarType() == MVT::i64);
+}
+
+/// Combine an SVE multiply by a constant that does not need MUL:
+///   x * 2     -> x + x
+///   x * 3/5/9 -> x + (x << 1/2/3), which can select ADR.
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tommat01 wrote:

Reimplemented as isel patterns

https://github.com/llvm/llvm-project/pull/198566