[llvm] d8388a1 - [AArch64] Use PNR rather than PPR register class for aarch64svcount (#202394)

[via llvm-commits]

Author: Benjamin Maxwell
Date: 2026-06-10T10:09:35+01:00
New Revision: d8388a15b33e67fd297a47a0e6ee80c3a5cd947a

URL: https://github.com/llvm/llvm-project/commit/d8388a15b33e67fd297a47a0e6ee80c3a5cd947a
DIFF: https://github.com/llvm/llvm-project/commit/d8388a15b33e67fd297a47a0e6ee80c3a5cd947a.diff

LOG: [AArch64] Use PNR rather than PPR register class for aarch64svcount (#202394)

While predicates and predicate-as-counter both use the same underlying
registers, within LLVM they use different register classes (PPR vs PNR).
Mapping aarch64svcount to the PPRRegClass results in some unnecessary
cross register class copies around PHIs, which results in some
unnecessary moves.

Added: 
    llvm/test/CodeGen/AArch64/predicate-as-counter-phi.ll

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index bb3d7b560b534..57a2d73e00f57 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -471,7 +471,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     addRegisterClass(MVT::nxv16i1, &AArch64::PPRRegClass);
 
     // Add sve predicate as counter type
-    addRegisterClass(MVT::aarch64svcount, &AArch64::PPRRegClass);
+    addRegisterClass(MVT::aarch64svcount, &AArch64::PNRRegClass);
 
     // Add legal sve data types
     addRegisterClass(MVT::nxv16i8, &AArch64::ZPRRegClass);

diff  --git a/llvm/test/CodeGen/AArch64/predicate-as-counter-phi.ll b/llvm/test/CodeGen/AArch64/predicate-as-counter-phi.ll
new file mode 100644
index 0000000000000..89352211eda04
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/predicate-as-counter-phi.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mattr=+sve2p1 < %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux"
+
+define void @predicate_as_counter_phi(i64 %N) {
+; CHECK-LABEL: predicate_as_counter_phi:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    rdvl x8, #2
+; CHECK-NEXT:    whilelo pn8.h, xzr, x0, vlx4
+; CHECK-NEXT:  .LBB0_1: // %vector.body
+; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    // fake_use: $pn8
+; CHECK-NEXT:    whilelo pn8.h, x8, x0, vlx4
+; CHECK-NEXT:    incb x8, all, mul #2
+; CHECK-NEXT:    b .LBB0_1
+entry:
+  %vscale = call i64 @llvm.vscale.i64()
+  %step = shl nuw i64 %vscale, 5
+  %pred.entry = call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c16(i64 0, i64 %N, i32 4)
+  br label %vector.body
+
+vector.body:
+  %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
+  %pred = phi target("aarch64.svcount") [ %pred.entry, %entry ], [ %pred.next, %vector.body ]
+
+  call void (...) @llvm.fake.use(target("aarch64.svcount") %pred)
+
+  %index.next = add i64 %index, %step
+  %pred.next = call target("aarch64.svcount") @llvm.aarch64.sve.whilelo.c16(i64 %index.next, i64 %N, i32 4)
+  br label %vector.body
+
+exit:
+  unreachable
+}