[llvm] 06f2542 - [VPlan] Also expand integer SCEVAddExpr in expandSCEVExpr. (#200925)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 9 13:48:48 PDT 2026
Author: Florian Hahn
Date: 2026-06-09T22:48:43+02:00
New Revision: 06f25425e324fdfa79613f5255dfb2c77ae7de6d
URL: https://github.com/llvm/llvm-project/commit/06f25425e324fdfa79613f5255dfb2c77ae7de6d
DIFF: https://github.com/llvm/llvm-project/commit/06f25425e324fdfa79613f5255dfb2c77ae7de6d.diff
LOG: [VPlan] Also expand integer SCEVAddExpr in expandSCEVExpr. (#200925)
Generalize the SCEVMulExpr handling in expandSCEVExpr to also handle
SCEVAddExpr. Currently limited to integer expressions only. Pointer to
follow separately, as they cannot use Instruction::Add.
Added:
Modified:
llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
llvm/lib/Transforms/Vectorize/VPlanUtils.h
llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory.ll
llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
llvm/test/Transforms/LoopVectorize/cast-induction.ll
llvm/test/Transforms/LoopVectorize/expand-ptrtoaddr.ll
llvm/test/Transforms/LoopVectorize/induction-step.ll
llvm/test/Transforms/LoopVectorize/miniters.ll
llvm/test/Transforms/LoopVectorize/pointer-induction.ll
llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll
llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index fcfcb96a68f07..cc19c1c1faa2d 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -5452,7 +5452,11 @@ void VPlanTransforms::expandSCEVsToVPInstructions(VPlan &Plan,
ScalarEvolution &SE) {
auto *Entry = Plan.getEntry();
VPBuilder Builder(Entry, Entry->begin());
- VPSCEVExpander Expander(Builder, SE);
+ DebugLoc DL = cast<VPIRBasicBlock>(Entry)
+ ->getIRBasicBlock()
+ ->getTerminator()
+ ->getDebugLoc();
+ VPSCEVExpander Expander(Builder, SE, DL);
// Expand VPExpandSCEVRecipes to VPInstructions using VPSCEVExpander. During
// the transition, unsupported VPExpandSCEVRecipes are skipped and left for
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
index f7f2d4591a3ce..442ddbdde66ca 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
@@ -16,6 +16,7 @@
#include "llvm/Analysis/MemoryLocation.h"
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
#include "llvm/Analysis/ScalarEvolutionPatternMatch.h"
+#include "llvm/IR/Dominators.h"
#include "llvm/Transforms/Utils/ScalarEvolutionExpander.h"
using namespace llvm;
@@ -909,12 +910,13 @@ VPValue *VPSCEVExpander::tryToReuseIRValue(const SCEV *S) {
VPlan &Plan = Builder.getPlan();
BasicBlock *PH = cast<VPIRBasicBlock>(Plan.getEntry())->getIRBasicBlock();
for (Value *V : SE.getSCEVValues(S)) {
- // Only reuse instructions in the plan's entry block, as instructions in
- // sibling branches may not dominate the entry block.
+ // Only reuse instructions in the plan's entry block, or, when a
+ // DominatorTree is available, any instruction that dominates it.
+ // Instructions in sibling branches may not dominate the entry block.
auto *I = dyn_cast<Instruction>(V);
if (!I)
return Plan.getOrAddLiveIn(V);
- if (I->getParent() != PH)
+ if (!SE.DT.dominates(I->getParent(), PH))
continue;
SmallVector<Instruction *> DropPoisonGeneratingInsts;
if (!SE.canReuseInstruction(S, I, DropPoisonGeneratingInsts))
@@ -937,21 +939,26 @@ VPValue *VPSCEVExpander::tryToExpand(const SCEV *S) {
return Builder.getPlan().getOrAddLiveIn(cast<SCEVUnknown>(S)->getValue());
case scVScale:
return Builder.createNaryOp(VPInstruction::VScale, {}, S->getType());
+ case scAddExpr:
case scMulExpr: {
- auto *Mul = cast<SCEVMulExpr>(S);
+ if (S->getType()->isPointerTy())
+ return nullptr;
+ auto *NAry = cast<SCEVNAryExpr>(S);
+ unsigned Opcode =
+ S->getSCEVType() == scAddExpr ? Instruction::Add : Instruction::Mul;
+ // Iterate in reverse so that constants are emitted last.
SmallVector<VPValue *, 2> Ops;
- for (const SCEVUse &Op : Mul->operands()) {
+ for (const SCEVUse &Op : reverse(NAry->operands())) {
VPValue *OpV = tryToExpand(Op);
if (!OpV)
return nullptr;
Ops.push_back(OpV);
}
- VPIRFlags::WrapFlagsTy WrapFlags(Mul->hasNoUnsignedWrap(),
- Mul->hasNoSignedWrap());
+ VPIRFlags::WrapFlagsTy WrapFlags(NAry->hasNoUnsignedWrap(),
+ NAry->hasNoSignedWrap());
VPValue *Result = Ops.front();
for (VPValue *Op : drop_begin(Ops))
- Result = Builder.createOverflowingOp(Instruction::Mul, {Result, Op},
- WrapFlags, DL);
+ Result = Builder.createOverflowingOp(Opcode, {Result, Op}, WrapFlags, DL);
return Result;
}
default:
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.h b/llvm/lib/Transforms/Vectorize/VPlanUtils.h
index 60ab2632a089c..deb025992c718 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.h
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.h
@@ -13,6 +13,7 @@
#include "llvm/Support/Compiler.h"
namespace llvm {
+class DominatorTree;
class MemoryLocation;
class ScalarEvolution;
class SCEV;
@@ -197,7 +198,7 @@ class VPSCEVExpander {
VPValue *tryToReuseIRValue(const SCEV *S);
public:
- VPSCEVExpander(VPBuilder &Builder, ScalarEvolution &SE, DebugLoc DL = {})
+ VPSCEVExpander(VPBuilder &Builder, ScalarEvolution &SE, DebugLoc DL)
: Builder(Builder), SE(SE), DL(DL) {}
/// Try to expand \p S into recipes and live-ins using the builder. Returns
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
index f70b68b94f375..ec5c95fb0b17d 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll
@@ -1129,10 +1129,10 @@ define void @pred_udiv_select_cost(ptr %A, ptr %B, ptr %C, i64 %n, i8 %y) #1 {
; DEFAULT-NEXT: [[B3:%.*]] = ptrtoaddr ptr [[B]] to i64
; DEFAULT-NEXT: [[A2:%.*]] = ptrtoaddr ptr [[A]] to i64
; DEFAULT-NEXT: [[C1:%.*]] = ptrtoaddr ptr [[C]] to i64
-; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
; DEFAULT-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; DEFAULT-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 2
; DEFAULT-NEXT: [[TMP3:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP2]], i64 8)
+; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP3]]
; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
; DEFAULT: [[VECTOR_MEMCHECK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
index d2d71bd1b79c5..882a55765e25e 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll
@@ -49,10 +49,10 @@ define i32 @chained_recurrences(i32 %x, i64 %y, ptr %src.1, i32 %z, ptr %src.2)
; VSCALEFORTUNING2-LABEL: define i32 @chained_recurrences(
; VSCALEFORTUNING2-SAME: i32 [[X:%.*]], i64 [[Y:%.*]], ptr [[SRC_1:%.*]], i32 [[Z:%.*]], ptr [[SRC_2:%.*]]) #[[ATTR0:[0-9]+]] {
; VSCALEFORTUNING2-NEXT: [[ENTRY:.*]]:
-; VSCALEFORTUNING2-NEXT: [[TMP0:%.*]] = add i64 [[Y]], 1
; VSCALEFORTUNING2-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; VSCALEFORTUNING2-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 3
; VSCALEFORTUNING2-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP2]], i64 16)
+; VSCALEFORTUNING2-NEXT: [[TMP0:%.*]] = add i64 [[Y]], 1
; VSCALEFORTUNING2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[UMAX]]
; VSCALEFORTUNING2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; VSCALEFORTUNING2: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
index 2abaf2ec0fdaa..7a7ae1edbc415 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-uniform-store.ll
@@ -12,7 +12,7 @@ define void @lshift_significand(i32 %n, ptr nocapture writeonly %dst) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[CMP1_PEEL:%.*]] = icmp eq i32 [[N]], 0
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[CMP1_PEEL]], i64 2, i64 0
-; CHECK-NEXT: [[TMP0:%.*]] = sub i64 3, [[SPEC_SELECT]]
+; CHECK-NEXT: [[TMP0:%.*]] = sub nsw i64 3, [[SPEC_SELECT]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory.ll b/llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory.ll
index 5a3c052df1c4d..2c9dfec8c1910 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/transform-narrow-interleave-to-widen-memory.ll
@@ -102,10 +102,10 @@ define void @interleave_group_with_countable_early_exit(i64 %n, ptr %dst) {
; CHECK-LABEL: define void @interleave_group_with_countable_early_exit(
; CHECK-SAME: i64 [[N:%.*]], ptr [[DST:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 1
; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP2]], i64 38)
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP0]], [[UMAX]]
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
@@ -163,10 +163,10 @@ define void @interleave_group_with_countable_early_exit(i64 %n, ptr %dst) {
; EPILOGUE-LABEL: define void @interleave_group_with_countable_early_exit(
; EPILOGUE-SAME: i64 [[N:%.*]], ptr [[DST:%.*]]) #[[ATTR0]] {
; EPILOGUE-NEXT: [[ENTRY:.*]]:
-; EPILOGUE-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
; EPILOGUE-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; EPILOGUE-NEXT: [[TMP2:%.*]] = shl nuw i64 [[TMP1]], 1
; EPILOGUE-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP2]], i64 40)
+; EPILOGUE-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
; EPILOGUE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP0]], [[UMAX]]
; EPILOGUE-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; EPILOGUE: [[VECTOR_SCEVCHECK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
index 870c78400def2..129e8a4a9197b 100644
--- a/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/expand-scev.ll
@@ -6,11 +6,10 @@
define void @scev_add_expanded(ptr %dst, i64 %n) {
; CHECK-LABEL: VPlan for loop in 'scev_add_expanded'
; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' {
-; CHECK-NEXT: Live-in ir<%0> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<loop.preheader>:
-; CHECK-NEXT: IR %0 = add i64 %n, 2
-; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult ir<%0>, ir<4>
+; CHECK-NEXT: EMIT vp<[[VP2:%[0-9]+]]> = add ir<%n>, ir<2>
+; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult vp<[[VP2]]>, ir<4>
; CHECK-NEXT: EMIT branch-on-cond vp<%min.iters.check>
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, vector.ph
;
@@ -119,7 +118,6 @@ exit:
define void @scev_expand_udiv(ptr %dst, i64 %n) {
; CHECK-LABEL: VPlan for loop in 'scev_expand_udiv'
; CHECK: VPlan 'Final VPlan for VF={4},UF={1}' {
-; CHECK-NEXT: Live-in ir<%div> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: ir-bb<loop.preheader>:
; CHECK-NEXT: EMIT vp<%min.iters.check> = icmp ult ir<%div>, ir<4>
diff --git a/llvm/test/Transforms/LoopVectorize/cast-induction.ll b/llvm/test/Transforms/LoopVectorize/cast-induction.ll
index 1f719673eb217..bf9dd4a84d506 100644
--- a/llvm/test/Transforms/LoopVectorize/cast-induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/cast-induction.ll
@@ -357,7 +357,7 @@ define void @test_start_zext(i32 %start, ptr %dst) {
; IC2-SAME: i32 [[START:%.*]], ptr [[DST:%.*]]) {
; IC2-NEXT: [[ENTRY:.*]]:
; IC2-NEXT: [[START_EXT:%.*]] = zext i32 [[START]] to i64
-; IC2-NEXT: [[TMP0:%.*]] = sub i64 100, [[START_EXT]]
+; IC2-NEXT: [[TMP0:%.*]] = sub nsw i64 100, [[START_EXT]]
; IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2
; IC2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; IC2: [[VECTOR_PH]]:
@@ -420,11 +420,11 @@ define i64 @induction_cast_chain_cleared_by_dce(i64 %n, i64 %mask.init) {
; VF4-SAME: i64 [[N:%.*]], i64 [[MASK_INIT:%.*]]) {
; VF4-NEXT: [[ENTRY:.*]]:
; VF4-NEXT: [[MASK:%.*]] = and i64 [[MASK_INIT]], -4294967296
-; VF4-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[MASK]], 1
; VF4-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[MASK]], 2
; VF4-NEXT: [[SMAX1:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 [[TMP0]])
; VF4-NEXT: [[TMP1:%.*]] = add i64 [[SMAX1]], -1
; VF4-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[MASK]]
+; VF4-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[MASK]], 1
; VF4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 4
; VF4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; VF4: [[VECTOR_SCEVCHECK]]:
@@ -488,11 +488,11 @@ define i64 @induction_cast_chain_cleared_by_dce(i64 %n, i64 %mask.init) {
; IC2-SAME: i64 [[N:%.*]], i64 [[MASK_INIT:%.*]]) {
; IC2-NEXT: [[ENTRY:.*]]:
; IC2-NEXT: [[MASK:%.*]] = and i64 [[MASK_INIT]], -4294967296
-; IC2-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[MASK]], 1
; IC2-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[MASK]], 2
; IC2-NEXT: [[SMAX1:%.*]] = call i64 @llvm.smax.i64(i64 [[N]], i64 [[TMP0]])
; IC2-NEXT: [[TMP1:%.*]] = add i64 [[SMAX1]], -1
; IC2-NEXT: [[TMP2:%.*]] = sub i64 [[TMP1]], [[MASK]]
+; IC2-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[MASK]], 1
; IC2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 2
; IC2-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; IC2: [[VECTOR_SCEVCHECK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/expand-ptrtoaddr.ll b/llvm/test/Transforms/LoopVectorize/expand-ptrtoaddr.ll
index e925e8422c3fd..707ecc00b862a 100644
--- a/llvm/test/Transforms/LoopVectorize/expand-ptrtoaddr.ll
+++ b/llvm/test/Transforms/LoopVectorize/expand-ptrtoaddr.ll
@@ -7,8 +7,8 @@ define void @test_ptrtoaddr_tripcount(ptr %start, ptr %end) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[START_ADDR:%.*]] = ptrtoaddr ptr [[START]] to i64
; CHECK-NEXT: [[END_ADDR:%.*]] = ptrtoaddr ptr [[END]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[END_ADDR]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START_ADDR]]
+; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[END_ADDR]], [[START_ADDR]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i64 [[TMP0]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/induction-step.ll b/llvm/test/Transforms/LoopVectorize/induction-step.ll
index 47b6181d430cb..ea2162b1a7fd6 100644
--- a/llvm/test/Transforms/LoopVectorize/induction-step.ll
+++ b/llvm/test/Transforms/LoopVectorize/induction-step.ll
@@ -452,8 +452,8 @@ define void @test_expand_scev_order(i32 %x, i32 %iv.2.step, i64 %n, ptr %dst) {
; CHECK-SAME: i32 [[X:%.*]], i32 [[IV_2_STEP:%.*]], i64 [[N:%.*]], ptr [[DST:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
; CHECK-NEXT: [[X_EXT:%.*]] = zext i32 [[X]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[IV_2_STEP]]
+; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
diff --git a/llvm/test/Transforms/LoopVectorize/miniters.ll b/llvm/test/Transforms/LoopVectorize/miniters.ll
index 0cedb5b644250..c48be01625600 100644
--- a/llvm/test/Transforms/LoopVectorize/miniters.ll
+++ b/llvm/test/Transforms/LoopVectorize/miniters.ll
@@ -60,7 +60,7 @@ define void @min_iters_known_via_loop_guards_add(i32 %start, i32 %end, ptr %src)
; CHECK-NEXT: call void @llvm.assume(i1 [[PRE]])
; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[SUB]], 1
; CHECK-NEXT: [[IV_START:%.*]] = zext i32 [[ADD_1]] to i64
-; CHECK-NEXT: [[TMP0:%.*]] = sub i64 101, [[IV_START]]
+; CHECK-NEXT: [[TMP0:%.*]] = sub nsw i64 101, [[IV_START]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
;
@@ -72,7 +72,7 @@ define void @min_iters_known_via_loop_guards_add(i32 %start, i32 %end, ptr %src)
; UNROLL-NEXT: call void @llvm.assume(i1 [[PRE]])
; UNROLL-NEXT: [[ADD_1:%.*]] = add i32 [[SUB]], 1
; UNROLL-NEXT: [[IV_START:%.*]] = zext i32 [[ADD_1]] to i64
-; UNROLL-NEXT: [[TMP0:%.*]] = sub i64 101, [[IV_START]]
+; UNROLL-NEXT: [[TMP0:%.*]] = sub nsw i64 101, [[IV_START]]
; UNROLL-NEXT: br label %[[VECTOR_PH:.*]]
; UNROLL: [[VECTOR_PH]]:
;
diff --git a/llvm/test/Transforms/LoopVectorize/pointer-induction.ll b/llvm/test/Transforms/LoopVectorize/pointer-induction.ll
index 0b312ea259349..760d8e4d1a465 100644
--- a/llvm/test/Transforms/LoopVectorize/pointer-induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/pointer-induction.ll
@@ -430,8 +430,8 @@ define i64 @ivopt_widen_ptr_indvar_1(ptr noalias %a, i64 %stride, i64 %n) {
;
; STRIDED-LABEL: @ivopt_widen_ptr_indvar_1(
; STRIDED-NEXT: entry:
-; STRIDED-NEXT: [[TMP0:%.*]] = add i64 [[N:%.*]], 1
; STRIDED-NEXT: [[TMP1:%.*]] = shl i64 [[STRIDE:%.*]], 3
+; STRIDED-NEXT: [[TMP0:%.*]] = add i64 [[N:%.*]], 1
; STRIDED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4
; STRIDED-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; STRIDED: vector.ph:
@@ -515,8 +515,8 @@ define i64 @ivopt_widen_ptr_indvar_2(ptr noalias %a, i64 %stride, i64 %n) {
;
; STRIDED-LABEL: @ivopt_widen_ptr_indvar_2(
; STRIDED-NEXT: entry:
-; STRIDED-NEXT: [[TMP0:%.*]] = add i64 [[N:%.*]], 1
; STRIDED-NEXT: [[TMP1:%.*]] = shl i64 [[STRIDE:%.*]], 3
+; STRIDED-NEXT: [[TMP0:%.*]] = add i64 [[N:%.*]], 1
; STRIDED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4
; STRIDED-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; STRIDED: vector.ph:
@@ -620,8 +620,8 @@ define i64 @ivopt_widen_ptr_indvar_3(ptr noalias %a, i64 %stride, i64 %n) {
;
; STRIDED-LABEL: @ivopt_widen_ptr_indvar_3(
; STRIDED-NEXT: entry:
-; STRIDED-NEXT: [[TMP0:%.*]] = add i64 [[N:%.*]], 1
; STRIDED-NEXT: [[TMP1:%.*]] = shl i64 [[STRIDE:%.*]], 3
+; STRIDED-NEXT: [[TMP0:%.*]] = add i64 [[N:%.*]], 1
; STRIDED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4
; STRIDED-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; STRIDED: vector.ph:
diff --git a/llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll b/llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll
index c46bae6628c29..6ed5e66121288 100644
--- a/llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll
+++ b/llvm/test/Transforms/LoopVectorize/reduction-minmax-users-and-predicated.ll
@@ -507,8 +507,8 @@ define i32 @smax_reduction_multiple_incoming(ptr %src, i32 %n, i1 %cond) {
; CHECK: [[LOOP_HEADER_PREHEADER]]:
; CHECK-NEXT: [[IV_PH:%.*]] = phi i32 [ 10, %[[ELSE]] ], [ 0, %[[ENTRY]] ]
; CHECK-NEXT: [[MAX_PH:%.*]] = phi i32 [ 5, %[[ELSE]] ], [ 0, %[[ENTRY]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], 1
-; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[IV_PH]]
+; CHECK-NEXT: [[TMP0:%.*]] = sub i32 [[N]], [[IV_PH]]
+; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP1]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
diff --git a/llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll b/llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
index 1ac7087ae9143..f89c32c03fa29 100644
--- a/llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
+++ b/llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll
@@ -969,12 +969,12 @@ define void @decreasing_inner_iv(ptr nocapture noundef %dst, ptr nocapture nound
; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 4
; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP13]]
; CHECK-NEXT: [[TMP14:%.*]] = shl nsw i64 [[TMP1]], 2
-; CHECK-NEXT: [[TMP15:%.*]] = add nuw nsw i64 [[TMP0]], 1
; CHECK-NEXT: br label [[OUTER_LOOP:%.*]]
; CHECK: outer.loop:
; CHECK-NEXT: [[OUTER_IV:%.*]] = phi i64 [ 0, [[OUTER_LOOP_PRE]] ], [ [[OUTER_IV_NEXT:%.*]], [[INNER_LOOP_EXIT:%.*]] ]
; CHECK-NEXT: [[TMP16:%.*]] = mul nsw i64 [[OUTER_IV]], [[TMP1]]
; CHECK-NEXT: [[TMP17:%.*]] = mul nsw i64 [[OUTER_IV]], [[TMP2]]
+; CHECK-NEXT: [[TMP15:%.*]] = add nuw nsw i64 [[TMP0]], 1
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP15]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]]
; CHECK: vector.memcheck:
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