[llvm] [WIP][AMDGPU] Support the RF inline asm constraint (PR #195123)
Jun Wang via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 9 12:59:44 PDT 2026
================
@@ -0,0 +1,213 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+
+; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck --check-prefix=VI %s
+
+define amdgpu_kernel void @flat_load_v(ptr addrspace(0) %ptr) {
+; VI-LABEL: flat_load_v:
+; VI: ; %bb.0: ; %entry
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_load_dword v0, s[0:1]
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+entry:
+ %a = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,*^RF"(ptr addrspace(0) elementtype(i32) %ptr)
+ ret void
+}
+
+define amdgpu_kernel void @flat_load_v_m_constraint(ptr addrspace(0) %ptr) {
+; VI-LABEL: flat_load_v_m_constraint:
+; VI: ; %bb.0: ; %entry
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_load_dword v0, s[0:1]
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+entry:
+ %a = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=v,*m"(ptr addrspace(0) elementtype(i32) %ptr)
+ ret void
+}
+
+define amdgpu_kernel void @flat_load_v_with_offset(ptr addrspace(0) %ptr) {
+; VI-LABEL: flat_load_v_with_offset:
+; VI: ; %bb.0: ; %entry
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_load_dword v0, s[0:1] offset:4095
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+entry:
+ %a = tail call i32 asm sideeffect "flat_load_dword $0, $1 offset:4095", "=v,*^RF"(ptr addrspace(0) elementtype(i32) %ptr)
+ ret void
+}
+
+define amdgpu_kernel void @flat_load_s(ptr addrspace(0) %ptr) {
+; VI-LABEL: flat_load_s:
+; VI: ; %bb.0: ; %entry
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_load_dword s0, s[0:1]
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+entry:
+ %a = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=s,*^RF"(ptr addrspace(0) elementtype(i32) %ptr)
+ ret void
+}
+
+define amdgpu_kernel void @flat_load_s_m_constraint(ptr addrspace(0) %ptr) {
+; VI-LABEL: flat_load_s_m_constraint:
+; VI: ; %bb.0: ; %entry
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_load_dword s0, s[0:1]
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+entry:
+ %a = tail call i32 asm sideeffect "flat_load_dword $0, $1", "=s,*m"(ptr addrspace(0) elementtype(i32) %ptr)
+ ret void
+}
+
+define amdgpu_kernel void @flat_load_s_with_offset(ptr addrspace(0) %ptr) {
+; VI-LABEL: flat_load_s_with_offset:
+; VI: ; %bb.0: ; %entry
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_load_dword s0, s[0:1] offset:4095
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+entry:
+ %a = tail call i32 asm sideeffect "flat_load_dword $0, $1 offset:4095", "=s,*^RF"(ptr addrspace(0) elementtype(i32) %ptr)
+ ret void
+}
+
+define amdgpu_kernel void @flat_store_imm(ptr addrspace(0) %out) {
+; VI-LABEL: flat_store_imm:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_store_dword s[0:1], 63
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+ call void asm "flat_store_dword $0, $1", "=*^RF,I"(ptr addrspace(0) elementtype(i32) %out, i32 63)
+ ret void
+}
+
+define amdgpu_kernel void @flat_store_imm_m_constraint(ptr addrspace(0) %out) {
+; VI-LABEL: flat_store_imm_m_constraint:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_store_dword s[0:1], 63
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+ call void asm "flat_store_dword $0, $1", "=*m,I"(ptr addrspace(0) elementtype(i32) %out, i32 63)
+ ret void
+}
+
+define amdgpu_kernel void @flat_store_imm_with_offset(ptr addrspace(0) %out) {
+; VI-LABEL: flat_store_imm_with_offset:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_store_dword s[0:1], 63 offset:4095
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+ call void asm "flat_store_dword $0, $1 offset:4095", "=*^RF,I"(ptr addrspace(0) elementtype(i32) %out, i32 63)
+ ret void
+}
+
+define amdgpu_kernel void @flat_store_v(ptr addrspace(0) %out, i32 %in) {
+; VI-LABEL: flat_store_v:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_store_dword s[0:1], v0
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+ call void asm "flat_store_dword $0, $1", "=*^RF,v"(ptr addrspace(0) elementtype(i32) %out, i32 %in)
+ ret void
+}
+
+define amdgpu_kernel void @flat_store_v_m_constraint(ptr addrspace(0) %out, i32 %in) {
+; VI-LABEL: flat_store_v_m_constraint:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_store_dword s[0:1], v0
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+ call void asm "flat_store_dword $0, $1", "=*m,v"(ptr addrspace(0) elementtype(i32) %out, i32 %in)
+ ret void
+}
+
+define amdgpu_kernel void @flat_store_v_with_offset(ptr addrspace(0) %out, i32 %in) {
+; VI-LABEL: flat_store_v_with_offset:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: v_mov_b32_e32 v0, s2
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_store_dword s[0:1], v0 offset:4095
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+ call void asm "flat_store_dword $0, $1 offset:4095", "=*^RF,v"(ptr addrspace(0) elementtype(i32) %out, i32 %in)
+ ret void
+}
+
+define amdgpu_kernel void @flat_store_s(ptr addrspace(0) %out, i32 %in) {
+; VI-LABEL: flat_store_s:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_store_dword s[0:1], s2
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+ call void asm "flat_store_dword $0, $1", "=*^RF,s"(ptr addrspace(0) elementtype(i32) %out, i32 %in)
+ ret void
+}
+
+define amdgpu_kernel void @flat_store_s_m_constraint(ptr addrspace(0) %out, i32 %in) {
+; VI-LABEL: flat_store_s_m_constraint:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_store_dword s[0:1], s2
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+ call void asm "flat_store_dword $0, $1", "=*m,s"(ptr addrspace(0) elementtype(i32) %out, i32 %in)
+ ret void
+}
+
+define amdgpu_kernel void @flat_store_s_with_offset(ptr addrspace(0) %out, i32 %in) {
+; VI-LABEL: flat_store_s_with_offset:
+; VI: ; %bb.0:
+; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; VI-NEXT: s_load_dword s2, s[4:5], 0x2c
+; VI-NEXT: s_waitcnt lgkmcnt(0)
+; VI-NEXT: ;;#ASMSTART
+; VI-NEXT: flat_store_dword s[0:1], s2 offset:4095
+; VI-NEXT: ;;#ASMEND
+; VI-NEXT: s_endpgm
+ call void asm "flat_store_dword $0, $1 offset:4095", "=*^RF,s"(ptr addrspace(0) elementtype(i32) %out, i32 %in)
+ ret void
+}
----------------
jwanggit86 wrote:
Crash is caused by this assert in `SelectionDAGBuilder.cpp : prepareDAGLevelOperands()`:
`
assert(InOperandVal.getValueType() ==
TLI.getPointerTy(DAG.getDataLayout()) &&
`
The function `getPointerTy()` has a parameter for addrspace which defaults to 0. So this assert always compares the operand's value type with the pointer of addrspace 0. In the case of AMDGPU, however, pointers of different addr spaces can have different types: 64-bit for addr spaces 0,1,4, and 32-bit for 2,3,5.
https://github.com/llvm/llvm-project/pull/195123
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