[llvm] [NewPM][AArch64] Port AArch64DAGToDAGISelLegacy to NewPM (PR #202739)

[Anshul Nigham via llvm-commits]

https://github.com/nigham created https://github.com/llvm/llvm-project/pull/202739

Adds `AArch64DAGToDAGISelPass`, the NewPM port for AArch64 instruction selection. Inherits from `SelectionDAGISelPass` and reuses its implementation, similar to X86 and AMDGPU ports and the Legacy pass implementation.

>From 488ee1deae56e1652c53b61a7efad9ebb79834aa Mon Sep 17 00:00:00 2001
From: Anshul Nigham <nigham at google.com>
Date: Tue, 9 Jun 2026 11:59:33 -0700
Subject: [PATCH] [NewPM][AArch64] Port AArch64DAGToDAGISelLegacy to NewPM

---
 llvm/lib/Target/AArch64/AArch64.h               | 7 +++++++
 llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 5 +++++
 llvm/lib/Target/AArch64/AArch64PassRegistry.def | 1 +
 3 files changed, 13 insertions(+)

diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h
index 9074e4e2eb672..a3660256ff4f9 100644
--- a/llvm/lib/Target/AArch64/AArch64.h
+++ b/llvm/lib/Target/AArch64/AArch64.h
@@ -18,6 +18,7 @@
 #include "Utils/AArch64BaseInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
+#include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/Pass.h"
 #include "llvm/PassRegistry.h"
 #include "llvm/Support/DataTypes.h"
@@ -264,6 +265,12 @@ class AArch64CompressJumpTablesPass
                         MachineFunctionAnalysisManager &MFAM);
 };
 
+// SelectionDAGISelPass is already a NewPM interface.
+class AArch64DAGToDAGISelPass : public SelectionDAGISelPass {
+public:
+  AArch64DAGToDAGISelPass(AArch64TargetMachine &TM);
+};
+
 class AArch64DeadRegisterDefinitionsPass
     : public OptionalPassInfoMixin<AArch64DeadRegisterDefinitionsPass> {
 public:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 43f97dd3b60e3..499bb2325186d 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -10,6 +10,7 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "AArch64.h"
 #include "AArch64MachineFunctionInfo.h"
 #include "AArch64TargetMachine.h"
 #include "MCTargetDesc/AArch64AddressingModes.h"
@@ -556,6 +557,10 @@ char AArch64DAGToDAGISelLegacy::ID = 0;
 
 INITIALIZE_PASS(AArch64DAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
 
+AArch64DAGToDAGISelPass::AArch64DAGToDAGISelPass(AArch64TargetMachine &TM)
+    : SelectionDAGISelPass(
+          std::make_unique<AArch64DAGToDAGISel>(TM, TM.getOptLevel())) {}
+
 /// addBitcastHints - This method adds bitcast hints to the operands of a node
 /// to help instruction selector determine which operands are in Neon registers.
 static SDValue addBitcastHints(SelectionDAG &DAG, SDNode &N) {
diff --git a/llvm/lib/Target/AArch64/AArch64PassRegistry.def b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
index 45eece036310e..6f9eb76930d18 100644
--- a/llvm/lib/Target/AArch64/AArch64PassRegistry.def
+++ b/llvm/lib/Target/AArch64/AArch64PassRegistry.def
@@ -36,6 +36,7 @@ MACHINE_FUNCTION_PASS("aarch64-copyelim", AArch64RedundantCopyEliminationPass())
 MACHINE_FUNCTION_PASS("aarch64-dead-defs", AArch64DeadRegisterDefinitionsPass())
 MACHINE_FUNCTION_PASS("aarch64-expand-pseudo", AArch64ExpandPseudoPass())
 MACHINE_FUNCTION_PASS("aarch64-fix-cortex-a53-835769", AArch64A53Fix835769Pass())
+MACHINE_FUNCTION_PASS("aarch64-isel", AArch64DAGToDAGISelPass(*this))
 MACHINE_FUNCTION_PASS("aarch64-jump-tables", AArch64CompressJumpTablesPass())
 MACHINE_FUNCTION_PASS("aarch64-ldst-opt", AArch64LoadStoreOptPass())
 MACHINE_FUNCTION_PASS("aarch64-mi-peephole-opt", AArch64MIPeepholeOptPass())