[llvm] [AMDGPU][GlobalIsel] Adding new reg bank rules for amdgcn_s_quadmask, amdgcn_s_wqm (PR #201898)

[Petar Avramovic via llvm-commits]

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@@ -1744,6 +1744,12 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
   addRulesForIOpcs({amdgcn_readlane}, StandardB)
       .Uni(B32, {{SgprB32}, {IntrId, VgprB32, SgprB32_ReadFirstLane}});
 
+  addRulesForIOpcs({amdgcn_s_quadmask, amdgcn_s_wqm}, StandardB)
+      .Uni(B32, {{SgprB32}, {IntrId, SgprB32}})
+      .Div(B32, {{Sgpr32ToVgprDst}, {IntrId, SgprB32_ReadFirstLane}})
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petar-avramovic wrote:

exactly. True divergent input should not really happen in practice, readfirstlane for inputs is more of a "input should always be uniform that can end up in vgpr for some reason" we just make sure we define intrinsic for that case as well in case it happens.

https://github.com/llvm/llvm-project/pull/201898