[llvm] e0d0d3d - [llvm][MC] Store RegSize using uint32_t instead of uint16_t. (#201886)
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Tue Jun 9 09:20:32 PDT 2026
Author: Chenguang Wang
Date: 2026-06-09T09:20:26-07:00
New Revision: e0d0d3db9dd47ab9649ebb356ce404b55a2e4a77
URL: https://github.com/llvm/llvm-project/commit/e0d0d3db9dd47ab9649ebb356ce404b55a2e4a77
DIFF: https://github.com/llvm/llvm-project/commit/e0d0d3db9dd47ab9649ebb356ce404b55a2e4a77.diff
LOG: [llvm][MC] Store RegSize using uint32_t instead of uint16_t. (#201886)
`uint32_t` is needed for working with registers with size >= 65535,
which is the case for a private ISA that I am currently working on. The
performance impact is negligible. See discussions in [LLVM
Discourse](https://discourse.llvm.org/t/rfc-support-reg-sizes-greater-than-65534/90970/2).
Added:
Modified:
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/include/llvm/MC/MCRegisterInfo.h
llvm/test/TableGen/ConcatenatedSubregs.td
llvm/test/TableGen/RegisterClassCopyCost.td
llvm/utils/TableGen/Common/CodeGenRegisters.cpp
llvm/utils/TableGen/Common/CodeGenRegisters.h
llvm/utils/TableGen/Common/InfoByHwMode.h
llvm/utils/TableGen/RegisterInfoEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 8ae24ff84401e..ecf027d97cc15 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -253,8 +253,8 @@ class LLVM_ABI TargetRegisterInfo : public MCRegisterInfo {
/// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
/// index, -1 in any being invalid.
struct SubRegCoveredBits {
- uint16_t Offset;
- uint16_t Size;
+ uint32_t Offset;
+ uint32_t Size;
};
private:
diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index 76ef62da3d35b..6e879ae108f0f 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -42,10 +42,10 @@ class MCRegisterClass {
const iterator RegsBegin;
const uint8_t *const RegSet;
const uint32_t NameIdx;
+ const uint32_t RegSizeInBits;
const uint16_t RegsSize;
const uint16_t RegSetSize;
const uint16_t ID;
- const uint16_t RegSizeInBits;
const uint8_t CopyCost;
const bool Allocatable;
const bool BaseClass;
diff --git a/llvm/test/TableGen/ConcatenatedSubregs.td b/llvm/test/TableGen/ConcatenatedSubregs.td
index d10c11ec42fbc..cd65e753f1849 100644
--- a/llvm/test/TableGen/ConcatenatedSubregs.td
+++ b/llvm/test/TableGen/ConcatenatedSubregs.td
@@ -98,11 +98,11 @@ def TestTarget : Target;
// Check inferred indexes:
// CHECK-LABEL: SubRegIndex ssub1_ssub2:
// CHECK: Offset: 16
-// CHECK: Size: 65535
+// CHECK: Size: 4294967295
// CHECK-LABEL: SubRegIndex ssub3_ssub4:
// CHECK-LABEL: SubRegIndex ssub0_ssub1_ssub2_ssub3:
-// CHECK: Offset: 65535
-// CHECK: Size: 65535
+// CHECK: Offset: 4294967295
+// CHECK: Size: 4294967295
// CHECK-LABEL: SubRegIndex ssub1_ssub2_ssub3_ssub4:
// Check that all subregs are generated on some examples
diff --git a/llvm/test/TableGen/RegisterClassCopyCost.td b/llvm/test/TableGen/RegisterClassCopyCost.td
index fc65fdb5fdbef..550a6c0a3955a 100644
--- a/llvm/test/TableGen/RegisterClassCopyCost.td
+++ b/llvm/test/TableGen/RegisterClassCopyCost.td
@@ -8,8 +8,8 @@
include "llvm/Target/Target.td"
// CHECK: extern const MCRegisterClass MyTargetMCRegisterClasses[] = {
-// CHECK-NEXT: { GPR32, GPR32Bits, 0, 2, sizeof(GPR32Bits), MyTarget::GPR32RegClassID, 32, 1, true, false },
-// CHECK-NEXT: { SPECIAL_CLASS, SPECIAL_CLASSBits, 6, 1, sizeof(SPECIAL_CLASSBits), MyTarget::SPECIAL_CLASSRegClassID, 32, 255, true, false },
+// CHECK-NEXT: { GPR32, GPR32Bits, 0, 32, 2, sizeof(GPR32Bits), MyTarget::GPR32RegClassID, 1, true, false },
+// CHECK-NEXT: { SPECIAL_CLASS, SPECIAL_CLASSBits, 6, 32, 1, sizeof(SPECIAL_CLASSBits), MyTarget::SPECIAL_CLASSRegClassID, 255, true, false },
// CHECK-NEXT: };
def MyTargetISA : InstrInfo;
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 506d9b2ee8d7c..eb6f07d761029 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -1381,7 +1381,7 @@ CodeGenSubRegIndex *CodeGenRegBank::getConcatSubRegIndex(
// None exists, synthesize one.
std::string Name = Parts.front()->getName();
- const unsigned UnknownSize = (uint16_t)-1;
+ const unsigned UnknownSize = (uint32_t)-1;
for (const CodeGenSubRegIndex *Part : ArrayRef(Parts).drop_front()) {
Name += '_';
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index 9a8c5aa25137c..077294783f8ae 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -124,8 +124,8 @@ class CodeGenSubRegIndex {
SubRegRange &ARange = A->Range.get(M);
SubRegRange &BRange = B->Range.get(M);
- if (Range.Offset != (uint16_t)-1 && ARange.Offset != (uint16_t)-1 &&
- BRange.Offset == (uint16_t)-1) {
+ if (Range.Offset != (uint32_t)-1 && ARange.Offset != (uint32_t)-1 &&
+ BRange.Offset == (uint32_t)-1) {
BRange.Offset = Range.Offset + ARange.Offset;
BRange.Size = ARange.Size;
}
@@ -135,8 +135,8 @@ class CodeGenSubRegIndex {
SubRegRange &Range = this->Range.get(DefaultMode);
SubRegRange &ARange = A->Range.get(DefaultMode);
SubRegRange &BRange = B->Range.get(DefaultMode);
- if (Range.Offset != (uint16_t)-1 && ARange.Offset != (uint16_t)-1 &&
- BRange.Offset == (uint16_t)-1) {
+ if (Range.Offset != (uint32_t)-1 && ARange.Offset != (uint32_t)-1 &&
+ BRange.Offset == (uint32_t)-1) {
BRange.Offset = Range.Offset + ARange.Offset;
BRange.Size = ARange.Size;
}
diff --git a/llvm/utils/TableGen/Common/InfoByHwMode.h b/llvm/utils/TableGen/Common/InfoByHwMode.h
index 2a2e5c23d3721..52549b0f60e7a 100644
--- a/llvm/utils/TableGen/Common/InfoByHwMode.h
+++ b/llvm/utils/TableGen/Common/InfoByHwMode.h
@@ -229,11 +229,11 @@ raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T);
raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T);
struct SubRegRange {
- uint16_t Size;
- uint16_t Offset;
+ uint32_t Size;
+ uint32_t Offset;
SubRegRange(const Record *R);
- SubRegRange(uint16_t Size, uint16_t Offset) : Size(Size), Offset(Offset) {}
+ SubRegRange(uint32_t Size, uint32_t Offset) : Size(Size), Offset(Offset) {}
};
struct SubRegRangeByHwMode : public InfoByHwMode<SubRegRange> {
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index fa845c24aa720..91baa79a70c33 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1122,10 +1122,10 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, raw_ostream &MainOS,
if (RC.RSI.isSimple())
RegSize = RC.RSI.getSimple().RegSize;
OS << " { " << RCName << ", " << RCBitsName << ", "
- << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size()
- << ", " << RCBitsSize << ", " << RC.getQualifiedIdName() << ", "
- << RegSize << ", " << static_cast<unsigned>(RC.CopyCost) << ", "
- << (RC.Allocatable ? "true" : "false") << ", "
+ << RegClassStrings.get(RC.getName()) << ", " << RegSize << ", "
+ << RC.getOrder().size() << ", " << RCBitsSize << ", "
+ << RC.getQualifiedIdName() << ", " << static_cast<unsigned>(RC.CopyCost)
+ << ", " << (RC.Allocatable ? "true" : "false") << ", "
<< (RC.getBaseClassOrder() ? "true" : "false") << " },\n";
}
@@ -1357,7 +1357,7 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, raw_ostream &MainOS,
OS << "static const TargetRegisterInfo::SubRegCoveredBits " << TargetName
<< "SubRegIdxRangeTable[] = {\n";
for (unsigned M = 0; M < NumModes; ++M) {
- OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n";
+ OS << " { " << (uint32_t)-1 << ", " << (uint32_t)-1 << " },\n";
for (const auto &Idx : SubRegIndices) {
const SubRegRange &Range = Idx.Range.get(M);
OS << " { " << Range.Offset << ", " << Range.Size << " },\t// "
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