[llvm] AMDGPU/GlobalISel: Implement RegBankLegalize rules for SALUFloat variants of G_INTRINSIC_TRUNC, G_FFLOOR and G_FCEIL. (PR #187679)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 9 08:03:38 PDT 2026
https://github.com/anjenner updated https://github.com/llvm/llvm-project/pull/187679
>From d8134dbdb759e9900718da6579313c12ced13a09 Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Fri, 20 Mar 2026 07:33:35 -0400
Subject: [PATCH 1/6] AMDGPU/GlobalISel: Add SALUFloat variants of
G_INTRINSIC_TRUNC, G_FFLOOR and G_FCEIL.
---
.../Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 41aa5802ad53d..87e1e125dd906 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1591,9 +1591,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{UniS1, _, S64}, {{UniInVcc}, {None, Vgpr64, Vgpr64}}})
.Any({{DivS1, _, S64}, {{Vcc}, {None, Vgpr64, Vgpr64}}});
- addRulesForGOpcs({G_INTRINSIC_TRUNC, G_INTRINSIC_ROUNDEVEN, G_FFLOOR, G_FCEIL,
- G_FEXP2, G_FLOG2},
- Standard)
+ addRulesForGOpcs({G_INTRINSIC_ROUNDEVEN, G_FEXP2, G_FLOG2}, Standard)
.Uni(S16, {{UniInVgprS16}, {Vgpr16}})
.Div(S16, {{Vgpr16}, {Vgpr16}})
.Uni(S32, {{UniInVgprS32}, {Vgpr32}})
@@ -1601,6 +1599,15 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S64, {{UniInVgprS64}, {Vgpr64}})
.Div(S64, {{Vgpr64}, {Vgpr64}});
+ addRulesForGOpcs({G_INTRINSIC_TRUNC, G_FFLOOR, G_FCEIL}, Standard)
+ .Uni(S16, {{UniInVgprS16}, {Vgpr16}})
+ .Div(S16, {{Vgpr16}, {Vgpr16}})
+ .Uni(S32, {{UniInVgprS32}, {Vgpr32}})
+ .Uni(S32, {{Sgpr32}, {Sgpr32}}, hasSALUFloat)
+ .Div(S32, {{Vgpr32}, {Vgpr32}})
+ .Uni(S64, {{UniInVgprS64}, {Vgpr64}})
+ .Div(S64, {{Vgpr64}, {Vgpr64}});
+
addRulesForGOpcs({G_AMDGPU_GLOBAL_LOAD_MONITOR, G_AMDGPU_FLAT_LOAD_MONITOR},
StandardB)
.Uni(B32, {{UniInVgprB32}, {SgprPtr64}})
>From 05f0bb0c098cc1e6eb6a05bbf10759b348b40315 Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Tue, 28 Apr 2026 12:52:07 -0400
Subject: [PATCH 2/6] Add testcases.
---
.../AMDGPU/GlobalISel/regbankselect-fceil.mir | 35 ++++++++++++-------
.../GlobalISel/regbankselect-ffloor.mir | 35 ++++++++++++-------
.../regbankselect-intrinsic-trunc.mir | 35 ++++++++++++-------
3 files changed, 69 insertions(+), 36 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
index 920eb0f9d5df3..26d97a5ad8bb3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=FIJI %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=GFX12 %s
---
name: fceil_s
@@ -8,12 +9,17 @@ legalized: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: fceil_s
- ; CHECK: liveins: $sgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY1]]
+ ; FIJI-LABEL: name: fceil_s
+ ; FIJI: liveins: $sgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY1]]
+ ; GFX12-LABEL: name: fceil_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:sgpr(s32) = G_FCEIL [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_FCEIL %0
...
@@ -25,11 +31,16 @@ legalized: true
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: fceil_v
- ; CHECK: liveins: $vgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
+ ; FIJI-LABEL: name: fceil_v
+ ; FIJI: liveins: $vgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
+ ; GFX12-LABEL: name: fceil_v
+ ; GFX12: liveins: $vgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FCEIL %0
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
index bff455e7b2a85..da2ec94089a30 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=FIJI %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=GFX12 %s
---
name: ffloor_s
@@ -8,12 +9,17 @@ legalized: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: ffloor_s
- ; CHECK: liveins: $sgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY1]]
+ ; FIJI-LABEL: name: ffloor_s
+ ; FIJI: liveins: $sgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY1]]
+ ; GFX12-LABEL: name: ffloor_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:sgpr(s32) = G_FFLOOR [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_FFLOOR %0
...
@@ -25,11 +31,16 @@ legalized: true
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: ffloor_v
- ; CHECK: liveins: $vgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY]]
+ ; FIJI-LABEL: name: ffloor_v
+ ; FIJI: liveins: $vgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY]]
+ ; GFX12-LABEL: name: ffloor_v
+ ; GFX12: liveins: $vgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FFLOOR %0
...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
index 6318297cc1133..4923665919340 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=FIJI %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=GFX12 %s
---
name: intrinsic_trunc_s
@@ -8,12 +9,17 @@ legalized: true
body: |
bb.0:
liveins: $sgpr0
- ; CHECK-LABEL: name: intrinsic_trunc_s
- ; CHECK: liveins: $sgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; CHECK-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY1]]
+ ; FIJI-LABEL: name: intrinsic_trunc_s
+ ; FIJI: liveins: $sgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY1]]
+ ; GFX12-LABEL: name: intrinsic_trunc_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_INTRINSIC_TRUNC %0
...
@@ -25,11 +31,16 @@ legalized: true
body: |
bb.0:
liveins: $vgpr0
- ; CHECK-LABEL: name: intrinsic_trunc_v
- ; CHECK: liveins: $vgpr0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; FIJI-LABEL: name: intrinsic_trunc_v
+ ; FIJI: liveins: $vgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX12-LABEL: name: intrinsic_trunc_v
+ ; GFX12: liveins: $vgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_INTRINSIC_TRUNC %0
...
>From b5179c3bda80aed4938a6e62049cf7fca409a201 Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Wed, 29 Apr 2026 09:15:17 -0400
Subject: [PATCH 3/6] Handle s16 SALUFloat variants. Add tests for s16 and s64,
uniform and divergent.
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 1 +
.../AMDGPU/GlobalISel/regbankselect-fceil.mir | 93 +++++++++++++++++++
.../GlobalISel/regbankselect-ffloor.mir | 93 +++++++++++++++++++
.../regbankselect-intrinsic-trunc.mir | 93 +++++++++++++++++++
4 files changed, 280 insertions(+)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 87e1e125dd906..ec7b3e5c79583 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1601,6 +1601,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForGOpcs({G_INTRINSIC_TRUNC, G_FFLOOR, G_FCEIL}, Standard)
.Uni(S16, {{UniInVgprS16}, {Vgpr16}})
+ .Uni(S16, {{Sgpr16}, {Sgpr16}}, hasSALUFloat)
.Div(S16, {{Vgpr16}, {Vgpr16}})
.Uni(S32, {{UniInVgprS32}, {Vgpr32}})
.Uni(S32, {{Sgpr32}, {Sgpr32}}, hasSALUFloat)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
index 26d97a5ad8bb3..12617e6873b98 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
@@ -44,3 +44,96 @@ body: |
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FCEIL %0
...
+
+---
+name: fceil_s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; FIJI-LABEL: name: fceil_s16_s
+ ; FIJI: liveins: $sgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
+ ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s16) = G_FCEIL [[COPY1]]
+ ; GFX12-LABEL: name: fceil_s16_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:sgpr(s16) = G_FCEIL [[TRUNC]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_FCEIL %1
+...
+
+---
+name: fceil_s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; FIJI-LABEL: name: fceil_s16_v
+ ; FIJI: liveins: $vgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s16) = G_FCEIL [[TRUNC]]
+ ; GFX12-LABEL: name: fceil_s16_v
+ ; GFX12: liveins: $vgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s16) = G_FCEIL [[TRUNC]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_FCEIL %1
+...
+
+---
+name: fceil_s64_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; FIJI-LABEL: name: fceil_s64_s
+ ; FIJI: liveins: $sgpr0_sgpr1
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s64) = G_FCEIL [[COPY1]]
+ ; GFX12-LABEL: name: fceil_s64_s
+ ; GFX12: liveins: $sgpr0_sgpr1
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s64) = G_FCEIL [[COPY1]]
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s64) = G_FCEIL %0
+...
+
+---
+name: fceil_s64_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; FIJI-LABEL: name: fceil_s64_v
+ ; FIJI: liveins: $vgpr0_vgpr1
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s64) = G_FCEIL [[COPY]]
+ ; GFX12-LABEL: name: fceil_s64_v
+ ; GFX12: liveins: $vgpr0_vgpr1
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s64) = G_FCEIL [[COPY]]
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_FCEIL %0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
index da2ec94089a30..f89727648aafc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
@@ -44,3 +44,96 @@ body: |
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FFLOOR %0
...
+
+---
+name: ffloor_s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; FIJI-LABEL: name: ffloor_s16_s
+ ; FIJI: liveins: $sgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
+ ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[COPY1]]
+ ; GFX12-LABEL: name: ffloor_s16_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:sgpr(s16) = G_FFLOOR [[TRUNC]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_FFLOOR %1
+...
+
+---
+name: ffloor_s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; FIJI-LABEL: name: ffloor_s16_v
+ ; FIJI: liveins: $vgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[TRUNC]]
+ ; GFX12-LABEL: name: ffloor_s16_v
+ ; GFX12: liveins: $vgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[TRUNC]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_FFLOOR %1
+...
+
+---
+name: ffloor_s64_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; FIJI-LABEL: name: ffloor_s64_s
+ ; FIJI: liveins: $sgpr0_sgpr1
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s64) = G_FFLOOR [[COPY1]]
+ ; GFX12-LABEL: name: ffloor_s64_s
+ ; GFX12: liveins: $sgpr0_sgpr1
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s64) = G_FFLOOR [[COPY1]]
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s64) = G_FFLOOR %0
+...
+
+---
+name: ffloor_s64_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; FIJI-LABEL: name: ffloor_s64_v
+ ; FIJI: liveins: $vgpr0_vgpr1
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s64) = G_FFLOOR [[COPY]]
+ ; GFX12-LABEL: name: ffloor_s64_v
+ ; GFX12: liveins: $vgpr0_vgpr1
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s64) = G_FFLOOR [[COPY]]
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_FFLOOR %0
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
index 4923665919340..1f878bd44f6ad 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
@@ -44,3 +44,96 @@ body: |
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_INTRINSIC_TRUNC %0
...
+
+---
+name: intrinsic_trunc_s16_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0
+ ; FIJI-LABEL: name: intrinsic_trunc_s16_s
+ ; FIJI: liveins: $sgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
+ ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s16) = G_INTRINSIC_TRUNC [[COPY1]]
+ ; GFX12-LABEL: name: intrinsic_trunc_s16_s
+ ; GFX12: liveins: $sgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:sgpr(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ %0:_(s32) = COPY $sgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_INTRINSIC_TRUNC %1
+...
+
+---
+name: intrinsic_trunc_s16_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0
+ ; FIJI-LABEL: name: intrinsic_trunc_s16_v
+ ; FIJI: liveins: $vgpr0
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ ; GFX12-LABEL: name: intrinsic_trunc_s16_v
+ ; GFX12: liveins: $vgpr0
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
+ ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
+ %0:_(s32) = COPY $vgpr0
+ %1:_(s16) = G_TRUNC %0
+ %2:_(s16) = G_INTRINSIC_TRUNC %1
+...
+
+---
+name: intrinsic_trunc_s64_s
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $sgpr0_sgpr1
+ ; FIJI-LABEL: name: intrinsic_trunc_s64_s
+ ; FIJI: liveins: $sgpr0_sgpr1
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s64) = G_INTRINSIC_TRUNC [[COPY1]]
+ ; GFX12-LABEL: name: intrinsic_trunc_s64_s
+ ; GFX12: liveins: $sgpr0_sgpr1
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
+ ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
+ ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s64) = G_INTRINSIC_TRUNC [[COPY1]]
+ %0:_(s64) = COPY $sgpr0_sgpr1
+ %1:_(s64) = G_INTRINSIC_TRUNC %0
+...
+
+---
+name: intrinsic_trunc_s64_v
+legalized: true
+
+body: |
+ bb.0:
+ liveins: $vgpr0_vgpr1
+ ; FIJI-LABEL: name: intrinsic_trunc_s64_v
+ ; FIJI: liveins: $vgpr0_vgpr1
+ ; FIJI-NEXT: {{ $}}
+ ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s64) = G_INTRINSIC_TRUNC [[COPY]]
+ ; GFX12-LABEL: name: intrinsic_trunc_s64_v
+ ; GFX12: liveins: $vgpr0_vgpr1
+ ; GFX12-NEXT: {{ $}}
+ ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
+ ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s64) = G_INTRINSIC_TRUNC [[COPY]]
+ %0:_(s64) = COPY $vgpr0_vgpr1
+ %1:_(s64) = G_INTRINSIC_TRUNC %0
+...
>From 2efe20cfccb79d00cb65f310605c12c98ebc18f9 Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Tue, 19 May 2026 08:11:10 -0400
Subject: [PATCH 4/6] Make new tests end-to-end IR tests instead of MIR tests.
---
llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll | 113 +++++++++++++++
llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll | 113 +++++++++++++++
.../AMDGPU/GlobalISel/intrinsic-trunc.ll | 113 +++++++++++++++
.../AMDGPU/GlobalISel/regbankselect-fceil.mir | 128 ++---------------
.../GlobalISel/regbankselect-ffloor.mir | 128 ++---------------
.../regbankselect-intrinsic-trunc.mir | 128 ++---------------
llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll | 132 +++++-------------
7 files changed, 411 insertions(+), 444 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
new file mode 100644
index 0000000000000..4a17444ca1add
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
@@ -0,0 +1,113 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=fiji -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=FIJI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX12 %s
+
+define float @fceil_s(float inreg %val) {
+; FIJI-LABEL: fceil_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_ceil_f32_e32 v0, s16
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fceil_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_ceil_f32 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call float @llvm.ceil.f32(float %val)
+ ret float %result
+}
+
+define float @fceil_v(float %val) {
+; FIJI-LABEL: fceil_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_ceil_f32_e32 v0, v0
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fceil_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_ceil_f32_e32 v0, v0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call float @llvm.ceil.f32(float %val)
+ ret float %result
+}
+
+define half @fceil_s16_s(half inreg %val) {
+; FIJI-LABEL: fceil_s16_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_ceil_f16_e32 v0, s16
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fceil_s16_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_ceil_f16 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call half @llvm.ceil.f16(half %val)
+ ret half %result
+}
+
+define half @fceil_s16_v(half %val) {
+; FIJI-LABEL: fceil_s16_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_ceil_f16_e32 v0, v0
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fceil_s16_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_ceil_f16_e32 v0.l, v0.l
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call half @llvm.ceil.f16(half %val)
+ ret half %result
+}
+
+define double @fceil_s64_v(double %val) {
+; FIJI-LABEL: fceil_s64_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_ceil_f64_e32 v[0:1], v[0:1]
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fceil_s64_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_ceil_f64_e32 v[0:1], v[0:1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call double @llvm.ceil.f64(double %val)
+ ret double %result
+}
+
+declare float @llvm.ceil.f32(float)
+declare half @llvm.ceil.f16(half)
+declare double @llvm.ceil.f64(double)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
new file mode 100644
index 0000000000000..7e31e2ea1df81
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
@@ -0,0 +1,113 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=fiji -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=FIJI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX12 %s
+
+define float @ffloor_s(float inreg %val) {
+; FIJI-LABEL: ffloor_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_floor_f32_e32 v0, s16
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: ffloor_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_floor_f32 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call float @llvm.floor.f32(float %val)
+ ret float %result
+}
+
+define float @ffloor_v(float %val) {
+; FIJI-LABEL: ffloor_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_floor_f32_e32 v0, v0
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: ffloor_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_floor_f32_e32 v0, v0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call float @llvm.floor.f32(float %val)
+ ret float %result
+}
+
+define half @ffloor_s16_s(half inreg %val) {
+; FIJI-LABEL: ffloor_s16_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_floor_f16_e32 v0, s16
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: ffloor_s16_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_floor_f16 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call half @llvm.floor.f16(half %val)
+ ret half %result
+}
+
+define half @ffloor_s16_v(half %val) {
+; FIJI-LABEL: ffloor_s16_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_floor_f16_e32 v0, v0
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: ffloor_s16_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_floor_f16_e32 v0.l, v0.l
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call half @llvm.floor.f16(half %val)
+ ret half %result
+}
+
+define double @ffloor_s64_v(double %val) {
+; FIJI-LABEL: ffloor_s64_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_floor_f64_e32 v[0:1], v[0:1]
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: ffloor_s64_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_floor_f64_e32 v[0:1], v[0:1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call double @llvm.floor.f64(double %val)
+ ret double %result
+}
+
+declare float @llvm.floor.f32(float)
+declare half @llvm.floor.f16(half)
+declare double @llvm.floor.f64(double)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
new file mode 100644
index 0000000000000..b8fb5131f7888
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
@@ -0,0 +1,113 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=fiji -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=FIJI %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefix=GFX12 %s
+
+define float @intrinsic_trunc_s(float inreg %val) {
+; FIJI-LABEL: intrinsic_trunc_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_trunc_f32_e32 v0, s16
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: intrinsic_trunc_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_trunc_f32 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call float @llvm.trunc.f32(float %val)
+ ret float %result
+}
+
+define float @intrinsic_trunc_v(float %val) {
+; FIJI-LABEL: intrinsic_trunc_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_trunc_f32_e32 v0, v0
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: intrinsic_trunc_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_trunc_f32_e32 v0, v0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call float @llvm.trunc.f32(float %val)
+ ret float %result
+}
+
+define half @intrinsic_trunc_s16_s(half inreg %val) {
+; FIJI-LABEL: intrinsic_trunc_s16_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_trunc_f16_e32 v0, s16
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: intrinsic_trunc_s16_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_trunc_f16 s0, s0
+; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
+; GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call half @llvm.trunc.f16(half %val)
+ ret half %result
+}
+
+define half @intrinsic_trunc_s16_v(half %val) {
+; FIJI-LABEL: intrinsic_trunc_s16_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_trunc_f16_e32 v0, v0
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: intrinsic_trunc_s16_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_trunc_f16_e32 v0.l, v0.l
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call half @llvm.trunc.f16(half %val)
+ ret half %result
+}
+
+define double @intrinsic_trunc_s64_v(double %val) {
+; FIJI-LABEL: intrinsic_trunc_s64_v:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: intrinsic_trunc_s64_v:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_trunc_f64_e32 v[0:1], v[0:1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call double @llvm.trunc.f64(double %val)
+ ret double %result
+}
+
+declare float @llvm.trunc.f32(float)
+declare half @llvm.trunc.f16(half)
+declare double @llvm.trunc.f64(double)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
index 12617e6873b98..920eb0f9d5df3 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=FIJI %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=GFX12 %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: fceil_s
@@ -9,17 +8,12 @@ legalized: true
body: |
bb.0:
liveins: $sgpr0
- ; FIJI-LABEL: name: fceil_s
- ; FIJI: liveins: $sgpr0
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY1]]
- ; GFX12-LABEL: name: fceil_s
- ; GFX12: liveins: $sgpr0
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:sgpr(s32) = G_FCEIL [[COPY]]
+ ; CHECK-LABEL: name: fceil_s
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_FCEIL %0
...
@@ -31,109 +25,11 @@ legalized: true
body: |
bb.0:
liveins: $vgpr0
- ; FIJI-LABEL: name: fceil_v
- ; FIJI: liveins: $vgpr0
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
- ; GFX12-LABEL: name: fceil_v
- ; GFX12: liveins: $vgpr0
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
+ ; CHECK-LABEL: name: fceil_v
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s32) = G_FCEIL [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FCEIL %0
...
-
----
-name: fceil_s16_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0
- ; FIJI-LABEL: name: fceil_s16_s
- ; FIJI: liveins: $sgpr0
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
- ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s16) = G_FCEIL [[COPY1]]
- ; GFX12-LABEL: name: fceil_s16_s
- ; GFX12: liveins: $sgpr0
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:sgpr(s16) = G_FCEIL [[TRUNC]]
- %0:_(s32) = COPY $sgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_FCEIL %1
-...
-
----
-name: fceil_s16_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0
- ; FIJI-LABEL: name: fceil_s16_v
- ; FIJI: liveins: $vgpr0
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s16) = G_FCEIL [[TRUNC]]
- ; GFX12-LABEL: name: fceil_s16_v
- ; GFX12: liveins: $vgpr0
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s16) = G_FCEIL [[TRUNC]]
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_FCEIL %1
-...
-
----
-name: fceil_s64_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1
- ; FIJI-LABEL: name: fceil_s64_s
- ; FIJI: liveins: $sgpr0_sgpr1
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
- ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s64) = G_FCEIL [[COPY1]]
- ; GFX12-LABEL: name: fceil_s64_s
- ; GFX12: liveins: $sgpr0_sgpr1
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
- ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s64) = G_FCEIL [[COPY1]]
- %0:_(s64) = COPY $sgpr0_sgpr1
- %1:_(s64) = G_FCEIL %0
-...
-
----
-name: fceil_s64_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
- ; FIJI-LABEL: name: fceil_s64_v
- ; FIJI: liveins: $vgpr0_vgpr1
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
- ; FIJI-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s64) = G_FCEIL [[COPY]]
- ; GFX12-LABEL: name: fceil_s64_v
- ; GFX12: liveins: $vgpr0_vgpr1
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
- ; GFX12-NEXT: [[FCEIL:%[0-9]+]]:vgpr(s64) = G_FCEIL [[COPY]]
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_FCEIL %0
-...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
index f89727648aafc..bff455e7b2a85 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ffloor.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=FIJI %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=GFX12 %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: ffloor_s
@@ -9,17 +8,12 @@ legalized: true
body: |
bb.0:
liveins: $sgpr0
- ; FIJI-LABEL: name: ffloor_s
- ; FIJI: liveins: $sgpr0
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY1]]
- ; GFX12-LABEL: name: ffloor_s
- ; GFX12: liveins: $sgpr0
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:sgpr(s32) = G_FFLOOR [[COPY]]
+ ; CHECK-LABEL: name: ffloor_s
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_FFLOOR %0
...
@@ -31,109 +25,11 @@ legalized: true
body: |
bb.0:
liveins: $vgpr0
- ; FIJI-LABEL: name: ffloor_v
- ; FIJI: liveins: $vgpr0
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY]]
- ; GFX12-LABEL: name: ffloor_v
- ; GFX12: liveins: $vgpr0
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY]]
+ ; CHECK-LABEL: name: ffloor_v
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s32) = G_FFLOOR [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FFLOOR %0
...
-
----
-name: ffloor_s16_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0
- ; FIJI-LABEL: name: ffloor_s16_s
- ; FIJI: liveins: $sgpr0
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
- ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[COPY1]]
- ; GFX12-LABEL: name: ffloor_s16_s
- ; GFX12: liveins: $sgpr0
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:sgpr(s16) = G_FFLOOR [[TRUNC]]
- %0:_(s32) = COPY $sgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_FFLOOR %1
-...
-
----
-name: ffloor_s16_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0
- ; FIJI-LABEL: name: ffloor_s16_v
- ; FIJI: liveins: $vgpr0
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[TRUNC]]
- ; GFX12-LABEL: name: ffloor_s16_v
- ; GFX12: liveins: $vgpr0
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s16) = G_FFLOOR [[TRUNC]]
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_FFLOOR %1
-...
-
----
-name: ffloor_s64_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1
- ; FIJI-LABEL: name: ffloor_s64_s
- ; FIJI: liveins: $sgpr0_sgpr1
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
- ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s64) = G_FFLOOR [[COPY1]]
- ; GFX12-LABEL: name: ffloor_s64_s
- ; GFX12: liveins: $sgpr0_sgpr1
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
- ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s64) = G_FFLOOR [[COPY1]]
- %0:_(s64) = COPY $sgpr0_sgpr1
- %1:_(s64) = G_FFLOOR %0
-...
-
----
-name: ffloor_s64_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
- ; FIJI-LABEL: name: ffloor_s64_v
- ; FIJI: liveins: $vgpr0_vgpr1
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
- ; FIJI-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s64) = G_FFLOOR [[COPY]]
- ; GFX12-LABEL: name: ffloor_s64_v
- ; GFX12: liveins: $vgpr0_vgpr1
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
- ; GFX12-NEXT: [[FFLOOR:%[0-9]+]]:vgpr(s64) = G_FFLOOR [[COPY]]
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_FFLOOR %0
-...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
index 1f878bd44f6ad..6318297cc1133 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
@@ -1,6 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=FIJI %s
-# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck -check-prefix=GFX12 %s
+# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - | FileCheck %s
---
name: intrinsic_trunc_s
@@ -9,17 +8,12 @@ legalized: true
body: |
bb.0:
liveins: $sgpr0
- ; FIJI-LABEL: name: intrinsic_trunc_s
- ; FIJI: liveins: $sgpr0
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
- ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY1]]
- ; GFX12-LABEL: name: intrinsic_trunc_s
- ; GFX12: liveins: $sgpr0
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:sgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; CHECK-LABEL: name: intrinsic_trunc_s
+ ; CHECK: liveins: $sgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
+ ; CHECK-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_INTRINSIC_TRUNC %0
...
@@ -31,109 +25,11 @@ legalized: true
body: |
bb.0:
liveins: $vgpr0
- ; FIJI-LABEL: name: intrinsic_trunc_v
- ; FIJI: liveins: $vgpr0
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
- ; GFX12-LABEL: name: intrinsic_trunc_v
- ; GFX12: liveins: $vgpr0
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
+ ; CHECK-LABEL: name: intrinsic_trunc_v
+ ; CHECK: liveins: $vgpr0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; CHECK-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s32) = G_INTRINSIC_TRUNC [[COPY]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_INTRINSIC_TRUNC %0
...
-
----
-name: intrinsic_trunc_s16_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0
- ; FIJI-LABEL: name: intrinsic_trunc_s16_s
- ; FIJI: liveins: $sgpr0
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[TRUNC]](s16)
- ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s16) = G_INTRINSIC_TRUNC [[COPY1]]
- ; GFX12-LABEL: name: intrinsic_trunc_s16_s
- ; GFX12: liveins: $sgpr0
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
- ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:sgpr(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- %0:_(s32) = COPY $sgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_INTRINSIC_TRUNC %1
-...
-
----
-name: intrinsic_trunc_s16_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0
- ; FIJI-LABEL: name: intrinsic_trunc_s16_v
- ; FIJI: liveins: $vgpr0
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; FIJI-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- ; GFX12-LABEL: name: intrinsic_trunc_s16_v
- ; GFX12: liveins: $vgpr0
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
- ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s16) = G_INTRINSIC_TRUNC [[TRUNC]]
- %0:_(s32) = COPY $vgpr0
- %1:_(s16) = G_TRUNC %0
- %2:_(s16) = G_INTRINSIC_TRUNC %1
-...
-
----
-name: intrinsic_trunc_s64_s
-legalized: true
-
-body: |
- bb.0:
- liveins: $sgpr0_sgpr1
- ; FIJI-LABEL: name: intrinsic_trunc_s64_s
- ; FIJI: liveins: $sgpr0_sgpr1
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; FIJI-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
- ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s64) = G_INTRINSIC_TRUNC [[COPY1]]
- ; GFX12-LABEL: name: intrinsic_trunc_s64_s
- ; GFX12: liveins: $sgpr0_sgpr1
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
- ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)
- ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s64) = G_INTRINSIC_TRUNC [[COPY1]]
- %0:_(s64) = COPY $sgpr0_sgpr1
- %1:_(s64) = G_INTRINSIC_TRUNC %0
-...
-
----
-name: intrinsic_trunc_s64_v
-legalized: true
-
-body: |
- bb.0:
- liveins: $vgpr0_vgpr1
- ; FIJI-LABEL: name: intrinsic_trunc_s64_v
- ; FIJI: liveins: $vgpr0_vgpr1
- ; FIJI-NEXT: {{ $}}
- ; FIJI-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
- ; FIJI-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s64) = G_INTRINSIC_TRUNC [[COPY]]
- ; GFX12-LABEL: name: intrinsic_trunc_s64_v
- ; GFX12: liveins: $vgpr0_vgpr1
- ; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
- ; GFX12-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:vgpr(s64) = G_INTRINSIC_TRUNC [[COPY]]
- %0:_(s64) = COPY $vgpr0_vgpr1
- %1:_(s64) = G_INTRINSIC_TRUNC %0
-...
diff --git a/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll b/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
index 76d58e0e46dd1..ea1cf34010607 100644
--- a/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
+++ b/llvm/test/CodeGen/AMDGPU/scalar-float-sop1.ll
@@ -97,64 +97,34 @@ define amdgpu_vs half @fptrunc_f32_to_f16(float inreg %val) {
}
define amdgpu_vs float @fceil_f32(float inreg %val) {
-; SDAG-LABEL: fceil_f32:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_ceil_f32 s0, s0
-; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; SDAG-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX11-LABEL: fceil_f32:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_ceil_f32_e32 v0, s0
-; GISEL-GFX11-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX12-LABEL: fceil_f32:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: v_ceil_f32_e32 v0, s0
-; GISEL-GFX12-NEXT: ; return to shader part epilog
+; CHECK-LABEL: fceil_f32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_ceil_f32 s0, s0
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: ; return to shader part epilog
%res = call float @llvm.ceil.f32(float %val)
ret float %res
}
define amdgpu_vs float @ffloor_f32(float inreg %val) {
-; SDAG-LABEL: ffloor_f32:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_floor_f32 s0, s0
-; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; SDAG-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX11-LABEL: ffloor_f32:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_floor_f32_e32 v0, s0
-; GISEL-GFX11-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX12-LABEL: ffloor_f32:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: v_floor_f32_e32 v0, s0
-; GISEL-GFX12-NEXT: ; return to shader part epilog
+; CHECK-LABEL: ffloor_f32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_floor_f32 s0, s0
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: ; return to shader part epilog
%res = call float @llvm.floor.f32(float %val)
ret float %res
}
define amdgpu_vs float @ftrunc_f32(float inreg %val) {
-; SDAG-LABEL: ftrunc_f32:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_trunc_f32 s0, s0
-; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; SDAG-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX11-LABEL: ftrunc_f32:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_trunc_f32_e32 v0, s0
-; GISEL-GFX11-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX12-LABEL: ftrunc_f32:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: v_trunc_f32_e32 v0, s0
-; GISEL-GFX12-NEXT: ; return to shader part epilog
+; CHECK-LABEL: ftrunc_f32:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_trunc_f32 s0, s0
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: ; return to shader part epilog
%res = call float @llvm.trunc.f32(float %val)
ret float %res
}
@@ -181,64 +151,34 @@ define amdgpu_vs float @frint_f32(float inreg %val) {
}
define amdgpu_vs half @fceil_f16(half inreg %val) {
-; SDAG-LABEL: fceil_f16:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_ceil_f16 s0, s0
-; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; SDAG-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX11-LABEL: fceil_f16:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_ceil_f16_e32 v0.l, s0
-; GISEL-GFX11-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX12-LABEL: fceil_f16:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: v_ceil_f16_e32 v0.l, s0
-; GISEL-GFX12-NEXT: ; return to shader part epilog
+; CHECK-LABEL: fceil_f16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_ceil_f16 s0, s0
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: ; return to shader part epilog
%res = call half @llvm.ceil.f16(half %val)
ret half %res
}
define amdgpu_vs half @ffloor_f16(half inreg %val) {
-; SDAG-LABEL: ffloor_f16:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_floor_f16 s0, s0
-; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; SDAG-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX11-LABEL: ffloor_f16:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_floor_f16_e32 v0.l, s0
-; GISEL-GFX11-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX12-LABEL: ffloor_f16:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: v_floor_f16_e32 v0.l, s0
-; GISEL-GFX12-NEXT: ; return to shader part epilog
+; CHECK-LABEL: ffloor_f16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_floor_f16 s0, s0
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: ; return to shader part epilog
%res = call half @llvm.floor.f16(half %val)
ret half %res
}
define amdgpu_vs half @ftrunc_f16(half inreg %val) {
-; SDAG-LABEL: ftrunc_f16:
-; SDAG: ; %bb.0:
-; SDAG-NEXT: s_trunc_f16 s0, s0
-; SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; SDAG-NEXT: v_mov_b32_e32 v0, s0
-; SDAG-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX11-LABEL: ftrunc_f16:
-; GISEL-GFX11: ; %bb.0:
-; GISEL-GFX11-NEXT: v_trunc_f16_e32 v0.l, s0
-; GISEL-GFX11-NEXT: ; return to shader part epilog
-;
-; GISEL-GFX12-LABEL: ftrunc_f16:
-; GISEL-GFX12: ; %bb.0:
-; GISEL-GFX12-NEXT: v_trunc_f16_e32 v0.l, s0
-; GISEL-GFX12-NEXT: ; return to shader part epilog
+; CHECK-LABEL: ftrunc_f16:
+; CHECK: ; %bb.0:
+; CHECK-NEXT: s_trunc_f16 s0, s0
+; CHECK-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; CHECK-NEXT: v_mov_b32_e32 v0, s0
+; CHECK-NEXT: ; return to shader part epilog
%res = call half @llvm.trunc.f16(half %val)
ret half %res
}
>From 13ed6593ed0250d82909308347459d37b6d8abaa Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Tue, 9 Jun 2026 08:29:46 -0400
Subject: [PATCH 5/6] Add s64 testcases.
---
llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll | 21 +++++++++++++++++++
llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll | 20 ++++++++++++++++++
.../AMDGPU/GlobalISel/intrinsic-trunc.ll | 20 ++++++++++++++++++
3 files changed, 61 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
index 4a17444ca1add..f040d702df605 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fceil.ll
@@ -108,6 +108,27 @@ define double @fceil_s64_v(double %val) {
ret double %result
}
+
+define double @fceil_s64_s(double inreg %val) {
+; FIJI-LABEL: fceil_s64_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_ceil_f64_e32 v[0:1], s[16:17]
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: fceil_s64_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_ceil_f64_e32 v[0:1], s[0:1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call double @llvm.ceil.f64(double %val)
+ ret double %result
+}
+
declare float @llvm.ceil.f32(float)
declare half @llvm.ceil.f16(half)
declare double @llvm.ceil.f64(double)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
index 7e31e2ea1df81..382c3eb9f54c5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ffloor.ll
@@ -108,6 +108,26 @@ define double @ffloor_s64_v(double %val) {
ret double %result
}
+define double @ffloor_s64_s(double inreg %val) {
+; FIJI-LABEL: ffloor_s64_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_floor_f64_e32 v[0:1], s[16:17]
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: ffloor_s64_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_floor_f64_e32 v[0:1], s[0:1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call double @llvm.floor.f64(double %val)
+ ret double %result
+}
+
declare float @llvm.floor.f32(float)
declare half @llvm.floor.f16(half)
declare double @llvm.floor.f64(double)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
index b8fb5131f7888..53e2fb384410c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/intrinsic-trunc.ll
@@ -108,6 +108,26 @@ define double @intrinsic_trunc_s64_v(double %val) {
ret double %result
}
+define double @intrinsic_trunc_s64_s(double inreg %val) {
+; FIJI-LABEL: intrinsic_trunc_s64_s:
+; FIJI: ; %bb.0:
+; FIJI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; FIJI-NEXT: v_trunc_f64_e32 v[0:1], s[16:17]
+; FIJI-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX12-LABEL: intrinsic_trunc_s64_s:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX12-NEXT: s_wait_expcnt 0x0
+; GFX12-NEXT: s_wait_samplecnt 0x0
+; GFX12-NEXT: s_wait_bvhcnt 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_trunc_f64_e32 v[0:1], s[0:1]
+; GFX12-NEXT: s_setpc_b64 s[30:31]
+ %result = call double @llvm.trunc.f64(double %val)
+ ret double %result
+}
+
declare float @llvm.trunc.f32(float)
declare half @llvm.trunc.f16(half)
declare double @llvm.trunc.f64(double)
>From b6c2e8986b45a117b3791046886a4148b1db8175 Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Tue, 9 Jun 2026 11:10:39 -0400
Subject: [PATCH 6/6] Regenerate test assertions now that floor/trunc
operations can be done on SALU.
---
llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll | 10 +++++-----
llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll | 8 ++++----
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
index 12e7211355080..92cad3f0f4bf3 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-scalar.ll
@@ -838,21 +838,21 @@ define i64 @test_s_signed_i64_f32(float inreg %f) nounwind {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: v_trunc_f32_e32 v0, s0
+; GFX12-GI-NEXT: s_trunc_f32 s1, s0
; GFX12-GI-NEXT: s_mov_b32 s6, 0
; GFX12-GI-NEXT: s_brev_b32 s7, 1
-; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_bitset0_b32 s1, 31
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_mul_f32 s2, s1, 0x2f800000
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: v_floor_f32_e32 v0, s2
+; GFX12-GI-NEXT: s_floor_f32 s3, s2
; GFX12-GI-NEXT: s_ashr_i32 s2, s0, 31
-; GFX12-GI-NEXT: v_readfirstlane_b32 s3, v0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_fmac_f32 s1, s3, 0xcf800000
; GFX12-GI-NEXT: s_cvt_u32_f32 s5, s3
-; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_mov_b32 s3, s2
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_cvt_u32_f32 s4, s1
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_xor_b64 s[4:5], s[4:5], s[2:3]
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
index b064ce6cec7a8..2b02c54f780ac 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-scalar.ll
@@ -575,13 +575,13 @@ define i64 @test_s_unsigned_i64_f32(float inreg %f) nounwind {
; GFX12-GI-NEXT: s_wait_samplecnt 0x0
; GFX12-GI-NEXT: s_wait_bvhcnt 0x0
; GFX12-GI-NEXT: s_wait_kmcnt 0x0
-; GFX12-GI-NEXT: v_trunc_f32_e32 v0, s0
+; GFX12-GI-NEXT: s_trunc_f32 s1, s0
; GFX12-GI-NEXT: s_cmp_nge_f32 s0, 0
-; GFX12-GI-NEXT: v_readfirstlane_b32 s1, v0
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_mul_f32 s2, s1, 0x2f800000
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-GI-NEXT: v_floor_f32_e32 v0, s2
-; GFX12-GI-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12-GI-NEXT: s_floor_f32 s2, s2
+; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GI-NEXT: s_fmac_f32 s1, s2, 0xcf800000
; GFX12-GI-NEXT: s_cvt_u32_f32 s3, s2
; GFX12-GI-NEXT: s_wait_alu depctr_sa_sdst(0)
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