[llvm] [MC][TableGen] Pack MCInstrDesc fields into 24 bytes (PR #202647)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions h,cpp -- llvm/unittests/MC/MCInstrDescTest.cpp llvm/include/llvm/MC/MCInstrDesc.h llvm/lib/MC/MCInstrDesc.cpp llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.cpp llvm/lib/Target/AMDGPU/SIInstrInfo.h llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp llvm/lib/Target/Mips/MipsSEInstrInfo.cpp llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp llvm/lib/Target/X86/X86InstrInfo.cpp llvm/utils/TableGen/InstrInfoEmitter.cpp --diff_from_common_commit
``````````

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``````````diff
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h
index 239bff602..e7f36718e 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -204,9 +204,9 @@ public:
   // the <Target>Insts table because they rely on knowing their own address to
   // find other information elsewhere in the same table.
 
-  uint64_t TSFlags; // Target-specific flag values.
-  uint64_t Flags : 41; // Flags identifying machine instruction classes.
-  uint64_t Opcode : 16; // The opcode number.
+  uint64_t TSFlags;         // Target-specific flag values.
+  uint64_t Flags : 41;      // Flags identifying machine instruction classes.
+  uint64_t Opcode : 16;     // The opcode number.
   uint64_t EncodedSize : 7; // Half the encoded size, or 127 for size 3.
 
   // Operand counts 126 through 128 are unused. Use 126 and 127 to encode
@@ -222,19 +222,16 @@ public:
 
   constexpr MCInstrDesc(uint32_t Opcode = 0, uint16_t NumOperands = 0,
                         uint8_t NumDefs = 0, uint8_t Size = 0,
-                        uint16_t SchedClass = 0,
-                        uint8_t NumImplicitUses = 0,
-                        uint8_t NumImplicitDefs = 0,
-                        uint16_t OpInfoOffset = 0,
+                        uint16_t SchedClass = 0, uint8_t NumImplicitUses = 0,
+                        uint8_t NumImplicitDefs = 0, uint16_t OpInfoOffset = 0,
                         uint16_t ImplicitOffset = 0, uint64_t Flags = 0,
                         uint64_t TSFlags = 0)
       : TSFlags(TSFlags), Flags(Flags), Opcode(Opcode),
         EncodedSize(Size == 3 ? 127 : Size / 2),
         EncodedNumOperands(NumOperands >= 129 ? NumOperands - 3 : NumOperands),
-        EncodedNumDefs(NumDefs == 128 ? 127 : NumDefs),
-        SchedClass(SchedClass), NumImplicitUses(NumImplicitUses),
-        NumImplicitDefs(NumImplicitDefs), OpInfoOffset(OpInfoOffset),
-        ImplicitOffset(ImplicitOffset) {}
+        EncodedNumDefs(NumDefs == 128 ? 127 : NumDefs), SchedClass(SchedClass),
+        NumImplicitUses(NumImplicitUses), NumImplicitDefs(NumImplicitDefs),
+        OpInfoOffset(OpInfoOffset), ImplicitOffset(ImplicitOffset) {}
 
   /// Returns the value of the specified operand constraint if
   /// it is present. Returns -1 if it is not present.
@@ -630,9 +627,7 @@ public:
 
   /// Return the number of bytes in the encoding of this instruction,
   /// or zero if the encoding size cannot be known from the opcode.
-  unsigned getSize() const {
-    return EncodedSize == 127 ? 3 : EncodedSize * 2;
-  }
+  unsigned getSize() const { return EncodedSize == 127 ? 3 : EncodedSize * 2; }
 
   /// Find the index of the first operand in the
   /// operand list that is used to represent the predicate. It returns -1 if
diff --git a/llvm/unittests/MC/MCInstrDescTest.cpp b/llvm/unittests/MC/MCInstrDescTest.cpp
index 722861494..63e90e699 100644
--- a/llvm/unittests/MC/MCInstrDescTest.cpp
+++ b/llvm/unittests/MC/MCInstrDescTest.cpp
@@ -17,9 +17,8 @@ TEST(MCInstrDescTest, PackedFields) {
   for (unsigned NumOperands : {0U, 1U, 125U, 129U, 130U}) {
     for (unsigned NumDefs : {0U, 1U, 126U, 128U}) {
       for (unsigned Size : {0U, 2U, 3U, 4U, 252U}) {
-        MCInstrDesc Desc(65535, NumOperands, NumDefs, Size, 8191, 63, 63,
-                         32767, 1023,
-                         (1ULL << MCID::Authenticated) | 1, UINT64_MAX);
+        MCInstrDesc Desc(65535, NumOperands, NumDefs, Size, 8191, 63, 63, 32767,
+                         1023, (1ULL << MCID::Authenticated) | 1, UINT64_MAX);
 
         EXPECT_EQ(Desc.getOpcode(), 65535U);
         EXPECT_EQ(Desc.getNumOperands(), NumOperands);
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index f18f17660..68a8043c5 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -1322,8 +1322,8 @@ void InstrInfoEmitter::emitRecord(
                     "implicit register count does not fit in 6 bits");
 
   OS << "    { ";
-  OS << Num << ",\t" << MinOperands << ",\t" << DefOperands << ",\t"
-     << Size << ",\t" << SchedClass << ",\t";
+  OS << Num << ",\t" << MinOperands << ",\t" << DefOperands << ",\t" << Size
+     << ",\t" << SchedClass << ",\t";
 
   const CodeGenTarget &Target = CDP.getTargetInfo();
 

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https://github.com/llvm/llvm-project/pull/202647