[llvm] [SelectionDAG] Fuse frequent adjacent matcher operations (PR #202635)

[via llvm-commits]

github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

<details>
<summary>
You can test this locally with the following command:
</summary>

``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/include/llvm/CodeGen/SelectionDAGISel.h llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/utils/TableGen/DAGISelMatcherEmitter.cpp --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 98c4e6edc..2ea46a39b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3053,8 +3053,7 @@ static constexpr uint16_t CompactISDOpcodes[] = {
 
 static_assert(sizeof(CompactISDOpcodes) / sizeof(*CompactISDOpcodes) ==
               SelectionDAGISel::OPC_CheckOpcodeISD_BUILD_VECTOR -
-                      SelectionDAGISel::OPC_CheckOpcodeISD_SRL +
-                  1);
+                  SelectionDAGISel::OPC_CheckOpcodeISD_SRL + 1);
 
 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
 CheckCompactISDOpcode(unsigned MatcherOpcode, SDNode *N) {
@@ -3735,9 +3734,9 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
       NodeStack.pop_back();
       assert(!NodeStack.empty() && "Node stack imbalance!");
       N = NodeStack.back();
-      unsigned PredicateOpcode =
-          Opcode == OPC_MoveParent_CheckPredicate0 ? OPC_CheckPredicate0
-                                                   : OPC_CheckPredicate1;
+      unsigned PredicateOpcode = Opcode == OPC_MoveParent_CheckPredicate0
+                                     ? OPC_CheckPredicate0
+                                     : OPC_CheckPredicate1;
       if (!::CheckNodePredicate(PredicateOpcode, MatcherTable, MatcherIndex,
                                 *this, N))
         break;
@@ -3755,8 +3754,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
 
     case OPC_MoveChild0_CheckOpcodeISD_SRL:
     case OPC_MoveChild1_CheckOpcodeISD_ADD: {
-      unsigned ChildNo =
-          Opcode == OPC_MoveChild0_CheckOpcodeISD_SRL ? 0 : 1;
+      unsigned ChildNo = Opcode == OPC_MoveChild0_CheckOpcodeISD_SRL ? 0 : 1;
       if (ChildNo >= N.getNumOperands())
         break;
       N = N.getOperand(ChildNo);
diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
index 95de32057..1e3455315 100644
--- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -299,8 +299,7 @@ private:
     }
 
     if (const auto *MSM = dyn_cast<MoveSiblingMatcher>(First)) {
-      if (MSM->getSiblingNo() == 2 &&
-          isa<CheckImmAllZerosVMatcher>(Second))
+      if (MSM->getSiblingNo() == 2 && isa<CheckImmAllZerosVMatcher>(Second))
         return "OPC_MoveSibling2_CheckImmAllZerosV";
 
       if (MSM->getSiblingNo() == 1) {
@@ -594,20 +593,16 @@ static unsigned emitMVT(MVT VT, raw_ostream &OS) {
 static StringRef getCompactISDOpcode(StringRef Opcode) {
   return StringSwitch<StringRef>(Opcode)
       .Case("ISD::SRL", "OPC_CheckOpcodeISD_SRL")
-      .Case("ISD::SIGN_EXTEND_INREG",
-            "OPC_CheckOpcodeISD_SIGN_EXTEND_INREG")
+      .Case("ISD::SIGN_EXTEND_INREG", "OPC_CheckOpcodeISD_SIGN_EXTEND_INREG")
       .Case("ISD::TargetConstant", "OPC_CheckOpcodeISD_TargetConstant")
       .Case("ISD::LOAD", "OPC_CheckOpcodeISD_LOAD")
       .Case("ISD::Constant", "OPC_CheckOpcodeISD_Constant")
-      .Case("ISD::INTRINSIC_WO_CHAIN",
-            "OPC_CheckOpcodeISD_INTRINSIC_WO_CHAIN")
+      .Case("ISD::INTRINSIC_WO_CHAIN", "OPC_CheckOpcodeISD_INTRINSIC_WO_CHAIN")
       .Case("ISD::SRA", "OPC_CheckOpcodeISD_SRA")
       .Case("ISD::ADD", "OPC_CheckOpcodeISD_ADD")
-      .Case("ISD::EXTRACT_SUBVECTOR",
-            "OPC_CheckOpcodeISD_EXTRACT_SUBVECTOR")
+      .Case("ISD::EXTRACT_SUBVECTOR", "OPC_CheckOpcodeISD_EXTRACT_SUBVECTOR")
       .Case("ISD::SPLAT_VECTOR", "OPC_CheckOpcodeISD_SPLAT_VECTOR")
-      .Case("ISD::EXTRACT_VECTOR_ELT",
-            "OPC_CheckOpcodeISD_EXTRACT_VECTOR_ELT")
+      .Case("ISD::EXTRACT_VECTOR_ELT", "OPC_CheckOpcodeISD_EXTRACT_VECTOR_ELT")
       .Case("ISD::XOR", "OPC_CheckOpcodeISD_XOR")
       .Case("ISD::MUL", "OPC_CheckOpcodeISD_MUL")
       .Case("ISD::AND", "OPC_CheckOpcodeISD_AND")

``````````

</details>


https://github.com/llvm/llvm-project/pull/202635