[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for cvt f16<->fp8/bf8 (PR #202361)
Petar Avramovic via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 9 07:03:15 PDT 2026
https://github.com/petar-avramovic updated https://github.com/llvm/llvm-project/pull/202361
>From afe3cb5f6b64c7084bc4396854c06bd2b814053f Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Mon, 8 Jun 2026 16:33:14 +0200
Subject: [PATCH] AMDGPU/GlobalISel: RegBankLegalize rules for cvt
f16<->fp8/bf8
Small types are impemented using integers in LLVMIR,
because of this there are no irtranslator failures.
---
.../AMDGPU/AMDGPURegBankLegalizeRules.cpp | 20 ++++
.../CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll | 96 +++++++++++++++++--
.../CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll | 34 ++++++-
.../CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll | 2 +-
4 files changed, 139 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 41aa5802ad53d..0cc596e4efcd1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1855,6 +1855,26 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{UniV2S32}, {{UniInVgprV2S32}, {IntrId, Vgpr32}}})
.Any({{DivV2S32}, {{VgprV2S32}, {IntrId, Vgpr32}}});
+ addRulesForIOpcs({amdgcn_cvt_f16_bf8, amdgcn_cvt_f16_fp8}, Standard)
+ .Uni(S16, {{UniInVgprS16}, {IntrId, Vgpr32, Imm}})
+ .Div(S16, {{Vgpr16}, {IntrId, Vgpr32, Imm}});
+
+ addRulesForIOpcs({amdgcn_cvt_pk_f16_bf8, amdgcn_cvt_pk_f16_fp8}, Standard)
+ .Uni(V2S16, {{UniInVgprV2S16}, {IntrId, Vgpr16}})
+ .Div(V2S16, {{VgprV2S16}, {IntrId, Vgpr16}});
+
+ addRulesForIOpcs({amdgcn_cvt_pk_bf8_f16, amdgcn_cvt_pk_fp8_f16}, Standard)
+ .Uni(S16, {{UniInVgprS16}, {IntrId, VgprV2S16}})
+ .Div(S16, {{Vgpr16}, {IntrId, VgprV2S16}});
+
+ addRulesForIOpcs({amdgcn_cvt_sr_bf8_f16, amdgcn_cvt_sr_fp8_f16}, Standard)
+ .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr16, Vgpr32, Vgpr32, Imm}})
+ .Div(S32, {{Vgpr32}, {IntrId, Vgpr16, Vgpr32, Vgpr32, Imm}});
+
+ addRulesForIOpcs({amdgcn_cvt_sr_pk_f16_f32}, Standard)
+ .Uni(V2S16, {{UniInVgprV2S16}, {IntrId, Vgpr32, Vgpr32, Vgpr32}})
+ .Div(V2S16, {{VgprV2S16}, {IntrId, Vgpr32, Vgpr32, Vgpr32}});
+
addRulesForIOpcs({amdgcn_cvt_scalef32_sr_fp8_f16})
.Any({{DivS32},
{{Vgpr32}, {IntrId, Vgpr32, Vgpr16, Vgpr32, Vgpr32, Imm}}});
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
index 4af8e949d621c..68102338a4661 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-REAL16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-REAL16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-REAL16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 %s -o - | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-FAKE16 %s
declare half @llvm.amdgcn.cvt.f16.bf8(i32, i32)
declare half @llvm.amdgcn.cvt.f16.fp8(i32, i32)
@@ -157,6 +157,47 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte3(i32 %a) {
ret float %ret
}
+define amdgpu_ps float @test_cvt_f16_bf8_byte0_s(i32 inreg %a) {
+; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_bf8_byte0_s:
+; GFX1250-SDAG-REAL16: ; %bb.0:
+; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_bf8_e32 v0.l, s0
+; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog
+;
+; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_bf8_byte0_s:
+; GFX1250-SDAG-FAKE16: ; %bb.0:
+; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_bf8_e32 v0, s0
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_bf8_byte0_s:
+; GFX1250-GISEL-REAL16: ; %bb.0:
+; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e32 v0.l, s0
+; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_3)
+; GFX1250-GISEL-REAL16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-GISEL-REAL16-NEXT: s_cvt_f32_f16 s0, s0
+; GFX1250-GISEL-REAL16-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_bf8_byte0_s:
+; GFX1250-GISEL-FAKE16: ; %bb.0:
+; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_bf8_e32 v0, s0
+; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_3)
+; GFX1250-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-GISEL-FAKE16-NEXT: s_cvt_f32_f16 s0, s0
+; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
+ %cvt = tail call half @llvm.amdgcn.cvt.f16.bf8(i32 %a, i32 0)
+ %ret = fpext half %cvt to float
+ ret float %ret
+}
+
define amdgpu_ps float @test_cvt_f16_bf8_byte3_hi(i32 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_bf8_byte3_hi:
; GFX1250-SDAG-REAL16: ; %bb.0:
@@ -176,9 +217,8 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte3_hi(i32 %a) {
; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_bf8_byte3_hi:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:3
-; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-GISEL-REAL16-NEXT: v_lshl_or_b32 v0, v0, 16, 0
+; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.h, v0 byte_sel:3
+; GFX1250-GISEL-REAL16-NEXT: v_mov_b16_e32 v0.l, 0
; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_bf8_byte3_hi:
@@ -362,9 +402,8 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte3_hi(i32 %a) {
; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_fp8_byte3_hi:
; GFX1250-GISEL-REAL16: ; %bb.0:
; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:3
-; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-GISEL-REAL16-NEXT: v_lshl_or_b32 v0, v0, 16, 0
+; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.h, v0 byte_sel:3
+; GFX1250-GISEL-REAL16-NEXT: v_mov_b16_e32 v0.l, 0
; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_fp8_byte3_hi:
@@ -381,6 +420,47 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte3_hi(i32 %a) {
ret float %ret
}
+define amdgpu_ps float @test_cvt_f16_fp8_byte0_s(i32 inreg %a) {
+; GFX1250-SDAG-REAL16-LABEL: test_cvt_f16_fp8_byte0_s:
+; GFX1250-SDAG-REAL16: ; %bb.0:
+; GFX1250-SDAG-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-REAL16-NEXT: v_cvt_f16_fp8_e32 v0.l, s0
+; GFX1250-SDAG-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-REAL16-NEXT: v_cvt_f32_f16_e32 v0, v0.l
+; GFX1250-SDAG-REAL16-NEXT: ; return to shader part epilog
+;
+; GFX1250-SDAG-FAKE16-LABEL: test_cvt_f16_fp8_byte0_s:
+; GFX1250-SDAG-FAKE16: ; %bb.0:
+; GFX1250-SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f16_fp8_e32 v0, s0
+; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-FAKE16-NEXT: v_cvt_f32_f16_e32 v0, v0
+; GFX1250-SDAG-FAKE16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-REAL16-LABEL: test_cvt_f16_fp8_byte0_s:
+; GFX1250-GISEL-REAL16: ; %bb.0:
+; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e32 v0.l, s0
+; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_3)
+; GFX1250-GISEL-REAL16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-GISEL-REAL16-NEXT: s_cvt_f32_f16 s0, s0
+; GFX1250-GISEL-REAL16-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
+;
+; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_fp8_byte0_s:
+; GFX1250-GISEL-FAKE16: ; %bb.0:
+; GFX1250-GISEL-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-FAKE16-NEXT: v_cvt_f16_fp8_e32 v0, s0
+; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_3)
+; GFX1250-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1250-GISEL-FAKE16-NEXT: s_cvt_f32_f16 s0, s0
+; GFX1250-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX1250-GISEL-FAKE16-NEXT: ; return to shader part epilog
+ %cvt = tail call half @llvm.amdgcn.cvt.f16.fp8(i32 %a, i32 0)
+ %ret = fpext half %cvt to float
+ ret float %ret
+}
+
define amdgpu_ps float @test_cvt_pk_f16_bf8_v(i16 %a) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_pk_f16_bf8_v:
; GFX1250-SDAG-REAL16: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
index 96d11665e7f80..9804bf7e1c1ef 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.f16.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-REAL16 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG-FAKE16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-REAL16 %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-FAKE16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-REAL16 %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL-FAKE16 %s
declare i16 @llvm.amdgcn.cvt.pk.bf8.f16(<2 x half>)
declare i16 @llvm.amdgcn.cvt.pk.fp8.f16(<2 x half>)
@@ -252,6 +252,20 @@ define amdgpu_ps void @test_cvt_sr_bf8_f16_byte0(half %a, i32 %sr, i32 %old, ptr
ret void
}
+define amdgpu_ps void @test_cvt_sr_bf8_f16_byte0_s(half inreg %a, i32 inreg %sr, i32 inreg %old, ptr addrspace(1) %out) {
+; GFX1250-LABEL: test_cvt_sr_bf8_f16_byte0_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: v_mov_b32_e32 v2, s2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cvt_sr_bf8_f16 v2, s0, s1
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250-NEXT: s_endpgm
+ %cvt = tail call i32 @llvm.amdgcn.cvt.sr.bf8.f16(half %a, i32 %sr, i32 %old, i32 0)
+ store i32 %cvt, ptr addrspace(1) %out
+ ret void
+}
+
define amdgpu_ps void @test_cvt_sr_bf8_f16_byte1(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_bf8_f16_byte1:
; GFX1250-SDAG-REAL16: ; %bb.0:
@@ -444,6 +458,20 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_byte0(half %a, i32 %sr, i32 %old, ptr
ret void
}
+define amdgpu_ps void @test_cvt_sr_fp8_f16_byte0_s(half inreg %a, i32 inreg %sr, i32 inreg %old, ptr addrspace(1) %out) {
+; GFX1250-LABEL: test_cvt_sr_fp8_f16_byte0_s:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: v_mov_b32_e32 v2, s2
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cvt_sr_fp8_f16 v2, s0, s1
+; GFX1250-NEXT: global_store_b32 v[0:1], v2, off
+; GFX1250-NEXT: s_endpgm
+ %cvt = tail call i32 @llvm.amdgcn.cvt.sr.fp8.f16(half %a, i32 %sr, i32 %old, i32 0)
+ store i32 %cvt, ptr addrspace(1) %out
+ ret void
+}
+
define amdgpu_ps void @test_cvt_sr_fp8_f16_byte1(half %a, i32 %sr, i32 %old, ptr addrspace(1) %out) {
; GFX1250-SDAG-REAL16-LABEL: test_cvt_sr_fp8_f16_byte1:
; GFX1250-SDAG-REAL16: ; %bb.0:
@@ -599,5 +627,3 @@ define amdgpu_ps void @test_cvt_sr_fp8_f16_hi_byte0(<2 x half> %a, i32 %sr, i32
ret void
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX1250: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
index 50936f9ff8fd4..70f3c3f1273ef 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pk.f16.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GCN %s
declare <2 x half> @llvm.amdgcn.cvt.sr.pk.f16.f32(float, float, i32) #0
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