[llvm] [AArch64] SME definitions for C1-Ultra scheduling model (PR #194850)

[Nashe Mncube via llvm-commits]

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@@ -703,6 +744,162 @@ def C1UWrite_3or4c_1M0_1M : SchedWriteVariant<[
                       SchedVar<NeoversePdIsPg,  [C1UWrite_4c_1M0_1M]>,
                       SchedVar<NoSchedPred,     [C1UWrite_3c_1M0_1M]>]>;
 
+def C1UWr_FMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_FMA>;
+def C1UWR_VA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VA>;
+def C1UWR_VDOT_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VDOT>;
+def C1UWR_VMMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VMMA>;
+def C1UWR_VMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VMA>;
+def C1UWR_VMAH_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VMAH>;
+def C1UWR_VPA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VPA>;
+def C1UWR_VSA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VSA>;
+def C1UWR_VFCMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VFCMA>;
+def C1UWR_VFMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VFMA>;
+def C1UWR_VBFDOT_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VBFDOT>;
+def C1UWR_VBFMMA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VBFMMA>;
+def C1UWR_VBFMAL_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWR_VBFMAL>;
+def C1UWr_ZA_CME : C1UStreamingSchedWrite<C1UWrite_0c_1C_4X, C1UWr_ZA>;
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nasherm wrote:

Thanks for spotting. This is resolved

https://github.com/llvm/llvm-project/pull/194850