[llvm] [AArch64] SME definitions for C1-Ultra scheduling model (PR #194850)

[Nashe Mncube via llvm-commits]

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@@ -3650,7 +3650,7 @@ multiclass sme_tmopa_32b<bits<5> opc, RegisterOperand zn_ty, RegisterOperand zm_
 class sme2_zero_zt<string mnemonic, bits<4> opc>
     : I<(outs ZTR:$ZT), (ins ),
          mnemonic, "\t\\{ $ZT \\}",
-         "", []>, Sched<[]> {
+         "", []>, Sched<[WriteI]> {
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nasherm wrote:

I've omitted this from the most recent patches

https://github.com/llvm/llvm-project/pull/194850