[llvm] 70b68df - [AMDGPU] Fix si-optimize-exec-masking stepping into debug values (#201947)

[via llvm-commits]

Author: Joseph Huber
Date: 2026-06-09T08:08:06-05:00
New Revision: 70b68dff845403f62d77f42850ac779a78662272

URL: https://github.com/llvm/llvm-project/commit/70b68dff845403f62d77f42850ac779a78662272
DIFF: https://github.com/llvm/llvm-project/commit/70b68dff845403f62d77f42850ac779a78662272.diff

LOG: [AMDGPU] Fix si-optimize-exec-masking stepping into debug values (#201947)

Summary:
This pass tries to step between register uses and would try to enter a
debug instruction if it managed to get between them.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
    llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
index 72a60f78b7348..53bc68036b204 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
@@ -468,7 +468,7 @@ bool SIOptimizeExecMasking::optimizeExecSequence() {
     auto *CopyToExecInst = &*I;
     auto CopyFromExecInst = findExecCopy(MBB, I);
     if (CopyFromExecInst == E) {
-      auto PrepareExecInst = std::next(I);
+      auto PrepareExecInst = next_nodbg(I, E);
       if (PrepareExecInst == E)
         continue;
       // Fold exec = COPY (S_AND_B64 reg, exec) -> exec = S_AND_B64 reg, exec
@@ -501,6 +501,9 @@ bool SIOptimizeExecMasking::optimizeExecSequence() {
              J = std::next(CopyFromExecInst->getIterator()),
              JE = I->getIterator();
          J != JE; ++J) {
+      if (J->isDebugInstr())
+        continue;
+
       if (SaveExecInst && J->readsRegister(LMC.ExecReg, TRI)) {
         LLVM_DEBUG(dbgs() << "exec read prevents saveexec: " << *J << '\n');
         // Make sure this is inserted after any VALU ops that may have been
@@ -759,9 +762,10 @@ void SIOptimizeExecMasking::tryRecordOrSaveexecXorSequence(MachineInstr &MI) {
         XorSrc1.isReg() &&
         (XorSrc0.getReg() == LMC.ExecReg || XorSrc1.getReg() == LMC.ExecReg)) {
 
-      // Peek at the previous instruction and check if this is a relevant
-      // s_or_saveexec instruction.
-      MachineInstr &PossibleOrSaveexec = *MI.getPrevNode();
+      // Peek at the previous non-debug instruction and check if this is a
+      // relevant s_or_saveexec instruction.
+      auto It = prev_nodbg(MI.getIterator(), MI.getParent()->instr_begin());
+      MachineInstr &PossibleOrSaveexec = *It;
       if (PossibleOrSaveexec.getOpcode() != LMC.OrSaveExecOpc)
         return;
 

diff  --git a/llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir b/llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
index 47f13cb5ebe16..12cbbcb02d62a 100644
--- a/llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
+++ b/llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
@@ -1,5 +1,6 @@
 # RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -run-pass=si-optimize-exec-masking -verify-machineinstrs %s -o - | FileCheck --check-prefixes=GCN,GFX1010 %s
 # RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 -run-pass=si-optimize-exec-masking -verify-machineinstrs %s -o - | FileCheck --check-prefixes=GCN,GFX1030 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 -run-pass=mir-debugify,si-optimize-exec-masking,mir-strip-debug -verify-machineinstrs %s -o - | FileCheck --check-prefixes=GCN,GFX1030 %s
 ---
 
 # After the Optimize exec masking (post-RA) pass, there's a change of having v_cmpx instructions