[llvm] 88caf8e - Reland "[PowerPC] set libcall lowering for fp setcc ops on SPE boards" (#199198)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 9 05:53:28 PDT 2026
Author: Erik Enikeev
Date: 2026-06-09T14:53:22+02:00
New Revision: 88caf8ef2bd61005e854952b8a1e699aa72347d8
URL: https://github.com/llvm/llvm-project/commit/88caf8ef2bd61005e854952b8a1e699aa72347d8
DIFF: https://github.com/llvm/llvm-project/commit/88caf8ef2bd61005e854952b8a1e699aa72347d8.diff
LOG: Reland "[PowerPC] set libcall lowering for fp setcc ops on SPE boards" (#199198)
This is a reland of 4d0100789dc9b4db7d77c033d8f53f8b7dc68437, which was
reverted by c24ab4c814f680c5ac71600bf80d551123abd84d.
The functionality is unchanged from the original patch. This version
only fixes the fast-math flag propagation issue by passing `SDNodeFlags`
explicitly to `DAG.getSetCC()` (same as #199105 which was closed because
the underlying patch had been reverted).
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
llvm/test/CodeGen/PowerPC/spe.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 38a493676e97d..549d9052a71be 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10305,22 +10305,25 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
LHS.getValueType());
if (!LegalOperations ||
TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) {
+ // Propagate fast-math-flags.
+ SDNodeFlags Flags = N0->getFlags();
switch (N0Opcode) {
default:
llvm_unreachable("Unhandled SetCC Equivalent!");
case ISD::SETCC:
- return DAG.getSetCC(SDLoc(N0), VT, LHS, RHS, NotCC);
+ return DAG.getSetCC(SDLoc(N0), VT, LHS, RHS, NotCC, SDValue(),
+ /*IsSignaling=*/false, Flags);
case ISD::SELECT_CC:
return DAG.getSelectCC(SDLoc(N0), LHS, RHS, N0.getOperand(2),
- N0.getOperand(3), NotCC);
+ N0.getOperand(3), NotCC, Flags);
case ISD::STRICT_FSETCC:
case ISD::STRICT_FSETCCS: {
if (N0.hasOneUse()) {
// FIXME Can we handle multiple uses? Could we token factor the chain
// results from the new/old setcc?
SDValue SetCC =
- DAG.getSetCC(SDLoc(N0), VT, LHS, RHS, NotCC,
- N0.getOperand(0), N0Opcode == ISD::STRICT_FSETCCS);
+ DAG.getSetCC(SDLoc(N0), VT, LHS, RHS, NotCC, N0.getOperand(0),
+ N0Opcode == ISD::STRICT_FSETCCS, Flags);
CombineTo(N, SetCC);
DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), SetCC.getValue(1));
recursivelyDeleteUnusedNodes(N0.getNode());
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index be901c718fb68..757b47431a165 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -557,8 +557,16 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal);
// SPE supports signaling compare of f32/f64.
- setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Legal);
- setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Legal);
+ // But it doesn't comply IEEE-754 rules for comparing
+ // special values like NaNs, Infs.
+ setOperationAction(ISD::SETCC, MVT::f32, Custom);
+ setOperationAction(ISD::SETCC, MVT::f64, Custom);
+ setOperationAction(ISD::STRICT_FSETCCS, MVT::f32, Custom);
+ setOperationAction(ISD::STRICT_FSETCCS, MVT::f64, Custom);
+ setOperationAction(ISD::STRICT_FSETCC, MVT::f32, Custom);
+ setOperationAction(ISD::STRICT_FSETCC, MVT::f64, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f32, Custom);
+ setOperationAction(ISD::BR_CC, MVT::f64, Custom);
} else {
// PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
@@ -3606,6 +3614,7 @@ SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
bool IsStrict = Op->isStrictFPOpcode();
+ const SDNodeFlags Flags = Op.getNode()->getFlags();
ISD::CondCode CC =
cast<CondCodeSDNode>(Op.getOperand(IsStrict ? 3 : 2))->get();
SDValue LHS = Op.getOperand(IsStrict ? 1 : 0);
@@ -3614,8 +3623,10 @@ SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
EVT LHSVT = LHS.getValueType();
SDLoc dl(Op);
- // Soften the setcc with libcall if it is fp128.
- if (LHSVT == MVT::f128) {
+ // Soften the setcc with libcall if it is fp128 or it is SPE and fp32/fp64.
+ if (LHSVT == MVT::f128 ||
+ (Subtarget.hasSPE() && (LHSVT == MVT::f32 || LHSVT == MVT::f64) &&
+ (!Flags.hasNoNaNs() || !Flags.hasNoInfs()))) {
assert(!Subtarget.hasP9Vector() &&
"SETCC for f128 is already legal under Power9!");
softenSetCCOperands(DAG, LHSVT, LHS, RHS, CC, dl, LHS, RHS, Chain,
@@ -3626,6 +3637,8 @@ SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
if (IsStrict)
return DAG.getMergeValues({LHS, Chain}, dl);
return LHS;
+ } else if (LHSVT == MVT::f32 || LHSVT == MVT::f64) {
+ return Op;
}
assert(!IsStrict && "Don't know how to handle STRICT_FSETCC!");
@@ -3680,6 +3693,35 @@ SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
return SDValue();
}
+SDValue PPCTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
+ const SDNodeFlags Flags = Op->getFlags();
+ SDValue Chain = Op.getOperand(0);
+ ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
+ SDValue LHS = Op.getOperand(2);
+ SDValue RHS = Op.getOperand(3);
+ SDValue Dest = Op.getOperand(4);
+ EVT LHSVT = LHS.getValueType();
+ SDLoc dl(Op);
+
+ assert(Subtarget.hasSPE() && "LowerBR_CC used only for targets with SPE");
+
+ if ((LHSVT == MVT::f32 || LHSVT == MVT::f64) && Flags.hasNoNaNs() &&
+ Flags.hasNoInfs())
+ return Op;
+
+ softenSetCCOperands(DAG, LHSVT, LHS, RHS, CC, dl, LHS, RHS);
+
+ // If softenSetCCOperands returned a scalar, we need to compare the result
+ // against zero to select between true and false values.
+ if (!RHS) {
+ RHS = DAG.getConstant(0, dl, LHSVT);
+ CC = ISD::SETNE;
+ }
+
+ return DAG.getNode(ISD::BR_CC, dl, Op.getValueType(), Chain,
+ DAG.getCondCode(CC), LHS, RHS, Dest);
+}
+
SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
SDNode *Node = Op.getNode();
EVT VT = Node->getValueType(0);
@@ -12798,6 +12840,7 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::STRICT_FSETCC:
case ISD::STRICT_FSETCCS:
case ISD::SETCC: return LowerSETCC(Op, DAG);
+ case ISD::BR_CC: return LowerBR_CC(Op, DAG);
case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
case ISD::SSUBO:
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index b7a862ac6d88f..64be786df7096 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -703,6 +703,7 @@ namespace llvm {
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSSUBO(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSADDO(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll b/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
index 75609a5ba3fdd..7f5e38cf24211 100644
--- a/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
@@ -9,7 +9,7 @@ entry:
; ELF64-LABEL: @t1a
; SPE-LABEL: @t1a
; VSX-LABEL: @t1a
- %cmp = fcmp oeq float %a, 0.000000e+00
+ %cmp = fcmp nnan ninf oeq float %a, 0.000000e+00
; ELF64: addis
; ELF64: lfs
; ELF64: fcmpu
@@ -33,7 +33,7 @@ entry:
; ELF64-LABEL: @t1b
; SPE-LABEL: @t1b
; VSX-LABEL: @t1b
- %cmp = fcmp oeq float %a, -0.000000e+00
+ %cmp = fcmp nnan ninf oeq float %a, -0.000000e+00
; ELF64: addis
; ELF64: lfs
; ELF64: fcmpu
@@ -57,7 +57,7 @@ entry:
; ELF64-LABEL: @t1c
; SPE-LABEL: @t1c
; VSX-LABEL: @t1c
- %cmp = fcmp oeq float -0.000000e+00, %a
+ %cmp = fcmp nnan ninf oeq float -0.000000e+00, %a
; ELF64: addis
; ELF64: lfs
; ELF64: fcmpu
@@ -81,7 +81,7 @@ entry:
; ELF64-LABEL: @t2a
; SPE-LABEL: @t2a
; VSX-LABEL: @t2a
- %cmp = fcmp oeq double %a, 0.000000e+00
+ %cmp = fcmp nnan ninf oeq double %a, 0.000000e+00
; ELF64: addis
; ELF64: lfd
; ELF64: fcmpu
@@ -105,7 +105,7 @@ entry:
; ELF64-LABEL: @t2b
; SPE-LABEL: @t2b
; VSX-LABEL: @t2b
- %cmp = fcmp oeq double %a, -0.000000e+00
+ %cmp = fcmp nnan ninf oeq double %a, -0.000000e+00
; ELF64: addis
; ELF64: lfd
; ELF64: fcmpu
@@ -129,7 +129,7 @@ entry:
; ELF64-LABEL: @t2c
; SPE-LABEL: @t2c
; VSX-LABEL: @t2c
- %cmp = fcmp oeq double -0.000000e+00, %a
+ %cmp = fcmp nnan ninf oeq double -0.000000e+00, %a
; ELF64: addis
; ELF64: lfd
; ELF64: fcmpu
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
index c20d319f2ac79..ddd06cf691c2e 100644
--- a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp-spe.ll
@@ -4,10 +4,27 @@
define i32 @test_f32_oeq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_oeq_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpeq cr0, r5, r6
-; SPE-NEXT: bclr 12, gt, 0
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r5
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: bl __eqsf2
+; SPE-NEXT: cmplwi r3, 0
+; SPE-NEXT: beq cr0, .LBB0_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB0_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"oeq", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -17,10 +34,27 @@ define i32 @test_f32_oeq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_ogt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_ogt_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpgt cr0, r5, r6
-; SPE-NEXT: bclr 12, gt, 0
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r5
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: bl __gtsf2
+; SPE-NEXT: cmpwi r3, 0
+; SPE-NEXT: bgt cr0, .LBB1_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB1_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ogt", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -30,16 +64,46 @@ define i32 @test_f32_ogt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_oge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_oge_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpeq cr0, r6, r6
-; SPE-NEXT: bc 4, gt, .LBB2_3
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -48(r1)
+; SPE-NEXT: mfcr r12
+; SPE-NEXT: stw r0, 52(r1)
+; SPE-NEXT: stw r12, 24(r1)
+; SPE-NEXT: stw r29, 36(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 40(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r5
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: stw r27, 28(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r27, r5
+; SPE-NEXT: stw r28, 32(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r28, r6
+; SPE-NEXT: bl __gesf2
+; SPE-NEXT: cmpwi cr2, r3, -1
+; SPE-NEXT: mr r3, r28
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: bl __eqsf2
+; SPE-NEXT: mr r28, r3
+; SPE-NEXT: mr r3, r27
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: bl __eqsf2
+; SPE-NEXT: or. r3, r3, r28
+; SPE-NEXT: crand 4*cr5+lt, 4*cr2+gt, eq
+; SPE-NEXT: bc 12, 4*cr5+lt, .LBB2_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efscmpeq cr0, r5, r5
-; SPE-NEXT: bc 4, gt, .LBB2_3
-; SPE-NEXT: # %bb.2:
-; SPE-NEXT: efscmplt cr0, r5, r6
-; SPE-NEXT: bclr 4, gt, 0
-; SPE-NEXT: .LBB2_3:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB2_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 40(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 36(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r28, 32(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r12, 24(r1)
+; SPE-NEXT: lwz r27, 28(r1) # 4-byte Folded Reload
+; SPE-NEXT: mtcrf 32, r12 # cr2
+; SPE-NEXT: lwz r0, 52(r1)
+; SPE-NEXT: addi r1, r1, 48
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"oge", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -49,10 +113,27 @@ define i32 @test_f32_oge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_olt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_olt_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmplt cr0, r5, r6
-; SPE-NEXT: bclr 12, gt, 0
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r5
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: bl __ltsf2
+; SPE-NEXT: cmpwi r3, 0
+; SPE-NEXT: blt cr0, .LBB3_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB3_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"olt", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -62,16 +143,46 @@ define i32 @test_f32_olt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_ole_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_ole_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpeq cr0, r6, r6
-; SPE-NEXT: bc 4, gt, .LBB4_3
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -48(r1)
+; SPE-NEXT: mfcr r12
+; SPE-NEXT: stw r0, 52(r1)
+; SPE-NEXT: stw r12, 24(r1)
+; SPE-NEXT: stw r29, 36(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 40(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r5
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: stw r27, 28(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r27, r5
+; SPE-NEXT: stw r28, 32(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r28, r6
+; SPE-NEXT: bl __lesf2
+; SPE-NEXT: cmpwi cr2, r3, 1
+; SPE-NEXT: mr r3, r28
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: bl __eqsf2
+; SPE-NEXT: mr r28, r3
+; SPE-NEXT: mr r3, r27
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: bl __eqsf2
+; SPE-NEXT: or. r3, r3, r28
+; SPE-NEXT: crand 4*cr5+lt, 4*cr2+lt, eq
+; SPE-NEXT: bc 12, 4*cr5+lt, .LBB4_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efscmpeq cr0, r5, r5
-; SPE-NEXT: bc 4, gt, .LBB4_3
-; SPE-NEXT: # %bb.2:
-; SPE-NEXT: efscmpgt cr0, r5, r6
-; SPE-NEXT: bclr 4, gt, 0
-; SPE-NEXT: .LBB4_3:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB4_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 40(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 36(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r28, 32(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r12, 24(r1)
+; SPE-NEXT: lwz r27, 28(r1) # 4-byte Folded Reload
+; SPE-NEXT: mtcrf 32, r12 # cr2
+; SPE-NEXT: lwz r0, 52(r1)
+; SPE-NEXT: addi r1, r1, 48
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ole", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -81,13 +192,43 @@ define i32 @test_f32_ole_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_one_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_one_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmplt cr0, r5, r6
-; SPE-NEXT: bclr 12, gt, 0
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -48(r1)
+; SPE-NEXT: mfcr r12
+; SPE-NEXT: stw r0, 52(r1)
+; SPE-NEXT: stw r12, 24(r1)
+; SPE-NEXT: stw r29, 36(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 40(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r5
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: stw r27, 28(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r27, r5
+; SPE-NEXT: stw r28, 32(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r28, r6
+; SPE-NEXT: bl __ltsf2
+; SPE-NEXT: cmpwi cr2, r3, 0
+; SPE-NEXT: mr r3, r27
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: bl __gtsf2
+; SPE-NEXT: bc 12, 4*cr2+lt, .LBB5_3
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efscmpgt cr0, r5, r6
-; SPE-NEXT: bclr 12, gt, 0
+; SPE-NEXT: cmpwi r3, 0
+; SPE-NEXT: bc 12, gt, .LBB5_3
; SPE-NEXT: # %bb.2:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB5_3:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 40(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 36(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r28, 32(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r12, 24(r1)
+; SPE-NEXT: lwz r27, 28(r1) # 4-byte Folded Reload
+; SPE-NEXT: mtcrf 32, r12 # cr2
+; SPE-NEXT: lwz r0, 52(r1)
+; SPE-NEXT: addi r1, r1, 48
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"one", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -97,13 +238,36 @@ define i32 @test_f32_one_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_ord_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_ord_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpeq cr0, r6, r6
-; SPE-NEXT: bc 4, gt, .LBB6_2
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r6
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: stw r27, 12(r1) # 4-byte Folded Spill
+; SPE-NEXT: stw r28, 16(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r28, r5
+; SPE-NEXT: bl __eqsf2
+; SPE-NEXT: mr r27, r3
+; SPE-NEXT: mr r3, r28
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: bl __eqsf2
+; SPE-NEXT: or. r3, r3, r27
+; SPE-NEXT: beq cr0, .LBB6_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efscmpeq cr0, r5, r5
-; SPE-NEXT: bclr 12, gt, 0
+; SPE-NEXT: mr r30, r29
; SPE-NEXT: .LBB6_2:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r28, 16(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r27, 12(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ord", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -113,15 +277,43 @@ define i32 @test_f32_ord_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_ueq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_ueq_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmplt cr0, r5, r6
-; SPE-NEXT: bc 12, gt, .LBB7_3
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -48(r1)
+; SPE-NEXT: mfcr r12
+; SPE-NEXT: stw r0, 52(r1)
+; SPE-NEXT: stw r12, 24(r1)
+; SPE-NEXT: stw r29, 36(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 40(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r5
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: stw r27, 28(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r27, r5
+; SPE-NEXT: stw r28, 32(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r28, r6
+; SPE-NEXT: bl __ltsf2
+; SPE-NEXT: cmpwi cr2, r3, -1
+; SPE-NEXT: mr r3, r27
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: bl __gtsf2
+; SPE-NEXT: bc 4, 4*cr2+gt, .LBB7_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efscmpgt cr0, r5, r6
-; SPE-NEXT: bc 12, gt, .LBB7_3
-; SPE-NEXT: # %bb.2:
-; SPE-NEXT: mr r4, r3
+; SPE-NEXT: cmpwi r3, 1
+; SPE-NEXT: bc 12, lt, .LBB7_3
+; SPE-NEXT: .LBB7_2:
+; SPE-NEXT: mr r30, r29
; SPE-NEXT: .LBB7_3:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 40(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 36(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r28, 32(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r12, 24(r1)
+; SPE-NEXT: lwz r27, 28(r1) # 4-byte Folded Reload
+; SPE-NEXT: mtcrf 32, r12 # cr2
+; SPE-NEXT: lwz r0, 52(r1)
+; SPE-NEXT: addi r1, r1, 48
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ueq", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -131,16 +323,46 @@ define i32 @test_f32_ueq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_ugt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_ugt_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpeq cr0, r5, r5
-; SPE-NEXT: bclr 4, gt, 0
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -48(r1)
+; SPE-NEXT: mfcr r12
+; SPE-NEXT: stw r0, 52(r1)
+; SPE-NEXT: stw r12, 24(r1)
+; SPE-NEXT: stw r29, 36(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 40(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r5
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: stw r27, 28(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r27, r5
+; SPE-NEXT: stw r28, 32(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r28, r6
+; SPE-NEXT: bl __gtsf2
+; SPE-NEXT: cmpwi cr2, r3, 0
+; SPE-NEXT: mr r3, r28
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: bl __nesf2
+; SPE-NEXT: mr r28, r3
+; SPE-NEXT: mr r3, r27
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: bl __nesf2
+; SPE-NEXT: or. r3, r3, r28
+; SPE-NEXT: crorc 4*cr5+lt, 4*cr2+gt, eq
+; SPE-NEXT: bc 12, 4*cr5+lt, .LBB8_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efscmpeq cr0, r6, r6
-; SPE-NEXT: bclr 4, gt, 0
-; SPE-NEXT: # %bb.2:
-; SPE-NEXT: efscmpgt cr0, r5, r6
-; SPE-NEXT: bclr 12, gt, 0
-; SPE-NEXT: # %bb.3:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB8_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 40(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 36(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r28, 32(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r12, 24(r1)
+; SPE-NEXT: lwz r27, 28(r1) # 4-byte Folded Reload
+; SPE-NEXT: mtcrf 32, r12 # cr2
+; SPE-NEXT: lwz r0, 52(r1)
+; SPE-NEXT: addi r1, r1, 48
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ugt", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -150,12 +372,27 @@ define i32 @test_f32_ugt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_uge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_uge_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmplt cr0, r5, r6
-; SPE-NEXT: bc 12, gt, .LBB9_2
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r5
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: bl __ltsf2
+; SPE-NEXT: cmpwi r3, 0
+; SPE-NEXT: bge cr0, .LBB9_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: mr r4, r3
+; SPE-NEXT: mr r30, r29
; SPE-NEXT: .LBB9_2:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"uge", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -165,16 +402,46 @@ define i32 @test_f32_uge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_ult_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_ult_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpeq cr0, r5, r5
-; SPE-NEXT: bclr 4, gt, 0
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -48(r1)
+; SPE-NEXT: mfcr r12
+; SPE-NEXT: stw r0, 52(r1)
+; SPE-NEXT: stw r12, 24(r1)
+; SPE-NEXT: stw r29, 36(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 40(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r5
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: stw r27, 28(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r27, r5
+; SPE-NEXT: stw r28, 32(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r28, r6
+; SPE-NEXT: bl __ltsf2
+; SPE-NEXT: cmpwi cr2, r3, 0
+; SPE-NEXT: mr r3, r28
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: bl __nesf2
+; SPE-NEXT: mr r28, r3
+; SPE-NEXT: mr r3, r27
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: bl __nesf2
+; SPE-NEXT: or. r3, r3, r28
+; SPE-NEXT: crorc 4*cr5+lt, 4*cr2+lt, eq
+; SPE-NEXT: bc 12, 4*cr5+lt, .LBB10_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efscmpeq cr0, r6, r6
-; SPE-NEXT: bclr 4, gt, 0
-; SPE-NEXT: # %bb.2:
-; SPE-NEXT: efscmplt cr0, r5, r6
-; SPE-NEXT: bclr 12, gt, 0
-; SPE-NEXT: # %bb.3:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB10_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 40(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 36(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r28, 32(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r12, 24(r1)
+; SPE-NEXT: lwz r27, 28(r1) # 4-byte Folded Reload
+; SPE-NEXT: mtcrf 32, r12 # cr2
+; SPE-NEXT: lwz r0, 52(r1)
+; SPE-NEXT: addi r1, r1, 48
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ult", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -184,12 +451,27 @@ define i32 @test_f32_ult_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_ule_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_ule_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpgt cr0, r5, r6
-; SPE-NEXT: bc 12, gt, .LBB11_2
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r5
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: bl __gtsf2
+; SPE-NEXT: cmpwi r3, 0
+; SPE-NEXT: ble cr0, .LBB11_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: mr r4, r3
+; SPE-NEXT: mr r30, r29
; SPE-NEXT: .LBB11_2:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"ule", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -199,12 +481,27 @@ define i32 @test_f32_ule_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_une_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_une_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpeq cr0, r5, r6
-; SPE-NEXT: bc 12, gt, .LBB12_2
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r5
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: bl __nesf2
+; SPE-NEXT: cmplwi r3, 0
+; SPE-NEXT: bne cr0, .LBB12_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: mr r4, r3
+; SPE-NEXT: mr r30, r29
; SPE-NEXT: .LBB12_2:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"une", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -214,13 +511,36 @@ define i32 @test_f32_une_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f32_uno_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
; SPE-LABEL: test_f32_uno_s:
; SPE: # %bb.0:
-; SPE-NEXT: efscmpeq cr0, r5, r5
-; SPE-NEXT: bclr 4, gt, 0
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: mr r3, r6
+; SPE-NEXT: mr r4, r6
+; SPE-NEXT: stw r27, 12(r1) # 4-byte Folded Spill
+; SPE-NEXT: stw r28, 16(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r28, r5
+; SPE-NEXT: bl __nesf2
+; SPE-NEXT: mr r27, r3
+; SPE-NEXT: mr r3, r28
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: bl __nesf2
+; SPE-NEXT: or. r3, r3, r27
+; SPE-NEXT: bne cr0, .LBB13_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efscmpeq cr0, r6, r6
-; SPE-NEXT: bclr 4, gt, 0
-; SPE-NEXT: # %bb.2:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB13_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r28, 16(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r27, 12(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f32(float %f1, float %f2, metadata !"uno", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -230,12 +550,30 @@ define i32 @test_f32_uno_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
define i32 @test_f64_oeq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_oeq_s:
; SPE: # %bb.0:
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
; SPE-NEXT: evmergelo r7, r7, r8
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: efdcmpeq cr0, r5, r7
-; SPE-NEXT: bclr 12, gt, 0
+; SPE-NEXT: evmergelo r4, r5, r6
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r3, r4, r4
+; SPE-NEXT: evmergehi r5, r7, r7
+; SPE-NEXT: mr r6, r7
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: cmplwi r3, 0
+; SPE-NEXT: beq cr0, .LBB14_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB14_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"oeq", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -245,12 +583,30 @@ define i32 @test_f64_oeq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_ogt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_ogt_s:
; SPE: # %bb.0:
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
; SPE-NEXT: evmergelo r7, r7, r8
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: efdcmpgt cr0, r5, r7
-; SPE-NEXT: bclr 12, gt, 0
+; SPE-NEXT: evmergelo r4, r5, r6
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r3, r4, r4
+; SPE-NEXT: evmergehi r5, r7, r7
+; SPE-NEXT: mr r6, r7
+; SPE-NEXT: bl __gtdf2
+; SPE-NEXT: cmpwi r3, 0
+; SPE-NEXT: bgt cr0, .LBB15_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB15_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ogt", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -260,18 +616,58 @@ define i32 @test_f64_ogt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_oge_s:
; SPE: # %bb.0:
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: evmergelo r6, r7, r8
-; SPE-NEXT: efdcmpeq cr0, r6, r6
-; SPE-NEXT: bc 4, gt, .LBB16_3
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -96(r1)
+; SPE-NEXT: mfcr r12
+; SPE-NEXT: stw r0, 100(r1)
+; SPE-NEXT: stw r12, 80(r1)
+; SPE-NEXT: evstdd r25, 24(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r26, 32(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r27, 40(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r28, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT: stw r29, 84(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 88(r1) # 4-byte Folded Spill
+; SPE-NEXT: evmergelo r28, r7, r8
+; SPE-NEXT: evmergelo r27, r5, r6
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r26, r27, r27
+; SPE-NEXT: evmergehi r25, r28, r28
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: mr r3, r26
+; SPE-NEXT: mr r5, r25
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __gedf2
+; SPE-NEXT: cmpwi cr2, r3, -1
+; SPE-NEXT: mr r3, r25
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: mr r5, r25
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: mr r28, r3
+; SPE-NEXT: mr r3, r26
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: mr r5, r26
+; SPE-NEXT: mr r6, r27
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: or. r3, r3, r28
+; SPE-NEXT: crand 4*cr5+lt, 4*cr2+gt, eq
+; SPE-NEXT: bc 12, 4*cr5+lt, .LBB16_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efdcmpeq cr0, r5, r5
-; SPE-NEXT: bc 4, gt, .LBB16_3
-; SPE-NEXT: # %bb.2:
-; SPE-NEXT: efdcmplt cr0, r5, r6
-; SPE-NEXT: bclr 4, gt, 0
-; SPE-NEXT: .LBB16_3:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB16_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 88(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 84(r1) # 4-byte Folded Reload
+; SPE-NEXT: evldd r28, 48(r1) # 8-byte Folded Reload
+; SPE-NEXT: evldd r27, 40(r1) # 8-byte Folded Reload
+; SPE-NEXT: evldd r26, 32(r1) # 8-byte Folded Reload
+; SPE-NEXT: lwz r12, 80(r1)
+; SPE-NEXT: evldd r25, 24(r1) # 8-byte Folded Reload
+; SPE-NEXT: mtcrf 32, r12 # cr2
+; SPE-NEXT: lwz r0, 100(r1)
+; SPE-NEXT: addi r1, r1, 96
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"oge", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -281,12 +677,30 @@ define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_olt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_olt_s:
; SPE: # %bb.0:
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
; SPE-NEXT: evmergelo r7, r7, r8
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: efdcmplt cr0, r5, r7
-; SPE-NEXT: bclr 12, gt, 0
+; SPE-NEXT: evmergelo r4, r5, r6
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r3, r4, r4
+; SPE-NEXT: evmergehi r5, r7, r7
+; SPE-NEXT: mr r6, r7
+; SPE-NEXT: bl __ltdf2
+; SPE-NEXT: cmpwi r3, 0
+; SPE-NEXT: blt cr0, .LBB17_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB17_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"olt", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -296,18 +710,58 @@ define i32 @test_f64_olt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_ole_s:
; SPE: # %bb.0:
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: evmergelo r6, r7, r8
-; SPE-NEXT: efdcmpeq cr0, r6, r6
-; SPE-NEXT: bc 4, gt, .LBB18_3
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -96(r1)
+; SPE-NEXT: mfcr r12
+; SPE-NEXT: stw r0, 100(r1)
+; SPE-NEXT: stw r12, 80(r1)
+; SPE-NEXT: evstdd r25, 24(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r26, 32(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r27, 40(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r28, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT: stw r29, 84(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 88(r1) # 4-byte Folded Spill
+; SPE-NEXT: evmergelo r28, r7, r8
+; SPE-NEXT: evmergelo r27, r5, r6
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r26, r27, r27
+; SPE-NEXT: evmergehi r25, r28, r28
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: mr r3, r26
+; SPE-NEXT: mr r5, r25
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __ledf2
+; SPE-NEXT: cmpwi cr2, r3, 1
+; SPE-NEXT: mr r3, r25
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: mr r5, r25
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: mr r28, r3
+; SPE-NEXT: mr r3, r26
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: mr r5, r26
+; SPE-NEXT: mr r6, r27
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: or. r3, r3, r28
+; SPE-NEXT: crand 4*cr5+lt, 4*cr2+lt, eq
+; SPE-NEXT: bc 12, 4*cr5+lt, .LBB18_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efdcmpeq cr0, r5, r5
-; SPE-NEXT: bc 4, gt, .LBB18_3
-; SPE-NEXT: # %bb.2:
-; SPE-NEXT: efdcmpgt cr0, r5, r6
-; SPE-NEXT: bclr 4, gt, 0
-; SPE-NEXT: .LBB18_3:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB18_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 88(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 84(r1) # 4-byte Folded Reload
+; SPE-NEXT: evldd r28, 48(r1) # 8-byte Folded Reload
+; SPE-NEXT: evldd r27, 40(r1) # 8-byte Folded Reload
+; SPE-NEXT: evldd r26, 32(r1) # 8-byte Folded Reload
+; SPE-NEXT: lwz r12, 80(r1)
+; SPE-NEXT: evldd r25, 24(r1) # 8-byte Folded Reload
+; SPE-NEXT: mtcrf 32, r12 # cr2
+; SPE-NEXT: lwz r0, 100(r1)
+; SPE-NEXT: addi r1, r1, 96
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ole", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -317,15 +771,53 @@ define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_one_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_one_s:
; SPE: # %bb.0:
-; SPE-NEXT: evmergelo r7, r7, r8
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: efdcmplt cr0, r5, r7
-; SPE-NEXT: bclr 12, gt, 0
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -96(r1)
+; SPE-NEXT: mfcr r12
+; SPE-NEXT: stw r0, 100(r1)
+; SPE-NEXT: stw r12, 80(r1)
+; SPE-NEXT: evstdd r25, 24(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r26, 32(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r27, 40(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r28, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT: stw r29, 84(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 88(r1) # 4-byte Folded Spill
+; SPE-NEXT: evmergelo r28, r7, r8
+; SPE-NEXT: evmergelo r27, r5, r6
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r26, r27, r27
+; SPE-NEXT: evmergehi r25, r28, r28
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: mr r3, r26
+; SPE-NEXT: mr r5, r25
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __ltdf2
+; SPE-NEXT: cmpwi cr2, r3, 0
+; SPE-NEXT: mr r3, r26
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: mr r5, r25
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __gtdf2
+; SPE-NEXT: bc 12, 4*cr2+lt, .LBB19_3
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efdcmpgt cr0, r5, r7
-; SPE-NEXT: bclr 12, gt, 0
+; SPE-NEXT: cmpwi r3, 0
+; SPE-NEXT: bc 12, gt, .LBB19_3
; SPE-NEXT: # %bb.2:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB19_3:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 88(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 84(r1) # 4-byte Folded Reload
+; SPE-NEXT: evldd r28, 48(r1) # 8-byte Folded Reload
+; SPE-NEXT: evldd r27, 40(r1) # 8-byte Folded Reload
+; SPE-NEXT: evldd r26, 32(r1) # 8-byte Folded Reload
+; SPE-NEXT: lwz r12, 80(r1)
+; SPE-NEXT: evldd r25, 24(r1) # 8-byte Folded Reload
+; SPE-NEXT: mtcrf 32, r12 # cr2
+; SPE-NEXT: lwz r0, 100(r1)
+; SPE-NEXT: addi r1, r1, 96
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"one", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -335,15 +827,40 @@ define i32 @test_f64_one_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_ord_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_ord_s:
; SPE: # %bb.0:
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: evmergelo r6, r7, r8
-; SPE-NEXT: efdcmpeq cr0, r6, r6
-; SPE-NEXT: bc 4, gt, .LBB20_2
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -80(r1)
+; SPE-NEXT: stw r0, 84(r1)
+; SPE-NEXT: stw r27, 60(r1) # 4-byte Folded Spill
+; SPE-NEXT: evstdd r28, 16(r1) # 8-byte Folded Spill
+; SPE-NEXT: stw r29, 68(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 72(r1) # 4-byte Folded Spill
+; SPE-NEXT: evmergelo r28, r5, r6
+; SPE-NEXT: evmergelo r4, r7, r8
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r3, r4, r4
+; SPE-NEXT: mr r6, r4
+; SPE-NEXT: mr r5, r3
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: mr r27, r3
+; SPE-NEXT: evmergehi r3, r28, r28
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: mr r5, r3
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: or. r3, r3, r27
+; SPE-NEXT: beq cr0, .LBB20_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efdcmpeq cr0, r5, r5
-; SPE-NEXT: bclr 12, gt, 0
+; SPE-NEXT: mr r30, r29
; SPE-NEXT: .LBB20_2:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload
+; SPE-NEXT: evldd r28, 16(r1) # 8-byte Folded Reload
+; SPE-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 84(r1)
+; SPE-NEXT: addi r1, r1, 80
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ord", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -353,17 +870,53 @@ define i32 @test_f64_ord_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_ueq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_ueq_s:
; SPE: # %bb.0:
-; SPE-NEXT: evmergelo r7, r7, r8
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: efdcmplt cr0, r5, r7
-; SPE-NEXT: bc 12, gt, .LBB21_3
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -96(r1)
+; SPE-NEXT: mfcr r12
+; SPE-NEXT: stw r0, 100(r1)
+; SPE-NEXT: stw r12, 80(r1)
+; SPE-NEXT: evstdd r25, 24(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r26, 32(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r27, 40(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r28, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT: stw r29, 84(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 88(r1) # 4-byte Folded Spill
+; SPE-NEXT: evmergelo r28, r7, r8
+; SPE-NEXT: evmergelo r27, r5, r6
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r26, r27, r27
+; SPE-NEXT: evmergehi r25, r28, r28
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: mr r3, r26
+; SPE-NEXT: mr r5, r25
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __ltdf2
+; SPE-NEXT: cmpwi cr2, r3, -1
+; SPE-NEXT: mr r3, r26
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: mr r5, r25
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __gtdf2
+; SPE-NEXT: bc 4, 4*cr2+gt, .LBB21_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efdcmpgt cr0, r5, r7
-; SPE-NEXT: bc 12, gt, .LBB21_3
-; SPE-NEXT: # %bb.2:
-; SPE-NEXT: mr r4, r3
+; SPE-NEXT: cmpwi r3, 1
+; SPE-NEXT: bc 12, lt, .LBB21_3
+; SPE-NEXT: .LBB21_2:
+; SPE-NEXT: mr r30, r29
; SPE-NEXT: .LBB21_3:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 88(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 84(r1) # 4-byte Folded Reload
+; SPE-NEXT: evldd r28, 48(r1) # 8-byte Folded Reload
+; SPE-NEXT: evldd r27, 40(r1) # 8-byte Folded Reload
+; SPE-NEXT: evldd r26, 32(r1) # 8-byte Folded Reload
+; SPE-NEXT: lwz r12, 80(r1)
+; SPE-NEXT: evldd r25, 24(r1) # 8-byte Folded Reload
+; SPE-NEXT: mtcrf 32, r12 # cr2
+; SPE-NEXT: lwz r0, 100(r1)
+; SPE-NEXT: addi r1, r1, 96
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ueq", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -373,18 +926,58 @@ define i32 @test_f64_ueq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_ugt_s:
; SPE: # %bb.0:
-; SPE-NEXT: evmergelo r7, r7, r8
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: efdcmpeq cr0, r5, r5
-; SPE-NEXT: bclr 4, gt, 0
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -96(r1)
+; SPE-NEXT: mfcr r12
+; SPE-NEXT: stw r0, 100(r1)
+; SPE-NEXT: stw r12, 80(r1)
+; SPE-NEXT: evstdd r25, 24(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r26, 32(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r27, 40(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r28, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT: stw r29, 84(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 88(r1) # 4-byte Folded Spill
+; SPE-NEXT: evmergelo r28, r7, r8
+; SPE-NEXT: evmergelo r27, r5, r6
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r26, r27, r27
+; SPE-NEXT: evmergehi r25, r28, r28
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: mr r3, r26
+; SPE-NEXT: mr r5, r25
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __gtdf2
+; SPE-NEXT: cmpwi cr2, r3, 0
+; SPE-NEXT: mr r3, r25
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: mr r5, r25
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __nedf2
+; SPE-NEXT: mr r28, r3
+; SPE-NEXT: mr r3, r26
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: mr r5, r26
+; SPE-NEXT: mr r6, r27
+; SPE-NEXT: bl __nedf2
+; SPE-NEXT: or. r3, r3, r28
+; SPE-NEXT: crorc 4*cr5+lt, 4*cr2+gt, eq
+; SPE-NEXT: bc 12, 4*cr5+lt, .LBB22_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efdcmpeq cr0, r7, r7
-; SPE-NEXT: bclr 4, gt, 0
-; SPE-NEXT: # %bb.2:
-; SPE-NEXT: efdcmpgt cr0, r5, r7
-; SPE-NEXT: bclr 12, gt, 0
-; SPE-NEXT: # %bb.3:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB22_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 88(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 84(r1) # 4-byte Folded Reload
+; SPE-NEXT: evldd r28, 48(r1) # 8-byte Folded Reload
+; SPE-NEXT: evldd r27, 40(r1) # 8-byte Folded Reload
+; SPE-NEXT: evldd r26, 32(r1) # 8-byte Folded Reload
+; SPE-NEXT: lwz r12, 80(r1)
+; SPE-NEXT: evldd r25, 24(r1) # 8-byte Folded Reload
+; SPE-NEXT: mtcrf 32, r12 # cr2
+; SPE-NEXT: lwz r0, 100(r1)
+; SPE-NEXT: addi r1, r1, 96
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ugt", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -394,14 +987,30 @@ define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_uge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_uge_s:
; SPE: # %bb.0:
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
; SPE-NEXT: evmergelo r7, r7, r8
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: efdcmplt cr0, r5, r7
-; SPE-NEXT: bc 12, gt, .LBB23_2
+; SPE-NEXT: evmergelo r4, r5, r6
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r3, r4, r4
+; SPE-NEXT: evmergehi r5, r7, r7
+; SPE-NEXT: mr r6, r7
+; SPE-NEXT: bl __ltdf2
+; SPE-NEXT: cmpwi r3, 0
+; SPE-NEXT: bge cr0, .LBB23_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: mr r4, r3
+; SPE-NEXT: mr r30, r29
; SPE-NEXT: .LBB23_2:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"uge", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -411,18 +1020,58 @@ define i32 @test_f64_uge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_ult_s:
; SPE: # %bb.0:
-; SPE-NEXT: evmergelo r7, r7, r8
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: efdcmpeq cr0, r5, r5
-; SPE-NEXT: bclr 4, gt, 0
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -96(r1)
+; SPE-NEXT: mfcr r12
+; SPE-NEXT: stw r0, 100(r1)
+; SPE-NEXT: stw r12, 80(r1)
+; SPE-NEXT: evstdd r25, 24(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r26, 32(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r27, 40(r1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd r28, 48(r1) # 8-byte Folded Spill
+; SPE-NEXT: stw r29, 84(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 88(r1) # 4-byte Folded Spill
+; SPE-NEXT: evmergelo r28, r7, r8
+; SPE-NEXT: evmergelo r27, r5, r6
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r26, r27, r27
+; SPE-NEXT: evmergehi r25, r28, r28
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: mr r3, r26
+; SPE-NEXT: mr r5, r25
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __ltdf2
+; SPE-NEXT: cmpwi cr2, r3, 0
+; SPE-NEXT: mr r3, r25
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: mr r5, r25
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __nedf2
+; SPE-NEXT: mr r28, r3
+; SPE-NEXT: mr r3, r26
+; SPE-NEXT: mr r4, r27
+; SPE-NEXT: mr r5, r26
+; SPE-NEXT: mr r6, r27
+; SPE-NEXT: bl __nedf2
+; SPE-NEXT: or. r3, r3, r28
+; SPE-NEXT: crorc 4*cr5+lt, 4*cr2+lt, eq
+; SPE-NEXT: bc 12, 4*cr5+lt, .LBB24_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efdcmpeq cr0, r7, r7
-; SPE-NEXT: bclr 4, gt, 0
-; SPE-NEXT: # %bb.2:
-; SPE-NEXT: efdcmplt cr0, r5, r7
-; SPE-NEXT: bclr 12, gt, 0
-; SPE-NEXT: # %bb.3:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB24_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 88(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 84(r1) # 4-byte Folded Reload
+; SPE-NEXT: evldd r28, 48(r1) # 8-byte Folded Reload
+; SPE-NEXT: evldd r27, 40(r1) # 8-byte Folded Reload
+; SPE-NEXT: evldd r26, 32(r1) # 8-byte Folded Reload
+; SPE-NEXT: lwz r12, 80(r1)
+; SPE-NEXT: evldd r25, 24(r1) # 8-byte Folded Reload
+; SPE-NEXT: mtcrf 32, r12 # cr2
+; SPE-NEXT: lwz r0, 100(r1)
+; SPE-NEXT: addi r1, r1, 96
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ult", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -432,14 +1081,30 @@ define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_ule_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_ule_s:
; SPE: # %bb.0:
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
; SPE-NEXT: evmergelo r7, r7, r8
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: efdcmpgt cr0, r5, r7
-; SPE-NEXT: bc 12, gt, .LBB25_2
+; SPE-NEXT: evmergelo r4, r5, r6
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r3, r4, r4
+; SPE-NEXT: evmergehi r5, r7, r7
+; SPE-NEXT: mr r6, r7
+; SPE-NEXT: bl __gtdf2
+; SPE-NEXT: cmpwi r3, 0
+; SPE-NEXT: ble cr0, .LBB25_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: mr r4, r3
+; SPE-NEXT: mr r30, r29
; SPE-NEXT: .LBB25_2:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"ule", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -449,14 +1114,30 @@ define i32 @test_f64_ule_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_une_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_une_s:
; SPE: # %bb.0:
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -32(r1)
+; SPE-NEXT: stw r0, 36(r1)
+; SPE-NEXT: stw r29, 20(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 24(r1) # 4-byte Folded Spill
; SPE-NEXT: evmergelo r7, r7, r8
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: efdcmpeq cr0, r5, r7
-; SPE-NEXT: bc 12, gt, .LBB26_2
+; SPE-NEXT: evmergelo r4, r5, r6
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r3, r4, r4
+; SPE-NEXT: evmergehi r5, r7, r7
+; SPE-NEXT: mr r6, r7
+; SPE-NEXT: bl __nedf2
+; SPE-NEXT: cmplwi r3, 0
+; SPE-NEXT: bne cr0, .LBB26_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: mr r4, r3
+; SPE-NEXT: mr r30, r29
; SPE-NEXT: .LBB26_2:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 24(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 20(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 36(r1)
+; SPE-NEXT: addi r1, r1, 32
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"une", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
@@ -466,15 +1147,40 @@ define i32 @test_f64_une_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
define i32 @test_f64_uno_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
; SPE-LABEL: test_f64_uno_s:
; SPE: # %bb.0:
-; SPE-NEXT: evmergelo r7, r7, r8
-; SPE-NEXT: evmergelo r5, r5, r6
-; SPE-NEXT: efdcmpeq cr0, r5, r5
-; SPE-NEXT: bclr 4, gt, 0
+; SPE-NEXT: mflr r0
+; SPE-NEXT: stwu r1, -80(r1)
+; SPE-NEXT: stw r0, 84(r1)
+; SPE-NEXT: stw r27, 60(r1) # 4-byte Folded Spill
+; SPE-NEXT: evstdd r28, 16(r1) # 8-byte Folded Spill
+; SPE-NEXT: stw r29, 68(r1) # 4-byte Folded Spill
+; SPE-NEXT: mr r29, r4
+; SPE-NEXT: stw r30, 72(r1) # 4-byte Folded Spill
+; SPE-NEXT: evmergelo r28, r5, r6
+; SPE-NEXT: evmergelo r4, r7, r8
+; SPE-NEXT: mr r30, r3
+; SPE-NEXT: evmergehi r3, r4, r4
+; SPE-NEXT: mr r6, r4
+; SPE-NEXT: mr r5, r3
+; SPE-NEXT: bl __nedf2
+; SPE-NEXT: mr r27, r3
+; SPE-NEXT: evmergehi r3, r28, r28
+; SPE-NEXT: mr r4, r28
+; SPE-NEXT: mr r5, r3
+; SPE-NEXT: mr r6, r28
+; SPE-NEXT: bl __nedf2
+; SPE-NEXT: or. r3, r3, r27
+; SPE-NEXT: bne cr0, .LBB27_2
; SPE-NEXT: # %bb.1:
-; SPE-NEXT: efdcmpeq cr0, r7, r7
-; SPE-NEXT: bclr 4, gt, 0
-; SPE-NEXT: # %bb.2:
-; SPE-NEXT: mr r3, r4
+; SPE-NEXT: mr r30, r29
+; SPE-NEXT: .LBB27_2:
+; SPE-NEXT: mr r3, r30
+; SPE-NEXT: lwz r30, 72(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r29, 68(r1) # 4-byte Folded Reload
+; SPE-NEXT: evldd r28, 16(r1) # 8-byte Folded Reload
+; SPE-NEXT: lwz r27, 60(r1) # 4-byte Folded Reload
+; SPE-NEXT: lwz r0, 84(r1)
+; SPE-NEXT: addi r1, r1, 80
+; SPE-NEXT: mtlr r0
; SPE-NEXT: blr
%cond = call i1 @llvm.experimental.constrained.fcmps.f64(double %f1, double %f2, metadata !"uno", metadata !"fpexcept.strict") #0
%res = select i1 %cond, i32 %a, i32 %b
diff --git a/llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll b/llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
index 1e109d0ea4a7f..604123c1aa48f 100644
--- a/llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
+++ b/llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll
@@ -8,20 +8,48 @@
define void @test_fcmpueq_legalize_br_cc_with_invert(float %a) {
; CHECK-LABEL: test_fcmpueq_legalize_br_cc_with_invert:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lis 4, .LCPI0_0 at ha
-; CHECK-NEXT: lwz 4, .LCPI0_0 at l(4)
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stwu 1, -32(1)
+; CHECK-NEXT: stw 0, 36(1)
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: .cfi_offset lr, 4
+; CHECK-NEXT: .cfi_offset r28, -16
+; CHECK-NEXT: .cfi_offset r29, -12
+; CHECK-NEXT: .cfi_offset r30, -8
+; CHECK-NEXT: stw 30, 24(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 30, 3
+; CHECK-NEXT: lis 3, .LCPI0_0 at ha
+; CHECK-NEXT: stw 29, 20(1) # 4-byte Folded Spill
+; CHECK-NEXT: lwz 29, .LCPI0_0 at l(3)
+; CHECK-NEXT: stw 28, 16(1) # 4-byte Folded Spill
+; CHECK-NEXT: b .LBB0_2
; CHECK-NEXT: .LBB0_1: # %l1
; CHECK-NEXT: #
-; CHECK-NEXT: efscmplt 7, 3, 4
-; CHECK-NEXT: efscmpgt 0, 3, 4
-; CHECK-NEXT: mfcr 5 # cr7
-; CHECK-NEXT: mcrf 7, 0
-; CHECK-NEXT: mfcr 6 # cr7
-; CHECK-NEXT: rlwinm 5, 5, 30, 31, 31
-; CHECK-NEXT: rlwinm 6, 6, 30, 31, 31
-; CHECK-NEXT: or. 5, 6, 5
-; CHECK-NEXT: beq 0, .LBB0_1
-; CHECK-NEXT: # %bb.2: # %l2
+; CHECK-NEXT: mr 3, 30
+; CHECK-NEXT: mr 4, 29
+; CHECK-NEXT: bl __ltsf2
+; CHECK-NEXT: srwi 3, 3, 31
+; CHECK-NEXT: or. 3, 28, 3
+; CHECK-NEXT: bne 0, .LBB0_4
+; CHECK-NEXT: .LBB0_2: # %l1
+; CHECK-NEXT: #
+; CHECK-NEXT: mr 3, 30
+; CHECK-NEXT: mr 4, 29
+; CHECK-NEXT: bl __gtsf2
+; CHECK-NEXT: cmpwi 3, 0
+; CHECK-NEXT: li 28, 1
+; CHECK-NEXT: bgt 0, .LBB0_1
+; CHECK-NEXT: # %bb.3: # %l1
+; CHECK-NEXT: #
+; CHECK-NEXT: li 28, 0
+; CHECK-NEXT: b .LBB0_1
+; CHECK-NEXT: .LBB0_4: # %l2
+; CHECK-NEXT: lwz 30, 24(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 29, 20(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 28, 16(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 0, 36(1)
+; CHECK-NEXT: addi 1, 1, 32
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
br label %l1
diff --git a/llvm/test/CodeGen/PowerPC/spe.ll b/llvm/test/CodeGen/PowerPC/spe.ll
index b9df47d6d6452..47df95423ce7c 100644
--- a/llvm/test/CodeGen/PowerPC/spe.ll
+++ b/llvm/test/CodeGen/PowerPC/spe.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
-; RUN: -mattr=+spe | FileCheck %s -check-prefixes=CHECK,SPE
+; RUN: -mattr=+spe | FileCheck %s -check-prefixes=CHECK,SPE
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
-; RUN: -mattr=+efpu2 | FileCheck %s -check-prefixes=CHECK,EFPU2
+; RUN: -mattr=+efpu2 | FileCheck %s -check-prefixes=CHECK,EFPU2
; single tests (identical for -mattr=+spe and -mattr=+efpu2)
@@ -82,8 +82,11 @@ define float @test_fneg(float %a) #0 {
define i32 @test_fcmpgt(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpgt:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -16(1)
-; CHECK-NEXT: efscmpgt 0, 3, 4
+; CHECK-NEXT: stw 0, 20(1)
+; CHECK-NEXT: bl __gtsf2
+; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: ble 0, .LBB7_2
; CHECK-NEXT: # %bb.1: # %tr
; CHECK-NEXT: li 3, 1
@@ -93,7 +96,9 @@ define i32 @test_fcmpgt(float %a, float %b) #0 {
; CHECK-NEXT: .LBB7_3: # %ret
; CHECK-NEXT: stw 3, 12(1)
; CHECK-NEXT: lwz 3, 12(1)
+; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = alloca i32, align 4
@@ -113,24 +118,42 @@ ret:
define i32 @test_fcmpugt(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpugt:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: stwu 1, -16(1)
-; CHECK-NEXT: efscmpeq 0, 4, 4
-; CHECK-NEXT: bc 4, 1, .LBB8_4
-; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: efscmpeq 0, 3, 3
-; CHECK-NEXT: bc 4, 1, .LBB8_4
-; CHECK-NEXT: # %bb.2: # %entry
-; CHECK-NEXT: efscmpgt 0, 3, 4
-; CHECK-NEXT: bc 12, 1, .LBB8_4
-; CHECK-NEXT: # %bb.3: # %fa
-; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: b .LBB8_5
-; CHECK-NEXT: .LBB8_4: # %tr
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stwu 1, -48(1)
+; CHECK-NEXT: mfcr 12
+; CHECK-NEXT: stw 0, 52(1)
+; CHECK-NEXT: stw 12, 32(1)
+; CHECK-NEXT: stw 29, 36(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 29, 3
+; CHECK-NEXT: stw 30, 40(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 30, 4
+; CHECK-NEXT: bl __lesf2
+; CHECK-NEXT: cmpwi 2, 3, 1
+; CHECK-NEXT: mr 3, 30
+; CHECK-NEXT: mr 4, 30
+; CHECK-NEXT: bl __eqsf2
+; CHECK-NEXT: mr 30, 3
+; CHECK-NEXT: mr 3, 29
+; CHECK-NEXT: mr 4, 29
+; CHECK-NEXT: bl __eqsf2
+; CHECK-NEXT: or. 3, 3, 30
+; CHECK-NEXT: crand 20, 8, 2
+; CHECK-NEXT: bc 12, 20, .LBB8_2
+; CHECK-NEXT: # %bb.1: # %tr
; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: .LBB8_5: # %ret
-; CHECK-NEXT: stw 3, 12(1)
-; CHECK-NEXT: lwz 3, 12(1)
-; CHECK-NEXT: addi 1, 1, 16
+; CHECK-NEXT: b .LBB8_3
+; CHECK-NEXT: .LBB8_2: # %fa
+; CHECK-NEXT: li 3, 0
+; CHECK-NEXT: .LBB8_3: # %ret
+; CHECK-NEXT: stw 3, 28(1)
+; CHECK-NEXT: lwz 3, 28(1)
+; CHECK-NEXT: lwz 30, 40(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 12, 32(1)
+; CHECK-NEXT: lwz 29, 36(1) # 4-byte Folded Reload
+; CHECK-NEXT: mtcrf 32, 12 # cr2
+; CHECK-NEXT: lwz 0, 52(1)
+; CHECK-NEXT: addi 1, 1, 48
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = alloca i32, align 4
@@ -150,24 +173,42 @@ ret:
define i32 @test_fcmple(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmple:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: stwu 1, -16(1)
-; CHECK-NEXT: efscmpeq 0, 3, 3
-; CHECK-NEXT: bc 4, 1, .LBB9_4
-; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: efscmpeq 0, 4, 4
-; CHECK-NEXT: bc 4, 1, .LBB9_4
-; CHECK-NEXT: # %bb.2: # %entry
-; CHECK-NEXT: efscmpgt 0, 3, 4
-; CHECK-NEXT: bc 12, 1, .LBB9_4
-; CHECK-NEXT: # %bb.3: # %tr
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stwu 1, -48(1)
+; CHECK-NEXT: mfcr 12
+; CHECK-NEXT: stw 0, 52(1)
+; CHECK-NEXT: stw 12, 32(1)
+; CHECK-NEXT: stw 29, 36(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 29, 3
+; CHECK-NEXT: stw 30, 40(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 30, 4
+; CHECK-NEXT: bl __gtsf2
+; CHECK-NEXT: cmpwi 2, 3, 0
+; CHECK-NEXT: mr 3, 30
+; CHECK-NEXT: mr 4, 30
+; CHECK-NEXT: bl __nesf2
+; CHECK-NEXT: mr 30, 3
+; CHECK-NEXT: mr 3, 29
+; CHECK-NEXT: mr 4, 29
+; CHECK-NEXT: bl __nesf2
+; CHECK-NEXT: or. 3, 3, 30
+; CHECK-NEXT: crorc 20, 9, 2
+; CHECK-NEXT: bc 12, 20, .LBB9_2
+; CHECK-NEXT: # %bb.1: # %tr
; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: b .LBB9_5
-; CHECK-NEXT: .LBB9_4: # %fa
+; CHECK-NEXT: b .LBB9_3
+; CHECK-NEXT: .LBB9_2: # %fa
; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: .LBB9_5: # %ret
-; CHECK-NEXT: stw 3, 12(1)
-; CHECK-NEXT: lwz 3, 12(1)
-; CHECK-NEXT: addi 1, 1, 16
+; CHECK-NEXT: .LBB9_3: # %ret
+; CHECK-NEXT: stw 3, 28(1)
+; CHECK-NEXT: lwz 3, 28(1)
+; CHECK-NEXT: lwz 30, 40(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 12, 32(1)
+; CHECK-NEXT: lwz 29, 36(1) # 4-byte Folded Reload
+; CHECK-NEXT: mtcrf 32, 12 # cr2
+; CHECK-NEXT: lwz 0, 52(1)
+; CHECK-NEXT: addi 1, 1, 48
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = alloca i32, align 4
@@ -187,8 +228,11 @@ ret:
define i32 @test_fcmpule(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpule:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -16(1)
-; CHECK-NEXT: efscmpgt 0, 3, 4
+; CHECK-NEXT: stw 0, 20(1)
+; CHECK-NEXT: bl __gtsf2
+; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: bgt 0, .LBB10_2
; CHECK-NEXT: # %bb.1: # %tr
; CHECK-NEXT: li 3, 1
@@ -198,7 +242,9 @@ define i32 @test_fcmpule(float %a, float %b) #0 {
; CHECK-NEXT: .LBB10_3: # %ret
; CHECK-NEXT: stw 3, 12(1)
; CHECK-NEXT: lwz 3, 12(1)
+; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = alloca i32, align 4
@@ -219,9 +265,12 @@ ret:
define i32 @test_fcmpeq(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpeq:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -16(1)
-; CHECK-NEXT: efscmpeq 0, 3, 4
-; CHECK-NEXT: ble 0, .LBB11_2
+; CHECK-NEXT: stw 0, 20(1)
+; CHECK-NEXT: bl __nesf2
+; CHECK-NEXT: cmplwi 3, 0
+; CHECK-NEXT: bne 0, .LBB11_2
; CHECK-NEXT: # %bb.1: # %tr
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: b .LBB11_3
@@ -230,7 +279,9 @@ define i32 @test_fcmpeq(float %a, float %b) #0 {
; CHECK-NEXT: .LBB11_3: # %ret
; CHECK-NEXT: stw 3, 12(1)
; CHECK-NEXT: lwz 3, 12(1)
+; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = alloca i32, align 4
@@ -251,14 +302,27 @@ ret:
define i1 @test_fcmpuno(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpuno:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: efscmpeq 0, 3, 3
-; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: bc 4, 1, .LBB12_2
-; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: efscmpeq 0, 4, 4
-; CHECK-NEXT: bclr 12, 1, 0
-; CHECK-NEXT: .LBB12_2: # %entry
-; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stwu 1, -32(1)
+; CHECK-NEXT: stw 0, 36(1)
+; CHECK-NEXT: stw 30, 24(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 30, 3
+; CHECK-NEXT: mr 3, 4
+; CHECK-NEXT: stw 29, 20(1) # 4-byte Folded Spill
+; CHECK-NEXT: bl __nesf2
+; CHECK-NEXT: mr 29, 3
+; CHECK-NEXT: mr 3, 30
+; CHECK-NEXT: mr 4, 30
+; CHECK-NEXT: bl __nesf2
+; CHECK-NEXT: or 3, 3, 29
+; CHECK-NEXT: cntlzw 3, 3
+; CHECK-NEXT: not 3, 3
+; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT: lwz 30, 24(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 29, 20(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 0, 36(1)
+; CHECK-NEXT: addi 1, 1, 32
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = fcmp uno float %a, %b
@@ -268,15 +332,26 @@ define i1 @test_fcmpuno(float %a, float %b) #0 {
define i1 @test_fcmpord(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpord:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: mr 5, 3
-; CHECK-NEXT: efscmpeq 0, 4, 4
-; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: bclr 4, 1, 0
-; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: efscmpeq 0, 5, 5
-; CHECK-NEXT: bclr 4, 1, 0
-; CHECK-NEXT: # %bb.2: # %entry
-; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stwu 1, -32(1)
+; CHECK-NEXT: stw 0, 36(1)
+; CHECK-NEXT: stw 30, 24(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 30, 3
+; CHECK-NEXT: mr 3, 4
+; CHECK-NEXT: stw 29, 20(1) # 4-byte Folded Spill
+; CHECK-NEXT: bl __eqsf2
+; CHECK-NEXT: mr 29, 3
+; CHECK-NEXT: mr 3, 30
+; CHECK-NEXT: mr 4, 30
+; CHECK-NEXT: bl __eqsf2
+; CHECK-NEXT: or 3, 3, 29
+; CHECK-NEXT: cntlzw 3, 3
+; CHECK-NEXT: rlwinm 3, 3, 27, 31, 31
+; CHECK-NEXT: lwz 30, 24(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 29, 20(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 0, 36(1)
+; CHECK-NEXT: addi 1, 1, 32
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = fcmp ord float %a, %b
@@ -286,15 +361,36 @@ define i1 @test_fcmpord(float %a, float %b) #0 {
define i1 @test_fcmpueq(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpueq:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: mr 5, 3
-; CHECK-NEXT: efscmpgt 0, 3, 4
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stwu 1, -32(1)
+; CHECK-NEXT: mfcr 12
+; CHECK-NEXT: stw 0, 36(1)
+; CHECK-NEXT: stw 12, 16(1)
+; CHECK-NEXT: stw 29, 20(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 29, 3
+; CHECK-NEXT: stw 30, 24(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 30, 4
+; CHECK-NEXT: bl __ltsf2
+; CHECK-NEXT: cmpwi 2, 3, -1
+; CHECK-NEXT: mr 3, 29
+; CHECK-NEXT: mr 4, 30
+; CHECK-NEXT: bl __gtsf2
+; CHECK-NEXT: mr 4, 3
; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: bclr 12, 1, 0
+; CHECK-NEXT: bc 4, 9, .LBB14_3
; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: efscmplt 0, 5, 4
-; CHECK-NEXT: bclr 12, 1, 0
+; CHECK-NEXT: cmpwi 4, 1
+; CHECK-NEXT: bc 4, 0, .LBB14_3
; CHECK-NEXT: # %bb.2: # %entry
; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: .LBB14_3: # %entry
+; CHECK-NEXT: lwz 30, 24(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 12, 16(1)
+; CHECK-NEXT: lwz 29, 20(1) # 4-byte Folded Reload
+; CHECK-NEXT: mtcrf 32, 12 # cr2
+; CHECK-NEXT: lwz 0, 36(1)
+; CHECK-NEXT: addi 1, 1, 32
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = fcmp ueq float %a, %b
@@ -304,15 +400,36 @@ define i1 @test_fcmpueq(float %a, float %b) #0 {
define i1 @test_fcmpne(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpne:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: mr 5, 3
-; CHECK-NEXT: efscmplt 0, 3, 4
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stwu 1, -32(1)
+; CHECK-NEXT: mfcr 12
+; CHECK-NEXT: stw 0, 36(1)
+; CHECK-NEXT: stw 12, 16(1)
+; CHECK-NEXT: stw 29, 20(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 29, 3
+; CHECK-NEXT: stw 30, 24(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 30, 4
+; CHECK-NEXT: bl __ltsf2
+; CHECK-NEXT: cmpwi 2, 3, 0
+; CHECK-NEXT: mr 3, 29
+; CHECK-NEXT: mr 4, 30
+; CHECK-NEXT: bl __gtsf2
+; CHECK-NEXT: mr 4, 3
; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: bc 12, 1, .LBB15_2
+; CHECK-NEXT: bc 12, 8, .LBB15_2
; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: efscmpgt 0, 5, 4
-; CHECK-NEXT: bclr 4, 1, 0
+; CHECK-NEXT: cmpwi 4, 0
+; CHECK-NEXT: bc 4, 1, .LBB15_3
; CHECK-NEXT: .LBB15_2: # %entry
; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: .LBB15_3: # %entry
+; CHECK-NEXT: lwz 30, 24(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 12, 16(1)
+; CHECK-NEXT: lwz 29, 20(1) # 4-byte Folded Reload
+; CHECK-NEXT: mtcrf 32, 12 # cr2
+; CHECK-NEXT: lwz 0, 36(1)
+; CHECK-NEXT: addi 1, 1, 32
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = fcmp one float %a, %b
@@ -322,9 +439,12 @@ define i1 @test_fcmpne(float %a, float %b) #0 {
define i32 @test_fcmpune(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpune:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -16(1)
-; CHECK-NEXT: efscmpeq 0, 3, 4
-; CHECK-NEXT: bgt 0, .LBB16_2
+; CHECK-NEXT: stw 0, 20(1)
+; CHECK-NEXT: bl __eqsf2
+; CHECK-NEXT: cmplwi 3, 0
+; CHECK-NEXT: beq 0, .LBB16_2
; CHECK-NEXT: # %bb.1: # %tr
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: b .LBB16_3
@@ -333,7 +453,9 @@ define i32 @test_fcmpune(float %a, float %b) #0 {
; CHECK-NEXT: .LBB16_3: # %ret
; CHECK-NEXT: stw 3, 12(1)
; CHECK-NEXT: lwz 3, 12(1)
+; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = alloca i32, align 4
@@ -353,9 +475,12 @@ ret:
define i32 @test_fcmplt(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmplt:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -16(1)
-; CHECK-NEXT: efscmplt 0, 3, 4
-; CHECK-NEXT: ble 0, .LBB17_2
+; CHECK-NEXT: stw 0, 20(1)
+; CHECK-NEXT: bl __ltsf2
+; CHECK-NEXT: cmpwi 3, 0
+; CHECK-NEXT: bge 0, .LBB17_2
; CHECK-NEXT: # %bb.1: # %tr
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: b .LBB17_3
@@ -364,7 +489,9 @@ define i32 @test_fcmplt(float %a, float %b) #0 {
; CHECK-NEXT: .LBB17_3: # %ret
; CHECK-NEXT: stw 3, 12(1)
; CHECK-NEXT: lwz 3, 12(1)
+; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = alloca i32, align 4
@@ -384,18 +511,38 @@ ret:
define i1 @test_fcmpult(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpult:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: mr 5, 3
-; CHECK-NEXT: efscmpeq 0, 3, 3
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stwu 1, -32(1)
+; CHECK-NEXT: mfcr 12
+; CHECK-NEXT: stw 0, 36(1)
+; CHECK-NEXT: stw 12, 16(1)
+; CHECK-NEXT: stw 29, 20(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 29, 3
+; CHECK-NEXT: stw 30, 24(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 30, 4
+; CHECK-NEXT: bl __ltsf2
+; CHECK-NEXT: cmpwi 2, 3, 0
+; CHECK-NEXT: mr 3, 30
+; CHECK-NEXT: mr 4, 30
+; CHECK-NEXT: bl __nesf2
+; CHECK-NEXT: mr 30, 3
+; CHECK-NEXT: mr 3, 29
+; CHECK-NEXT: mr 4, 29
+; CHECK-NEXT: bl __nesf2
+; CHECK-NEXT: or. 3, 3, 30
+; CHECK-NEXT: crandc 20, 2, 8
; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: bc 4, 1, .LBB18_3
+; CHECK-NEXT: bc 12, 20, .LBB18_2
; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: efscmpeq 0, 4, 4
-; CHECK-NEXT: bc 4, 1, .LBB18_3
-; CHECK-NEXT: # %bb.2: # %entry
-; CHECK-NEXT: efscmplt 0, 5, 4
-; CHECK-NEXT: bclr 4, 1, 0
-; CHECK-NEXT: .LBB18_3: # %entry
; CHECK-NEXT: li 3, 1
+; CHECK-NEXT: .LBB18_2: # %entry
+; CHECK-NEXT: lwz 30, 24(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 12, 16(1)
+; CHECK-NEXT: lwz 29, 20(1) # 4-byte Folded Reload
+; CHECK-NEXT: mtcrf 32, 12 # cr2
+; CHECK-NEXT: lwz 0, 36(1)
+; CHECK-NEXT: addi 1, 1, 32
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = fcmp ult float %a, %b
@@ -405,24 +552,42 @@ define i1 @test_fcmpult(float %a, float %b) #0 {
define i32 @test_fcmpge(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpge:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: stwu 1, -16(1)
-; CHECK-NEXT: efscmpeq 0, 3, 3
-; CHECK-NEXT: bc 4, 1, .LBB19_4
-; CHECK-NEXT: # %bb.1: # %entry
-; CHECK-NEXT: efscmpeq 0, 4, 4
-; CHECK-NEXT: bc 4, 1, .LBB19_4
-; CHECK-NEXT: # %bb.2: # %entry
-; CHECK-NEXT: efscmplt 0, 3, 4
-; CHECK-NEXT: bc 12, 1, .LBB19_4
-; CHECK-NEXT: # %bb.3: # %tr
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stwu 1, -48(1)
+; CHECK-NEXT: mfcr 12
+; CHECK-NEXT: stw 0, 52(1)
+; CHECK-NEXT: stw 12, 32(1)
+; CHECK-NEXT: stw 29, 36(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 29, 3
+; CHECK-NEXT: stw 30, 40(1) # 4-byte Folded Spill
+; CHECK-NEXT: mr 30, 4
+; CHECK-NEXT: bl __ltsf2
+; CHECK-NEXT: cmpwi 2, 3, 0
+; CHECK-NEXT: mr 3, 30
+; CHECK-NEXT: mr 4, 30
+; CHECK-NEXT: bl __nesf2
+; CHECK-NEXT: mr 30, 3
+; CHECK-NEXT: mr 3, 29
+; CHECK-NEXT: mr 4, 29
+; CHECK-NEXT: bl __nesf2
+; CHECK-NEXT: or. 3, 3, 30
+; CHECK-NEXT: crorc 20, 8, 2
+; CHECK-NEXT: bc 12, 20, .LBB19_2
+; CHECK-NEXT: # %bb.1: # %tr
; CHECK-NEXT: li 3, 1
-; CHECK-NEXT: b .LBB19_5
-; CHECK-NEXT: .LBB19_4: # %fa
+; CHECK-NEXT: b .LBB19_3
+; CHECK-NEXT: .LBB19_2: # %fa
; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: .LBB19_5: # %ret
-; CHECK-NEXT: stw 3, 12(1)
-; CHECK-NEXT: lwz 3, 12(1)
-; CHECK-NEXT: addi 1, 1, 16
+; CHECK-NEXT: .LBB19_3: # %ret
+; CHECK-NEXT: stw 3, 28(1)
+; CHECK-NEXT: lwz 3, 28(1)
+; CHECK-NEXT: lwz 30, 40(1) # 4-byte Folded Reload
+; CHECK-NEXT: lwz 12, 32(1)
+; CHECK-NEXT: lwz 29, 36(1) # 4-byte Folded Reload
+; CHECK-NEXT: mtcrf 32, 12 # cr2
+; CHECK-NEXT: lwz 0, 52(1)
+; CHECK-NEXT: addi 1, 1, 48
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = alloca i32, align 4
@@ -442,9 +607,12 @@ ret:
define i32 @test_fcmpuge(float %a, float %b) #0 {
; CHECK-LABEL: test_fcmpuge:
; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -16(1)
-; CHECK-NEXT: efscmplt 0, 3, 4
-; CHECK-NEXT: bgt 0, .LBB20_2
+; CHECK-NEXT: stw 0, 20(1)
+; CHECK-NEXT: bl __ltsf2
+; CHECK-NEXT: cmpwi 3, 0
+; CHECK-NEXT: blt 0, .LBB20_2
; CHECK-NEXT: # %bb.1: # %tr
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: b .LBB20_3
@@ -453,7 +621,9 @@ define i32 @test_fcmpuge(float %a, float %b) #0 {
; CHECK-NEXT: .LBB20_3: # %ret
; CHECK-NEXT: stw 3, 12(1)
; CHECK-NEXT: lwz 3, 12(1)
+; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
+; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
%r = alloca i32, align 4
@@ -740,16 +910,32 @@ define double @test_stod(float %a) #0 {
define i1 @test_dcmpuno(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpuno:
; SPE: # %bb.0: # %entry
-; SPE-NEXT: evmergelo 5, 5, 6
-; SPE-NEXT: evmergelo 3, 3, 4
-; SPE-NEXT: efdcmpeq 0, 3, 3
-; SPE-NEXT: li 3, 0
-; SPE-NEXT: bc 4, 1, .LBB35_2
-; SPE-NEXT: # %bb.1: # %entry
-; SPE-NEXT: efdcmpeq 0, 5, 5
-; SPE-NEXT: bclr 12, 1, 0
-; SPE-NEXT: .LBB35_2: # %entry
-; SPE-NEXT: li 3, 1
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -48(1)
+; SPE-NEXT: stw 0, 52(1)
+; SPE-NEXT: stw 29, 36(1) # 4-byte Folded Spill
+; SPE-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill
+; SPE-NEXT: evmergelo 30, 3, 4
+; SPE-NEXT: evmergelo 4, 5, 6
+; SPE-NEXT: evmergehi 3, 4, 4
+; SPE-NEXT: mr 6, 4
+; SPE-NEXT: mr 5, 3
+; SPE-NEXT: bl __nedf2
+; SPE-NEXT: mr 29, 3
+; SPE-NEXT: evmergehi 3, 30, 30
+; SPE-NEXT: mr 4, 30
+; SPE-NEXT: mr 5, 3
+; SPE-NEXT: mr 6, 30
+; SPE-NEXT: bl __nedf2
+; SPE-NEXT: or 3, 3, 29
+; SPE-NEXT: cntlzw 3, 3
+; SPE-NEXT: not 3, 3
+; SPE-NEXT: rlwinm 3, 3, 27, 31, 31
+; SPE-NEXT: evldd 30, 16(1) # 8-byte Folded Reload
+; SPE-NEXT: lwz 29, 36(1) # 4-byte Folded Reload
+; SPE-NEXT: lwz 0, 52(1)
+; SPE-NEXT: addi 1, 1, 48
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmpuno:
@@ -773,16 +959,31 @@ define i1 @test_dcmpuno(double %a, double %b) #0 {
define i1 @test_dcmpord(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpord:
; SPE: # %bb.0: # %entry
-; SPE-NEXT: evmergelo 4, 3, 4
-; SPE-NEXT: evmergelo 3, 5, 6
-; SPE-NEXT: efdcmpeq 0, 3, 3
-; SPE-NEXT: li 3, 0
-; SPE-NEXT: bclr 4, 1, 0
-; SPE-NEXT: # %bb.1: # %entry
-; SPE-NEXT: efdcmpeq 0, 4, 4
-; SPE-NEXT: bclr 4, 1, 0
-; SPE-NEXT: # %bb.2: # %entry
-; SPE-NEXT: li 3, 1
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -48(1)
+; SPE-NEXT: stw 0, 52(1)
+; SPE-NEXT: stw 29, 36(1) # 4-byte Folded Spill
+; SPE-NEXT: evstdd 30, 16(1) # 8-byte Folded Spill
+; SPE-NEXT: evmergelo 30, 3, 4
+; SPE-NEXT: evmergelo 4, 5, 6
+; SPE-NEXT: evmergehi 3, 4, 4
+; SPE-NEXT: mr 6, 4
+; SPE-NEXT: mr 5, 3
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: mr 29, 3
+; SPE-NEXT: evmergehi 3, 30, 30
+; SPE-NEXT: mr 4, 30
+; SPE-NEXT: mr 5, 3
+; SPE-NEXT: mr 6, 30
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: or 3, 3, 29
+; SPE-NEXT: cntlzw 3, 3
+; SPE-NEXT: rlwinm 3, 3, 27, 31, 31
+; SPE-NEXT: evldd 30, 16(1) # 8-byte Folded Reload
+; SPE-NEXT: lwz 29, 36(1) # 4-byte Folded Reload
+; SPE-NEXT: lwz 0, 52(1)
+; SPE-NEXT: addi 1, 1, 48
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmpord:
@@ -805,10 +1006,15 @@ define i1 @test_dcmpord(double %a, double %b) #0 {
define i32 @test_dcmpgt(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpgt:
; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
; SPE-NEXT: stwu 1, -16(1)
-; SPE-NEXT: evmergelo 5, 5, 6
-; SPE-NEXT: evmergelo 3, 3, 4
-; SPE-NEXT: efdcmpgt 0, 3, 5
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: evmergelo 6, 5, 6
+; SPE-NEXT: evmergelo 4, 3, 4
+; SPE-NEXT: evmergehi 3, 4, 4
+; SPE-NEXT: evmergehi 5, 6, 6
+; SPE-NEXT: bl __gtdf2
+; SPE-NEXT: cmpwi 3, 0
; SPE-NEXT: ble 0, .LBB37_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
@@ -818,7 +1024,9 @@ define i32 @test_dcmpgt(double %a, double %b) #0 {
; SPE-NEXT: .LBB37_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
+; SPE-NEXT: lwz 0, 20(1)
; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmpgt:
@@ -859,26 +1067,56 @@ ret:
define i32 @test_dcmpugt(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpugt:
; SPE: # %bb.0: # %entry
-; SPE-NEXT: stwu 1, -16(1)
-; SPE-NEXT: evmergelo 3, 3, 4
-; SPE-NEXT: evmergelo 4, 5, 6
-; SPE-NEXT: efdcmpeq 0, 4, 4
-; SPE-NEXT: bc 4, 1, .LBB38_4
-; SPE-NEXT: # %bb.1: # %entry
-; SPE-NEXT: efdcmpeq 0, 3, 3
-; SPE-NEXT: bc 4, 1, .LBB38_4
-; SPE-NEXT: # %bb.2: # %entry
-; SPE-NEXT: efdcmpgt 0, 3, 4
-; SPE-NEXT: bc 12, 1, .LBB38_4
-; SPE-NEXT: # %bb.3: # %fa
-; SPE-NEXT: li 3, 0
-; SPE-NEXT: b .LBB38_5
-; SPE-NEXT: .LBB38_4: # %tr
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -80(1)
+; SPE-NEXT: mfcr 12
+; SPE-NEXT: stw 0, 84(1)
+; SPE-NEXT: stw 12, 76(1)
+; SPE-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill
+; SPE-NEXT: evmergelo 30, 5, 6
+; SPE-NEXT: evmergelo 29, 3, 4
+; SPE-NEXT: evmergehi 28, 29, 29
+; SPE-NEXT: evmergehi 27, 30, 30
+; SPE-NEXT: mr 4, 29
+; SPE-NEXT: mr 3, 28
+; SPE-NEXT: mr 5, 27
+; SPE-NEXT: mr 6, 30
+; SPE-NEXT: bl __ledf2
+; SPE-NEXT: cmpwi 2, 3, 1
+; SPE-NEXT: mr 3, 27
+; SPE-NEXT: mr 4, 30
+; SPE-NEXT: mr 5, 27
+; SPE-NEXT: mr 6, 30
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: mr 30, 3
+; SPE-NEXT: mr 3, 28
+; SPE-NEXT: mr 4, 29
+; SPE-NEXT: mr 5, 28
+; SPE-NEXT: mr 6, 29
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: or. 3, 3, 30
+; SPE-NEXT: crand 20, 8, 2
+; SPE-NEXT: bc 12, 20, .LBB38_2
+; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
-; SPE-NEXT: .LBB38_5: # %ret
-; SPE-NEXT: stw 3, 12(1)
-; SPE-NEXT: lwz 3, 12(1)
-; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: b .LBB38_3
+; SPE-NEXT: .LBB38_2: # %fa
+; SPE-NEXT: li 3, 0
+; SPE-NEXT: .LBB38_3: # %ret
+; SPE-NEXT: stw 3, 20(1)
+; SPE-NEXT: lwz 3, 20(1)
+; SPE-NEXT: evldd 30, 48(1) # 8-byte Folded Reload
+; SPE-NEXT: evldd 29, 40(1) # 8-byte Folded Reload
+; SPE-NEXT: evldd 28, 32(1) # 8-byte Folded Reload
+; SPE-NEXT: lwz 12, 76(1)
+; SPE-NEXT: evldd 27, 24(1) # 8-byte Folded Reload
+; SPE-NEXT: mtcrf 32, 12 # cr2
+; SPE-NEXT: lwz 0, 84(1)
+; SPE-NEXT: addi 1, 1, 80
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmpugt:
@@ -919,10 +1157,15 @@ ret:
define i32 @test_dcmple(double %a, double %b) #0 {
; SPE-LABEL: test_dcmple:
; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
; SPE-NEXT: stwu 1, -16(1)
-; SPE-NEXT: evmergelo 5, 5, 6
-; SPE-NEXT: evmergelo 3, 3, 4
-; SPE-NEXT: efdcmpgt 0, 3, 5
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: evmergelo 6, 5, 6
+; SPE-NEXT: evmergelo 4, 3, 4
+; SPE-NEXT: evmergehi 3, 4, 4
+; SPE-NEXT: evmergehi 5, 6, 6
+; SPE-NEXT: bl __gtdf2
+; SPE-NEXT: cmpwi 3, 0
; SPE-NEXT: bgt 0, .LBB39_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
@@ -932,7 +1175,9 @@ define i32 @test_dcmple(double %a, double %b) #0 {
; SPE-NEXT: .LBB39_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
+; SPE-NEXT: lwz 0, 20(1)
; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmple:
@@ -973,10 +1218,15 @@ ret:
define i32 @test_dcmpule(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpule:
; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
; SPE-NEXT: stwu 1, -16(1)
-; SPE-NEXT: evmergelo 5, 5, 6
-; SPE-NEXT: evmergelo 3, 3, 4
-; SPE-NEXT: efdcmpgt 0, 3, 5
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: evmergelo 6, 5, 6
+; SPE-NEXT: evmergelo 4, 3, 4
+; SPE-NEXT: evmergehi 3, 4, 4
+; SPE-NEXT: evmergehi 5, 6, 6
+; SPE-NEXT: bl __gtdf2
+; SPE-NEXT: cmpwi 3, 0
; SPE-NEXT: bgt 0, .LBB40_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
@@ -986,7 +1236,9 @@ define i32 @test_dcmpule(double %a, double %b) #0 {
; SPE-NEXT: .LBB40_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
+; SPE-NEXT: lwz 0, 20(1)
; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmpule:
@@ -1028,11 +1280,16 @@ ret:
define i32 @test_dcmpeq(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpeq:
; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
; SPE-NEXT: stwu 1, -16(1)
-; SPE-NEXT: evmergelo 5, 5, 6
-; SPE-NEXT: evmergelo 3, 3, 4
-; SPE-NEXT: efdcmpeq 0, 3, 5
-; SPE-NEXT: ble 0, .LBB41_2
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: evmergelo 6, 5, 6
+; SPE-NEXT: evmergelo 4, 3, 4
+; SPE-NEXT: evmergehi 3, 4, 4
+; SPE-NEXT: evmergehi 5, 6, 6
+; SPE-NEXT: bl __nedf2
+; SPE-NEXT: cmplwi 3, 0
+; SPE-NEXT: bne 0, .LBB41_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
; SPE-NEXT: b .LBB41_3
@@ -1041,7 +1298,9 @@ define i32 @test_dcmpeq(double %a, double %b) #0 {
; SPE-NEXT: .LBB41_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
+; SPE-NEXT: lwz 0, 20(1)
; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmpeq:
@@ -1082,13 +1341,33 @@ ret:
define i32 @test_dcmpueq(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpueq:
; SPE: # %bb.0: # %entry
-; SPE-NEXT: stwu 1, -16(1)
-; SPE-NEXT: evmergelo 5, 5, 6
-; SPE-NEXT: evmergelo 3, 3, 4
-; SPE-NEXT: efdcmplt 0, 3, 5
-; SPE-NEXT: bc 12, 1, .LBB42_3
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -80(1)
+; SPE-NEXT: mfcr 12
+; SPE-NEXT: stw 0, 84(1)
+; SPE-NEXT: stw 12, 76(1)
+; SPE-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill
+; SPE-NEXT: evmergelo 30, 5, 6
+; SPE-NEXT: evmergelo 29, 3, 4
+; SPE-NEXT: evmergehi 28, 29, 29
+; SPE-NEXT: evmergehi 27, 30, 30
+; SPE-NEXT: mr 4, 29
+; SPE-NEXT: mr 3, 28
+; SPE-NEXT: mr 5, 27
+; SPE-NEXT: mr 6, 30
+; SPE-NEXT: bl __ltdf2
+; SPE-NEXT: cmpwi 2, 3, 0
+; SPE-NEXT: mr 3, 28
+; SPE-NEXT: mr 4, 29
+; SPE-NEXT: mr 5, 27
+; SPE-NEXT: mr 6, 30
+; SPE-NEXT: bl __gtdf2
+; SPE-NEXT: bc 12, 8, .LBB42_3
; SPE-NEXT: # %bb.1: # %entry
-; SPE-NEXT: efdcmpgt 0, 3, 5
+; SPE-NEXT: cmpwi 3, 0
; SPE-NEXT: bc 12, 1, .LBB42_3
; SPE-NEXT: # %bb.2: # %tr
; SPE-NEXT: li 3, 1
@@ -1096,9 +1375,17 @@ define i32 @test_dcmpueq(double %a, double %b) #0 {
; SPE-NEXT: .LBB42_3: # %fa
; SPE-NEXT: li 3, 0
; SPE-NEXT: .LBB42_4: # %ret
-; SPE-NEXT: stw 3, 12(1)
-; SPE-NEXT: lwz 3, 12(1)
-; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: stw 3, 20(1)
+; SPE-NEXT: lwz 3, 20(1)
+; SPE-NEXT: evldd 30, 48(1) # 8-byte Folded Reload
+; SPE-NEXT: evldd 29, 40(1) # 8-byte Folded Reload
+; SPE-NEXT: evldd 28, 32(1) # 8-byte Folded Reload
+; SPE-NEXT: lwz 12, 76(1)
+; SPE-NEXT: evldd 27, 24(1) # 8-byte Folded Reload
+; SPE-NEXT: mtcrf 32, 12 # cr2
+; SPE-NEXT: lwz 0, 84(1)
+; SPE-NEXT: addi 1, 1, 80
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmpueq:
@@ -1163,16 +1450,48 @@ ret:
define i1 @test_dcmpne(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpne:
; SPE: # %bb.0: # %entry
-; SPE-NEXT: evmergelo 5, 5, 6
-; SPE-NEXT: evmergelo 4, 3, 4
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -80(1)
+; SPE-NEXT: mfcr 12
+; SPE-NEXT: stw 0, 84(1)
+; SPE-NEXT: stw 12, 76(1)
+; SPE-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill
+; SPE-NEXT: evmergelo 30, 5, 6
+; SPE-NEXT: evmergelo 29, 3, 4
+; SPE-NEXT: evmergehi 28, 29, 29
+; SPE-NEXT: evmergehi 27, 30, 30
+; SPE-NEXT: mr 4, 29
+; SPE-NEXT: mr 3, 28
+; SPE-NEXT: mr 5, 27
+; SPE-NEXT: mr 6, 30
+; SPE-NEXT: bl __ltdf2
+; SPE-NEXT: cmpwi 2, 3, 0
+; SPE-NEXT: mr 3, 28
+; SPE-NEXT: mr 4, 29
+; SPE-NEXT: mr 5, 27
+; SPE-NEXT: mr 6, 30
+; SPE-NEXT: bl __gtdf2
+; SPE-NEXT: mr 4, 3
; SPE-NEXT: li 3, 0
-; SPE-NEXT: efdcmplt 0, 4, 5
-; SPE-NEXT: bc 12, 1, .LBB43_2
+; SPE-NEXT: bc 12, 8, .LBB43_2
; SPE-NEXT: # %bb.1: # %entry
-; SPE-NEXT: efdcmpgt 0, 4, 5
-; SPE-NEXT: bclr 4, 1, 0
+; SPE-NEXT: cmpwi 4, 0
+; SPE-NEXT: bc 4, 1, .LBB43_3
; SPE-NEXT: .LBB43_2: # %entry
; SPE-NEXT: li 3, 1
+; SPE-NEXT: .LBB43_3: # %entry
+; SPE-NEXT: evldd 30, 48(1) # 8-byte Folded Reload
+; SPE-NEXT: evldd 29, 40(1) # 8-byte Folded Reload
+; SPE-NEXT: evldd 28, 32(1) # 8-byte Folded Reload
+; SPE-NEXT: lwz 12, 76(1)
+; SPE-NEXT: evldd 27, 24(1) # 8-byte Folded Reload
+; SPE-NEXT: mtcrf 32, 12 # cr2
+; SPE-NEXT: lwz 0, 84(1)
+; SPE-NEXT: addi 1, 1, 80
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmpne:
@@ -1224,11 +1543,16 @@ define i1 @test_dcmpne(double %a, double %b) #0 {
define i32 @test_dcmpune(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpune:
; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
; SPE-NEXT: stwu 1, -16(1)
-; SPE-NEXT: evmergelo 5, 5, 6
-; SPE-NEXT: evmergelo 3, 3, 4
-; SPE-NEXT: efdcmpeq 0, 3, 5
-; SPE-NEXT: bgt 0, .LBB44_2
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: evmergelo 6, 5, 6
+; SPE-NEXT: evmergelo 4, 3, 4
+; SPE-NEXT: evmergehi 3, 4, 4
+; SPE-NEXT: evmergehi 5, 6, 6
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: cmplwi 3, 0
+; SPE-NEXT: beq 0, .LBB44_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
; SPE-NEXT: b .LBB44_3
@@ -1237,7 +1561,9 @@ define i32 @test_dcmpune(double %a, double %b) #0 {
; SPE-NEXT: .LBB44_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
+; SPE-NEXT: lwz 0, 20(1)
; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmpune:
@@ -1278,11 +1604,16 @@ ret:
define i32 @test_dcmplt(double %a, double %b) #0 {
; SPE-LABEL: test_dcmplt:
; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
; SPE-NEXT: stwu 1, -16(1)
-; SPE-NEXT: evmergelo 5, 5, 6
-; SPE-NEXT: evmergelo 3, 3, 4
-; SPE-NEXT: efdcmplt 0, 3, 5
-; SPE-NEXT: ble 0, .LBB45_2
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: evmergelo 6, 5, 6
+; SPE-NEXT: evmergelo 4, 3, 4
+; SPE-NEXT: evmergehi 3, 4, 4
+; SPE-NEXT: evmergehi 5, 6, 6
+; SPE-NEXT: bl __ltdf2
+; SPE-NEXT: cmpwi 3, 0
+; SPE-NEXT: bge 0, .LBB45_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
; SPE-NEXT: b .LBB45_3
@@ -1291,7 +1622,9 @@ define i32 @test_dcmplt(double %a, double %b) #0 {
; SPE-NEXT: .LBB45_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
+; SPE-NEXT: lwz 0, 20(1)
; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmplt:
@@ -1332,26 +1665,56 @@ ret:
define i32 @test_dcmpult(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpult:
; SPE: # %bb.0: # %entry
-; SPE-NEXT: stwu 1, -16(1)
-; SPE-NEXT: evmergelo 3, 3, 4
-; SPE-NEXT: evmergelo 4, 5, 6
-; SPE-NEXT: efdcmpeq 0, 4, 4
-; SPE-NEXT: bc 4, 1, .LBB46_4
-; SPE-NEXT: # %bb.1: # %entry
-; SPE-NEXT: efdcmpeq 0, 3, 3
-; SPE-NEXT: bc 4, 1, .LBB46_4
-; SPE-NEXT: # %bb.2: # %entry
-; SPE-NEXT: efdcmplt 0, 3, 4
-; SPE-NEXT: bc 12, 1, .LBB46_4
-; SPE-NEXT: # %bb.3: # %fa
-; SPE-NEXT: li 3, 0
-; SPE-NEXT: b .LBB46_5
-; SPE-NEXT: .LBB46_4: # %tr
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -80(1)
+; SPE-NEXT: mfcr 12
+; SPE-NEXT: stw 0, 84(1)
+; SPE-NEXT: stw 12, 76(1)
+; SPE-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill
+; SPE-NEXT: evmergelo 30, 5, 6
+; SPE-NEXT: evmergelo 29, 3, 4
+; SPE-NEXT: evmergehi 28, 29, 29
+; SPE-NEXT: evmergehi 27, 30, 30
+; SPE-NEXT: mr 4, 29
+; SPE-NEXT: mr 3, 28
+; SPE-NEXT: mr 5, 27
+; SPE-NEXT: mr 6, 30
+; SPE-NEXT: bl __gedf2
+; SPE-NEXT: cmpwi 2, 3, -1
+; SPE-NEXT: mr 3, 27
+; SPE-NEXT: mr 4, 30
+; SPE-NEXT: mr 5, 27
+; SPE-NEXT: mr 6, 30
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: mr 30, 3
+; SPE-NEXT: mr 3, 28
+; SPE-NEXT: mr 4, 29
+; SPE-NEXT: mr 5, 28
+; SPE-NEXT: mr 6, 29
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: or. 3, 3, 30
+; SPE-NEXT: crand 20, 9, 2
+; SPE-NEXT: bc 12, 20, .LBB46_2
+; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
-; SPE-NEXT: .LBB46_5: # %ret
-; SPE-NEXT: stw 3, 12(1)
-; SPE-NEXT: lwz 3, 12(1)
-; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: b .LBB46_3
+; SPE-NEXT: .LBB46_2: # %fa
+; SPE-NEXT: li 3, 0
+; SPE-NEXT: .LBB46_3: # %ret
+; SPE-NEXT: stw 3, 20(1)
+; SPE-NEXT: lwz 3, 20(1)
+; SPE-NEXT: evldd 30, 48(1) # 8-byte Folded Reload
+; SPE-NEXT: evldd 29, 40(1) # 8-byte Folded Reload
+; SPE-NEXT: evldd 28, 32(1) # 8-byte Folded Reload
+; SPE-NEXT: lwz 12, 76(1)
+; SPE-NEXT: evldd 27, 24(1) # 8-byte Folded Reload
+; SPE-NEXT: mtcrf 32, 12 # cr2
+; SPE-NEXT: lwz 0, 84(1)
+; SPE-NEXT: addi 1, 1, 80
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmpult:
@@ -1392,19 +1755,52 @@ ret:
define i1 @test_dcmpge(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpge:
; SPE: # %bb.0: # %entry
-; SPE-NEXT: evmergelo 4, 3, 4
-; SPE-NEXT: evmergelo 5, 5, 6
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -80(1)
+; SPE-NEXT: mfcr 12
+; SPE-NEXT: stw 0, 84(1)
+; SPE-NEXT: stw 12, 76(1)
+; SPE-NEXT: evstdd 27, 24(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 28, 32(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 29, 40(1) # 8-byte Folded Spill
+; SPE-NEXT: evstdd 30, 48(1) # 8-byte Folded Spill
+; SPE-NEXT: evmergelo 30, 5, 6
+; SPE-NEXT: evmergelo 29, 3, 4
+; SPE-NEXT: evmergehi 28, 29, 29
+; SPE-NEXT: evmergehi 27, 30, 30
+; SPE-NEXT: mr 4, 29
+; SPE-NEXT: mr 3, 28
+; SPE-NEXT: mr 5, 27
+; SPE-NEXT: mr 6, 30
+; SPE-NEXT: bl __gedf2
+; SPE-NEXT: cmpwi 2, 3, -1
+; SPE-NEXT: mr 3, 27
+; SPE-NEXT: mr 4, 30
+; SPE-NEXT: mr 5, 27
+; SPE-NEXT: mr 6, 30
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: mr 30, 3
+; SPE-NEXT: mr 3, 28
+; SPE-NEXT: mr 4, 29
+; SPE-NEXT: mr 5, 28
+; SPE-NEXT: mr 6, 29
+; SPE-NEXT: bl __eqdf2
+; SPE-NEXT: or. 3, 3, 30
+; SPE-NEXT: crnand 20, 9, 2
; SPE-NEXT: li 3, 0
-; SPE-NEXT: efdcmpeq 0, 5, 5
-; SPE-NEXT: bclr 4, 1, 0
+; SPE-NEXT: bc 12, 20, .LBB47_2
; SPE-NEXT: # %bb.1: # %entry
-; SPE-NEXT: efdcmpeq 0, 4, 4
-; SPE-NEXT: bclr 4, 1, 0
-; SPE-NEXT: # %bb.2: # %entry
-; SPE-NEXT: efdcmplt 0, 4, 5
-; SPE-NEXT: bclr 12, 1, 0
-; SPE-NEXT: # %bb.3: # %entry
; SPE-NEXT: li 3, 1
+; SPE-NEXT: .LBB47_2: # %entry
+; SPE-NEXT: evldd 30, 48(1) # 8-byte Folded Reload
+; SPE-NEXT: evldd 29, 40(1) # 8-byte Folded Reload
+; SPE-NEXT: evldd 28, 32(1) # 8-byte Folded Reload
+; SPE-NEXT: lwz 12, 76(1)
+; SPE-NEXT: evldd 27, 24(1) # 8-byte Folded Reload
+; SPE-NEXT: mtcrf 32, 12 # cr2
+; SPE-NEXT: lwz 0, 84(1)
+; SPE-NEXT: addi 1, 1, 80
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmpge:
@@ -1427,11 +1823,16 @@ define i1 @test_dcmpge(double %a, double %b) #0 {
define i32 @test_dcmpuge(double %a, double %b) #0 {
; SPE-LABEL: test_dcmpuge:
; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
; SPE-NEXT: stwu 1, -16(1)
-; SPE-NEXT: evmergelo 5, 5, 6
-; SPE-NEXT: evmergelo 3, 3, 4
-; SPE-NEXT: efdcmplt 0, 3, 5
-; SPE-NEXT: bgt 0, .LBB48_2
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: evmergelo 6, 5, 6
+; SPE-NEXT: evmergelo 4, 3, 4
+; SPE-NEXT: evmergehi 3, 4, 4
+; SPE-NEXT: evmergehi 5, 6, 6
+; SPE-NEXT: bl __ltdf2
+; SPE-NEXT: cmpwi 3, 0
+; SPE-NEXT: blt 0, .LBB48_2
; SPE-NEXT: # %bb.1: # %tr
; SPE-NEXT: li 3, 1
; SPE-NEXT: b .LBB48_3
@@ -1440,7 +1841,9 @@ define i32 @test_dcmpuge(double %a, double %b) #0 {
; SPE-NEXT: .LBB48_3: # %ret
; SPE-NEXT: stw 3, 12(1)
; SPE-NEXT: lwz 3, 12(1)
+; SPE-NEXT: lwz 0, 20(1)
; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
; SPE-NEXT: blr
;
; EFPU2-LABEL: test_dcmpuge:
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