[llvm] [AMDGPU][NFC] Add atomic optimization tests for gfx13 (PR #201299)
Mariusz Sikora via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 9 05:11:33 PDT 2026
https://github.com/mariusz-sikora-at-amd updated https://github.com/llvm/llvm-project/pull/201299
>From 0ce28ba9778c7dfef1edbb6ee354dcd1695fad70 Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Tue, 2 Jun 2026 03:20:56 -0400
Subject: [PATCH 1/2] [AMDGPU][NFC] Add atomic optimization tests for gfx13
---
.../AMDGPU/atomic_optimizations_buffer.ll | 526 +++
.../atomic_optimizations_global_pointer.ll | 2864 +++++++++++++
.../atomic_optimizations_local_pointer.ll | 3685 +++++++++++++++++
.../atomic_optimizations_pixelshader.ll | 207 +
.../AMDGPU/atomic_optimizations_raw_buffer.ll | 438 ++
.../atomic_optimizations_struct_buffer.ll | 498 +++
6 files changed, 8218 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
index bbdec31772127..1768559f26f45 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
@@ -8,6 +8,8 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11W32 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12W64 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12W32 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W64 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W32 %s
declare i32 @llvm.amdgcn.workitem.id.x()
declare i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32, ptr addrspace(8), i32, i32, i32 immarg)
@@ -275,6 +277,65 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: add_i32_constant:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_mov_b64 s[2:3], exec
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX13W64-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W64-NEXT: s_cbranch_execz .LBB0_2
+; GFX13W64-NEXT: ; %bb.1:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX13W64-NEXT: s_mul_i32 s2, s2, 5
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB0_2:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_mad_u32_u24 v0, 5, v0, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: add_i32_constant:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s0, exec_lo
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W32-NEXT: s_cbranch_execz .LBB0_2
+; GFX13W32-NEXT: ; %bb.1:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: s_bcnt1_i32_b32 s1, s1
+; GFX13W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: s_mul_i32 s1, s1, 5
+; GFX13W32-NEXT: v_mov_b32_e32 v1, s1
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB0_2:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W32-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W32-NEXT: v_mad_u32_u24 v0, 5, v0, s2
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
store i32 %old, ptr addrspace(1) %out
@@ -553,6 +614,67 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: v_mov_b32_e32 v1, 0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[2:3]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: add_i32_uniform:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_load_b32 s6, s[4:5], 0x44 nv
+; GFX13W64-NEXT: s_mov_b64 s[2:3], exec
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX13W64-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W64-NEXT: s_cbranch_execz .LBB1_2
+; GFX13W64-NEXT: ; %bb.1:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: s_mul_i32 s2, s6, s2
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB1_2:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W64-NEXT: v_mad_co_u64_u32 v[0:1], null, s6, v0, s[2:3]
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: add_i32_uniform:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_load_b32 s0, s[4:5], 0x44 nv
+; GFX13W32-NEXT: s_mov_b32 s2, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W32-NEXT: s_cbranch_execz .LBB1_2
+; GFX13W32-NEXT: ; %bb.1:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: s_bcnt1_i32_b32 s2, s2
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: s_mul_i32 s2, s0, s2
+; GFX13W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB1_2:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX13W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_mad_co_u64_u32 v[0:1], null, s0, v0, s[4:5]
+; GFX13W32-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX13W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 %additive, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
store i32 %old, ptr addrspace(1) %out
@@ -930,6 +1052,89 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: add_i32_varying_vdata:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: s_mov_b32 s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr0
+; GFX13W64-NEXT: .LBB2_1: ; %ComputeLoop
+; GFX13W64-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_readlane_b32 s8, v1, s3
+; GFX13W64-NEXT: v_writelane_b32 v0, s2, s3
+; GFX13W64-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX13W64-NEXT: s_add_co_i32 s2, s2, s8
+; GFX13W64-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[6:7]
+; GFX13W64-NEXT: s_cbranch_scc1 .LBB2_1
+; GFX13W64-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX13W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
+; GFX13W64-NEXT: s_cbranch_execz .LBB2_4
+; GFX13W64-NEXT: ; %bb.3:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB2_4:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_add_nc_u32_e32 v0, s2, v0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: add_i32_varying_vdata:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s0, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr0
+; GFX13W32-NEXT: .LBB2_1: ; %ComputeLoop
+; GFX13W32-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W32-NEXT: s_ctz_i32_b32 s2, s1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_readlane_b32 s3, v1, s2
+; GFX13W32-NEXT: v_writelane_b32 v0, s0, s2
+; GFX13W32-NEXT: s_lshl_b32 s2, 1, s2
+; GFX13W32-NEXT: s_add_co_i32 s0, s0, s3
+; GFX13W32-NEXT: s_and_not1_b32 s1, s1, s2
+; GFX13W32-NEXT: s_cbranch_scc1 .LBB2_1
+; GFX13W32-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX13W32-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX13W32-NEXT: s_cbranch_execz .LBB2_4
+; GFX13W32-NEXT: ; %bb.3:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: v_mov_b32_e32 v1, s0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB2_4:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 %lane, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
@@ -1330,6 +1535,94 @@ define amdgpu_kernel void @struct_add_i32_varying_vdata(ptr addrspace(1) %out, p
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: struct_add_i32_varying_vdata:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: s_mov_b32 s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr0
+; GFX13W64-NEXT: .LBB3_1: ; %ComputeLoop
+; GFX13W64-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_readlane_b32 s8, v1, s3
+; GFX13W64-NEXT: v_writelane_b32 v0, s2, s3
+; GFX13W64-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX13W64-NEXT: s_add_co_i32 s2, s2, s8
+; GFX13W64-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[6:7]
+; GFX13W64-NEXT: s_cbranch_scc1 .LBB3_1
+; GFX13W64-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX13W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
+; GFX13W64-NEXT: s_cbranch_execz .LBB3_4
+; GFX13W64-NEXT: ; %bb.3:
+; GFX13W64-NEXT: s_clause 0x1
+; GFX13W64-NEXT: s_load_b32 s3, s[4:5], 0x44 nv
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: v_mov_b32_e32 v2, s3
+; GFX13W64-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB3_4:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_add_nc_u32_e32 v0, s2, v0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: struct_add_i32_varying_vdata:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s0, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr0
+; GFX13W32-NEXT: .LBB3_1: ; %ComputeLoop
+; GFX13W32-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W32-NEXT: s_ctz_i32_b32 s2, s1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_readlane_b32 s3, v1, s2
+; GFX13W32-NEXT: v_writelane_b32 v0, s0, s2
+; GFX13W32-NEXT: s_lshl_b32 s2, 1, s2
+; GFX13W32-NEXT: s_add_co_i32 s0, s0, s3
+; GFX13W32-NEXT: s_and_not1_b32 s1, s1, s2
+; GFX13W32-NEXT: s_cbranch_scc1 .LBB3_1
+; GFX13W32-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX13W32-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX13W32-NEXT: s_cbranch_execz .LBB3_4
+; GFX13W32-NEXT: ; %bb.3:
+; GFX13W32-NEXT: s_clause 0x1
+; GFX13W32-NEXT: s_load_b32 s2, s[4:5], 0x44 nv
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s2
+; GFX13W32-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB3_4:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add(i32 %lane, ptr addrspace(8) %inout, i32 %vindex, i32 0, i32 0, i32 0)
@@ -1441,6 +1734,20 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13-LABEL: add_i32_varying_offset:
+; GFX13: ; %bb.0: ; %entry
+; GFX13-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX13-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX13-NEXT: v_mov_b32_e32 v1, 1
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: buffer_atomic_add_u32 v1, v0, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX13-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13-NEXT: v_mov_b32_e32 v0, 0
+; GFX13-NEXT: s_wait_loadcnt 0x0
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX13-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 1, ptr addrspace(8) %inout, i32 %lane, i32 0, i32 0)
@@ -1716,6 +2023,66 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: sub_i32_constant:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_mov_b64 s[2:3], exec
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX13W64-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W64-NEXT: s_cbranch_execz .LBB5_2
+; GFX13W64-NEXT: ; %bb.1:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX13W64-NEXT: s_mul_i32 s2, s2, 5
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB5_2:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mul_u32_u24_e32 v0, 5, v0
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: sub_i32_constant:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s0, exec_lo
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W32-NEXT: s_cbranch_execz .LBB5_2
+; GFX13W32-NEXT: ; %bb.1:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: s_bcnt1_i32_b32 s1, s1
+; GFX13W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: s_mul_i32 s1, s1, 5
+; GFX13W32-NEXT: v_mov_b32_e32 v1, s1
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB5_2:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W32-NEXT: v_mul_u32_u24_e32 v0, 5, v0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_sub_nc_u32 v0, s2, v0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.sub(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
store i32 %old, ptr addrspace(1) %out
@@ -2000,6 +2367,68 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s0, v0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[2:3]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: sub_i32_uniform:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_load_b32 s6, s[4:5], 0x44 nv
+; GFX13W64-NEXT: s_mov_b64 s[2:3], exec
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX13W64-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W64-NEXT: s_cbranch_execz .LBB6_2
+; GFX13W64-NEXT: ; %bb.1:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: s_mul_i32 s2, s6, s2
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB6_2:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: v_mul_lo_u32 v0, s6, v0
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: sub_i32_uniform:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_load_b32 s0, s[4:5], 0x44 nv
+; GFX13W32-NEXT: s_mov_b32 s2, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W32-NEXT: s_cbranch_execz .LBB6_2
+; GFX13W32-NEXT: ; %bb.1:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: s_bcnt1_i32_b32 s2, s2
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: s_mul_i32 s2, s0, s2
+; GFX13W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB6_2:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX13W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: v_mul_lo_u32 v0, s0, v0
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s0, v1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_sub_nc_u32 v0, s0, v0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX13W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.sub(i32 %subitive, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
store i32 %old, ptr addrspace(1) %out
@@ -2379,6 +2808,89 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: sub_i32_varying_vdata:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: s_mov_b32 s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr0
+; GFX13W64-NEXT: .LBB7_1: ; %ComputeLoop
+; GFX13W64-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_readlane_b32 s8, v1, s3
+; GFX13W64-NEXT: v_writelane_b32 v0, s2, s3
+; GFX13W64-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX13W64-NEXT: s_add_co_i32 s2, s2, s8
+; GFX13W64-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[6:7]
+; GFX13W64-NEXT: s_cbranch_scc1 .LBB7_1
+; GFX13W64-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX13W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
+; GFX13W64-NEXT: s_cbranch_execz .LBB7_4
+; GFX13W64-NEXT: ; %bb.3:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB7_4:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: sub_i32_varying_vdata:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s0, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr0
+; GFX13W32-NEXT: .LBB7_1: ; %ComputeLoop
+; GFX13W32-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W32-NEXT: s_ctz_i32_b32 s2, s1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_readlane_b32 s3, v1, s2
+; GFX13W32-NEXT: v_writelane_b32 v0, s0, s2
+; GFX13W32-NEXT: s_lshl_b32 s2, 1, s2
+; GFX13W32-NEXT: s_add_co_i32 s0, s0, s3
+; GFX13W32-NEXT: s_and_not1_b32 s1, s1, s2
+; GFX13W32-NEXT: s_cbranch_scc1 .LBB7_1
+; GFX13W32-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX13W32-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX13W32-NEXT: s_cbranch_execz .LBB7_4
+; GFX13W32-NEXT: ; %bb.3:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: v_mov_b32_e32 v1, s0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB7_4:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_sub_nc_u32 v0, s2, v0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.sub(i32 %lane, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
@@ -2490,6 +3002,20 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13-LABEL: sub_i32_varying_offset:
+; GFX13: ; %bb.0: ; %entry
+; GFX13-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX13-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX13-NEXT: v_mov_b32_e32 v1, 1
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: buffer_atomic_sub_u32 v1, v0, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX13-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13-NEXT: v_mov_b32_e32 v0, 0
+; GFX13-NEXT: s_wait_loadcnt 0x0
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX13-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.sub(i32 1, ptr addrspace(8) %inout, i32 %lane, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
index aed1e4fe685f5..6f74ad3daefd8 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
@@ -25,6 +25,10 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1264,GFX1264-FAKE16,GFX1264_DPP,GFX1264_DPP-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1232,GFX1232-TRUE16,GFX1232_DPP,GFX1232_DPP-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1232,GFX1232-FAKE16,GFX1232_DPP,GFX1232_DPP-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1364,GFX1364-TRUE16,GFX1364_DPP,GFX1364_DPP-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1364,GFX1364-FAKE16,GFX1364_DPP,GFX1364_DPP-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1332,GFX1332-TRUE16,GFX1332_DPP,GFX1332_DPP-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1332,GFX1332-FAKE16,GFX1332_DPP,GFX1332_DPP-FAKE16 %s
declare i32 @llvm.amdgcn.workitem.id.x()
@@ -327,6 +331,77 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1232-NEXT: s_mov_b32 s2, -1
; GFX1232-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX1232-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i32_constant:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-NEXT: s_mov_b64 s[4:5], exec
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1364-NEXT: ; implicit-def: $vgpr1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1364-NEXT: s_cbranch_execz .LBB0_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1364-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1364-NEXT: s_mul_i32 s6, s6, 5
+; GFX1364-NEXT: s_mov_b32 s10, -1
+; GFX1364-NEXT: v_mov_b32_e32 v1, s6
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mov_b32 s8, s2
+; GFX1364-NEXT: s_mov_b32 s9, s3
+; GFX1364-NEXT: global_wb scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_storecnt 0x0
+; GFX1364-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: .LBB0_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: v_mad_u32_u24 v0, 5, v0, s2
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i32_constant:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-NEXT: s_mov_b32 s4, exec_lo
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1332-NEXT: ; implicit-def: $vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1332-NEXT: s_cbranch_execz .LBB0_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s5, s6
+; GFX1332-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1332-NEXT: s_mul_i32 s5, s5, 5
+; GFX1332-NEXT: s_mov_b32 s10, -1
+; GFX1332-NEXT: v_mov_b32_e32 v1, s5
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mov_b32 s8, s2
+; GFX1332-NEXT: s_mov_b32 s9, s3
+; GFX1332-NEXT: global_wb scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_storecnt 0x0
+; GFX1332-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: .LBB0_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s4
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: v_mad_u32_u24 v0, 5, v0, s2
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw add ptr addrspace(1) %inout, i32 5 syncscope("agent") acq_rel
store i32 %old, ptr addrspace(1) %out
@@ -654,6 +729,83 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1232-NEXT: s_mov_b32 s2, -1
; GFX1232-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX1232-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i32_uniform:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_clause 0x1
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1364-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-NEXT: s_mov_b64 s[4:5], exec
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1364-NEXT: ; implicit-def: $vgpr1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1364-NEXT: s_cbranch_execz .LBB1_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1364-NEXT: s_mov_b32 s15, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mul_i32 s6, s8, s6
+; GFX1364-NEXT: s_mov_b32 s14, -1
+; GFX1364-NEXT: v_mov_b32_e32 v1, s6
+; GFX1364-NEXT: s_mov_b32 s12, s2
+; GFX1364-NEXT: s_mov_b32 s13, s3
+; GFX1364-NEXT: global_wb scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_storecnt 0x0
+; GFX1364-NEXT: buffer_atomic_add_u32 v1, off, s[12:15], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: .LBB1_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_mad_co_u64_u32 v[0:1], null, s8, v0, s[2:3]
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i32_uniform:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_clause 0x1
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_load_b32 s4, s[4:5], 0x34 nv
+; GFX1332-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-NEXT: s_mov_b32 s5, exec_lo
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1332-NEXT: ; implicit-def: $vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1332-NEXT: s_cbranch_execz .LBB1_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s6, s6
+; GFX1332-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mul_i32 s6, s4, s6
+; GFX1332-NEXT: s_mov_b32 s10, -1
+; GFX1332-NEXT: v_mov_b32_e32 v1, s6
+; GFX1332-NEXT: s_mov_b32 s8, s2
+; GFX1332-NEXT: s_mov_b32 s9, s3
+; GFX1332-NEXT: global_wb scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_storecnt 0x0
+; GFX1332-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: .LBB1_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s5
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_mad_co_u64_u32 v[0:1], null, s4, v0, s[2:3]
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw add ptr addrspace(1) %inout, i32 %additive syncscope("agent") acq_rel
store i32 %old, ptr addrspace(1) %out
@@ -1558,6 +1710,136 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: s_mov_b32 s2, s6
; GFX1232_DPP-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX1232_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i32_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_or_saveexec_b64 s[4:5], -1
+; GFX1364-NEXT: v_readlane_b32 s7, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v3, s6, 16
+; GFX1364-NEXT: s_mov_b64 exec, s[4:5]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[4:5], -1
+; GFX1364-NEXT: v_readlane_b32 s8, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s9, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v3, s7, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[4:5]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[6:7], -1
+; GFX1364-NEXT: s_mov_b32 s4, s9
+; GFX1364-NEXT: v_writelane_b32 v3, s8, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[6:7]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: s_mov_b32 s6, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr0
+; GFX1364-NEXT: s_and_saveexec_b64 s[8:9], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB2_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, s4
+; GFX1364-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mov_b32 s4, s2
+; GFX1364-NEXT: s_mov_b32 s5, s3
+; GFX1364-NEXT: global_wb scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_storecnt 0x0
+; GFX1364-NEXT: buffer_atomic_add_u32 v0, off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: .LBB2_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, v3
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_e32 v0, s2, v0
+; GFX1364-NEXT: s_mov_b32 s2, s6
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i32_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, v0, s0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_or_saveexec_b32 s4, -1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_e32 v3, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_readlane_b32 s6, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s5, v1, 15
+; GFX1332-NEXT: s_mov_b32 exec_lo, s4
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s4, -1
+; GFX1332-NEXT: v_writelane_b32 v3, s5, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s4
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: s_mov_b32 s4, s6
+; GFX1332-NEXT: s_mov_b32 s6, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr0
+; GFX1332-NEXT: s_and_saveexec_b32 s8, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB2_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_mov_b32_e32 v0, s4
+; GFX1332-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mov_b32 s4, s2
+; GFX1332-NEXT: s_mov_b32 s5, s3
+; GFX1332-NEXT: global_wb scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_storecnt 0x0
+; GFX1332-NEXT: buffer_atomic_add_u32 v0, off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: .LBB2_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s8
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-NEXT: v_mov_b32_e32 v0, v3
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_e32 v0, s2, v0
+; GFX1332-NEXT: s_mov_b32 s2, s6
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw add ptr addrspace(1) %inout, i32 %lane syncscope("agent") acq_rel
@@ -1894,6 +2176,82 @@ define amdgpu_kernel void @add_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1232-NEXT: s_mov_b32 s2, -1
; GFX1232-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX1232-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i64_constant:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-NEXT: s_mov_b64 s[4:5], exec
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
+; GFX1364-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1364-NEXT: s_cbranch_execz .LBB3_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1364-NEXT: v_mov_b32_e32 v1, 0
+; GFX1364-NEXT: s_mul_i32 s6, s6, 5
+; GFX1364-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1364-NEXT: v_mov_b32_e32 v0, s6
+; GFX1364-NEXT: s_mov_b32 s10, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mov_b32 s8, s2
+; GFX1364-NEXT: s_mov_b32 s9, s3
+; GFX1364-NEXT: global_wb scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_storecnt 0x0
+; GFX1364-NEXT: buffer_atomic_add_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: .LBB3_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_mad_co_u64_u32 v[0:1], null, 5, v2, s[2:3]
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i64_constant:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-NEXT: s_mov_b32 s4, exec_lo
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v2, s6, 0
+; GFX1332-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1332-NEXT: s_cbranch_execz .LBB3_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s5, s6
+; GFX1332-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1332-NEXT: s_mul_i32 s5, s5, 5
+; GFX1332-NEXT: s_mov_b32 s10, -1
+; GFX1332-NEXT: v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v1, 0
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mov_b32 s8, s2
+; GFX1332-NEXT: s_mov_b32 s9, s3
+; GFX1332-NEXT: global_wb scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_storecnt 0x0
+; GFX1332-NEXT: buffer_atomic_add_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: .LBB3_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s4
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_mad_co_u64_u32 v[0:1], null, 5, v2, s[2:3]
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw add ptr addrspace(1) %inout, i64 5 syncscope("agent") acq_rel
store i64 %old, ptr addrspace(1) %out
@@ -2279,6 +2637,90 @@ define amdgpu_kernel void @add_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1232-NEXT: v_mad_co_u64_u32 v[1:2], null, s5, v2, v[1:2]
; GFX1232-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX1232-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i64_uniform:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_clause 0x1
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 nv
+; GFX1364-NEXT: s_mov_b64 s[8:9], exec
+; GFX1364-NEXT: s_mov_b32 s11, 0
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0
+; GFX1364-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0
+; GFX1364-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1364-NEXT: s_cbranch_execz .LBB4_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s10, s[8:9]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mul_u64 s[8:9], s[4:5], s[10:11]
+; GFX1364-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1364-NEXT: v_mov_b32_e32 v0, s8
+; GFX1364-NEXT: v_mov_b32_e32 v1, s9
+; GFX1364-NEXT: s_mov_b32 s10, -1
+; GFX1364-NEXT: s_mov_b32 s8, s2
+; GFX1364-NEXT: s_mov_b32 s9, s3
+; GFX1364-NEXT: global_wb scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_storecnt 0x0
+; GFX1364-NEXT: buffer_atomic_add_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: .LBB4_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_mad_co_u64_u32 v[0:1], null, s4, v2, s[2:3]
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: v_mad_co_u64_u32 v[1:2], null, s5, v2, v[1:2]
+; GFX1364-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i64_uniform:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_clause 0x1
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 nv
+; GFX1332-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-NEXT: s_mov_b32 s7, 0
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v2, s6, 0
+; GFX1332-NEXT: s_mov_b32 s8, exec_lo
+; GFX1332-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1332-NEXT: s_cbranch_execz .LBB4_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s6, s6
+; GFX1332-NEXT: s_mov_b32 s15, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mul_u64 s[6:7], s[4:5], s[6:7]
+; GFX1332-NEXT: s_mov_b32 s14, -1
+; GFX1332-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1332-NEXT: s_mov_b32 s12, s2
+; GFX1332-NEXT: s_mov_b32 s13, s3
+; GFX1332-NEXT: global_wb scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_storecnt 0x0
+; GFX1332-NEXT: buffer_atomic_add_u64 v[0:1], off, s[12:15], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: .LBB4_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s8
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_mad_co_u64_u32 v[0:1], null, s4, v2, s[2:3]
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: v_mad_co_u64_u32 v[1:2], null, s5, v2, v[1:2]
+; GFX1332-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw add ptr addrspace(1) %inout, i64 %additive syncscope("agent") acq_rel
store i64 %old, ptr addrspace(1) %out
@@ -3537,6 +3979,199 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: s_mov_b32 s2, s6
; GFX1232_DPP-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
; GFX1232_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i64_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_e32 v5, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1364-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_e32 v4, s2
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1364-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[4:5], -1
+; GFX1364-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s6, v2, 15
+; GFX1364-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s7, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s8, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s9, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v4, s6, 16
+; GFX1364-NEXT: v_readlane_b32 s6, v2, 63
+; GFX1364-NEXT: v_writelane_b32 v5, s7, 16
+; GFX1364-NEXT: v_readlane_b32 s10, v2, 47
+; GFX1364-NEXT: v_readlane_b32 s11, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s7, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v4, s8, 32
+; GFX1364-NEXT: v_writelane_b32 v5, s9, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[4:5]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[8:9], -1
+; GFX1364-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX1364-NEXT: v_writelane_b32 v4, s10, 48
+; GFX1364-NEXT: v_writelane_b32 v5, s11, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[8:9]
+; GFX1364-NEXT: s_mov_b32 s6, -1
+; GFX1364-NEXT: s_mov_b64 s[8:9], exec
+; GFX1364-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1364-NEXT: s_cbranch_execz .LBB5_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v7, s5
+; GFX1364-NEXT: v_mov_b32_e32 v6, s4
+; GFX1364-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mov_b32 s4, s2
+; GFX1364-NEXT: s_mov_b32 s5, s3
+; GFX1364-NEXT: global_wb scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_storecnt 0x0
+; GFX1364-NEXT: buffer_atomic_add_u64 v[6:7], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: .LBB5_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v6
+; GFX1364-NEXT: v_mov_b32_e32 v8, v4
+; GFX1364-NEXT: v_mov_b32_e32 v9, v5
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v7
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_co_u32 v6, vcc, s2, v8
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v7, null, s3, v9, vcc
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, s6
+; GFX1364-NEXT: buffer_store_b64 v[6:7], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i64_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, 0, s0
+; GFX1332-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v3, 0, v0, s0
+; GFX1332-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, 0
+; GFX1332-NEXT: v_mov_b32_e32 v6, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1332-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
+; GFX1332-NEXT: v_mov_b32_e32 v2, 0
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_mov_b32_e32 v4, 0
+; GFX1332-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_mov_b32_e32 v3, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1332-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_or_saveexec_b32 s6, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
+; GFX1332-NEXT: v_readlane_b32 s4, v2, 31
+; GFX1332-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s7, v2, 15
+; GFX1332-NEXT: v_readlane_b32 s8, v1, 15
+; GFX1332-NEXT: v_readlane_b32 s5, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v7, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_mov_b32 exec_lo, s6
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s6, -1
+; GFX1332-NEXT: v_writelane_b32 v6, s7, 16
+; GFX1332-NEXT: v_writelane_b32 v7, s8, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s6
+; GFX1332-NEXT: s_mov_b32 s6, -1
+; GFX1332-NEXT: s_mov_b32 s8, exec_lo
+; GFX1332-NEXT: ; implicit-def: $vgpr8_vgpr9
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1332-NEXT: s_cbranch_execz .LBB5_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4
+; GFX1332-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mov_b32 s4, s2
+; GFX1332-NEXT: s_mov_b32 s5, s3
+; GFX1332-NEXT: global_wb scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_storecnt 0x0
+; GFX1332-NEXT: buffer_atomic_add_u64 v[8:9], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: .LBB5_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s8
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v8
+; GFX1332-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v11, v7
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v9
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_co_u32 v8, vcc_lo, s2, v10
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v9, null, s3, v11, vcc_lo
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, s6
+; GFX1332-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%zext = zext i32 %lane to i64
@@ -3965,6 +4600,81 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1232-NEXT: s_mov_b32 s2, -1
; GFX1232-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX1232-NEXT: s_endpgm
+;
+; GFX1364-LABEL: sub_i32_constant:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-NEXT: s_mov_b64 s[4:5], exec
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1364-NEXT: ; implicit-def: $vgpr1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1364-NEXT: s_cbranch_execz .LBB6_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1364-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1364-NEXT: s_mul_i32 s6, s6, 5
+; GFX1364-NEXT: s_mov_b32 s10, -1
+; GFX1364-NEXT: v_mov_b32_e32 v1, s6
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mov_b32 s8, s2
+; GFX1364-NEXT: s_mov_b32 s9, s3
+; GFX1364-NEXT: global_wb scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_storecnt 0x0
+; GFX1364-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: .LBB6_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1364-NEXT: v_mul_u32_u24_e32 v0, 5, v0
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: sub_i32_constant:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-NEXT: s_mov_b32 s4, exec_lo
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1332-NEXT: ; implicit-def: $vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1332-NEXT: s_cbranch_execz .LBB6_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s5, s6
+; GFX1332-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1332-NEXT: s_mul_i32 s5, s5, 5
+; GFX1332-NEXT: s_mov_b32 s10, -1
+; GFX1332-NEXT: v_mov_b32_e32 v1, s5
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mov_b32 s8, s2
+; GFX1332-NEXT: s_mov_b32 s9, s3
+; GFX1332-NEXT: global_wb scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_storecnt 0x0
+; GFX1332-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: .LBB6_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s4
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1332-NEXT: v_mul_u32_u24_e32 v0, 5, v0
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw sub ptr addrspace(1) %inout, i32 5 syncscope("agent") acq_rel
store i32 %old, ptr addrspace(1) %out
@@ -4406,6 +5116,83 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1232-NEXT: s_mov_b32 s2, -1
; GFX1232-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX1232-NEXT: s_endpgm
+;
+; GFX1364-LABEL: sub_i32_uniform:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_clause 0x1
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1364-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-NEXT: s_mov_b64 s[4:5], exec
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1364-NEXT: ; implicit-def: $vgpr1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1364-NEXT: s_cbranch_execz .LBB7_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1364-NEXT: s_mov_b32 s15, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mul_i32 s6, s8, s6
+; GFX1364-NEXT: s_mov_b32 s14, -1
+; GFX1364-NEXT: v_mov_b32_e32 v1, s6
+; GFX1364-NEXT: s_mov_b32 s12, s2
+; GFX1364-NEXT: s_mov_b32 s13, s3
+; GFX1364-NEXT: global_wb scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_storecnt 0x0
+; GFX1364-NEXT: buffer_atomic_sub_u32 v1, off, s[12:15], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: .LBB7_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_mul_lo_u32 v0, s8, v0
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: sub_i32_uniform:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_clause 0x1
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_load_b32 s4, s[4:5], 0x34 nv
+; GFX1332-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-NEXT: s_mov_b32 s5, exec_lo
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1332-NEXT: ; implicit-def: $vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1332-NEXT: s_cbranch_execz .LBB7_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s6, s6
+; GFX1332-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mul_i32 s6, s4, s6
+; GFX1332-NEXT: s_mov_b32 s10, -1
+; GFX1332-NEXT: v_mov_b32_e32 v1, s6
+; GFX1332-NEXT: s_mov_b32 s8, s2
+; GFX1332-NEXT: s_mov_b32 s9, s3
+; GFX1332-NEXT: global_wb scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_storecnt 0x0
+; GFX1332-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: .LBB7_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s5
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_mul_lo_u32 v0, s4, v0
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw sub ptr addrspace(1) %inout, i32 %subitive syncscope("agent") acq_rel
store i32 %old, ptr addrspace(1) %out
@@ -5521,6 +6308,136 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: s_mov_b32 s2, s6
; GFX1232_DPP-NEXT: buffer_store_b32 v0, off, s[0:3], null
; GFX1232_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: sub_i32_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_or_saveexec_b64 s[4:5], -1
+; GFX1364-NEXT: v_readlane_b32 s7, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v3, s6, 16
+; GFX1364-NEXT: s_mov_b64 exec, s[4:5]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[4:5], -1
+; GFX1364-NEXT: v_readlane_b32 s8, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s9, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v3, s7, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[4:5]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[6:7], -1
+; GFX1364-NEXT: s_mov_b32 s4, s9
+; GFX1364-NEXT: v_writelane_b32 v3, s8, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[6:7]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: s_mov_b32 s6, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr0
+; GFX1364-NEXT: s_and_saveexec_b64 s[8:9], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB8_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, s4
+; GFX1364-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mov_b32 s4, s2
+; GFX1364-NEXT: s_mov_b32 s5, s3
+; GFX1364-NEXT: global_wb scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_storecnt 0x0
+; GFX1364-NEXT: buffer_atomic_sub_u32 v0, off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: .LBB8_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, v3
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX1364-NEXT: s_mov_b32 s2, s6
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: sub_i32_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, v0, s0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_or_saveexec_b32 s4, -1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_e32 v3, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_readlane_b32 s6, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s5, v1, 15
+; GFX1332-NEXT: s_mov_b32 exec_lo, s4
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s4, -1
+; GFX1332-NEXT: v_writelane_b32 v3, s5, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s4
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: s_mov_b32 s4, s6
+; GFX1332-NEXT: s_mov_b32 s6, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr0
+; GFX1332-NEXT: s_and_saveexec_b32 s8, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB8_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_mov_b32_e32 v0, s4
+; GFX1332-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mov_b32 s4, s2
+; GFX1332-NEXT: s_mov_b32 s5, s3
+; GFX1332-NEXT: global_wb scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_storecnt 0x0
+; GFX1332-NEXT: buffer_atomic_sub_u32 v0, off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: .LBB8_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s8
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-NEXT: v_mov_b32_e32 v0, v3
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX1332-NEXT: s_mov_b32 s2, s6
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw sub ptr addrspace(1) %inout, i32 %lane syncscope("agent") acq_rel
@@ -6017,6 +6934,88 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out, ptr addrspace
; GFX1232-NEXT: s_mov_b32 s2, -1
; GFX1232-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX1232-NEXT: s_endpgm
+;
+; GFX1364-LABEL: sub_i64_constant:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-NEXT: s_mov_b64 s[4:5], exec
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
+; GFX1364-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1364-NEXT: s_cbranch_execz .LBB9_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1364-NEXT: v_mov_b32_e32 v1, 0
+; GFX1364-NEXT: s_mul_i32 s6, s6, 5
+; GFX1364-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1364-NEXT: v_mov_b32_e32 v0, s6
+; GFX1364-NEXT: s_mov_b32 s10, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mov_b32 s8, s2
+; GFX1364-NEXT: s_mov_b32 s9, s3
+; GFX1364-NEXT: global_wb scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_storecnt 0x0
+; GFX1364-NEXT: buffer_atomic_sub_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: .LBB9_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-NEXT: v_mul_u32_u24_e32 v0, 5, v2
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1364-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_sub_co_u32 v0, vcc, s2, v0
+; GFX1364-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v1, vcc
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: sub_i64_constant:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-NEXT: s_mov_b32 s4, exec_lo
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v2, s6, 0
+; GFX1332-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1332-NEXT: s_cbranch_execz .LBB9_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s5, s6
+; GFX1332-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1332-NEXT: s_mul_i32 s5, s5, 5
+; GFX1332-NEXT: s_mov_b32 s10, -1
+; GFX1332-NEXT: v_dual_mov_b32 v0, s5 :: v_dual_mov_b32 v1, 0
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mov_b32 s8, s2
+; GFX1332-NEXT: s_mov_b32 s9, s3
+; GFX1332-NEXT: global_wb scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_storecnt 0x0
+; GFX1332-NEXT: buffer_atomic_sub_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: .LBB9_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s4
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-NEXT: v_mul_u32_u24_e32 v0, 5, v2
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1332-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_sub_co_u32 v0, vcc_lo, s2, v0
+; GFX1332-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v1, vcc_lo
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw sub ptr addrspace(1) %inout, i64 5 syncscope("agent") acq_rel
store i64 %old, ptr addrspace(1) %out
@@ -6558,6 +7557,94 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX1232-NEXT: s_mov_b32 s3, 0x31016000
; GFX1232-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
; GFX1232-NEXT: s_endpgm
+;
+; GFX1364-LABEL: sub_i64_uniform:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_clause 0x1
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 nv
+; GFX1364-NEXT: s_mov_b64 s[8:9], exec
+; GFX1364-NEXT: s_mov_b32 s11, 0
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s8, 0
+; GFX1364-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v2, s9, v0
+; GFX1364-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1364-NEXT: s_cbranch_execz .LBB10_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s10, s[8:9]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mul_u64 s[8:9], s[4:5], s[10:11]
+; GFX1364-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1364-NEXT: v_mov_b32_e32 v0, s8
+; GFX1364-NEXT: v_mov_b32_e32 v1, s9
+; GFX1364-NEXT: s_mov_b32 s10, -1
+; GFX1364-NEXT: s_mov_b32 s8, s2
+; GFX1364-NEXT: s_mov_b32 s9, s3
+; GFX1364-NEXT: global_wb scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_storecnt 0x0
+; GFX1364-NEXT: buffer_atomic_sub_u64 v[0:1], off, s[8:11], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: .LBB10_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_mad_co_u64_u32 v[3:4], null, s4, v2, 0
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_mad_co_u64_u32 v[4:5], null, s5, v2, v[4:5]
+; GFX1364-NEXT: v_sub_co_u32 v0, vcc, s2, v3
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v4, vcc
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: sub_i64_uniform:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_clause 0x1
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 nv
+; GFX1332-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-NEXT: s_mov_b32 s7, 0
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v2, s6, 0
+; GFX1332-NEXT: s_mov_b32 s8, exec_lo
+; GFX1332-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1332-NEXT: s_cbranch_execz .LBB10_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s6, s6
+; GFX1332-NEXT: s_mov_b32 s15, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mul_u64 s[6:7], s[4:5], s[6:7]
+; GFX1332-NEXT: s_mov_b32 s14, -1
+; GFX1332-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
+; GFX1332-NEXT: s_mov_b32 s12, s2
+; GFX1332-NEXT: s_mov_b32 s13, s3
+; GFX1332-NEXT: global_wb scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_storecnt 0x0
+; GFX1332-NEXT: buffer_atomic_sub_u64 v[0:1], off, s[12:15], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: .LBB10_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s8
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_mad_co_u64_u32 v[3:4], null, s4, v2, 0
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mad_co_u64_u32 v[4:5], null, s5, v2, v[4:5]
+; GFX1332-NEXT: v_sub_co_u32 v0, vcc_lo, s2, v3
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v4, vcc_lo
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw sub ptr addrspace(1) %inout, i64 %subitive syncscope("agent") acq_rel
store i64 %old, ptr addrspace(1) %out
@@ -8096,6 +9183,199 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out, ptr addrspace(
; GFX1232_DPP-NEXT: s_mov_b32 s2, s6
; GFX1232_DPP-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
; GFX1232_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: sub_i64_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_e32 v5, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1364-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_e32 v4, s2
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1364-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[4:5], -1
+; GFX1364-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s6, v2, 15
+; GFX1364-NEXT: v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s7, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s8, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s9, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v4, s6, 16
+; GFX1364-NEXT: v_readlane_b32 s6, v2, 63
+; GFX1364-NEXT: v_writelane_b32 v5, s7, 16
+; GFX1364-NEXT: v_readlane_b32 s10, v2, 47
+; GFX1364-NEXT: v_readlane_b32 s11, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s7, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v4, s8, 32
+; GFX1364-NEXT: v_writelane_b32 v5, s9, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[4:5]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[8:9], -1
+; GFX1364-NEXT: s_mov_b64 s[4:5], s[6:7]
+; GFX1364-NEXT: v_writelane_b32 v4, s10, 48
+; GFX1364-NEXT: v_writelane_b32 v5, s11, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[8:9]
+; GFX1364-NEXT: s_mov_b32 s6, -1
+; GFX1364-NEXT: s_mov_b64 s[8:9], exec
+; GFX1364-NEXT: ; implicit-def: $vgpr6_vgpr7
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1364-NEXT: s_cbranch_execz .LBB11_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v7, s5
+; GFX1364-NEXT: v_mov_b32_e32 v6, s4
+; GFX1364-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mov_b32 s4, s2
+; GFX1364-NEXT: s_mov_b32 s5, s3
+; GFX1364-NEXT: global_wb scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_storecnt 0x0
+; GFX1364-NEXT: buffer_atomic_sub_u64 v[6:7], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_DEV
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: .LBB11_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v6
+; GFX1364-NEXT: v_mov_b32_e32 v8, v4
+; GFX1364-NEXT: v_mov_b32_e32 v9, v5
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v7
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_sub_co_u32 v6, vcc, s2, v8
+; GFX1364-NEXT: v_sub_co_ci_u32_e64 v7, null, s3, v9, vcc
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, s6
+; GFX1364-NEXT: buffer_store_b64 v[6:7], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: sub_i64_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, 0, s0
+; GFX1332-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v3, 0, v0, s0
+; GFX1332-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, 0
+; GFX1332-NEXT: v_mov_b32_e32 v6, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1332-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
+; GFX1332-NEXT: v_mov_b32_e32 v2, 0
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_mov_b32_e32 v4, 0
+; GFX1332-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_mov_b32_e32 v3, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1332-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_or_saveexec_b32 s6, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
+; GFX1332-NEXT: v_readlane_b32 s4, v2, 31
+; GFX1332-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s7, v2, 15
+; GFX1332-NEXT: v_readlane_b32 s8, v1, 15
+; GFX1332-NEXT: v_readlane_b32 s5, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v7, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_mov_b32 exec_lo, s6
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s6, -1
+; GFX1332-NEXT: v_writelane_b32 v6, s7, 16
+; GFX1332-NEXT: v_writelane_b32 v7, s8, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s6
+; GFX1332-NEXT: s_mov_b32 s6, -1
+; GFX1332-NEXT: s_mov_b32 s8, exec_lo
+; GFX1332-NEXT: ; implicit-def: $vgpr8_vgpr9
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1332-NEXT: s_cbranch_execz .LBB11_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v9, s5 :: v_dual_mov_b32 v8, s4
+; GFX1332-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mov_b32 s4, s2
+; GFX1332-NEXT: s_mov_b32 s5, s3
+; GFX1332-NEXT: global_wb scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_storecnt 0x0
+; GFX1332-NEXT: buffer_atomic_sub_u64 v[8:9], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_DEV
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: .LBB11_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s8
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v8
+; GFX1332-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v11, v7
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v9
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_sub_co_u32 v8, vcc_lo, s2, v10
+; GFX1332-NEXT: v_sub_co_ci_u32_e64 v9, null, s3, v11, vcc_lo
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, s6
+; GFX1332-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%zext = zext i32 %lane to i64
@@ -8799,6 +10079,218 @@ define amdgpu_kernel void @uniform_or_i8(ptr addrspace(1) %result, ptr addrspace
; GFX1232-FAKE16-NEXT: v_or_b32_e32 v0, s0, v0
; GFX1232-FAKE16-NEXT: buffer_store_b8 v0, off, s[8:11], null
; GFX1232-FAKE16-NEXT: s_endpgm
+;
+; GFX1364-TRUE16-LABEL: uniform_or_i8:
+; GFX1364-TRUE16: ; %bb.0:
+; GFX1364-TRUE16-NEXT: s_clause 0x1
+; GFX1364-TRUE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24 nv
+; GFX1364-TRUE16-NEXT: s_load_b32 s12, s[4:5], 0x34 nv
+; GFX1364-TRUE16-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-TRUE16-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX1364-TRUE16-NEXT: s_and_saveexec_b64 s[2:3], vcc
+; GFX1364-TRUE16-NEXT: s_cbranch_execz .LBB12_4
+; GFX1364-TRUE16-NEXT: ; %bb.1:
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: s_and_b64 s[4:5], s[10:11], -4
+; GFX1364-TRUE16-NEXT: s_and_b32 s1, s10, 3
+; GFX1364-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x0
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s13, s1, 3
+; GFX1364-TRUE16-NEXT: s_and_b32 s1, s12, 0xff
+; GFX1364-TRUE16-NEXT: s_mov_b64 s[10:11], 0
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s14, s1, s13
+; GFX1364-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v1, s0
+; GFX1364-TRUE16-NEXT: .LBB12_2: ; %atomicrmw.start
+; GFX1364-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-TRUE16-NEXT: v_or_b32_e32 v0, s14, v1
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1364-TRUE16-NEXT: v_cmp_eq_u32_e64 s[0:1], v2, v1
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-TRUE16-NEXT: s_or_b64 s[10:11], s[0:1], s[10:11]
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-TRUE16-NEXT: s_and_not1_b64 exec, exec, s[10:11]
+; GFX1364-TRUE16-NEXT: s_cbranch_execnz .LBB12_2
+; GFX1364-TRUE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[10:11]
+; GFX1364-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s13, v2
+; GFX1364-TRUE16-NEXT: .LBB12_4: ; %Flow
+; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1364-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: v_cndmask_b16 v0.l, s12, 0, vcc
+; GFX1364-TRUE16-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1364-TRUE16-NEXT: s_mov_b32 s10, -1
+; GFX1364-TRUE16-NEXT: v_or_b16 v0.l, s0, v0.l
+; GFX1364-TRUE16-NEXT: buffer_store_b8 v0, off, s[8:11], null
+; GFX1364-TRUE16-NEXT: s_endpgm
+;
+; GFX1364-FAKE16-LABEL: uniform_or_i8:
+; GFX1364-FAKE16: ; %bb.0:
+; GFX1364-FAKE16-NEXT: s_clause 0x1
+; GFX1364-FAKE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24 nv
+; GFX1364-FAKE16-NEXT: s_load_b32 s12, s[4:5], 0x34 nv
+; GFX1364-FAKE16-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1364-FAKE16-NEXT: s_and_saveexec_b64 s[2:3], vcc
+; GFX1364-FAKE16-NEXT: s_cbranch_execz .LBB12_4
+; GFX1364-FAKE16-NEXT: ; %bb.1:
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: s_and_b64 s[4:5], s[10:11], -4
+; GFX1364-FAKE16-NEXT: s_and_b32 s1, s10, 3
+; GFX1364-FAKE16-NEXT: s_load_b32 s0, s[4:5], 0x0
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s13, s1, 3
+; GFX1364-FAKE16-NEXT: s_and_b32 s1, s12, 0xff
+; GFX1364-FAKE16-NEXT: s_mov_b64 s[10:11], 0
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s14, s1, s13
+; GFX1364-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-FAKE16-NEXT: s_mov_b32 s6, -1
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v1, s0
+; GFX1364-FAKE16-NEXT: .LBB12_2: ; %atomicrmw.start
+; GFX1364-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-FAKE16-NEXT: v_or_b32_e32 v0, s14, v1
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1364-FAKE16-NEXT: v_cmp_eq_u32_e64 s[0:1], v2, v1
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-FAKE16-NEXT: s_or_b64 s[10:11], s[0:1], s[10:11]
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-FAKE16-NEXT: s_and_not1_b64 exec, exec, s[10:11]
+; GFX1364-FAKE16-NEXT: s_cbranch_execnz .LBB12_2
+; GFX1364-FAKE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1364-FAKE16-NEXT: s_or_b64 exec, exec, s[10:11]
+; GFX1364-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s13, v2
+; GFX1364-FAKE16-NEXT: .LBB12_4: ; %Flow
+; GFX1364-FAKE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: v_cndmask_b32_e64 v0, s12, 0, vcc
+; GFX1364-FAKE16-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1364-FAKE16-NEXT: s_mov_b32 s10, -1
+; GFX1364-FAKE16-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX1364-FAKE16-NEXT: buffer_store_b8 v0, off, s[8:11], null
+; GFX1364-FAKE16-NEXT: s_endpgm
+;
+; GFX1332-TRUE16-LABEL: uniform_or_i8:
+; GFX1332-TRUE16: ; %bb.0:
+; GFX1332-TRUE16-NEXT: s_clause 0x1
+; GFX1332-TRUE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24 nv
+; GFX1332-TRUE16-NEXT: s_load_b32 s1, s[4:5], 0x34 nv
+; GFX1332-TRUE16-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-TRUE16-NEXT: s_mov_b32 s3, 0
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX1332-TRUE16-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX1332-TRUE16-NEXT: s_cbranch_execz .LBB12_4
+; GFX1332-TRUE16-NEXT: ; %bb.1:
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: s_and_b64 s[4:5], s[10:11], -4
+; GFX1332-TRUE16-NEXT: s_and_b32 s6, s10, 3
+; GFX1332-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x0
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s10, s6, 3
+; GFX1332-TRUE16-NEXT: s_and_b32 s6, s1, 0xff
+; GFX1332-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s11, s6, s10
+; GFX1332-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: v_mov_b32_e32 v1, s0
+; GFX1332-TRUE16-NEXT: .LBB12_2: ; %atomicrmw.start
+; GFX1332-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_or_b32_e32 v0, s11, v1
+; GFX1332-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1332-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, v2, v1
+; GFX1332-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-TRUE16-NEXT: s_or_b32 s3, s0, s3
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s3
+; GFX1332-TRUE16-NEXT: s_cbranch_execnz .LBB12_2
+; GFX1332-TRUE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX1332-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s10, v2
+; GFX1332-TRUE16-NEXT: .LBB12_4: ; %Flow
+; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: v_cndmask_b16 v0.l, s1, 0, vcc_lo
+; GFX1332-TRUE16-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1332-TRUE16-NEXT: s_mov_b32 s10, -1
+; GFX1332-TRUE16-NEXT: v_or_b16 v0.l, s0, v0.l
+; GFX1332-TRUE16-NEXT: buffer_store_b8 v0, off, s[8:11], null
+; GFX1332-TRUE16-NEXT: s_endpgm
+;
+; GFX1332-FAKE16-LABEL: uniform_or_i8:
+; GFX1332-FAKE16: ; %bb.0:
+; GFX1332-FAKE16-NEXT: s_clause 0x1
+; GFX1332-FAKE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24 nv
+; GFX1332-FAKE16-NEXT: s_load_b32 s1, s[4:5], 0x34 nv
+; GFX1332-FAKE16-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-FAKE16-NEXT: s_mov_b32 s3, 0
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1332-FAKE16-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX1332-FAKE16-NEXT: s_cbranch_execz .LBB12_4
+; GFX1332-FAKE16-NEXT: ; %bb.1:
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: s_and_b64 s[4:5], s[10:11], -4
+; GFX1332-FAKE16-NEXT: s_and_b32 s6, s10, 3
+; GFX1332-FAKE16-NEXT: s_load_b32 s0, s[4:5], 0x0
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s10, s6, 3
+; GFX1332-FAKE16-NEXT: s_and_b32 s6, s1, 0xff
+; GFX1332-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s11, s6, s10
+; GFX1332-FAKE16-NEXT: s_mov_b32 s6, -1
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: v_mov_b32_e32 v1, s0
+; GFX1332-FAKE16-NEXT: .LBB12_2: ; %atomicrmw.start
+; GFX1332-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_or_b32_e32 v0, s11, v1
+; GFX1332-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1332-FAKE16-NEXT: v_cmp_eq_u32_e64 s0, v2, v1
+; GFX1332-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-FAKE16-NEXT: s_or_b32 s3, s0, s3
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s3
+; GFX1332-FAKE16-NEXT: s_cbranch_execnz .LBB12_2
+; GFX1332-FAKE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1332-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX1332-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s10, v2
+; GFX1332-FAKE16-NEXT: .LBB12_4: ; %Flow
+; GFX1332-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: v_cndmask_b32_e64 v0, s1, 0, vcc_lo
+; GFX1332-FAKE16-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1332-FAKE16-NEXT: s_mov_b32 s10, -1
+; GFX1332-FAKE16-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX1332-FAKE16-NEXT: buffer_store_b8 v0, off, s[8:11], null
+; GFX1332-FAKE16-NEXT: s_endpgm
%rmw = atomicrmw or ptr addrspace(1) %uniform.ptr, i8 %val monotonic, align 1
store i8 %rmw, ptr addrspace(1) %result
ret void
@@ -9594,6 +11086,246 @@ define amdgpu_kernel void @uniform_add_i8(ptr addrspace(1) %result, ptr addrspac
; GFX1232-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1232-FAKE16-NEXT: buffer_store_b8 v0, off, s[0:3], null
; GFX1232-FAKE16-NEXT: s_endpgm
+;
+; GFX1364-TRUE16-LABEL: uniform_add_i8:
+; GFX1364-TRUE16: ; %bb.0:
+; GFX1364-TRUE16-NEXT: s_clause 0x1
+; GFX1364-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-TRUE16-NEXT: s_load_b32 s10, s[4:5], 0x34 nv
+; GFX1364-TRUE16-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-TRUE16-NEXT: s_mov_b64 s[8:9], exec
+; GFX1364-TRUE16-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-TRUE16-NEXT: v_mbcnt_hi_u32_b32 v4, s7, v0
+; GFX1364-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX1364-TRUE16-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1364-TRUE16-NEXT: s_cbranch_execz .LBB13_4
+; GFX1364-TRUE16-NEXT: ; %bb.1:
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1364-TRUE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1364-TRUE16-NEXT: s_load_b32 s3, s[4:5], 0x0
+; GFX1364-TRUE16-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s11, s2, 3
+; GFX1364-TRUE16-NEXT: s_mul_i32 s2, s10, s6
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s12, 0xff, s11
+; GFX1364-TRUE16-NEXT: s_and_b32 s2, s2, 0xff
+; GFX1364-TRUE16-NEXT: s_not_b32 s13, s12
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s14, s2, s11
+; GFX1364-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v1, s3
+; GFX1364-TRUE16-NEXT: s_mov_b64 s[2:3], 0
+; GFX1364-TRUE16-NEXT: .LBB13_2: ; %atomicrmw.start
+; GFX1364-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-TRUE16-NEXT: v_add_nc_u32_e32 v0, s14, v1
+; GFX1364-TRUE16-NEXT: v_and_b32_e32 v0, s12, v0
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-TRUE16-NEXT: v_and_or_b32 v0, v1, s13, v0
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1364-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-TRUE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-TRUE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
+; GFX1364-TRUE16-NEXT: s_cbranch_execnz .LBB13_2
+; GFX1364-TRUE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s11, v2
+; GFX1364-TRUE16-NEXT: .LBB13_4: ; %Flow
+; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-TRUE16-NEXT: v_mad_u16 v0.l, s10, v4.l, s2
+; GFX1364-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX1364-TRUE16-NEXT: buffer_store_b8 v0, off, s[0:3], null
+; GFX1364-TRUE16-NEXT: s_endpgm
+;
+; GFX1364-FAKE16-LABEL: uniform_add_i8:
+; GFX1364-FAKE16: ; %bb.0:
+; GFX1364-FAKE16-NEXT: s_clause 0x1
+; GFX1364-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-FAKE16-NEXT: s_load_b32 s10, s[4:5], 0x34 nv
+; GFX1364-FAKE16-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-FAKE16-NEXT: s_mov_b64 s[8:9], exec
+; GFX1364-FAKE16-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_mbcnt_hi_u32_b32 v4, s7, v0
+; GFX1364-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1364-FAKE16-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1364-FAKE16-NEXT: s_cbranch_execz .LBB13_4
+; GFX1364-FAKE16-NEXT: ; %bb.1:
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1364-FAKE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1364-FAKE16-NEXT: s_load_b32 s3, s[4:5], 0x0
+; GFX1364-FAKE16-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s11, s2, 3
+; GFX1364-FAKE16-NEXT: s_mul_i32 s2, s10, s6
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s12, 0xff, s11
+; GFX1364-FAKE16-NEXT: s_and_b32 s2, s2, 0xff
+; GFX1364-FAKE16-NEXT: s_not_b32 s13, s12
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s14, s2, s11
+; GFX1364-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-FAKE16-NEXT: s_mov_b32 s6, -1
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v1, s3
+; GFX1364-FAKE16-NEXT: s_mov_b64 s[2:3], 0
+; GFX1364-FAKE16-NEXT: .LBB13_2: ; %atomicrmw.start
+; GFX1364-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_add_nc_u32_e32 v0, s14, v1
+; GFX1364-FAKE16-NEXT: v_and_b32_e32 v0, s12, v0
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-FAKE16-NEXT: v_and_or_b32 v0, v1, s13, v0
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1364-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-FAKE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-FAKE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
+; GFX1364-FAKE16-NEXT: s_cbranch_execnz .LBB13_2
+; GFX1364-FAKE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1364-FAKE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s11, v2
+; GFX1364-FAKE16-NEXT: .LBB13_4: ; %Flow
+; GFX1364-FAKE16-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-FAKE16-NEXT: v_mad_u16 v0, s10, v4, s2
+; GFX1364-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX1364-FAKE16-NEXT: buffer_store_b8 v0, off, s[0:3], null
+; GFX1364-FAKE16-NEXT: s_endpgm
+;
+; GFX1332-TRUE16-LABEL: uniform_add_i8:
+; GFX1332-TRUE16: ; %bb.0:
+; GFX1332-TRUE16-NEXT: s_clause 0x1
+; GFX1332-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-TRUE16-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1332-TRUE16-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-TRUE16-NEXT: s_mov_b32 s10, 0
+; GFX1332-TRUE16-NEXT: v_mbcnt_lo_u32_b32 v4, s6, 0
+; GFX1332-TRUE16-NEXT: s_mov_b32 s9, exec_lo
+; GFX1332-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1332-TRUE16-NEXT: s_cbranch_execz .LBB13_4
+; GFX1332-TRUE16-NEXT: ; %bb.1:
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1332-TRUE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1332-TRUE16-NEXT: s_load_b32 s7, s[4:5], 0x0
+; GFX1332-TRUE16-NEXT: s_bcnt1_i32_b32 s6, s6
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s2, s2, 3
+; GFX1332-TRUE16-NEXT: s_mul_i32 s6, s8, s6
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s3, 0xff, s2
+; GFX1332-TRUE16-NEXT: s_and_b32 s6, s6, 0xff
+; GFX1332-TRUE16-NEXT: s_not_b32 s11, s3
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s12, s6, s2
+; GFX1332-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: v_mov_b32_e32 v1, s7
+; GFX1332-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-TRUE16-NEXT: .LBB13_2: ; %atomicrmw.start
+; GFX1332-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_add_nc_u32_e32 v0, s12, v1
+; GFX1332-TRUE16-NEXT: v_and_b32_e32 v0, s3, v0
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_and_or_b32 v0, v1, s11, v0
+; GFX1332-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1332-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1332-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-TRUE16-NEXT: s_or_b32 s10, vcc_lo, s10
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s10
+; GFX1332-TRUE16-NEXT: s_cbranch_execnz .LBB13_2
+; GFX1332-TRUE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s10
+; GFX1332-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
+; GFX1332-TRUE16-NEXT: .LBB13_4: ; %Flow
+; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-TRUE16-NEXT: v_mad_u16 v0.l, s8, v4.l, s2
+; GFX1332-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX1332-TRUE16-NEXT: buffer_store_b8 v0, off, s[0:3], null
+; GFX1332-TRUE16-NEXT: s_endpgm
+;
+; GFX1332-FAKE16-LABEL: uniform_add_i8:
+; GFX1332-FAKE16: ; %bb.0:
+; GFX1332-FAKE16-NEXT: s_clause 0x1
+; GFX1332-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-FAKE16-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1332-FAKE16-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-FAKE16-NEXT: s_mov_b32 s10, 0
+; GFX1332-FAKE16-NEXT: v_mbcnt_lo_u32_b32 v4, s6, 0
+; GFX1332-FAKE16-NEXT: s_mov_b32 s9, exec_lo
+; GFX1332-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1332-FAKE16-NEXT: s_cbranch_execz .LBB13_4
+; GFX1332-FAKE16-NEXT: ; %bb.1:
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1332-FAKE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1332-FAKE16-NEXT: s_load_b32 s7, s[4:5], 0x0
+; GFX1332-FAKE16-NEXT: s_bcnt1_i32_b32 s6, s6
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s2, s2, 3
+; GFX1332-FAKE16-NEXT: s_mul_i32 s6, s8, s6
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s3, 0xff, s2
+; GFX1332-FAKE16-NEXT: s_and_b32 s6, s6, 0xff
+; GFX1332-FAKE16-NEXT: s_not_b32 s11, s3
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s12, s6, s2
+; GFX1332-FAKE16-NEXT: s_mov_b32 s6, -1
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: v_mov_b32_e32 v1, s7
+; GFX1332-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-FAKE16-NEXT: .LBB13_2: ; %atomicrmw.start
+; GFX1332-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_add_nc_u32_e32 v0, s12, v1
+; GFX1332-FAKE16-NEXT: v_and_b32_e32 v0, s3, v0
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_and_or_b32 v0, v1, s11, v0
+; GFX1332-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1332-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1332-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-FAKE16-NEXT: s_or_b32 s10, vcc_lo, s10
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s10
+; GFX1332-FAKE16-NEXT: s_cbranch_execnz .LBB13_2
+; GFX1332-FAKE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1332-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s10
+; GFX1332-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
+; GFX1332-FAKE16-NEXT: .LBB13_4: ; %Flow
+; GFX1332-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-FAKE16-NEXT: v_mad_u16 v0, s8, v4, s2
+; GFX1332-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX1332-FAKE16-NEXT: buffer_store_b8 v0, off, s[0:3], null
+; GFX1332-FAKE16-NEXT: s_endpgm
%rmw = atomicrmw add ptr addrspace(1) %uniform.ptr, i8 %val monotonic, align 1
store i8 %rmw, ptr addrspace(1) %result
ret void
@@ -9966,6 +11698,87 @@ define amdgpu_kernel void @uniform_xchg_i8(ptr addrspace(1) %result, ptr addrspa
; GFX1232-NEXT: s_mov_b32 s2, -1
; GFX1232-NEXT: buffer_store_b8 v0, off, s[0:3], null
; GFX1232-NEXT: s_endpgm
+;
+; GFX1364-LABEL: uniform_xchg_i8:
+; GFX1364: ; %bb.0:
+; GFX1364-NEXT: s_clause 0x1
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_load_b32 s6, s[4:5], 0x34 nv
+; GFX1364-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1364-NEXT: s_and_b32 s2, s2, 3
+; GFX1364-NEXT: s_load_b32 s3, s[4:5], 0x0
+; GFX1364-NEXT: s_lshl_b32 s8, s2, 3
+; GFX1364-NEXT: s_and_b32 s6, s6, 0xff
+; GFX1364-NEXT: s_lshl_b32 s2, 0xff, s8
+; GFX1364-NEXT: s_lshl_b32 s10, s6, s8
+; GFX1364-NEXT: s_not_b32 s9, s2
+; GFX1364-NEXT: s_mov_b32 s6, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_mov_b32_e32 v1, s3
+; GFX1364-NEXT: s_mov_b64 s[2:3], 0
+; GFX1364-NEXT: .LBB14_1: ; %atomicrmw.start
+; GFX1364-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_and_or_b32 v0, v1, s9, s10
+; GFX1364-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1364-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: s_and_not1_b64 exec, exec, s[2:3]
+; GFX1364-NEXT: s_cbranch_execnz .LBB14_1
+; GFX1364-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1364-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-NEXT: v_lshrrev_b32_e32 v0, s8, v2
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: buffer_store_b8 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: uniform_xchg_i8:
+; GFX1332: ; %bb.0:
+; GFX1332-NEXT: s_clause 0x1
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_load_b32 s6, s[4:5], 0x34 nv
+; GFX1332-NEXT: s_mov_b32 s9, 0
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1332-NEXT: s_and_b32 s2, s2, 3
+; GFX1332-NEXT: s_load_b32 s7, s[4:5], 0x0
+; GFX1332-NEXT: s_lshl_b32 s2, s2, 3
+; GFX1332-NEXT: s_and_b32 s6, s6, 0xff
+; GFX1332-NEXT: s_lshl_b32 s3, 0xff, s2
+; GFX1332-NEXT: s_lshl_b32 s8, s6, s2
+; GFX1332-NEXT: s_not_b32 s3, s3
+; GFX1332-NEXT: s_mov_b32 s6, -1
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_mov_b32_e32 v1, s7
+; GFX1332-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-NEXT: .LBB14_1: ; %atomicrmw.start
+; GFX1332-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_and_or_b32 v0, v1, s3, s8
+; GFX1332-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1332-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-NEXT: s_or_b32 s9, vcc_lo, s9
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: s_and_not1_b32 exec_lo, exec_lo, s9
+; GFX1332-NEXT: s_cbranch_execnz .LBB14_1
+; GFX1332-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-NEXT: v_lshrrev_b32_e32 v0, s2, v2
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: buffer_store_b8 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
%rmw = atomicrmw xchg ptr addrspace(1) %uniform.ptr, i8 %val monotonic, align 1
store i8 %rmw, ptr addrspace(1) %result
ret void
@@ -10666,6 +12479,218 @@ define amdgpu_kernel void @uniform_or_i16(ptr addrspace(1) %result, ptr addrspac
; GFX1232-FAKE16-NEXT: v_or_b32_e32 v0, s0, v0
; GFX1232-FAKE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
; GFX1232-FAKE16-NEXT: s_endpgm
+;
+; GFX1364-TRUE16-LABEL: uniform_or_i16:
+; GFX1364-TRUE16: ; %bb.0:
+; GFX1364-TRUE16-NEXT: s_clause 0x1
+; GFX1364-TRUE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24 nv
+; GFX1364-TRUE16-NEXT: s_load_b32 s12, s[4:5], 0x34 nv
+; GFX1364-TRUE16-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-TRUE16-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX1364-TRUE16-NEXT: s_and_saveexec_b64 s[2:3], vcc
+; GFX1364-TRUE16-NEXT: s_cbranch_execz .LBB15_4
+; GFX1364-TRUE16-NEXT: ; %bb.1:
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: s_and_b64 s[4:5], s[10:11], -4
+; GFX1364-TRUE16-NEXT: s_and_b32 s1, s10, 3
+; GFX1364-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x0
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s13, s1, 3
+; GFX1364-TRUE16-NEXT: s_and_b32 s1, 0xffff, s12
+; GFX1364-TRUE16-NEXT: s_mov_b64 s[10:11], 0
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s14, s1, s13
+; GFX1364-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v1, s0
+; GFX1364-TRUE16-NEXT: .LBB15_2: ; %atomicrmw.start
+; GFX1364-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-TRUE16-NEXT: v_or_b32_e32 v0, s14, v1
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1364-TRUE16-NEXT: v_cmp_eq_u32_e64 s[0:1], v2, v1
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-TRUE16-NEXT: s_or_b64 s[10:11], s[0:1], s[10:11]
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-TRUE16-NEXT: s_and_not1_b64 exec, exec, s[10:11]
+; GFX1364-TRUE16-NEXT: s_cbranch_execnz .LBB15_2
+; GFX1364-TRUE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[10:11]
+; GFX1364-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s13, v2
+; GFX1364-TRUE16-NEXT: .LBB15_4: ; %Flow
+; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1364-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: v_cndmask_b16 v0.l, s12, 0, vcc
+; GFX1364-TRUE16-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1364-TRUE16-NEXT: s_mov_b32 s10, -1
+; GFX1364-TRUE16-NEXT: v_or_b16 v0.l, s0, v0.l
+; GFX1364-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
+; GFX1364-TRUE16-NEXT: s_endpgm
+;
+; GFX1364-FAKE16-LABEL: uniform_or_i16:
+; GFX1364-FAKE16: ; %bb.0:
+; GFX1364-FAKE16-NEXT: s_clause 0x1
+; GFX1364-FAKE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24 nv
+; GFX1364-FAKE16-NEXT: s_load_b32 s12, s[4:5], 0x34 nv
+; GFX1364-FAKE16-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1364-FAKE16-NEXT: s_and_saveexec_b64 s[2:3], vcc
+; GFX1364-FAKE16-NEXT: s_cbranch_execz .LBB15_4
+; GFX1364-FAKE16-NEXT: ; %bb.1:
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: s_and_b64 s[4:5], s[10:11], -4
+; GFX1364-FAKE16-NEXT: s_and_b32 s1, s10, 3
+; GFX1364-FAKE16-NEXT: s_load_b32 s0, s[4:5], 0x0
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s13, s1, 3
+; GFX1364-FAKE16-NEXT: s_and_b32 s1, 0xffff, s12
+; GFX1364-FAKE16-NEXT: s_mov_b64 s[10:11], 0
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s14, s1, s13
+; GFX1364-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-FAKE16-NEXT: s_mov_b32 s6, -1
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v1, s0
+; GFX1364-FAKE16-NEXT: .LBB15_2: ; %atomicrmw.start
+; GFX1364-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-FAKE16-NEXT: v_or_b32_e32 v0, s14, v1
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1364-FAKE16-NEXT: v_cmp_eq_u32_e64 s[0:1], v2, v1
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-FAKE16-NEXT: s_or_b64 s[10:11], s[0:1], s[10:11]
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-FAKE16-NEXT: s_and_not1_b64 exec, exec, s[10:11]
+; GFX1364-FAKE16-NEXT: s_cbranch_execnz .LBB15_2
+; GFX1364-FAKE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1364-FAKE16-NEXT: s_or_b64 exec, exec, s[10:11]
+; GFX1364-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s13, v2
+; GFX1364-FAKE16-NEXT: .LBB15_4: ; %Flow
+; GFX1364-FAKE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: v_cndmask_b32_e64 v0, s12, 0, vcc
+; GFX1364-FAKE16-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1364-FAKE16-NEXT: s_mov_b32 s10, -1
+; GFX1364-FAKE16-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX1364-FAKE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
+; GFX1364-FAKE16-NEXT: s_endpgm
+;
+; GFX1332-TRUE16-LABEL: uniform_or_i16:
+; GFX1332-TRUE16: ; %bb.0:
+; GFX1332-TRUE16-NEXT: s_clause 0x1
+; GFX1332-TRUE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24 nv
+; GFX1332-TRUE16-NEXT: s_load_b32 s1, s[4:5], 0x34 nv
+; GFX1332-TRUE16-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-TRUE16-NEXT: s_mov_b32 s3, 0
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX1332-TRUE16-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX1332-TRUE16-NEXT: s_cbranch_execz .LBB15_4
+; GFX1332-TRUE16-NEXT: ; %bb.1:
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: s_and_b64 s[4:5], s[10:11], -4
+; GFX1332-TRUE16-NEXT: s_and_b32 s6, s10, 3
+; GFX1332-TRUE16-NEXT: s_load_b32 s0, s[4:5], 0x0
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s10, s6, 3
+; GFX1332-TRUE16-NEXT: s_and_b32 s6, 0xffff, s1
+; GFX1332-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s11, s6, s10
+; GFX1332-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: v_mov_b32_e32 v1, s0
+; GFX1332-TRUE16-NEXT: .LBB15_2: ; %atomicrmw.start
+; GFX1332-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_or_b32_e32 v0, s11, v1
+; GFX1332-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1332-TRUE16-NEXT: v_cmp_eq_u32_e64 s0, v2, v1
+; GFX1332-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-TRUE16-NEXT: s_or_b32 s3, s0, s3
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s3
+; GFX1332-TRUE16-NEXT: s_cbranch_execnz .LBB15_2
+; GFX1332-TRUE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX1332-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s10, v2
+; GFX1332-TRUE16-NEXT: .LBB15_4: ; %Flow
+; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: v_cndmask_b16 v0.l, s1, 0, vcc_lo
+; GFX1332-TRUE16-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1332-TRUE16-NEXT: s_mov_b32 s10, -1
+; GFX1332-TRUE16-NEXT: v_or_b16 v0.l, s0, v0.l
+; GFX1332-TRUE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
+; GFX1332-TRUE16-NEXT: s_endpgm
+;
+; GFX1332-FAKE16-LABEL: uniform_or_i16:
+; GFX1332-FAKE16: ; %bb.0:
+; GFX1332-FAKE16-NEXT: s_clause 0x1
+; GFX1332-FAKE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24 nv
+; GFX1332-FAKE16-NEXT: s_load_b32 s1, s[4:5], 0x34 nv
+; GFX1332-FAKE16-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-FAKE16-NEXT: s_mov_b32 s3, 0
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1332-FAKE16-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX1332-FAKE16-NEXT: s_cbranch_execz .LBB15_4
+; GFX1332-FAKE16-NEXT: ; %bb.1:
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: s_and_b64 s[4:5], s[10:11], -4
+; GFX1332-FAKE16-NEXT: s_and_b32 s6, s10, 3
+; GFX1332-FAKE16-NEXT: s_load_b32 s0, s[4:5], 0x0
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s10, s6, 3
+; GFX1332-FAKE16-NEXT: s_and_b32 s6, 0xffff, s1
+; GFX1332-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s11, s6, s10
+; GFX1332-FAKE16-NEXT: s_mov_b32 s6, -1
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: v_mov_b32_e32 v1, s0
+; GFX1332-FAKE16-NEXT: .LBB15_2: ; %atomicrmw.start
+; GFX1332-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_or_b32_e32 v0, s11, v1
+; GFX1332-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1332-FAKE16-NEXT: v_cmp_eq_u32_e64 s0, v2, v1
+; GFX1332-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-FAKE16-NEXT: s_or_b32 s3, s0, s3
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s3
+; GFX1332-FAKE16-NEXT: s_cbranch_execnz .LBB15_2
+; GFX1332-FAKE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1332-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX1332-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s10, v2
+; GFX1332-FAKE16-NEXT: .LBB15_4: ; %Flow
+; GFX1332-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: v_cndmask_b32_e64 v0, s1, 0, vcc_lo
+; GFX1332-FAKE16-NEXT: s_mov_b32 s11, 0x31016000
+; GFX1332-FAKE16-NEXT: s_mov_b32 s10, -1
+; GFX1332-FAKE16-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX1332-FAKE16-NEXT: buffer_store_b16 v0, off, s[8:11], null
+; GFX1332-FAKE16-NEXT: s_endpgm
%rmw = atomicrmw or ptr addrspace(1) %uniform.ptr, i16 %val monotonic, align 2
store i16 %rmw, ptr addrspace(1) %result
ret void
@@ -11461,6 +13486,246 @@ define amdgpu_kernel void @uniform_add_i16(ptr addrspace(1) %result, ptr addrspa
; GFX1232-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1232-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1232-FAKE16-NEXT: s_endpgm
+;
+; GFX1364-TRUE16-LABEL: uniform_add_i16:
+; GFX1364-TRUE16: ; %bb.0:
+; GFX1364-TRUE16-NEXT: s_clause 0x1
+; GFX1364-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-TRUE16-NEXT: s_load_b32 s10, s[4:5], 0x34 nv
+; GFX1364-TRUE16-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-TRUE16-NEXT: s_mov_b64 s[8:9], exec
+; GFX1364-TRUE16-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-TRUE16-NEXT: v_mbcnt_hi_u32_b32 v4, s7, v0
+; GFX1364-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX1364-TRUE16-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1364-TRUE16-NEXT: s_cbranch_execz .LBB16_4
+; GFX1364-TRUE16-NEXT: ; %bb.1:
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1364-TRUE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1364-TRUE16-NEXT: s_load_b32 s3, s[4:5], 0x0
+; GFX1364-TRUE16-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s11, s2, 3
+; GFX1364-TRUE16-NEXT: s_mul_i32 s2, s10, s6
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s12, 0xffff, s11
+; GFX1364-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1364-TRUE16-NEXT: s_not_b32 s13, s12
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s14, s2, s11
+; GFX1364-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v1, s3
+; GFX1364-TRUE16-NEXT: s_mov_b64 s[2:3], 0
+; GFX1364-TRUE16-NEXT: .LBB16_2: ; %atomicrmw.start
+; GFX1364-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-TRUE16-NEXT: v_add_nc_u32_e32 v0, s14, v1
+; GFX1364-TRUE16-NEXT: v_and_b32_e32 v0, s12, v0
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-TRUE16-NEXT: v_and_or_b32 v0, v1, s13, v0
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1364-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-TRUE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-TRUE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
+; GFX1364-TRUE16-NEXT: s_cbranch_execnz .LBB16_2
+; GFX1364-TRUE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s11, v2
+; GFX1364-TRUE16-NEXT: .LBB16_4: ; %Flow
+; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-TRUE16-NEXT: v_mad_u16 v0.l, s10, v4.l, s2
+; GFX1364-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX1364-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1364-TRUE16-NEXT: s_endpgm
+;
+; GFX1364-FAKE16-LABEL: uniform_add_i16:
+; GFX1364-FAKE16: ; %bb.0:
+; GFX1364-FAKE16-NEXT: s_clause 0x1
+; GFX1364-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-FAKE16-NEXT: s_load_b32 s10, s[4:5], 0x34 nv
+; GFX1364-FAKE16-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-FAKE16-NEXT: s_mov_b64 s[8:9], exec
+; GFX1364-FAKE16-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_mbcnt_hi_u32_b32 v4, s7, v0
+; GFX1364-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1364-FAKE16-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1364-FAKE16-NEXT: s_cbranch_execz .LBB16_4
+; GFX1364-FAKE16-NEXT: ; %bb.1:
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1364-FAKE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1364-FAKE16-NEXT: s_load_b32 s3, s[4:5], 0x0
+; GFX1364-FAKE16-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s11, s2, 3
+; GFX1364-FAKE16-NEXT: s_mul_i32 s2, s10, s6
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s12, 0xffff, s11
+; GFX1364-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1364-FAKE16-NEXT: s_not_b32 s13, s12
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s14, s2, s11
+; GFX1364-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-FAKE16-NEXT: s_mov_b32 s6, -1
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v1, s3
+; GFX1364-FAKE16-NEXT: s_mov_b64 s[2:3], 0
+; GFX1364-FAKE16-NEXT: .LBB16_2: ; %atomicrmw.start
+; GFX1364-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_add_nc_u32_e32 v0, s14, v1
+; GFX1364-FAKE16-NEXT: v_and_b32_e32 v0, s12, v0
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-FAKE16-NEXT: v_and_or_b32 v0, v1, s13, v0
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1364-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-FAKE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-FAKE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
+; GFX1364-FAKE16-NEXT: s_cbranch_execnz .LBB16_2
+; GFX1364-FAKE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1364-FAKE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s11, v2
+; GFX1364-FAKE16-NEXT: .LBB16_4: ; %Flow
+; GFX1364-FAKE16-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-FAKE16-NEXT: v_mad_u16 v0, s10, v4, s2
+; GFX1364-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX1364-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1364-FAKE16-NEXT: s_endpgm
+;
+; GFX1332-TRUE16-LABEL: uniform_add_i16:
+; GFX1332-TRUE16: ; %bb.0:
+; GFX1332-TRUE16-NEXT: s_clause 0x1
+; GFX1332-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-TRUE16-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1332-TRUE16-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-TRUE16-NEXT: s_mov_b32 s10, 0
+; GFX1332-TRUE16-NEXT: v_mbcnt_lo_u32_b32 v4, s6, 0
+; GFX1332-TRUE16-NEXT: s_mov_b32 s9, exec_lo
+; GFX1332-TRUE16-NEXT: ; implicit-def: $vgpr0_lo16
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1332-TRUE16-NEXT: s_cbranch_execz .LBB16_4
+; GFX1332-TRUE16-NEXT: ; %bb.1:
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1332-TRUE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1332-TRUE16-NEXT: s_load_b32 s7, s[4:5], 0x0
+; GFX1332-TRUE16-NEXT: s_bcnt1_i32_b32 s6, s6
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s2, s2, 3
+; GFX1332-TRUE16-NEXT: s_mul_i32 s6, s8, s6
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s3, 0xffff, s2
+; GFX1332-TRUE16-NEXT: s_and_b32 s6, s6, 0xffff
+; GFX1332-TRUE16-NEXT: s_not_b32 s11, s3
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s12, s6, s2
+; GFX1332-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: v_mov_b32_e32 v1, s7
+; GFX1332-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-TRUE16-NEXT: .LBB16_2: ; %atomicrmw.start
+; GFX1332-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_add_nc_u32_e32 v0, s12, v1
+; GFX1332-TRUE16-NEXT: v_and_b32_e32 v0, s3, v0
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_and_or_b32 v0, v1, s11, v0
+; GFX1332-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1332-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1332-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-TRUE16-NEXT: s_or_b32 s10, vcc_lo, s10
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s10
+; GFX1332-TRUE16-NEXT: s_cbranch_execnz .LBB16_2
+; GFX1332-TRUE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s10
+; GFX1332-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
+; GFX1332-TRUE16-NEXT: .LBB16_4: ; %Flow
+; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-TRUE16-NEXT: v_mad_u16 v0.l, s8, v4.l, s2
+; GFX1332-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX1332-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1332-TRUE16-NEXT: s_endpgm
+;
+; GFX1332-FAKE16-LABEL: uniform_add_i16:
+; GFX1332-FAKE16: ; %bb.0:
+; GFX1332-FAKE16-NEXT: s_clause 0x1
+; GFX1332-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-FAKE16-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1332-FAKE16-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-FAKE16-NEXT: s_mov_b32 s10, 0
+; GFX1332-FAKE16-NEXT: v_mbcnt_lo_u32_b32 v4, s6, 0
+; GFX1332-FAKE16-NEXT: s_mov_b32 s9, exec_lo
+; GFX1332-FAKE16-NEXT: ; implicit-def: $vgpr0
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1332-FAKE16-NEXT: s_cbranch_execz .LBB16_4
+; GFX1332-FAKE16-NEXT: ; %bb.1:
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1332-FAKE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1332-FAKE16-NEXT: s_load_b32 s7, s[4:5], 0x0
+; GFX1332-FAKE16-NEXT: s_bcnt1_i32_b32 s6, s6
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s2, s2, 3
+; GFX1332-FAKE16-NEXT: s_mul_i32 s6, s8, s6
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s3, 0xffff, s2
+; GFX1332-FAKE16-NEXT: s_and_b32 s6, s6, 0xffff
+; GFX1332-FAKE16-NEXT: s_not_b32 s11, s3
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s12, s6, s2
+; GFX1332-FAKE16-NEXT: s_mov_b32 s6, -1
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: v_mov_b32_e32 v1, s7
+; GFX1332-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-FAKE16-NEXT: .LBB16_2: ; %atomicrmw.start
+; GFX1332-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_add_nc_u32_e32 v0, s12, v1
+; GFX1332-FAKE16-NEXT: v_and_b32_e32 v0, s3, v0
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_and_or_b32 v0, v1, s11, v0
+; GFX1332-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1332-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1332-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-FAKE16-NEXT: s_or_b32 s10, vcc_lo, s10
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s10
+; GFX1332-FAKE16-NEXT: s_cbranch_execnz .LBB16_2
+; GFX1332-FAKE16-NEXT: ; %bb.3: ; %atomicrmw.end
+; GFX1332-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s10
+; GFX1332-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
+; GFX1332-FAKE16-NEXT: .LBB16_4: ; %Flow
+; GFX1332-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-FAKE16-NEXT: v_mad_u16 v0, s8, v4, s2
+; GFX1332-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX1332-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1332-FAKE16-NEXT: s_endpgm
%rmw = atomicrmw add ptr addrspace(1) %uniform.ptr, i16 %val monotonic, align 2
store i16 %rmw, ptr addrspace(1) %result
ret void
@@ -11833,6 +14098,87 @@ define amdgpu_kernel void @uniform_xchg_i16(ptr addrspace(1) %result, ptr addrsp
; GFX1232-NEXT: s_mov_b32 s2, -1
; GFX1232-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1232-NEXT: s_endpgm
+;
+; GFX1364-LABEL: uniform_xchg_i16:
+; GFX1364: ; %bb.0:
+; GFX1364-NEXT: s_clause 0x1
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_load_b32 s6, s[4:5], 0x34 nv
+; GFX1364-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1364-NEXT: s_and_b32 s2, s2, 3
+; GFX1364-NEXT: s_load_b32 s3, s[4:5], 0x0
+; GFX1364-NEXT: s_lshl_b32 s8, s2, 3
+; GFX1364-NEXT: s_and_b32 s6, s6, 0xffff
+; GFX1364-NEXT: s_lshl_b32 s2, 0xffff, s8
+; GFX1364-NEXT: s_lshl_b32 s10, s6, s8
+; GFX1364-NEXT: s_not_b32 s9, s2
+; GFX1364-NEXT: s_mov_b32 s6, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_mov_b32_e32 v1, s3
+; GFX1364-NEXT: s_mov_b64 s[2:3], 0
+; GFX1364-NEXT: .LBB17_1: ; %atomicrmw.start
+; GFX1364-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_and_or_b32 v0, v1, s9, s10
+; GFX1364-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1364-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: s_and_not1_b64 exec, exec, s[2:3]
+; GFX1364-NEXT: s_cbranch_execnz .LBB17_1
+; GFX1364-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1364-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-NEXT: v_lshrrev_b32_e32 v0, s8, v2
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: uniform_xchg_i16:
+; GFX1332: ; %bb.0:
+; GFX1332-NEXT: s_clause 0x1
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_load_b32 s6, s[4:5], 0x34 nv
+; GFX1332-NEXT: s_mov_b32 s9, 0
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1332-NEXT: s_and_b32 s2, s2, 3
+; GFX1332-NEXT: s_load_b32 s7, s[4:5], 0x0
+; GFX1332-NEXT: s_lshl_b32 s2, s2, 3
+; GFX1332-NEXT: s_and_b32 s6, s6, 0xffff
+; GFX1332-NEXT: s_lshl_b32 s3, 0xffff, s2
+; GFX1332-NEXT: s_lshl_b32 s8, s6, s2
+; GFX1332-NEXT: s_not_b32 s3, s3
+; GFX1332-NEXT: s_mov_b32 s6, -1
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_mov_b32_e32 v1, s7
+; GFX1332-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-NEXT: .LBB17_1: ; %atomicrmw.start
+; GFX1332-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_and_or_b32 v0, v1, s3, s8
+; GFX1332-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1332-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-NEXT: s_or_b32 s9, vcc_lo, s9
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: s_and_not1_b32 exec_lo, exec_lo, s9
+; GFX1332-NEXT: s_cbranch_execnz .LBB17_1
+; GFX1332-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-NEXT: v_lshrrev_b32_e32 v0, s2, v2
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
%rmw = atomicrmw xchg ptr addrspace(1) %uniform.ptr, i16 %val monotonic, align 2
store i16 %rmw, ptr addrspace(1) %result
ret void
@@ -12418,6 +14764,188 @@ define amdgpu_kernel void @uniform_fadd_f16(ptr addrspace(1) %result, ptr addrsp
; GFX1232-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1232-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1232-FAKE16-NEXT: s_endpgm
+;
+; GFX1364-TRUE16-LABEL: uniform_fadd_f16:
+; GFX1364-TRUE16: ; %bb.0:
+; GFX1364-TRUE16-NEXT: s_clause 0x1
+; GFX1364-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-TRUE16-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1364-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1364-TRUE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1364-TRUE16-NEXT: s_load_b32 s3, s[4:5], 0x0
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s9, s2, 3
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s2, 0xffff, s9
+; GFX1364-TRUE16-NEXT: s_not_b32 s10, s2
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v1, s3
+; GFX1364-TRUE16-NEXT: s_mov_b64 s[2:3], 0
+; GFX1364-TRUE16-NEXT: .LBB18_1: ; %atomicrmw.start
+; GFX1364-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s9, v1
+; GFX1364-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0
+; GFX1364-TRUE16-NEXT: v_add_f16_e32 v0.l, s8, v0.l
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-TRUE16-NEXT: v_lshlrev_b32_e32 v0, s9, v0
+; GFX1364-TRUE16-NEXT: v_and_or_b32 v0, v1, s10, v0
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1364-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-TRUE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-TRUE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
+; GFX1364-TRUE16-NEXT: s_cbranch_execnz .LBB18_1
+; GFX1364-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s9, v2
+; GFX1364-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX1364-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1364-TRUE16-NEXT: s_endpgm
+;
+; GFX1364-FAKE16-LABEL: uniform_fadd_f16:
+; GFX1364-FAKE16: ; %bb.0:
+; GFX1364-FAKE16-NEXT: s_clause 0x1
+; GFX1364-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-FAKE16-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1364-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-FAKE16-NEXT: s_mov_b32 s6, -1
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1364-FAKE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1364-FAKE16-NEXT: s_load_b32 s3, s[4:5], 0x0
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s9, s2, 3
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s2, 0xffff, s9
+; GFX1364-FAKE16-NEXT: s_not_b32 s10, s2
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v1, s3
+; GFX1364-FAKE16-NEXT: s_mov_b64 s[2:3], 0
+; GFX1364-FAKE16-NEXT: .LBB18_1: ; %atomicrmw.start
+; GFX1364-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s9, v1
+; GFX1364-FAKE16-NEXT: v_add_f16_e32 v0, s8, v0
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX1364-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s9, v0
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-FAKE16-NEXT: v_and_or_b32 v0, v1, s10, v0
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1364-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-FAKE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-FAKE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
+; GFX1364-FAKE16-NEXT: s_cbranch_execnz .LBB18_1
+; GFX1364-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1364-FAKE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s9, v2
+; GFX1364-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX1364-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1364-FAKE16-NEXT: s_endpgm
+;
+; GFX1332-TRUE16-LABEL: uniform_fadd_f16:
+; GFX1332-TRUE16: ; %bb.0:
+; GFX1332-TRUE16-NEXT: s_clause 0x1
+; GFX1332-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-TRUE16-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1332-TRUE16-NEXT: s_mov_b32 s9, 0
+; GFX1332-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1332-TRUE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1332-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x0
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s2, s2, 3
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s3, 0xffff, s2
+; GFX1332-TRUE16-NEXT: s_not_b32 s3, s3
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: v_mov_b32_e32 v1, s6
+; GFX1332-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1332-TRUE16-NEXT: .LBB18_1: ; %atomicrmw.start
+; GFX1332-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1332-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v1
+; GFX1332-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0
+; GFX1332-TRUE16-NEXT: v_add_f16_e32 v0.l, s8, v0.l
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_lshlrev_b32_e32 v0, s2, v0
+; GFX1332-TRUE16-NEXT: v_and_or_b32 v0, v1, s3, v0
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1332-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1332-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-TRUE16-NEXT: s_or_b32 s9, vcc_lo, s9
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s9
+; GFX1332-TRUE16-NEXT: s_cbranch_execnz .LBB18_1
+; GFX1332-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
+; GFX1332-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX1332-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1332-TRUE16-NEXT: s_endpgm
+;
+; GFX1332-FAKE16-LABEL: uniform_fadd_f16:
+; GFX1332-FAKE16: ; %bb.0:
+; GFX1332-FAKE16-NEXT: s_clause 0x1
+; GFX1332-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-FAKE16-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1332-FAKE16-NEXT: s_mov_b32 s9, 0
+; GFX1332-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1332-FAKE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1332-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x0
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s2, s2, 3
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s3, 0xffff, s2
+; GFX1332-FAKE16-NEXT: s_not_b32 s3, s3
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: v_mov_b32_e32 v1, s6
+; GFX1332-FAKE16-NEXT: s_mov_b32 s6, -1
+; GFX1332-FAKE16-NEXT: .LBB18_1: ; %atomicrmw.start
+; GFX1332-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s2, v1
+; GFX1332-FAKE16-NEXT: v_add_f16_e32 v0, s8, v0
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX1332-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s2, v0
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_and_or_b32 v0, v1, s3, v0
+; GFX1332-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1332-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1332-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-FAKE16-NEXT: s_or_b32 s9, vcc_lo, s9
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s9
+; GFX1332-FAKE16-NEXT: s_cbranch_execnz .LBB18_1
+; GFX1332-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1332-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
+; GFX1332-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX1332-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1332-FAKE16-NEXT: s_endpgm
%rmw = atomicrmw fadd ptr addrspace(1) %uniform.ptr, half %val monotonic, align 2
store half %rmw, ptr addrspace(1) %result
ret void
@@ -13110,6 +15638,198 @@ define amdgpu_kernel void @uniform_fadd_bf16(ptr addrspace(1) %result, ptr addrs
; GFX1232-FAKE16-NEXT: s_mov_b32 s2, -1
; GFX1232-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1232-FAKE16-NEXT: s_endpgm
+;
+; GFX1364-TRUE16-LABEL: uniform_fadd_bf16:
+; GFX1364-TRUE16: ; %bb.0:
+; GFX1364-TRUE16-NEXT: s_clause 0x1
+; GFX1364-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-TRUE16-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1364-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1364-TRUE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1364-TRUE16-NEXT: s_load_b32 s3, s[4:5], 0x0
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s9, s2, 3
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1364-TRUE16-NEXT: s_lshl_b32 s2, 0xffff, s9
+; GFX1364-TRUE16-NEXT: s_not_b32 s10, s2
+; GFX1364-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v1, s3
+; GFX1364-TRUE16-NEXT: s_mov_b64 s[2:3], 0
+; GFX1364-TRUE16-NEXT: .LBB19_1: ; %atomicrmw.start
+; GFX1364-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s9, v1
+; GFX1364-TRUE16-NEXT: v_mov_b16_e32 v2.h, 0
+; GFX1364-TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, s8 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1364-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-TRUE16-NEXT: v_lshlrev_b32_e32 v0, s9, v2
+; GFX1364-TRUE16-NEXT: v_and_or_b32 v0, v1, s10, v0
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1364-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1364-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-TRUE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1364-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-TRUE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
+; GFX1364-TRUE16-NEXT: s_cbranch_execnz .LBB19_1
+; GFX1364-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1364-TRUE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s9, v2
+; GFX1364-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX1364-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1364-TRUE16-NEXT: s_endpgm
+;
+; GFX1364-FAKE16-LABEL: uniform_fadd_bf16:
+; GFX1364-FAKE16: ; %bb.0:
+; GFX1364-FAKE16-NEXT: s_clause 0x1
+; GFX1364-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-FAKE16-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1364-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-FAKE16-NEXT: s_mov_b32 s6, -1
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1364-FAKE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1364-FAKE16-NEXT: s_load_b32 s3, s[4:5], 0x0
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s9, s2, 3
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1364-FAKE16-NEXT: s_lshl_b32 s2, 0xffff, s9
+; GFX1364-FAKE16-NEXT: s_not_b32 s10, s2
+; GFX1364-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v1, s3
+; GFX1364-FAKE16-NEXT: s_mov_b64 s[2:3], 0
+; GFX1364-FAKE16-NEXT: .LBB19_1: ; %atomicrmw.start
+; GFX1364-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s9, v1
+; GFX1364-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, s8 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1364-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s9, v0
+; GFX1364-FAKE16-NEXT: v_and_or_b32 v0, v1, s10, v0
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1364-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1364-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-FAKE16-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
+; GFX1364-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-FAKE16-NEXT: s_and_not1_b64 exec, exec, s[2:3]
+; GFX1364-FAKE16-NEXT: s_cbranch_execnz .LBB19_1
+; GFX1364-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1364-FAKE16-NEXT: s_or_b64 exec, exec, s[2:3]
+; GFX1364-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s9, v2
+; GFX1364-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX1364-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1364-FAKE16-NEXT: s_endpgm
+;
+; GFX1332-TRUE16-LABEL: uniform_fadd_bf16:
+; GFX1332-TRUE16: ; %bb.0:
+; GFX1332-TRUE16-NEXT: s_clause 0x1
+; GFX1332-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-TRUE16-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1332-TRUE16-NEXT: s_mov_b32 s9, 0
+; GFX1332-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1332-TRUE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1332-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x0
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s2, s2, 3
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1332-TRUE16-NEXT: s_lshl_b32 s3, 0xffff, s2
+; GFX1332-TRUE16-NEXT: s_not_b32 s3, s3
+; GFX1332-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-TRUE16-NEXT: v_mov_b32_e32 v1, s6
+; GFX1332-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1332-TRUE16-NEXT: .LBB19_1: ; %atomicrmw.start
+; GFX1332-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1332-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v1
+; GFX1332-TRUE16-NEXT: v_mov_b16_e32 v2.h, 0
+; GFX1332-TRUE16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, s8 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1332-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_lshlrev_b32_e32 v0, s2, v2
+; GFX1332-TRUE16-NEXT: v_and_or_b32 v0, v1, s3, v0
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-TRUE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-TRUE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-TRUE16-NEXT: s_wait_loadcnt 0x0
+; GFX1332-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1332-TRUE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-TRUE16-NEXT: s_or_b32 s9, vcc_lo, s9
+; GFX1332-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s9
+; GFX1332-TRUE16-NEXT: s_cbranch_execnz .LBB19_1
+; GFX1332-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1332-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
+; GFX1332-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-TRUE16-NEXT: s_mov_b32 s2, -1
+; GFX1332-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1332-TRUE16-NEXT: s_endpgm
+;
+; GFX1332-FAKE16-LABEL: uniform_fadd_bf16:
+; GFX1332-FAKE16: ; %bb.0:
+; GFX1332-FAKE16-NEXT: s_clause 0x1
+; GFX1332-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-FAKE16-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1332-FAKE16-NEXT: s_mov_b32 s9, 0
+; GFX1332-FAKE16-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: s_and_b64 s[4:5], s[2:3], -4
+; GFX1332-FAKE16-NEXT: s_and_b32 s2, s2, 3
+; GFX1332-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x0
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s2, s2, 3
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1332-FAKE16-NEXT: s_lshl_b32 s3, 0xffff, s2
+; GFX1332-FAKE16-NEXT: s_not_b32 s3, s3
+; GFX1332-FAKE16-NEXT: s_wait_kmcnt 0x0
+; GFX1332-FAKE16-NEXT: v_mov_b32_e32 v1, s6
+; GFX1332-FAKE16-NEXT: s_mov_b32 s6, -1
+; GFX1332-FAKE16-NEXT: .LBB19_1: ; %atomicrmw.start
+; GFX1332-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s2, v1
+; GFX1332-FAKE16-NEXT: v_fma_mix_f32_bf16 v0, v0, 1.0, s8 op_sel:[0,1,0] op_sel_hi:[1,1,1]
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_cvt_pk_bf16_f32 v0, v0, s0
+; GFX1332-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s2, v0
+; GFX1332-FAKE16-NEXT: v_and_or_b32 v0, v1, s3, v0
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-FAKE16-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-FAKE16-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-FAKE16-NEXT: s_wait_loadcnt 0x0
+; GFX1332-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1332-FAKE16-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-FAKE16-NEXT: s_or_b32 s9, vcc_lo, s9
+; GFX1332-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s9
+; GFX1332-FAKE16-NEXT: s_cbranch_execnz .LBB19_1
+; GFX1332-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1332-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s2, v2
+; GFX1332-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-FAKE16-NEXT: s_mov_b32 s2, -1
+; GFX1332-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
+; GFX1332-FAKE16-NEXT: s_endpgm
%rmw = atomicrmw fadd ptr addrspace(1) %uniform.ptr, bfloat %val monotonic, align 2
store bfloat %rmw, ptr addrspace(1) %result
ret void
@@ -13438,6 +16158,75 @@ define amdgpu_kernel void @uniform_fadd_v2f16(ptr addrspace(1) %result, ptr addr
; GFX1232-NEXT: s_mov_b32 s2, -1
; GFX1232-NEXT: buffer_store_b32 v2, off, s[0:3], null
; GFX1232-NEXT: s_endpgm
+;
+; GFX1364-LABEL: uniform_fadd_v2f16:
+; GFX1364: ; %bb.0:
+; GFX1364-NEXT: s_clause 0x1
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_load_b32 s10, s[4:5], 0x34 nv
+; GFX1364-NEXT: s_mov_b64 s[8:9], 0
+; GFX1364-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s6, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_load_b32 s4, s[2:3], 0x0
+; GFX1364-NEXT: s_mov_b32 s5, s3
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_mov_b32_e32 v1, s4
+; GFX1364-NEXT: s_mov_b32 s4, s2
+; GFX1364-NEXT: .LBB20_1: ; %atomicrmw.start
+; GFX1364-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_pk_add_f16 v0, v1, s10
+; GFX1364-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1364-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: s_and_not1_b64 exec, exec, s[8:9]
+; GFX1364-NEXT: s_cbranch_execnz .LBB20_1
+; GFX1364-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1364-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: buffer_store_b32 v2, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: uniform_fadd_v2f16:
+; GFX1332: ; %bb.0:
+; GFX1332-NEXT: s_clause 0x1
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1332-NEXT: s_mov_b32 s9, 0
+; GFX1332-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s6, -1
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_load_b32 s4, s[2:3], 0x0
+; GFX1332-NEXT: s_mov_b32 s5, s3
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_mov_b32_e32 v1, s4
+; GFX1332-NEXT: s_mov_b32 s4, s2
+; GFX1332-NEXT: .LBB20_1: ; %atomicrmw.start
+; GFX1332-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_pk_add_f16 v0, v1, s8
+; GFX1332-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1332-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-NEXT: s_or_b32 s9, vcc_lo, s9
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: s_and_not1_b32 exec_lo, exec_lo, s9
+; GFX1332-NEXT: s_cbranch_execnz .LBB20_1
+; GFX1332-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: buffer_store_b32 v2, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
%rmw = atomicrmw fadd ptr addrspace(1) %uniform.ptr, <2 x half> %val monotonic, align 4
store <2 x half> %rmw, ptr addrspace(1) %result
ret void
@@ -14160,6 +16949,75 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1232-FAKE16-NEXT: s_mov_b32 s10, -1
; GFX1232-FAKE16-NEXT: buffer_store_b32 v2, off, s[8:11], null
; GFX1232-FAKE16-NEXT: s_endpgm
+;
+; GFX1364-LABEL: uniform_fadd_v2bf16:
+; GFX1364: ; %bb.0:
+; GFX1364-NEXT: s_clause 0x1
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_load_b32 s10, s[4:5], 0x34 nv
+; GFX1364-NEXT: s_mov_b64 s[8:9], 0
+; GFX1364-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s6, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_load_b32 s4, s[2:3], 0x0
+; GFX1364-NEXT: s_mov_b32 s5, s3
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_mov_b32_e32 v1, s4
+; GFX1364-NEXT: s_mov_b32 s4, s2
+; GFX1364-NEXT: .LBB21_1: ; %atomicrmw.start
+; GFX1364-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_pk_add_bf16 v0, v1, s10
+; GFX1364-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-NEXT: v_mov_b32_e32 v2, v0
+; GFX1364-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, v2, v1
+; GFX1364-NEXT: v_mov_b32_e32 v1, v2
+; GFX1364-NEXT: s_or_b64 s[8:9], vcc, s[8:9]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: s_and_not1_b64 exec, exec, s[8:9]
+; GFX1364-NEXT: s_cbranch_execnz .LBB21_1
+; GFX1364-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1364-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: buffer_store_b32 v2, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: uniform_fadd_v2bf16:
+; GFX1332: ; %bb.0:
+; GFX1332-NEXT: s_clause 0x1
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_load_b32 s8, s[4:5], 0x34 nv
+; GFX1332-NEXT: s_mov_b32 s9, 0
+; GFX1332-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s6, -1
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_load_b32 s4, s[2:3], 0x0
+; GFX1332-NEXT: s_mov_b32 s5, s3
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_mov_b32_e32 v1, s4
+; GFX1332-NEXT: s_mov_b32 s4, s2
+; GFX1332-NEXT: .LBB21_1: ; %atomicrmw.start
+; GFX1332-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_pk_add_bf16 v0, v1, s8
+; GFX1332-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
+; GFX1332-NEXT: buffer_atomic_cmpswap_b32 v[2:3], off, s[4:7], null th:TH_ATOMIC_RETURN scope:SCOPE_SYS
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v1
+; GFX1332-NEXT: v_mov_b32_e32 v1, v2
+; GFX1332-NEXT: s_or_b32 s9, vcc_lo, s9
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: s_and_not1_b32 exec_lo, exec_lo, s9
+; GFX1332-NEXT: s_cbranch_execnz .LBB21_1
+; GFX1332-NEXT: ; %bb.2: ; %atomicrmw.end
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: buffer_store_b32 v2, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
%rmw = atomicrmw fadd ptr addrspace(1) %uniform.ptr, <2 x bfloat> %val monotonic, align 4
store <2 x bfloat> %rmw, ptr addrspace(1) %result
ret void
@@ -14181,3 +17039,9 @@ define amdgpu_kernel void @uniform_fadd_v2bf16(ptr addrspace(1) %result, ptr add
; GFX1264_DPP-TRUE16: {{.*}}
; GFX1264_ITERATIVE-FAKE16: {{.*}}
; GFX1264_ITERATIVE-TRUE16: {{.*}}
+; GFX1332_DPP: {{.*}}
+; GFX1332_DPP-FAKE16: {{.*}}
+; GFX1332_DPP-TRUE16: {{.*}}
+; GFX1364_DPP: {{.*}}
+; GFX1364_DPP-FAKE16: {{.*}}
+; GFX1364_DPP-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
index 29190ad5a695a..7c336d198a9c2 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
@@ -13,6 +13,8 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1032,GFX1032_DPP %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1164,GFX1164_DPP %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1132,GFX1132_DPP %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize64 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1364,GFX1364_DPP %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize32 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1332,GFX1332_DPP %s
declare i32 @llvm.amdgcn.workitem.id.x()
@@ -219,6 +221,64 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out) {
; GFX1132-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i32_constant:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_mov_b64 s[2:3], exec
+; GFX1364-NEXT: s_mov_b64 s[0:1], exec
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX1364-NEXT: ; implicit-def: $vgpr1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1364-NEXT: s_cbranch_execz .LBB0_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX1364-NEXT: v_mov_b32_e32 v1, 0
+; GFX1364-NEXT: s_mul_i32 s2, s2, 5
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: ds_add_rtn_u32 v1, v1, v2
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB0_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: v_mad_u32_u24 v0, 5, v0, s2
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i32_constant:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_mov_b32 s1, exec_lo
+; GFX1332-NEXT: s_mov_b32 s0, exec_lo
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0
+; GFX1332-NEXT: ; implicit-def: $vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1332-NEXT: s_cbranch_execz .LBB0_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s1, s1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: s_mul_i32 s1, s1, 5
+; GFX1332-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s1
+; GFX1332-NEXT: ds_add_rtn_u32 v1, v1, v2
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB0_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: v_mad_u32_u24 v0, 5, v0, s2
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw add ptr addrspace(3) @local_var32, i32 5 acq_rel
store i32 %old, ptr addrspace(1) %out
@@ -441,6 +501,69 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, i32 %additive)
; GFX1132-NEXT: v_mad_u64_u32 v[1:2], null, s0, v0, s[2:3]
; GFX1132-NEXT: buffer_store_b32 v1, off, s[4:7], 0
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i32_uniform:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_load_b32 s6, s[4:5], 0x2c nv
+; GFX1364-NEXT: s_mov_b64 s[2:3], exec
+; GFX1364-NEXT: s_mov_b64 s[0:1], exec
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX1364-NEXT: ; implicit-def: $vgpr1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1364-NEXT: s_cbranch_execz .LBB1_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX1364-NEXT: v_mov_b32_e32 v1, 0
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mul_i32 s2, s6, s2
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: ds_add_rtn_u32 v1, v1, v2
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB1_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_mad_co_u64_u32 v[0:1], null, s6, v0, s[2:3]
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i32_uniform:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_load_b32 s0, s[4:5], 0x2c nv
+; GFX1332-NEXT: s_mov_b32 s2, exec_lo
+; GFX1332-NEXT: s_mov_b32 s1, exec_lo
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX1332-NEXT: ; implicit-def: $vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1332-NEXT: s_cbranch_execz .LBB1_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s2, s2
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mul_i32 s2, s0, s2
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s2
+; GFX1332-NEXT: ds_add_rtn_u32 v1, v1, v2
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB1_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX1332-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1332-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s6, -1
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_mad_co_u64_u32 v[0:1], null, s0, v0, s[2:3]
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[4:7], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw add ptr addrspace(3) @local_var32, i32 %additive acq_rel
store i32 %old, ptr addrspace(1) %out
@@ -1038,6 +1161,115 @@ define amdgpu_kernel void @add_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i32_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 16
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v3, s3, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr0
+; GFX1364-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB2_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, s6
+; GFX1364-NEXT: ds_add_rtn_u32 v0, v4, v0
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB2_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, v3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_e32 v0, s3, v0
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i32_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, 0, v0, s0 :: v_dual_mov_b32 v3, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s1, v1, 15
+; GFX1332-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v4, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: v_writelane_b32 v3, s1, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: s_mov_b32 s0, s2
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr0
+; GFX1332-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB2_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_mov_b32_e32 v0, s0
+; GFX1332-NEXT: ds_add_rtn_u32 v0, v4, v0
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB2_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1332-NEXT: v_mov_b32_e32 v0, v3
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_e32 v0, s3, v0
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw add ptr addrspace(3) @local_var32, i32 %lane acq_rel
@@ -1440,6 +1672,74 @@ define amdgpu_kernel void @add_i32_varying_nouse() {
; GFX1132_DPP-NEXT: buffer_gl0_inv
; GFX1132_DPP-NEXT: .LBB3_2:
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i32_varying_nouse:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v2, v1, 0, 0
+; GFX1364-NEXT: v_add_nc_u32_e32 v1, v1, v2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_permlane64_b32 v2, v1
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1364-NEXT: v_add_nc_u32_e32 v1, v1, v2
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-NEXT: s_mov_b64 s[0:1], exec
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1364-NEXT: s_cbranch_execz .LBB3_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: ds_add_u32 v0, v3
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB3_2:
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i32_varying_nouse:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, v0, s0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v2, v1, 0, 0
+; GFX1332-NEXT: v_add_nc_u32_e32 v1, v1, v2
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
+; GFX1332-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, v1
+; GFX1332-NEXT: s_mov_b32 s0, exec_lo
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1332-NEXT: s_cbranch_execz .LBB3_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: ds_add_u32 v0, v3
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB3_2:
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw add ptr addrspace(3) @local_var32, i32 %lane acq_rel
@@ -1665,6 +1965,69 @@ define amdgpu_kernel void @add_i64_constant(ptr addrspace(1) %out) {
; GFX1132-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i64_constant:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_mov_b64 s[2:3], exec
+; GFX1364-NEXT: s_mov_b64 s[0:1], exec
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v2, s3, v0
+; GFX1364-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1364-NEXT: s_cbranch_execz .LBB4_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX1364-NEXT: v_mov_b32_e32 v1, 0
+; GFX1364-NEXT: s_mul_i32 s2, s2, 5
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mov_b32_e32 v0, s2
+; GFX1364-NEXT: ds_add_rtn_u64 v[0:1], v1, v[0:1]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB4_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_mad_co_u64_u32 v[0:1], null, 5, v2, s[2:3]
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i64_constant:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_mov_b32 s1, exec_lo
+; GFX1332-NEXT: s_mov_b32 s0, exec_lo
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v2, s1, 0
+; GFX1332-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1332-NEXT: s_cbranch_execz .LBB4_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s1, s1
+; GFX1332-NEXT: v_mov_b32_e32 v1, 0
+; GFX1332-NEXT: s_mul_i32 s1, s1, 5
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: v_mov_b32_e32 v0, s1
+; GFX1332-NEXT: ds_add_rtn_u64 v[0:1], v1, v[0:1]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB4_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_mad_co_u64_u32 v[0:1], null, 5, v2, s[2:3]
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw add ptr addrspace(3) @local_var64, i64 5 acq_rel
store i64 %old, ptr addrspace(1) %out
@@ -1935,6 +2298,76 @@ define amdgpu_kernel void @add_i64_uniform(ptr addrspace(1) %out, i64 %additive)
; GFX1132-NEXT: v_mov_b32_e32 v1, v3
; GFX1132-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i64_uniform:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-NEXT: s_mov_b32 s9, 0
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1364-NEXT: s_mov_b64 s[4:5], exec
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
+; GFX1364-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1364-NEXT: s_cbranch_execz .LBB5_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s8, s[6:7]
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mul_u64 s[6:7], s[2:3], s[8:9]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mov_b32_e32 v0, s6
+; GFX1364-NEXT: v_mov_b32_e32 v1, s7
+; GFX1364-NEXT: ds_add_rtn_u64 v[0:1], v3, v[0:1]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB5_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX1364-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1364-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_mad_co_u64_u32 v[0:1], null, s2, v2, s[4:5]
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: v_mad_co_u64_u32 v[1:2], null, s3, v2, v[1:2]
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i64_uniform:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-NEXT: s_mov_b32 s5, 0
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v2, s6, 0
+; GFX1332-NEXT: s_mov_b32 s7, exec_lo
+; GFX1332-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1332-NEXT: s_cbranch_execz .LBB5_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s4, s6
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mul_u64 s[4:5], s[2:3], s[4:5]
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s4
+; GFX1332-NEXT: v_mov_b32_e32 v1, s5
+; GFX1332-NEXT: ds_add_rtn_u64 v[0:1], v3, v[0:1]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB5_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s7
+; GFX1332-NEXT: v_readfirstlane_b32 s5, v1
+; GFX1332-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_mad_co_u64_u32 v[0:1], null, s2, v2, s[4:5]
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: v_mad_co_u64_u32 v[1:2], null, s3, v2, v[1:2]
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw add ptr addrspace(3) @local_var64, i64 %additive acq_rel
store i64 %old, ptr addrspace(1) %out
@@ -2811,6 +3244,184 @@ define amdgpu_kernel void @add_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b64 v[8:9], off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i64_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_mov_b32_e32 v6, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_e32 v5, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1364-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_e32 v4, s2
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1364-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 15
+; GFX1364-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s6, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s7, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 63
+; GFX1364-NEXT: v_writelane_b32 v6, s3, 16
+; GFX1364-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1364-NEXT: v_readlane_b32 s9, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v5, s6, 32
+; GFX1364-NEXT: v_writelane_b32 v6, s7, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[6:7], -1
+; GFX1364-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1364-NEXT: v_writelane_b32 v5, s8, 48
+; GFX1364-NEXT: v_writelane_b32 v6, s9, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[6:7]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1364-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB6_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v8, s1
+; GFX1364-NEXT: v_mov_b32_e32 v7, s0
+; GFX1364-NEXT: ds_add_rtn_u64 v[7:8], v0, v[7:8]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB6_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v7
+; GFX1364-NEXT: v_mov_b32_e32 v9, v5
+; GFX1364-NEXT: v_mov_b32_e32 v10, v6
+; GFX1364-NEXT: v_readfirstlane_b32 s4, v8
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_co_u32 v7, vcc, s3, v9
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v8, null, s4, v10, vcc
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[7:8], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i64_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, 0, s2
+; GFX1332-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v3, 0, v0, s2
+; GFX1332-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v6, 0
+; GFX1332-NEXT: v_mov_b32_e32 v7, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1332-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
+; GFX1332-NEXT: v_mov_b32_e32 v2, 0
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_mov_b32_e32 v4, 0
+; GFX1332-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_mov_b32_e32 v3, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1332-NEXT: v_readlane_b32 s3, v2, 15
+; GFX1332-NEXT: v_readlane_b32 s0, v2, 31
+; GFX1332-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s1, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v7, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v8, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v0, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: v_writelane_b32 v6, s3, 16
+; GFX1332-NEXT: v_writelane_b32 v7, s6, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr8_vgpr9
+; GFX1332-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB6_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v9, s1 :: v_dual_mov_b32 v8, s0
+; GFX1332-NEXT: ds_add_rtn_u64 v[8:9], v0, v[8:9]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB6_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v8
+; GFX1332-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v11, v7
+; GFX1332-NEXT: v_readfirstlane_b32 s4, v9
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_co_u32 v8, vcc_lo, s3, v10
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v9, null, s4, v11, vcc_lo
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%zext = zext i32 %lane to i64
@@ -3395,6 +4006,115 @@ define amdgpu_kernel void @add_i64_varying_nouse() {
; GFX1132_DPP-NEXT: buffer_gl0_inv
; GFX1132_DPP-NEXT: .LBB7_2:
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i64_varying_nouse:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_mov_b32_dpp v2, v1 row_xmask:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_xmask:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_mov_b32_dpp v2, v1 row_xmask:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_xmask:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_permlanex16_b32 v3, v2, 0, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1364-NEXT: v_add_co_u32 v2, vcc, v2, v3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_permlanex16_b32 v4, v1, 0, 0
+; GFX1364-NEXT: v_permlane64_b32 v3, v2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1364-NEXT: v_permlane64_b32 v4, v1
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_add_co_u32 v2, vcc, v2, v3
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v4, vcc
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: v_mov_b32_e32 v5, v2
+; GFX1364-NEXT: v_mov_b32_e32 v6, v3
+; GFX1364-NEXT: s_mov_b64 s[0:1], exec
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v7
+; GFX1364-NEXT: s_cbranch_execz .LBB7_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: ds_add_u64 v0, v[5:6]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB7_2:
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i64_varying_nouse:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, 0, s0
+; GFX1332-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v3, 0, v0, s0
+; GFX1332-NEXT: v_mov_b32_e32 v4, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mov_b32_dpp v2, v1 row_xmask:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
+; GFX1332-NEXT: v_mov_b32_e32 v2, 0
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_xmask:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_mov_b32_e32 v4, 0
+; GFX1332-NEXT: v_mov_b32_dpp v2, v1 row_xmask:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_xmask:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_permlanex16_b32 v3, v2, 0, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
+; GFX1332-NEXT: v_add_co_u32 v2, vcc_lo, v2, v3
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v4, v1, 0, 0
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v3, null, v1, v4, vcc_lo
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
+; GFX1332-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v5, v2
+; GFX1332-NEXT: v_mov_b32_e32 v6, v3
+; GFX1332-NEXT: s_mov_b32 s0, exec_lo
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v7
+; GFX1332-NEXT: s_cbranch_execz .LBB7_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: ds_add_u64 v0, v[5:6]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB7_2:
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%zext = zext i32 %lane to i64
@@ -3609,6 +4329,68 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out) {
; GFX1132-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: sub_i32_constant:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_mov_b64 s[2:3], exec
+; GFX1364-NEXT: s_mov_b64 s[0:1], exec
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX1364-NEXT: ; implicit-def: $vgpr1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1364-NEXT: s_cbranch_execz .LBB8_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX1364-NEXT: v_mov_b32_e32 v1, 0
+; GFX1364-NEXT: s_mul_i32 s2, s2, 5
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: ds_sub_rtn_u32 v1, v1, v2
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB8_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1364-NEXT: v_mul_u32_u24_e32 v0, 5, v0
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: sub_i32_constant:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_mov_b32 s1, exec_lo
+; GFX1332-NEXT: s_mov_b32 s0, exec_lo
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0
+; GFX1332-NEXT: ; implicit-def: $vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1332-NEXT: s_cbranch_execz .LBB8_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s1, s1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: s_mul_i32 s1, s1, 5
+; GFX1332-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s1
+; GFX1332-NEXT: ds_sub_rtn_u32 v1, v1, v2
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB8_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1332-NEXT: v_mul_u32_u24_e32 v0, 5, v0
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw sub ptr addrspace(3) @local_var32, i32 5 acq_rel
store i32 %old, ptr addrspace(1) %out
@@ -3834,6 +4616,70 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, i32 %subitive)
; GFX1132-NEXT: v_sub_nc_u32_e32 v0, s0, v0
; GFX1132-NEXT: buffer_store_b32 v0, off, s[4:7], 0
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: sub_i32_uniform:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_load_b32 s6, s[4:5], 0x2c nv
+; GFX1364-NEXT: s_mov_b64 s[2:3], exec
+; GFX1364-NEXT: s_mov_b64 s[0:1], exec
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX1364-NEXT: ; implicit-def: $vgpr1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1364-NEXT: s_cbranch_execz .LBB9_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX1364-NEXT: v_mov_b32_e32 v1, 0
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mul_i32 s2, s6, s2
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: ds_sub_rtn_u32 v1, v1, v2
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB9_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_mul_lo_u32 v0, s6, v0
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v1
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: sub_i32_uniform:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_load_b32 s0, s[4:5], 0x2c nv
+; GFX1332-NEXT: s_mov_b32 s2, exec_lo
+; GFX1332-NEXT: s_mov_b32 s1, exec_lo
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX1332-NEXT: ; implicit-def: $vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1332-NEXT: s_cbranch_execz .LBB9_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s2, s2
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mul_i32 s2, s0, s2
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, s2
+; GFX1332-NEXT: ds_sub_rtn_u32 v1, v1, v2
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB9_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX1332-NEXT: s_load_b64 s[4:5], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_mul_lo_u32 v0, s0, v0
+; GFX1332-NEXT: v_readfirstlane_b32 s0, v1
+; GFX1332-NEXT: s_mov_b32 s7, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s6, -1
+; GFX1332-NEXT: v_sub_nc_u32_e32 v0, s0, v0
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[4:7], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw sub ptr addrspace(3) @local_var32, i32 %subitive acq_rel
store i32 %old, ptr addrspace(1) %out
@@ -4431,6 +5277,115 @@ define amdgpu_kernel void @sub_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: sub_i32_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 16
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v3, s3, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr0
+; GFX1364-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB10_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, s6
+; GFX1364-NEXT: ds_sub_rtn_u32 v0, v4, v0
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB10_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, v3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_sub_nc_u32_e32 v0, s3, v0
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: sub_i32_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, 0, v0, s0 :: v_dual_mov_b32 v3, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s1, v1, 15
+; GFX1332-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v4, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: v_writelane_b32 v3, s1, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: s_mov_b32 s0, s2
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr0
+; GFX1332-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB10_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_mov_b32_e32 v0, s0
+; GFX1332-NEXT: ds_sub_rtn_u32 v0, v4, v0
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB10_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1332-NEXT: v_mov_b32_e32 v0, v3
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_sub_nc_u32_e32 v0, s3, v0
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw sub ptr addrspace(3) @local_var32, i32 %lane acq_rel
@@ -4833,6 +5788,74 @@ define amdgpu_kernel void @sub_i32_varying_nouse() {
; GFX1132_DPP-NEXT: buffer_gl0_inv
; GFX1132_DPP-NEXT: .LBB11_2:
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: sub_i32_varying_nouse:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v2, v1, 0, 0
+; GFX1364-NEXT: v_add_nc_u32_e32 v1, v1, v2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_permlane64_b32 v2, v1
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1364-NEXT: v_add_nc_u32_e32 v1, v1, v2
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v4, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_mov_b32_e32 v3, v1
+; GFX1364-NEXT: s_mov_b64 s[0:1], exec
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1364-NEXT: s_cbranch_execz .LBB11_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: ds_sub_u32 v0, v3
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB11_2:
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: sub_i32_varying_nouse:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, v0, s0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v2, v1, 0, 0
+; GFX1332-NEXT: v_add_nc_u32_e32 v1, v1, v2
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v4, exec_lo, 0
+; GFX1332-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v3, v1
+; GFX1332-NEXT: s_mov_b32 s0, exec_lo
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v4
+; GFX1332-NEXT: s_cbranch_execz .LBB11_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: ds_sub_u32 v0, v3
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB11_2:
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw sub ptr addrspace(3) @local_var32, i32 %lane acq_rel
@@ -5071,6 +6094,75 @@ define amdgpu_kernel void @sub_i64_constant(ptr addrspace(1) %out) {
; GFX1132-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: sub_i64_constant:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_mov_b64 s[2:3], exec
+; GFX1364-NEXT: s_mov_b64 s[0:1], exec
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v2, s3, v0
+; GFX1364-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1364-NEXT: s_cbranch_execz .LBB12_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX1364-NEXT: v_mov_b32_e32 v1, 0
+; GFX1364-NEXT: s_mul_i32 s2, s2, 5
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mov_b32_e32 v0, s2
+; GFX1364-NEXT: ds_sub_rtn_u64 v[0:1], v1, v[0:1]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB12_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-NEXT: v_mul_u32_u24_e32 v0, 5, v2
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1364-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_sub_co_u32 v0, vcc, s2, v0
+; GFX1364-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v1, vcc
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: sub_i64_constant:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_mov_b32 s1, exec_lo
+; GFX1332-NEXT: s_mov_b32 s0, exec_lo
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v2, s1, 0
+; GFX1332-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1332-NEXT: s_cbranch_execz .LBB12_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s1, s1
+; GFX1332-NEXT: v_mov_b32_e32 v1, 0
+; GFX1332-NEXT: s_mul_i32 s1, s1, 5
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: v_mov_b32_e32 v0, s1
+; GFX1332-NEXT: ds_sub_rtn_u64 v[0:1], v1, v[0:1]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB12_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-NEXT: v_mul_u32_u24_e32 v0, 5, v2
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1332-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v2
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_sub_co_u32 v0, vcc_lo, s2, v0
+; GFX1332-NEXT: v_sub_co_ci_u32_e64 v1, null, s3, v1, vcc_lo
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw sub ptr addrspace(3) @local_var64, i64 5 acq_rel
store i64 %old, ptr addrspace(1) %out
@@ -5349,6 +6441,80 @@ define amdgpu_kernel void @sub_i64_uniform(ptr addrspace(1) %out, i64 %subitive)
; GFX1132-NEXT: v_sub_co_ci_u32_e64 v1, null, s4, v5, vcc_lo
; GFX1132-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: sub_i64_uniform:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1364-NEXT: s_mov_b64 s[6:7], exec
+; GFX1364-NEXT: s_mov_b32 s9, 0
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1364-NEXT: s_mov_b64 s[4:5], exec
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v2, s7, v0
+; GFX1364-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1364-NEXT: s_cbranch_execz .LBB13_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s8, s[6:7]
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: s_mul_u64 s[6:7], s[2:3], s[8:9]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mov_b32_e32 v0, s6
+; GFX1364-NEXT: v_mov_b32_e32 v1, s7
+; GFX1364-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB13_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: v_mad_co_u64_u32 v[3:4], null, s2, v2, 0
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-NEXT: v_readfirstlane_b32 s4, v1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_mad_co_u64_u32 v[4:5], null, s3, v2, v[4:5]
+; GFX1364-NEXT: v_sub_co_u32 v0, vcc, s2, v3
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: v_sub_co_ci_u32_e64 v1, null, s4, v4, vcc
+; GFX1364-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: sub_i64_uniform:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
+; GFX1332-NEXT: s_mov_b32 s6, exec_lo
+; GFX1332-NEXT: s_mov_b32 s5, 0
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v2, s6, 0
+; GFX1332-NEXT: s_mov_b32 s7, exec_lo
+; GFX1332-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX1332-NEXT: s_cbranch_execz .LBB13_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s4, s6
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: s_mul_u64 s[4:5], s[2:3], s[4:5]
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s4
+; GFX1332-NEXT: v_mov_b32_e32 v1, s5
+; GFX1332-NEXT: ds_sub_rtn_u64 v[0:1], v3, v[0:1]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB13_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s7
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: v_mad_co_u64_u32 v[3:4], null, s2, v2, 0
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-NEXT: v_readfirstlane_b32 s4, v1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mad_co_u64_u32 v[4:5], null, s3, v2, v[4:5]
+; GFX1332-NEXT: v_sub_co_u32 v0, vcc_lo, s2, v3
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: v_sub_co_ci_u32_e64 v1, null, s4, v4, vcc_lo
+; GFX1332-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw sub ptr addrspace(3) @local_var64, i64 %subitive acq_rel
store i64 %old, ptr addrspace(1) %out
@@ -6225,6 +7391,184 @@ define amdgpu_kernel void @sub_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b64 v[8:9], off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: sub_i64_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: v_cndmask_b32_e64 v3, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_mov_b32_e32 v6, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v3, vcc, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v2, vcc, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v2, vcc, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_e32 v5, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1364-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_e32 v4, s2
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1364-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_co_u32_e64_dpp v2, vcc, v2, s2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 15
+; GFX1364-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s6, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s7, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 63
+; GFX1364-NEXT: v_writelane_b32 v6, s3, 16
+; GFX1364-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1364-NEXT: v_readlane_b32 s9, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v5, s6, 32
+; GFX1364-NEXT: v_writelane_b32 v6, s7, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[6:7], -1
+; GFX1364-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1364-NEXT: v_writelane_b32 v5, s8, 48
+; GFX1364-NEXT: v_writelane_b32 v6, s9, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[6:7]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1364-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB14_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v8, s1
+; GFX1364-NEXT: v_mov_b32_e32 v7, s0
+; GFX1364-NEXT: ds_sub_rtn_u64 v[7:8], v0, v[7:8]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB14_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v7
+; GFX1364-NEXT: v_mov_b32_e32 v9, v5
+; GFX1364-NEXT: v_mov_b32_e32 v10, v6
+; GFX1364-NEXT: v_readfirstlane_b32 s4, v8
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_sub_co_u32 v7, vcc, s3, v9
+; GFX1364-NEXT: v_sub_co_ci_u32_e64 v8, null, s4, v10, vcc
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[7:8], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: sub_i64_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, 0, s2
+; GFX1332-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v3, 0, v0, s2
+; GFX1332-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v6, 0
+; GFX1332-NEXT: v_mov_b32_e32 v7, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1332-NEXT: v_mov_b32_dpp v2, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
+; GFX1332-NEXT: v_mov_b32_e32 v2, 0
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v3, vcc_lo, v3, v3 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_mov_b32_e32 v4, 0
+; GFX1332-NEXT: v_mov_b32_dpp v2, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v2, vcc_lo
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v3, v3 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_mov_b32_e32 v3, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v4, vcc_lo
+; GFX1332-NEXT: v_add_co_u32_e64_dpp v2, vcc_lo, v5, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_permlanex16_b32 v4, v1, -1, -1
+; GFX1332-NEXT: v_readlane_b32 s3, v2, 15
+; GFX1332-NEXT: v_readlane_b32 s0, v2, 31
+; GFX1332-NEXT: v_mov_b32_dpp v6, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v3, v4 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s1, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v7, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v8, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v0, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: v_writelane_b32 v6, s3, 16
+; GFX1332-NEXT: v_writelane_b32 v7, s6, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr8_vgpr9
+; GFX1332-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB14_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v9, s1 :: v_dual_mov_b32 v8, s0
+; GFX1332-NEXT: ds_sub_rtn_u64 v[8:9], v0, v[8:9]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB14_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v8
+; GFX1332-NEXT: v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v11, v7
+; GFX1332-NEXT: v_readfirstlane_b32 s4, v9
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_sub_co_u32 v8, vcc_lo, s3, v10
+; GFX1332-NEXT: v_sub_co_ci_u32_e64 v9, null, s4, v11, vcc_lo
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%zext = zext i32 %lane to i64
@@ -6825,6 +8169,142 @@ define amdgpu_kernel void @and_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: and_i32_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_mov_b32_e32 v1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1364-NEXT: v_cndmask_b32_e64 v2, -1, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v3, -1
+; GFX1364-NEXT: v_mov_b32_e32 v5, -1
+; GFX1364-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_and_b32_e32 v4, v2, v1
+; GFX1364-NEXT: v_mov_b32_dpp v3, v4 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_bitop3_b32 v1, v2, v3, v1 bitop3:0x80
+; GFX1364-NEXT: v_mov_b32_e32 v2, -1
+; GFX1364-NEXT: v_mov_b32_dpp v5, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_bitop3_b32 v3, v4, v5, v3 bitop3:0x80
+; GFX1364-NEXT: v_mov_b32_e32 v4, -1
+; GFX1364-NEXT: v_mov_b32_dpp v2, v3 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_bitop3_b32 v1, v1, v2, v5 bitop3:0x80
+; GFX1364-NEXT: v_permlanex16_b32 v5, v1, -1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: v_bitop3_b32 v2, v3, v4, v2 bitop3:0x80
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1364-NEXT: v_mov_b32_e32 v2, -1
+; GFX1364-NEXT: v_mov_b32_e32 v3, s2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_dpp v2, v3 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_e32 v3, -1
+; GFX1364-NEXT: v_bitop3_b32 v1, v1, v2, v4 bitop3:0x80
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 16
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v3, s3, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr0
+; GFX1364-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB15_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: v_mov_b32_e32 v6, s6
+; GFX1364-NEXT: ds_and_rtn_b32 v0, v0, v6
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB15_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, v3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_and_b32_e32 v0, s3, v0
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: and_i32_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_dual_mov_b32 v1, -1 :: v_dual_cndmask_b32 v2, -1, v0, s0
+; GFX1332-NEXT: v_mov_b32_e32 v5, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_dual_mov_b32 v3, -1 :: v_dual_bitop2_b32 v4, v2, v1 bitop3:0x40
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v3, v4 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_bitop3_b32 v1, v2, v3, v1 bitop3:0x80
+; GFX1332-NEXT: v_mov_b32_e32 v2, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v5, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_bitop3_b32 v3, v4, v5, v3 bitop3:0x80
+; GFX1332-NEXT: v_mov_b32_e32 v4, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v2, v3 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_bitop3_b32 v1, v1, v2, v5 bitop3:0x80
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v1, v1, -1, -1
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_e32 v1, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_bitop3_b32 v2, v3, v4, v2 bitop3:0x80
+; GFX1332-NEXT: v_readlane_b32 s1, v2, 15
+; GFX1332-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: v_writelane_b32 v1, s1, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: s_mov_b32 s0, s2
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr0
+; GFX1332-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB15_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v6, s0
+; GFX1332-NEXT: ds_and_rtn_b32 v0, v0, v6
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB15_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1332-NEXT: v_mov_b32_e32 v0, v1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_and_b32_e32 v0, s3, v0
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw and ptr addrspace(3) @local_var32, i32 %lane acq_rel
@@ -7573,6 +9053,160 @@ define amdgpu_kernel void @and_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b64 v[8:9], off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: and_i64_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, -1, 0, s[0:1]
+; GFX1364-NEXT: v_cndmask_b32_e64 v2, -1, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v6, -1
+; GFX1364-NEXT: v_mov_b32_e32 v5, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_and_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_and_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_and_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_and_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_permlanex16_b32 v3, v1, -1, -1
+; GFX1364-NEXT: v_permlanex16_b32 v4, v2, -1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_and_b32_dpp v1, v3, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: v_and_b32_dpp v2, v4, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: v_readlane_b32 s3, v2, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_e32 v3, s2
+; GFX1364-NEXT: v_mov_b32_e32 v4, s3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_and_b32_dpp v1, v3, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_and_b32_dpp v2, v4, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 15
+; GFX1364-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s3, v2, 15
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v6, s2, 16
+; GFX1364-NEXT: v_readlane_b32 s7, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 63
+; GFX1364-NEXT: v_writelane_b32 v5, s3, 16
+; GFX1364-NEXT: v_readlane_b32 s8, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v6, s6, 32
+; GFX1364-NEXT: v_readlane_b32 s9, v2, 47
+; GFX1364-NEXT: v_writelane_b32 v5, s7, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[6:7], -1
+; GFX1364-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1364-NEXT: v_writelane_b32 v6, s8, 48
+; GFX1364-NEXT: v_writelane_b32 v5, s9, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[6:7]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1364-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB16_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v8, s1
+; GFX1364-NEXT: v_mov_b32_e32 v7, s0
+; GFX1364-NEXT: ds_and_rtn_b64 v[7:8], v0, v[7:8]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB16_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v8
+; GFX1364-NEXT: v_mov_b32_e32 v8, v5
+; GFX1364-NEXT: v_mov_b32_e32 v9, v6
+; GFX1364-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_and_b32_e32 v9, s3, v9
+; GFX1364-NEXT: v_and_b32_e32 v8, s4, v8
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: and_i64_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, -1, 0, s2
+; GFX1332-NEXT: v_dual_cndmask_b32 v2, -1, v0, s2 :: v_dual_mov_b32 v6, -1
+; GFX1332-NEXT: v_mov_b32_e32 v5, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_and_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_and_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_and_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_and_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_permlanex16_b32 v3, v1, -1, -1
+; GFX1332-NEXT: v_permlanex16_b32 v4, v2, -1, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_and_b32_dpp v1, v3, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_and_b32_dpp v2, v4, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_readlane_b32 s3, v1, 15
+; GFX1332-NEXT: v_readlane_b32 s1, v1, 31
+; GFX1332-NEXT: v_readlane_b32 s0, v2, 31
+; GFX1332-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s6, v2, 15
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v0, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: v_writelane_b32 v6, s3, 16
+; GFX1332-NEXT: v_writelane_b32 v5, s6, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1332-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB16_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1332-NEXT: ds_and_rtn_b64 v[7:8], v0, v[7:8]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB16_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v8
+; GFX1332-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6
+; GFX1332-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_and_b32_e32 v9, s3, v9
+; GFX1332-NEXT: v_and_b32_e32 v8, s4, v8
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%lane_ext = zext i32 %lane to i64
@@ -8172,6 +9806,115 @@ define amdgpu_kernel void @or_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: or_i32_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1364-NEXT: v_or_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_or_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 16
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v3, s3, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr0
+; GFX1364-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB17_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, s6
+; GFX1364-NEXT: ds_or_rtn_b32 v0, v4, v0
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB17_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, v3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_or_b32_e32 v0, s3, v0
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: or_i32_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, 0, v0, s0 :: v_dual_mov_b32 v3, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1332-NEXT: v_or_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s1, v1, 15
+; GFX1332-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v4, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: v_writelane_b32 v3, s1, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: s_mov_b32 s0, s2
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr0
+; GFX1332-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB17_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_mov_b32_e32 v0, s0
+; GFX1332-NEXT: ds_or_rtn_b32 v0, v4, v0
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB17_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1332-NEXT: v_mov_b32_e32 v0, v3
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_or_b32_e32 v0, s3, v0
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw or ptr addrspace(3) @local_var32, i32 %lane acq_rel
@@ -8920,6 +10663,160 @@ define amdgpu_kernel void @or_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b64 v[8:9], off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: or_i64_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
+; GFX1364-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v6, 0
+; GFX1364-NEXT: v_mov_b32_e32 v5, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_permlanex16_b32 v3, v1, -1, -1
+; GFX1364-NEXT: v_permlanex16_b32 v4, v2, -1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_or_b32_dpp v1, v3, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: v_or_b32_dpp v2, v4, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: v_readlane_b32 s3, v2, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_e32 v3, s2
+; GFX1364-NEXT: v_mov_b32_e32 v4, s3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_or_b32_dpp v1, v3, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_or_b32_dpp v2, v4, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 15
+; GFX1364-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s3, v2, 15
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v6, s2, 16
+; GFX1364-NEXT: v_readlane_b32 s7, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 63
+; GFX1364-NEXT: v_writelane_b32 v5, s3, 16
+; GFX1364-NEXT: v_readlane_b32 s8, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v6, s6, 32
+; GFX1364-NEXT: v_readlane_b32 s9, v2, 47
+; GFX1364-NEXT: v_writelane_b32 v5, s7, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[6:7], -1
+; GFX1364-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1364-NEXT: v_writelane_b32 v6, s8, 48
+; GFX1364-NEXT: v_writelane_b32 v5, s9, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[6:7]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1364-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB18_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v8, s1
+; GFX1364-NEXT: v_mov_b32_e32 v7, s0
+; GFX1364-NEXT: ds_or_rtn_b64 v[7:8], v0, v[7:8]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB18_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v8
+; GFX1364-NEXT: v_mov_b32_e32 v8, v5
+; GFX1364-NEXT: v_mov_b32_e32 v9, v6
+; GFX1364-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_or_b32_e32 v9, s3, v9
+; GFX1364-NEXT: v_or_b32_e32 v8, s4, v8
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: or_i64_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, 0, s2
+; GFX1332-NEXT: v_dual_cndmask_b32 v2, 0, v0, s2 :: v_dual_mov_b32 v6, 0
+; GFX1332-NEXT: v_mov_b32_e32 v5, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_or_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_permlanex16_b32 v3, v1, -1, -1
+; GFX1332-NEXT: v_permlanex16_b32 v4, v2, -1, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_or_b32_dpp v1, v3, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_or_b32_dpp v2, v4, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_readlane_b32 s3, v1, 15
+; GFX1332-NEXT: v_readlane_b32 s1, v1, 31
+; GFX1332-NEXT: v_readlane_b32 s0, v2, 31
+; GFX1332-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s6, v2, 15
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v0, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: v_writelane_b32 v6, s3, 16
+; GFX1332-NEXT: v_writelane_b32 v5, s6, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1332-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB18_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1332-NEXT: ds_or_rtn_b64 v[7:8], v0, v[7:8]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB18_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v8
+; GFX1332-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6
+; GFX1332-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_or_b32_e32 v9, s3, v9
+; GFX1332-NEXT: v_or_b32_e32 v8, s4, v8
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%lane_ext = zext i32 %lane to i64
@@ -9519,6 +11416,115 @@ define amdgpu_kernel void @xor_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: xor_i32_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1364-NEXT: v_xor_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_xor_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 16
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v3, s3, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr0
+; GFX1364-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB19_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, s6
+; GFX1364-NEXT: ds_xor_rtn_b32 v0, v4, v0
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB19_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, v3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_xor_b32_e32 v0, s3, v0
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: xor_i32_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, 0, v0, s0 :: v_dual_mov_b32 v3, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1332-NEXT: v_xor_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s1, v1, 15
+; GFX1332-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v4, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: v_writelane_b32 v3, s1, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: s_mov_b32 s0, s2
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr0
+; GFX1332-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB19_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_mov_b32_e32 v0, s0
+; GFX1332-NEXT: ds_xor_rtn_b32 v0, v4, v0
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB19_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1332-NEXT: v_mov_b32_e32 v0, v3
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_xor_b32_e32 v0, s3, v0
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw xor ptr addrspace(3) @local_var32, i32 %lane acq_rel
@@ -10267,6 +12273,160 @@ define amdgpu_kernel void @xor_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b64 v[8:9], off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: xor_i64_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, 0, s[0:1]
+; GFX1364-NEXT: v_cndmask_b32_e64 v2, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v6, 0
+; GFX1364-NEXT: v_mov_b32_e32 v5, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_permlanex16_b32 v3, v1, -1, -1
+; GFX1364-NEXT: v_permlanex16_b32 v4, v2, -1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_xor_b32_dpp v1, v3, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: v_xor_b32_dpp v2, v4, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: v_readlane_b32 s3, v2, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_e32 v3, s2
+; GFX1364-NEXT: v_mov_b32_e32 v4, s3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_xor_b32_dpp v1, v3, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_xor_b32_dpp v2, v4, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 15
+; GFX1364-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s3, v2, 15
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v6, s2, 16
+; GFX1364-NEXT: v_readlane_b32 s7, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 63
+; GFX1364-NEXT: v_writelane_b32 v5, s3, 16
+; GFX1364-NEXT: v_readlane_b32 s8, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v6, s6, 32
+; GFX1364-NEXT: v_readlane_b32 s9, v2, 47
+; GFX1364-NEXT: v_writelane_b32 v5, s7, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[6:7], -1
+; GFX1364-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1364-NEXT: v_writelane_b32 v6, s8, 48
+; GFX1364-NEXT: v_writelane_b32 v5, s9, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[6:7]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1364-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB20_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v8, s1
+; GFX1364-NEXT: v_mov_b32_e32 v7, s0
+; GFX1364-NEXT: ds_xor_rtn_b64 v[7:8], v0, v[7:8]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB20_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v8
+; GFX1364-NEXT: v_mov_b32_e32 v8, v5
+; GFX1364-NEXT: v_mov_b32_e32 v9, v6
+; GFX1364-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_xor_b32_e32 v9, s3, v9
+; GFX1364-NEXT: v_xor_b32_e32 v8, s4, v8
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: xor_i64_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, 0, s2
+; GFX1332-NEXT: v_dual_cndmask_b32 v2, 0, v0, s2 :: v_dual_mov_b32 v6, 0
+; GFX1332-NEXT: v_mov_b32_e32 v5, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_xor_b32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_permlanex16_b32 v3, v1, -1, -1
+; GFX1332-NEXT: v_permlanex16_b32 v4, v2, -1, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_xor_b32_dpp v1, v3, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_xor_b32_dpp v2, v4, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_readlane_b32 s3, v1, 15
+; GFX1332-NEXT: v_readlane_b32 s1, v1, 31
+; GFX1332-NEXT: v_readlane_b32 s0, v2, 31
+; GFX1332-NEXT: v_mov_b32_dpp v6, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s6, v2, 15
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v0, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: v_writelane_b32 v6, s3, 16
+; GFX1332-NEXT: v_writelane_b32 v5, s6, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1332-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB20_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1332-NEXT: ds_xor_rtn_b64 v[7:8], v0, v[7:8]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB20_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v8
+; GFX1332-NEXT: v_dual_mov_b32 v8, v5 :: v_dual_mov_b32 v9, v6
+; GFX1332-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_xor_b32_e32 v9, s3, v9
+; GFX1332-NEXT: v_xor_b32_e32 v8, s4, v8
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[8:9], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%lane_ext = zext i32 %lane to i64
@@ -10867,6 +13027,116 @@ define amdgpu_kernel void @max_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: max_i32_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0x80000000, v0, s[0:1]
+; GFX1364-NEXT: v_bfrev_b32_e32 v3, 1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_max_i32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_max_i32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_max_i32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_max_i32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1364-NEXT: v_max_i32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_max_i32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 16
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v3, s3, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr0
+; GFX1364-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB21_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: v_mov_b32_e32 v4, s6
+; GFX1364-NEXT: ds_max_rtn_i32 v0, v0, v4
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB21_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, v3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_max_i32_e32 v0, s3, v0
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: max_i32_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0x80000000, v0, s0
+; GFX1332-NEXT: v_bfrev_b32_e32 v3, 1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_max_i32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_max_i32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_max_i32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_max_i32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1332-NEXT: v_max_i32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s1, v1, 15
+; GFX1332-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: v_writelane_b32 v3, s1, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: s_mov_b32 s0, s2
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr0
+; GFX1332-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB21_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v4, s0
+; GFX1332-NEXT: ds_max_rtn_i32 v0, v0, v4
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB21_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1332-NEXT: v_mov_b32_e32 v0, v3
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_max_i32_e32 v0, s3, v0
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw max ptr addrspace(3) @local_var32, i32 %lane acq_rel
@@ -11103,6 +13373,70 @@ define amdgpu_kernel void @max_i64_constant(ptr addrspace(1) %out) {
; GFX1132-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: max_i64_constant:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1364-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB22_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, 5
+; GFX1364-NEXT: v_mov_b32_e32 v1, 0
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB22_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc
+; GFX1364-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
+; GFX1364-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: max_i64_constant:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1332-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB22_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v0, 5 :: v_dual_mov_b32 v1, 0
+; GFX1332-NEXT: v_mov_b32_e32 v2, 0
+; GFX1332-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB22_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc_lo
+; GFX1332-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
+; GFX1332-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw max ptr addrspace(3) @local_var64, i64 5 acq_rel
store i64 %old, ptr addrspace(1) %out
@@ -12090,6 +14424,214 @@ define amdgpu_kernel void @max_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b64 v[7:8], off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: max_i64_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v2, 0x80000000, 0, s[0:1]
+; GFX1364-NEXT: v_bfrev_b32_e32 v4, 1
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
+; GFX1364-NEXT: v_bfrev_b32_e32 v6, 1
+; GFX1364-NEXT: v_mov_b32_e32 v5, 0
+; GFX1364-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_cmp_gt_i64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: v_bfrev_b32_e32 v4, 1
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_mov_b32_dpp v6, v2 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v5, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_cmp_gt_i64_e32 vcc, v[1:2], v[5:6]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX1364-NEXT: v_bfrev_b32_e32 v6, 1
+; GFX1364-NEXT: v_mov_b32_e32 v5, 0
+; GFX1364-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_cmp_gt_i64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: v_bfrev_b32_e32 v4, 1
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_mov_b32_dpp v6, v2 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v5, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_cmp_gt_i64_e32 vcc, v[1:2], v[5:6]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX1364-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_permlanex16_b32 v6, v1, -1, -1
+; GFX1364-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: v_cmp_gt_i64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: v_bfrev_b32_e32 v4, 1
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_e32 v5, s2
+; GFX1364-NEXT: v_mov_b32_e32 v6, s3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_bfrev_b32_e32 v5, 1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cmp_gt_i64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 15
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s6, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s7, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v4, s3, 16
+; GFX1364-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1364-NEXT: v_readlane_b32 s3, v2, 63
+; GFX1364-NEXT: v_readlane_b32 s9, v1, 47
+; GFX1364-NEXT: v_writelane_b32 v5, s6, 32
+; GFX1364-NEXT: v_writelane_b32 v4, s7, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[6:7], -1
+; GFX1364-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1364-NEXT: v_writelane_b32 v5, s8, 48
+; GFX1364-NEXT: v_writelane_b32 v4, s9, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[6:7]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1364-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB23_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v8, s1
+; GFX1364-NEXT: v_mov_b32_e32 v7, s0
+; GFX1364-NEXT: ds_max_rtn_i64 v[7:8], v0, v[7:8]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB23_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s5, v8
+; GFX1364-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1364-NEXT: v_mov_b32_e32 v7, v4
+; GFX1364-NEXT: v_mov_b32_e32 v8, v5
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[7:8]
+; GFX1364-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc
+; GFX1364-NEXT: v_cndmask_b32_e64 v7, v7, s4, vcc
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[7:8], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: max_i64_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_cndmask_b32_e64 v2, 0x80000000, 0, s2
+; GFX1332-NEXT: v_bfrev_b32_e32 v4, 1
+; GFX1332-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v1, 0, v0, s2
+; GFX1332-NEXT: v_bfrev_b32_e32 v6, 1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[1:2], v[3:4]
+; GFX1332-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_cndmask_b32 v2, v4, v2
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, v3, v1, vcc_lo :: v_dual_mov_b32 v3, 0
+; GFX1332-NEXT: v_bfrev_b32_e32 v4, 1
+; GFX1332-NEXT: v_mov_b32_dpp v6, v2 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v5, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[1:2], v[5:6]
+; GFX1332-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v1, v5, v1
+; GFX1332-NEXT: v_bfrev_b32_e32 v6, 1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[1:2], v[3:4]
+; GFX1332-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_cndmask_b32 v2, v4, v2
+; GFX1332-NEXT: v_bfrev_b32_e32 v4, 1
+; GFX1332-NEXT: v_mov_b32_dpp v6, v2 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, v3, v1, vcc_lo :: v_dual_mov_b32 v3, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v5, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[1:2], v[5:6]
+; GFX1332-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v1, v5, v1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1332-NEXT: v_permlanex16_b32 v6, v1, -1, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_bfrev_b32_e32 v5, 1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_gt_i64_e32 vcc_lo, v[1:2], v[3:4]
+; GFX1332-NEXT: v_dual_cndmask_b32 v2, v4, v2, vcc_lo :: v_dual_mov_b32 v4, 0
+; GFX1332-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX1332-NEXT: v_readlane_b32 s3, v2, 15
+; GFX1332-NEXT: v_readlane_b32 s1, v2, 31
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s0, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v0, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: v_writelane_b32 v5, s3, 16
+; GFX1332-NEXT: v_writelane_b32 v4, s6, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1332-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB23_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1332-NEXT: ds_max_rtn_i64 v[7:8], v0, v[7:8]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB23_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s5, v8
+; GFX1332-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1332-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v5
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[7:8]
+; GFX1332-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc_lo
+; GFX1332-NEXT: v_cndmask_b32_e64 v7, v7, s4, vcc_lo
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[7:8], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%lane_ext = zext i32 %lane to i64
@@ -12690,6 +15232,116 @@ define amdgpu_kernel void @min_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: min_i32_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0x7fffffff, v0, s[0:1]
+; GFX1364-NEXT: v_bfrev_b32_e32 v3, -2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_min_i32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_min_i32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_min_i32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_min_i32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1364-NEXT: v_min_i32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_min_i32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 16
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v3, s3, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr0
+; GFX1364-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB24_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: v_mov_b32_e32 v4, s6
+; GFX1364-NEXT: ds_min_rtn_i32 v0, v0, v4
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB24_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, v3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_min_i32_e32 v0, s3, v0
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: min_i32_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0x7fffffff, v0, s0
+; GFX1332-NEXT: v_bfrev_b32_e32 v3, -2
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_min_i32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_min_i32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_min_i32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_min_i32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1332-NEXT: v_min_i32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s1, v1, 15
+; GFX1332-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: v_writelane_b32 v3, s1, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: s_mov_b32 s0, s2
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr0
+; GFX1332-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB24_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v4, s0
+; GFX1332-NEXT: ds_min_rtn_i32 v0, v0, v4
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB24_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1332-NEXT: v_mov_b32_e32 v0, v3
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_min_i32_e32 v0, s3, v0
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw min ptr addrspace(3) @local_var32, i32 %lane acq_rel
@@ -12926,6 +15578,70 @@ define amdgpu_kernel void @min_i64_constant(ptr addrspace(1) %out) {
; GFX1132-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: min_i64_constant:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1364-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB25_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, 5
+; GFX1364-NEXT: v_mov_b32_e32 v1, 0
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB25_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc
+; GFX1364-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
+; GFX1364-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: min_i64_constant:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1332-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB25_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v0, 5 :: v_dual_mov_b32 v1, 0
+; GFX1332-NEXT: v_mov_b32_e32 v2, 0
+; GFX1332-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB25_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc_lo
+; GFX1332-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
+; GFX1332-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw min ptr addrspace(3) @local_var64, i64 5 acq_rel
store i64 %old, ptr addrspace(1) %out
@@ -13913,6 +16629,214 @@ define amdgpu_kernel void @min_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b64 v[7:8], off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: min_i64_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v2, 0x7fffffff, 0, s[0:1]
+; GFX1364-NEXT: v_bfrev_b32_e32 v4, -2
+; GFX1364-NEXT: v_mov_b32_e32 v3, -1
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, -1, v0, s[0:1]
+; GFX1364-NEXT: v_bfrev_b32_e32 v6, -2
+; GFX1364-NEXT: v_mov_b32_e32 v5, -1
+; GFX1364-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_cmp_lt_i64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: v_bfrev_b32_e32 v4, -2
+; GFX1364-NEXT: v_mov_b32_e32 v3, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_mov_b32_dpp v6, v2 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v5, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_cmp_lt_i64_e32 vcc, v[1:2], v[5:6]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX1364-NEXT: v_bfrev_b32_e32 v6, -2
+; GFX1364-NEXT: v_mov_b32_e32 v5, -1
+; GFX1364-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_cmp_lt_i64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: v_bfrev_b32_e32 v4, -2
+; GFX1364-NEXT: v_mov_b32_e32 v3, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_mov_b32_dpp v6, v2 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v5, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_cmp_lt_i64_e32 vcc, v[1:2], v[5:6]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX1364-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_permlanex16_b32 v6, v1, -1, -1
+; GFX1364-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: v_cmp_lt_i64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: v_bfrev_b32_e32 v4, -2
+; GFX1364-NEXT: v_mov_b32_e32 v3, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_e32 v5, s2
+; GFX1364-NEXT: v_mov_b32_e32 v6, s3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_bfrev_b32_e32 v5, -2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cmp_lt_i64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v4, -1
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 15
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s6, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s7, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v4, s3, 16
+; GFX1364-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1364-NEXT: v_readlane_b32 s3, v2, 63
+; GFX1364-NEXT: v_readlane_b32 s9, v1, 47
+; GFX1364-NEXT: v_writelane_b32 v5, s6, 32
+; GFX1364-NEXT: v_writelane_b32 v4, s7, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[6:7], -1
+; GFX1364-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1364-NEXT: v_writelane_b32 v5, s8, 48
+; GFX1364-NEXT: v_writelane_b32 v4, s9, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[6:7]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1364-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB26_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v8, s1
+; GFX1364-NEXT: v_mov_b32_e32 v7, s0
+; GFX1364-NEXT: ds_min_rtn_i64 v[7:8], v0, v[7:8]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB26_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s5, v8
+; GFX1364-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1364-NEXT: v_mov_b32_e32 v7, v4
+; GFX1364-NEXT: v_mov_b32_e32 v8, v5
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[7:8]
+; GFX1364-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc
+; GFX1364-NEXT: v_cndmask_b32_e64 v7, v7, s4, vcc
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[7:8], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: min_i64_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_cndmask_b32_e64 v2, 0x7fffffff, 0, s2
+; GFX1332-NEXT: v_bfrev_b32_e32 v4, -2
+; GFX1332-NEXT: v_dual_mov_b32 v3, -1 :: v_dual_cndmask_b32 v1, -1, v0, s2
+; GFX1332-NEXT: v_bfrev_b32_e32 v6, -2
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[1:2], v[3:4]
+; GFX1332-NEXT: v_dual_mov_b32 v5, -1 :: v_dual_cndmask_b32 v2, v4, v2
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, v3, v1, vcc_lo :: v_dual_mov_b32 v3, -1
+; GFX1332-NEXT: v_bfrev_b32_e32 v4, -2
+; GFX1332-NEXT: v_mov_b32_dpp v6, v2 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v5, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[1:2], v[5:6]
+; GFX1332-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v1, v5, v1
+; GFX1332-NEXT: v_bfrev_b32_e32 v6, -2
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[1:2], v[3:4]
+; GFX1332-NEXT: v_dual_mov_b32 v5, -1 :: v_dual_cndmask_b32 v2, v4, v2
+; GFX1332-NEXT: v_bfrev_b32_e32 v4, -2
+; GFX1332-NEXT: v_mov_b32_dpp v6, v2 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, v3, v1, vcc_lo :: v_dual_mov_b32 v3, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v5, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[1:2], v[5:6]
+; GFX1332-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v1, v5, v1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1332-NEXT: v_permlanex16_b32 v6, v1, -1, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_bfrev_b32_e32 v5, -2
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[1:2], v[3:4]
+; GFX1332-NEXT: v_dual_cndmask_b32 v2, v4, v2, vcc_lo :: v_dual_mov_b32 v4, -1
+; GFX1332-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX1332-NEXT: v_readlane_b32 s3, v2, 15
+; GFX1332-NEXT: v_readlane_b32 s1, v2, 31
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s0, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v0, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: v_writelane_b32 v5, s3, 16
+; GFX1332-NEXT: v_writelane_b32 v4, s6, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1332-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB26_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1332-NEXT: ds_min_rtn_i64 v[7:8], v0, v[7:8]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB26_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s5, v8
+; GFX1332-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1332-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v5
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[4:5], v[7:8]
+; GFX1332-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc_lo
+; GFX1332-NEXT: v_cndmask_b32_e64 v7, v7, s4, vcc_lo
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[7:8], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%lane_ext = zext i32 %lane to i64
@@ -14512,6 +17436,115 @@ define amdgpu_kernel void @umax_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: umax_i32_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1364-NEXT: v_max_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_max_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 16
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v3, s3, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr0
+; GFX1364-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB27_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, s6
+; GFX1364-NEXT: ds_max_rtn_u32 v0, v4, v0
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB27_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, v3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_max_u32_e32 v0, s3, v0
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: umax_i32_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, 0, v0, s0 :: v_dual_mov_b32 v3, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_max_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1332-NEXT: v_max_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s1, v1, 15
+; GFX1332-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v4, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: v_writelane_b32 v3, s1, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: s_mov_b32 s0, s2
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr0
+; GFX1332-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB27_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_mov_b32_e32 v0, s0
+; GFX1332-NEXT: ds_max_rtn_u32 v0, v4, v0
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB27_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1332-NEXT: v_mov_b32_e32 v0, v3
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_max_u32_e32 v0, s3, v0
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw umax ptr addrspace(3) @local_var32, i32 %lane acq_rel
@@ -14745,6 +17778,70 @@ define amdgpu_kernel void @umax_i64_constant(ptr addrspace(1) %out) {
; GFX1132-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: umax_i64_constant:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1364-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB28_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, 5
+; GFX1364-NEXT: v_mov_b32_e32 v1, 0
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB28_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-NEXT: v_mov_b32_e32 v1, 0
+; GFX1364-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
+; GFX1364-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, s3, vcc
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: umax_i64_constant:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1332-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB28_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v0, 5 :: v_dual_mov_b32 v1, 0
+; GFX1332-NEXT: v_mov_b32_e32 v2, 0
+; GFX1332-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB28_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-NEXT: v_mov_b32_e32 v1, 0
+; GFX1332-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX1332-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, s3, vcc_lo
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw umax ptr addrspace(3) @local_var64, i64 5 acq_rel
store i64 %old, ptr addrspace(1) %out
@@ -15721,6 +18818,212 @@ define amdgpu_kernel void @umax_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b64 v[7:8], off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: umax_i64_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v2, 0, 0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v6, 0
+; GFX1364-NEXT: v_mov_b32_e32 v5, 0
+; GFX1364-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_mov_b32_dpp v6, v2 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v5, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[5:6]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v6, 0
+; GFX1364-NEXT: v_mov_b32_e32 v5, 0
+; GFX1364-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_mov_b32_dpp v6, v2 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v5, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[5:6]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX1364-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_permlanex16_b32 v6, v1, -1, -1
+; GFX1364-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_e32 v5, s2
+; GFX1364-NEXT: v_mov_b32_e32 v6, s3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_e32 v5, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cmp_gt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v4, 0
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 15
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s6, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s7, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v4, s3, 16
+; GFX1364-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1364-NEXT: v_readlane_b32 s3, v2, 63
+; GFX1364-NEXT: v_readlane_b32 s9, v1, 47
+; GFX1364-NEXT: v_writelane_b32 v5, s6, 32
+; GFX1364-NEXT: v_writelane_b32 v4, s7, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[6:7], -1
+; GFX1364-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1364-NEXT: v_writelane_b32 v5, s8, 48
+; GFX1364-NEXT: v_writelane_b32 v4, s9, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[6:7]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1364-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB29_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v8, s1
+; GFX1364-NEXT: v_mov_b32_e32 v7, s0
+; GFX1364-NEXT: ds_max_rtn_u64 v[7:8], v0, v[7:8]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB29_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s5, v8
+; GFX1364-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1364-NEXT: v_mov_b32_e32 v7, v4
+; GFX1364-NEXT: v_mov_b32_e32 v8, v5
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[7:8]
+; GFX1364-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc
+; GFX1364-NEXT: v_cndmask_b32_e64 v7, v7, s4, vcc
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[7:8], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: umax_i64_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_cndmask_b32_e64 v2, 0, 0, s2
+; GFX1332-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, 0, v0, s2 :: v_dual_mov_b32 v6, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[1:2], v[3:4]
+; GFX1332-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_cndmask_b32 v2, v4, v2
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, v3, v1 :: v_dual_mov_b32 v4, 0
+; GFX1332-NEXT: v_mov_b32_dpp v6, v2 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v5, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[1:2], v[5:6]
+; GFX1332-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_cndmask_b32 v2, v6, v2
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_mov_b32 v6, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[1:2], v[3:4]
+; GFX1332-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_cndmask_b32 v2, v4, v2
+; GFX1332-NEXT: v_mov_b32_e32 v4, 0
+; GFX1332-NEXT: v_mov_b32_dpp v6, v2 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, v3, v1, vcc_lo :: v_dual_mov_b32 v3, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v5, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[1:2], v[5:6]
+; GFX1332-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v1, v5, v1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1332-NEXT: v_permlanex16_b32 v6, v1, -1, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_e32 v5, 0
+; GFX1332-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_gt_u64_e32 vcc_lo, v[1:2], v[3:4]
+; GFX1332-NEXT: v_dual_cndmask_b32 v2, v4, v2, vcc_lo :: v_dual_mov_b32 v4, 0
+; GFX1332-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX1332-NEXT: v_readlane_b32 s3, v2, 15
+; GFX1332-NEXT: v_readlane_b32 s1, v2, 31
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s0, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v0, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: v_writelane_b32 v5, s3, 16
+; GFX1332-NEXT: v_writelane_b32 v4, s6, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1332-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB29_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1332-NEXT: ds_max_rtn_u64 v[7:8], v0, v[7:8]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB29_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s5, v8
+; GFX1332-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1332-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v5
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[7:8]
+; GFX1332-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc_lo
+; GFX1332-NEXT: v_cndmask_b32_e64 v7, v7, s4, vcc_lo
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[7:8], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%lane_ext = zext i32 %lane to i64
@@ -16321,6 +19624,115 @@ define amdgpu_kernel void @umin_i32_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: umin_i32_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, -1, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v3, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_min_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_min_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_min_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_min_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1364-NEXT: v_min_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1364-NEXT: v_mov_b32_e32 v2, s2
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_min_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 16
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 47
+; GFX1364-NEXT: v_readlane_b32 s6, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v3, s3, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_writelane_b32 v3, s2, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr0
+; GFX1364-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB30_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: v_mov_b32_e32 v4, s6
+; GFX1364-NEXT: ds_min_rtn_u32 v0, v0, v4
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB30_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, v3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_min_u32_e32 v0, s3, v0
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: umin_i32_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, -1, v0, s0 :: v_dual_mov_b32 v3, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_min_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_min_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_min_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_min_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1332-NEXT: v_min_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s1, v1, 15
+; GFX1332-NEXT: v_readlane_b32 s2, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s0, -1
+; GFX1332-NEXT: v_writelane_b32 v3, s1, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: s_mov_b32 s0, s2
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr0
+; GFX1332-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB30_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v4, s0
+; GFX1332-NEXT: ds_min_rtn_u32 v0, v0, v4
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB30_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1332-NEXT: v_mov_b32_e32 v0, v3
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_min_u32_e32 v0, s3, v0
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = atomicrmw umin ptr addrspace(3) @local_var32, i32 %lane acq_rel
@@ -16554,6 +19966,70 @@ define amdgpu_kernel void @umin_i64_constant(ptr addrspace(1) %out) {
; GFX1132-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132-NEXT: buffer_store_b64 v[0:1], off, s[0:3], 0
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: umin_i64_constant:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1364-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB31_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v0, 5
+; GFX1364-NEXT: v_mov_b32_e32 v1, 0
+; GFX1364-NEXT: v_mov_b32_e32 v2, 0
+; GFX1364-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB31_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1364-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc
+; GFX1364-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc
+; GFX1364-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: umin_i64_constant:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: ; implicit-def: $vgpr0_vgpr1
+; GFX1332-NEXT: s_and_saveexec_b32 s0, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB31_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v0, 5 :: v_dual_mov_b32 v1, 0
+; GFX1332-NEXT: v_mov_b32_e32 v2, 0
+; GFX1332-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB31_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s3, v1
+; GFX1332-NEXT: v_readfirstlane_b32 s2, v0
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo
+; GFX1332-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX1332-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
+; GFX1332-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[0:1], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%old = atomicrmw umin ptr addrspace(3) @local_var64, i64 5 acq_rel
store i64 %old, ptr addrspace(1) %out
@@ -17528,6 +21004,212 @@ define amdgpu_kernel void @umin_i64_varying(ptr addrspace(1) %out) {
; GFX1132_DPP-NEXT: s_waitcnt lgkmcnt(0)
; GFX1132_DPP-NEXT: buffer_store_b64 v[7:8], off, s[0:3], 0
; GFX1132_DPP-NEXT: s_endpgm
+;
+; GFX1364-LABEL: umin_i64_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cndmask_b32_e64 v2, -1, 0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v4, -1
+; GFX1364-NEXT: v_mov_b32_e32 v3, -1
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, -1, v0, s[0:1]
+; GFX1364-NEXT: v_mov_b32_e32 v6, -1
+; GFX1364-NEXT: v_mov_b32_e32 v5, -1
+; GFX1364-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_cmp_lt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v4, -1
+; GFX1364-NEXT: v_mov_b32_e32 v3, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_mov_b32_dpp v6, v2 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v5, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_cmp_lt_u64_e32 vcc, v[1:2], v[5:6]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v6, -1
+; GFX1364-NEXT: v_mov_b32_e32 v5, -1
+; GFX1364-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_cmp_lt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v4, -1
+; GFX1364-NEXT: v_mov_b32_e32 v3, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_mov_b32_dpp v6, v2 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v5, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_cmp_lt_u64_e32 vcc, v[1:2], v[5:6]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
+; GFX1364-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_permlanex16_b32 v6, v1, -1, -1
+; GFX1364-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: v_cmp_lt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v4, -1
+; GFX1364-NEXT: v_mov_b32_e32 v3, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_e32 v5, s2
+; GFX1364-NEXT: v_mov_b32_e32 v6, s3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: v_mov_b32_e32 v5, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: v_cmp_lt_u64_e32 vcc, v[1:2], v[3:4]
+; GFX1364-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; GFX1364-NEXT: v_mov_b32_e32 v4, -1
+; GFX1364-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[0:1], -1
+; GFX1364-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s2, v2, 15
+; GFX1364-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s3, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s6, v2, 31
+; GFX1364-NEXT: v_readlane_b32 s7, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v5, s2, 16
+; GFX1364-NEXT: v_readlane_b32 s2, v1, 63
+; GFX1364-NEXT: v_writelane_b32 v4, s3, 16
+; GFX1364-NEXT: v_readlane_b32 s8, v2, 47
+; GFX1364-NEXT: v_readlane_b32 s3, v2, 63
+; GFX1364-NEXT: v_readlane_b32 s9, v1, 47
+; GFX1364-NEXT: v_writelane_b32 v5, s6, 32
+; GFX1364-NEXT: v_writelane_b32 v4, s7, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[0:1]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v7, exec_hi, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[6:7], -1
+; GFX1364-NEXT: s_mov_b64 s[0:1], s[2:3]
+; GFX1364-NEXT: v_writelane_b32 v5, s8, 48
+; GFX1364-NEXT: v_writelane_b32 v4, s9, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[6:7]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v7
+; GFX1364-NEXT: s_mov_b32 s2, -1
+; GFX1364-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1364-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB32_2
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: v_mov_b32_e32 v8, s1
+; GFX1364-NEXT: v_mov_b32_e32 v7, s0
+; GFX1364-NEXT: ds_min_rtn_u64 v[7:8], v0, v[7:8]
+; GFX1364-NEXT: s_wait_dscnt 0x0
+; GFX1364-NEXT: global_inv scope:SCOPE_SE
+; GFX1364-NEXT: .LBB32_2:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX1364-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1364-NEXT: v_readfirstlane_b32 s5, v8
+; GFX1364-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1364-NEXT: v_mov_b32_e32 v7, v4
+; GFX1364-NEXT: v_mov_b32_e32 v8, v5
+; GFX1364-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[7:8]
+; GFX1364-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc
+; GFX1364-NEXT: v_cndmask_b32_e64 v7, v7, s4, vcc
+; GFX1364-NEXT: s_wait_kmcnt 0x0
+; GFX1364-NEXT: buffer_store_b64 v[7:8], off, s[0:3], null
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: umin_i64_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_cndmask_b32_e64 v2, -1, 0, s2
+; GFX1332-NEXT: v_dual_mov_b32 v4, -1 :: v_dual_mov_b32 v3, -1
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, -1, v0, s2 :: v_dual_mov_b32 v6, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[1:2], v[3:4]
+; GFX1332-NEXT: v_dual_mov_b32 v5, -1 :: v_dual_cndmask_b32 v2, v4, v2
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, v3, v1 :: v_dual_mov_b32 v4, -1
+; GFX1332-NEXT: v_mov_b32_dpp v6, v2 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v5, v1 row_shr:2 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[1:2], v[5:6]
+; GFX1332-NEXT: v_dual_mov_b32 v3, -1 :: v_dual_cndmask_b32 v2, v6, v2
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_mov_b32 v6, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v2 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:4 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[1:2], v[3:4]
+; GFX1332-NEXT: v_dual_mov_b32 v5, -1 :: v_dual_cndmask_b32 v2, v4, v2
+; GFX1332-NEXT: v_mov_b32_e32 v4, -1
+; GFX1332-NEXT: v_mov_b32_dpp v6, v2 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, v3, v1, vcc_lo :: v_dual_mov_b32 v3, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_mov_b32_dpp v5, v1 row_shr:8 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[1:2], v[5:6]
+; GFX1332-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v1, v5, v1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_permlanex16_b32 v5, v2, -1, -1
+; GFX1332-NEXT: v_permlanex16_b32 v6, v1, -1, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1332-NEXT: v_mov_b32_dpp v4, v5 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_e32 v5, -1
+; GFX1332-NEXT: v_mov_b32_dpp v3, v6 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[1:2], v[3:4]
+; GFX1332-NEXT: v_dual_cndmask_b32 v2, v4, v2, vcc_lo :: v_dual_mov_b32 v4, -1
+; GFX1332-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
+; GFX1332-NEXT: v_readlane_b32 s3, v2, 15
+; GFX1332-NEXT: v_readlane_b32 s1, v2, 31
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: v_readlane_b32 s0, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v5, v2 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_mov_b32_dpp v4, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s6, v1, 15
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v7, exec_lo, 0
+; GFX1332-NEXT: v_mov_b32_e32 v0, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s2, -1
+; GFX1332-NEXT: v_writelane_b32 v5, s3, 16
+; GFX1332-NEXT: v_writelane_b32 v4, s6, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s2
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v7
+; GFX1332-NEXT: s_mov_b32 s2, -1
+; GFX1332-NEXT: ; implicit-def: $vgpr7_vgpr8
+; GFX1332-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB32_2
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v7, s0
+; GFX1332-NEXT: ds_min_rtn_u64 v[7:8], v0, v[7:8]
+; GFX1332-NEXT: s_wait_dscnt 0x0
+; GFX1332-NEXT: global_inv scope:SCOPE_SE
+; GFX1332-NEXT: .LBB32_2:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX1332-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX1332-NEXT: v_readfirstlane_b32 s5, v8
+; GFX1332-NEXT: v_readfirstlane_b32 s4, v7
+; GFX1332-NEXT: v_dual_mov_b32 v7, v4 :: v_dual_mov_b32 v8, v5
+; GFX1332-NEXT: s_mov_b32 s3, 0x31016000
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[4:5], v[7:8]
+; GFX1332-NEXT: v_cndmask_b32_e64 v8, v8, s5, vcc_lo
+; GFX1332-NEXT: v_cndmask_b32_e64 v7, v7, s4, vcc_lo
+; GFX1332-NEXT: s_wait_kmcnt 0x0
+; GFX1332-NEXT: buffer_store_b64 v[7:8], off, s[0:3], null
+; GFX1332-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%lane_ext = zext i32 %lane to i64
@@ -17535,3 +21217,6 @@ entry:
store i64 %old, ptr addrspace(1) %out
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1332_DPP: {{.*}}
+; GFX1364_DPP: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
index e7ade6614795c..8dcdd6ec38420 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
@@ -6,6 +6,8 @@
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1010 -mattr=+wavefrontsize32 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1032 %s
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+wavefrontsize64 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1164 %s
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+wavefrontsize32 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1132 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1310 -mattr=+wavefrontsize64 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1364 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1310 -mattr=+wavefrontsize32 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1332 %s
declare i1 @llvm.amdgcn.wqm.vote(i1)
declare i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32, ptr addrspace(8), i32, i32, i32 immarg)
@@ -233,6 +235,85 @@ define amdgpu_ps void @add_i32_constant(ptr addrspace(8) inreg %out, ptr addrspa
; GFX1132-NEXT: buffer_store_b32 v0, off, s[0:3], 0
; GFX1132-NEXT: .LBB0_6: ; %UnifiedReturnBlock
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i32_constant:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_mov_b64 s[10:11], exec
+; GFX1364-NEXT: ; implicit-def: $vgpr0
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
+; GFX1364-NEXT: s_cbranch_execz .LBB0_4
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_mov_b64 s[12:13], exec
+; GFX1364-NEXT: s_mov_b64 s[10:11], exec
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, s12, 0
+; GFX1364-NEXT: ; implicit-def: $vgpr1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, s13, v0
+; GFX1364-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1364-NEXT: s_cbranch_execz .LBB0_3
+; GFX1364-NEXT: ; %bb.2:
+; GFX1364-NEXT: s_bcnt1_i32_b64 s12, s[12:13]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: s_mul_i32 s12, s12, 5
+; GFX1364-NEXT: v_mov_b32_e32 v1, s12
+; GFX1364-NEXT: buffer_atomic_add_u32 v1, off, s[4:7], null th:TH_ATOMIC_RETURN
+; GFX1364-NEXT: .LBB0_3:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[10:11]
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: v_readfirstlane_b32 s4, v1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_mad_u32_u24 v0, 5, v0, s4
+; GFX1364-NEXT: .LBB0_4: ; %Flow
+; GFX1364-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-NEXT: s_wqm_b64 s[4:5], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: s_and_b64 s[4:5], s[4:5], s[4:5]
+; GFX1364-NEXT: s_and_not1_b64 vcc, exec, s[4:5]
+; GFX1364-NEXT: s_cbranch_vccnz .LBB0_6
+; GFX1364-NEXT: ; %bb.5: ; %if
+; GFX1364-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1364-NEXT: .LBB0_6: ; %UnifiedReturnBlock
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i32_constant:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_mov_b32 s9, exec_lo
+; GFX1332-NEXT: ; implicit-def: $vgpr0
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1332-NEXT: s_and_saveexec_b32 s8, s9
+; GFX1332-NEXT: s_cbranch_execz .LBB0_4
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_mov_b32 s10, exec_lo
+; GFX1332-NEXT: s_mov_b32 s9, exec_lo
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, s10, 0
+; GFX1332-NEXT: ; implicit-def: $vgpr1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX1332-NEXT: s_cbranch_execz .LBB0_3
+; GFX1332-NEXT: ; %bb.2:
+; GFX1332-NEXT: s_bcnt1_i32_b32 s10, s10
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: s_mul_i32 s10, s10, 5
+; GFX1332-NEXT: v_mov_b32_e32 v1, s10
+; GFX1332-NEXT: buffer_atomic_add_u32 v1, off, s[4:7], null th:TH_ATOMIC_RETURN
+; GFX1332-NEXT: .LBB0_3:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: v_readfirstlane_b32 s4, v1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_mad_u32_u24 v0, 5, v0, s4
+; GFX1332-NEXT: .LBB0_4: ; %Flow
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s8
+; GFX1332-NEXT: s_wqm_b32 s4, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: s_and_b32 s4, s4, s4
+; GFX1332-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
+; GFX1332-NEXT: s_cbranch_vccnz .LBB0_6
+; GFX1332-NEXT: ; %bb.5: ; %if
+; GFX1332-NEXT: buffer_store_b32 v0, off, s[0:3], null
+; GFX1332-NEXT: .LBB0_6: ; %UnifiedReturnBlock
+; GFX1332-NEXT: s_endpgm
entry:
%cond1 = call i1 @llvm.amdgcn.wqm.vote(i1 true)
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
@@ -607,6 +688,132 @@ define amdgpu_ps void @add_i32_varying(ptr addrspace(8) inreg %out, ptr addrspac
; GFX1132-NEXT: buffer_store_b32 v4, off, s[0:3], 0
; GFX1132-NEXT: .LBB1_6: ; %UnifiedReturnBlock
; GFX1132-NEXT: s_endpgm
+;
+; GFX1364-LABEL: add_i32_varying:
+; GFX1364: ; %bb.0: ; %entry
+; GFX1364-NEXT: s_mov_b64 s[8:9], exec
+; GFX1364-NEXT: ; implicit-def: $vgpr4
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: s_mov_b64 s[10:11], s[8:9]
+; GFX1364-NEXT: s_and_saveexec_b64 s[8:9], s[10:11]
+; GFX1364-NEXT: s_cbranch_execz .LBB1_4
+; GFX1364-NEXT: ; %bb.1:
+; GFX1364-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_cndmask_b32_e64 v1, 0, v0, s[10:11]
+; GFX1364-NEXT: v_mov_b32_e32 v3, 0
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1364-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s12, v1, 31
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1364-NEXT: v_mov_b32_e32 v2, s12
+; GFX1364-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1364-NEXT: v_readlane_b32 s12, v1, 15
+; GFX1364-NEXT: v_readlane_b32 s13, v1, 31
+; GFX1364-NEXT: v_writelane_b32 v3, s12, 16
+; GFX1364-NEXT: s_mov_b64 exec, s[10:11]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1364-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1364-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GFX1364-NEXT: v_readlane_b32 s12, v1, 63
+; GFX1364-NEXT: v_readlane_b32 s14, v1, 47
+; GFX1364-NEXT: v_writelane_b32 v3, s13, 32
+; GFX1364-NEXT: s_mov_b64 exec, s[10:11]
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1364-NEXT: v_mbcnt_hi_u32_b32 v0, exec_hi, v0
+; GFX1364-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GFX1364-NEXT: v_writelane_b32 v3, s14, 48
+; GFX1364-NEXT: s_mov_b64 exec, s[10:11]
+; GFX1364-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX1364-NEXT: ; implicit-def: $vgpr0
+; GFX1364-NEXT: s_and_saveexec_b64 s[10:11], vcc
+; GFX1364-NEXT: s_cbranch_execz .LBB1_3
+; GFX1364-NEXT: ; %bb.2:
+; GFX1364-NEXT: v_mov_b32_e32 v0, s12
+; GFX1364-NEXT: buffer_atomic_add_u32 v0, off, s[4:7], null th:TH_ATOMIC_RETURN
+; GFX1364-NEXT: .LBB1_3:
+; GFX1364-NEXT: s_or_b64 exec, exec, s[10:11]
+; GFX1364-NEXT: s_wait_loadcnt 0x0
+; GFX1364-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1364-NEXT: v_mov_b32_e32 v0, v3
+; GFX1364-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1364-NEXT: v_add_nc_u32_e32 v4, s4, v0
+; GFX1364-NEXT: .LBB1_4: ; %Flow
+; GFX1364-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX1364-NEXT: s_wqm_b64 s[4:5], -1
+; GFX1364-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1364-NEXT: s_and_b64 s[4:5], s[4:5], s[4:5]
+; GFX1364-NEXT: s_and_not1_b64 vcc, exec, s[4:5]
+; GFX1364-NEXT: s_cbranch_vccnz .LBB1_6
+; GFX1364-NEXT: ; %bb.5: ; %if
+; GFX1364-NEXT: buffer_store_b32 v4, off, s[0:3], null
+; GFX1364-NEXT: .LBB1_6: ; %UnifiedReturnBlock
+; GFX1364-NEXT: s_endpgm
+;
+; GFX1332-LABEL: add_i32_varying:
+; GFX1332: ; %bb.0: ; %entry
+; GFX1332-NEXT: s_mov_b32 s8, exec_lo
+; GFX1332-NEXT: ; implicit-def: $vgpr4
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: s_mov_b32 s9, s8
+; GFX1332-NEXT: s_and_saveexec_b32 s8, s9
+; GFX1332-NEXT: s_cbranch_execz .LBB1_4
+; GFX1332-NEXT: ; %bb.1:
+; GFX1332-NEXT: s_or_saveexec_b32 s9, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_dual_cndmask_b32 v1, 0, v0, s9 :: v_dual_mov_b32 v3, 0
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
+; GFX1332-NEXT: v_permlanex16_b32 v2, v1, -1, -1
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s11, v1, 31
+; GFX1332-NEXT: v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
+; GFX1332-NEXT: v_readlane_b32 s10, v1, 15
+; GFX1332-NEXT: s_mov_b32 exec_lo, s9
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1332-NEXT: v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1332-NEXT: s_or_saveexec_b32 s9, -1
+; GFX1332-NEXT: v_writelane_b32 v3, s10, 16
+; GFX1332-NEXT: s_mov_b32 exec_lo, s9
+; GFX1332-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX1332-NEXT: ; implicit-def: $vgpr0
+; GFX1332-NEXT: s_and_saveexec_b32 s9, vcc_lo
+; GFX1332-NEXT: s_cbranch_execz .LBB1_3
+; GFX1332-NEXT: ; %bb.2:
+; GFX1332-NEXT: v_mov_b32_e32 v0, s11
+; GFX1332-NEXT: buffer_atomic_add_u32 v0, off, s[4:7], null th:TH_ATOMIC_RETURN
+; GFX1332-NEXT: .LBB1_3:
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s9
+; GFX1332-NEXT: s_wait_loadcnt 0x0
+; GFX1332-NEXT: v_readfirstlane_b32 s4, v0
+; GFX1332-NEXT: v_mov_b32_e32 v0, v3
+; GFX1332-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1332-NEXT: v_add_nc_u32_e32 v4, s4, v0
+; GFX1332-NEXT: .LBB1_4: ; %Flow
+; GFX1332-NEXT: s_or_b32 exec_lo, exec_lo, s8
+; GFX1332-NEXT: s_wqm_b32 s4, -1
+; GFX1332-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1332-NEXT: s_and_b32 s4, s4, s4
+; GFX1332-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4
+; GFX1332-NEXT: s_cbranch_vccnz .LBB1_6
+; GFX1332-NEXT: ; %bb.5: ; %if
+; GFX1332-NEXT: buffer_store_b32 v4, off, s[0:3], null
+; GFX1332-NEXT: .LBB1_6: ; %UnifiedReturnBlock
+; GFX1332-NEXT: s_endpgm
entry:
%cond1 = call i1 @llvm.amdgcn.wqm.vote(i1 true)
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 %val, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
index 70a2e396cfa06..29938f6c1d46a 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
@@ -8,6 +8,8 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11W32 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12W64 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12W32 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W64 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W32 %s
declare i32 @llvm.amdgcn.workitem.id.x()
declare i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32, ptr addrspace(8), i32, i32, i32)
@@ -274,6 +276,65 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: add_i32_constant:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_mov_b64 s[2:3], exec
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX13W64-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W64-NEXT: s_cbranch_execz .LBB0_2
+; GFX13W64-NEXT: ; %bb.1:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX13W64-NEXT: s_mul_i32 s2, s2, 5
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB0_2:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_mad_u32_u24 v0, 5, v0, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: add_i32_constant:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s0, exec_lo
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W32-NEXT: s_cbranch_execz .LBB0_2
+; GFX13W32-NEXT: ; %bb.1:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: s_bcnt1_i32_b32 s1, s1
+; GFX13W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: s_mul_i32 s1, s1, 5
+; GFX13W32-NEXT: v_mov_b32_e32 v1, s1
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB0_2:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W32-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W32-NEXT: v_mad_u32_u24 v0, 5, v0, s2
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
store i32 %old, ptr addrspace(1) %out
@@ -552,6 +613,67 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: v_mov_b32_e32 v1, 0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[2:3]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: add_i32_uniform:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_load_b32 s6, s[4:5], 0x44 nv
+; GFX13W64-NEXT: s_mov_b64 s[2:3], exec
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX13W64-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W64-NEXT: s_cbranch_execz .LBB1_2
+; GFX13W64-NEXT: ; %bb.1:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: s_mul_i32 s2, s6, s2
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB1_2:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W64-NEXT: v_mad_co_u64_u32 v[0:1], null, s6, v0, s[2:3]
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: add_i32_uniform:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_load_b32 s0, s[4:5], 0x44 nv
+; GFX13W32-NEXT: s_mov_b32 s2, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W32-NEXT: s_cbranch_execz .LBB1_2
+; GFX13W32-NEXT: ; %bb.1:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: s_bcnt1_i32_b32 s2, s2
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: s_mul_i32 s2, s0, s2
+; GFX13W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB1_2:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX13W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_mad_co_u64_u32 v[0:1], null, s0, v0, s[4:5]
+; GFX13W32-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX13W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 %additive, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
store i32 %old, ptr addrspace(1) %out
@@ -929,6 +1051,89 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: add_i32_varying_vdata:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: s_mov_b32 s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr0
+; GFX13W64-NEXT: .LBB2_1: ; %ComputeLoop
+; GFX13W64-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_readlane_b32 s8, v1, s3
+; GFX13W64-NEXT: v_writelane_b32 v0, s2, s3
+; GFX13W64-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX13W64-NEXT: s_add_co_i32 s2, s2, s8
+; GFX13W64-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[6:7]
+; GFX13W64-NEXT: s_cbranch_scc1 .LBB2_1
+; GFX13W64-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX13W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
+; GFX13W64-NEXT: s_cbranch_execz .LBB2_4
+; GFX13W64-NEXT: ; %bb.3:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB2_4:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_add_nc_u32_e32 v0, s2, v0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: add_i32_varying_vdata:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s0, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr0
+; GFX13W32-NEXT: .LBB2_1: ; %ComputeLoop
+; GFX13W32-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W32-NEXT: s_ctz_i32_b32 s2, s1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_readlane_b32 s3, v1, s2
+; GFX13W32-NEXT: v_writelane_b32 v0, s0, s2
+; GFX13W32-NEXT: s_lshl_b32 s2, 1, s2
+; GFX13W32-NEXT: s_add_co_i32 s0, s0, s3
+; GFX13W32-NEXT: s_and_not1_b32 s1, s1, s2
+; GFX13W32-NEXT: s_cbranch_scc1 .LBB2_1
+; GFX13W32-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX13W32-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX13W32-NEXT: s_cbranch_execz .LBB2_4
+; GFX13W32-NEXT: ; %bb.3:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: v_mov_b32_e32 v1, s0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_add_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB2_4:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 %lane, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
@@ -1040,6 +1245,20 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13-LABEL: add_i32_varying_offset:
+; GFX13: ; %bb.0: ; %entry
+; GFX13-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX13-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX13-NEXT: v_mov_b32_e32 v1, 1
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: buffer_atomic_add_u32 v1, v0, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX13-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13-NEXT: v_mov_b32_e32 v0, 0
+; GFX13-NEXT: s_wait_loadcnt 0x0
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX13-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32 1, ptr addrspace(8) %inout, i32 %lane, i32 0, i32 0)
@@ -1315,6 +1534,66 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: sub_i32_constant:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_mov_b64 s[2:3], exec
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX13W64-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W64-NEXT: s_cbranch_execz .LBB4_2
+; GFX13W64-NEXT: ; %bb.1:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX13W64-NEXT: s_mul_i32 s2, s2, 5
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB4_2:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mul_u32_u24_e32 v0, 5, v0
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: sub_i32_constant:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s0, exec_lo
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W32-NEXT: s_cbranch_execz .LBB4_2
+; GFX13W32-NEXT: ; %bb.1:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: s_bcnt1_i32_b32 s1, s1
+; GFX13W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: s_mul_i32 s1, s1, 5
+; GFX13W32-NEXT: v_mov_b32_e32 v1, s1
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB4_2:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W32-NEXT: v_mul_u32_u24_e32 v0, 5, v0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_sub_nc_u32 v0, s2, v0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.sub(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
store i32 %old, ptr addrspace(1) %out
@@ -1599,6 +1878,68 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s0, v0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[2:3]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: sub_i32_uniform:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_load_b32 s6, s[4:5], 0x44 nv
+; GFX13W64-NEXT: s_mov_b64 s[2:3], exec
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX13W64-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W64-NEXT: s_cbranch_execz .LBB5_2
+; GFX13W64-NEXT: ; %bb.1:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: s_mul_i32 s2, s6, s2
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB5_2:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: v_mul_lo_u32 v0, s6, v0
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: sub_i32_uniform:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_load_b32 s0, s[4:5], 0x44 nv
+; GFX13W32-NEXT: s_mov_b32 s2, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W32-NEXT: s_cbranch_execz .LBB5_2
+; GFX13W32-NEXT: ; %bb.1:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: s_bcnt1_i32_b32 s2, s2
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: s_mul_i32 s2, s0, s2
+; GFX13W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB5_2:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX13W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: v_mul_lo_u32 v0, s0, v0
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s0, v1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_sub_nc_u32 v0, s0, v0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX13W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.sub(i32 %subitive, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
store i32 %old, ptr addrspace(1) %out
@@ -1978,6 +2319,89 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: sub_i32_varying_vdata:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: s_mov_b32 s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr0
+; GFX13W64-NEXT: .LBB6_1: ; %ComputeLoop
+; GFX13W64-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_readlane_b32 s8, v1, s3
+; GFX13W64-NEXT: v_writelane_b32 v0, s2, s3
+; GFX13W64-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX13W64-NEXT: s_add_co_i32 s2, s2, s8
+; GFX13W64-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[6:7]
+; GFX13W64-NEXT: s_cbranch_scc1 .LBB6_1
+; GFX13W64-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX13W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
+; GFX13W64-NEXT: s_cbranch_execz .LBB6_4
+; GFX13W64-NEXT: ; %bb.3:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB6_4:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: sub_i32_varying_vdata:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s0, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr0
+; GFX13W32-NEXT: .LBB6_1: ; %ComputeLoop
+; GFX13W32-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W32-NEXT: s_ctz_i32_b32 s2, s1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_readlane_b32 s3, v1, s2
+; GFX13W32-NEXT: v_writelane_b32 v0, s0, s2
+; GFX13W32-NEXT: s_lshl_b32 s2, 1, s2
+; GFX13W32-NEXT: s_add_co_i32 s0, s0, s3
+; GFX13W32-NEXT: s_and_not1_b32 s1, s1, s2
+; GFX13W32-NEXT: s_cbranch_scc1 .LBB6_1
+; GFX13W32-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX13W32-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX13W32-NEXT: s_cbranch_execz .LBB6_4
+; GFX13W32-NEXT: ; %bb.3:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: v_mov_b32_e32 v1, s0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_sub_u32 v1, off, s[8:11], null th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB6_4:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_sub_nc_u32 v0, s2, v0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.sub(i32 %lane, ptr addrspace(8) %inout, i32 0, i32 0, i32 0)
@@ -2089,6 +2513,20 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13-LABEL: sub_i32_varying_offset:
+; GFX13: ; %bb.0: ; %entry
+; GFX13-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX13-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX13-NEXT: v_mov_b32_e32 v1, 1
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: buffer_atomic_sub_u32 v1, v0, s[0:3], null offen th:TH_ATOMIC_RETURN
+; GFX13-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13-NEXT: v_mov_b32_e32 v0, 0
+; GFX13-NEXT: s_wait_loadcnt 0x0
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX13-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.sub(i32 1, ptr addrspace(8) %inout, i32 %lane, i32 0, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
index 228f048246a19..3b3f555dea2f1 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
@@ -8,6 +8,8 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX11,GFX11W32 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12W64 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12W32 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W64 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W32 %s
declare i32 @llvm.amdgcn.workitem.id.x()
declare i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add(i32, ptr addrspace(8), i32, i32, i32, i32)
@@ -282,6 +284,66 @@ define amdgpu_kernel void @add_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: add_i32_constant:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_mov_b64 s[2:3], exec
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX13W64-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W64-NEXT: s_cbranch_execz .LBB0_2
+; GFX13W64-NEXT: ; %bb.1:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX13W64-NEXT: v_mov_b32_e32 v2, 0
+; GFX13W64-NEXT: s_mul_i32 s2, s2, 5
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB0_2:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_mad_u32_u24 v0, 5, v0, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: add_i32_constant:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s0, exec_lo
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W32-NEXT: s_cbranch_execz .LBB0_2
+; GFX13W32-NEXT: ; %bb.1:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: s_bcnt1_i32_b32 s1, s1
+; GFX13W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: s_mul_i32 s1, s1, 5
+; GFX13W32-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB0_2:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W32-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W32-NEXT: v_mad_u32_u24 v0, 5, v0, s2
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 0, i32 0)
store i32 %old, ptr addrspace(1) %out
@@ -568,6 +630,68 @@ define amdgpu_kernel void @add_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: v_mov_b32_e32 v1, 0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[2:3]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: add_i32_uniform:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_load_b32 s6, s[4:5], 0x44 nv
+; GFX13W64-NEXT: s_mov_b64 s[2:3], exec
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX13W64-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W64-NEXT: s_cbranch_execz .LBB1_2
+; GFX13W64-NEXT: ; %bb.1:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX13W64-NEXT: v_mov_b32_e32 v2, 0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: s_mul_i32 s2, s6, s2
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB1_2:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W64-NEXT: v_mad_co_u64_u32 v[0:1], null, s6, v0, s[2:3]
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: add_i32_uniform:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_load_b32 s0, s[4:5], 0x44 nv
+; GFX13W32-NEXT: s_mov_b32 s2, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W32-NEXT: s_cbranch_execz .LBB1_2
+; GFX13W32-NEXT: ; %bb.1:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: s_bcnt1_i32_b32 s2, s2
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: s_mul_i32 s2, s0, s2
+; GFX13W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX13W32-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB1_2:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX13W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s4, v1
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_mad_co_u64_u32 v[0:1], null, s0, v0, s[4:5]
+; GFX13W32-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX13W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add(i32 %additive, ptr addrspace(8) %inout, i32 0, i32 0, i32 0, i32 0)
store i32 %old, ptr addrspace(1) %out
@@ -952,6 +1076,90 @@ define amdgpu_kernel void @add_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: add_i32_varying_vdata:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: s_mov_b32 s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr0
+; GFX13W64-NEXT: .LBB2_1: ; %ComputeLoop
+; GFX13W64-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_readlane_b32 s8, v1, s3
+; GFX13W64-NEXT: v_writelane_b32 v0, s2, s3
+; GFX13W64-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX13W64-NEXT: s_add_co_i32 s2, s2, s8
+; GFX13W64-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[6:7]
+; GFX13W64-NEXT: s_cbranch_scc1 .LBB2_1
+; GFX13W64-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX13W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
+; GFX13W64-NEXT: s_cbranch_execz .LBB2_4
+; GFX13W64-NEXT: ; %bb.3:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: v_mov_b32_e32 v2, 0
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB2_4:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_add_nc_u32_e32 v0, s2, v0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: add_i32_varying_vdata:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s0, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr0
+; GFX13W32-NEXT: .LBB2_1: ; %ComputeLoop
+; GFX13W32-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W32-NEXT: s_ctz_i32_b32 s2, s1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_readlane_b32 s3, v1, s2
+; GFX13W32-NEXT: v_writelane_b32 v0, s0, s2
+; GFX13W32-NEXT: s_lshl_b32 s2, 1, s2
+; GFX13W32-NEXT: s_add_co_i32 s0, s0, s3
+; GFX13W32-NEXT: s_and_not1_b32 s1, s1, s2
+; GFX13W32-NEXT: s_cbranch_scc1 .LBB2_1
+; GFX13W32-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX13W32-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX13W32-NEXT: s_cbranch_execz .LBB2_4
+; GFX13W32-NEXT: ; %bb.3:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_add_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB2_4:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, s2, v0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add(i32 %lane, ptr addrspace(8) %inout, i32 0, i32 0, i32 0, i32 0)
@@ -1063,6 +1271,20 @@ define amdgpu_kernel void @add_i32_varying_vindex(ptr addrspace(1) %out, ptr add
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13-LABEL: add_i32_varying_vindex:
+; GFX13: ; %bb.0: ; %entry
+; GFX13-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX13-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX13-NEXT: v_mov_b32_e32 v1, 1
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: buffer_atomic_add_u32 v1, v0, s[0:3], null idxen th:TH_ATOMIC_RETURN
+; GFX13-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13-NEXT: v_mov_b32_e32 v0, 0
+; GFX13-NEXT: s_wait_loadcnt 0x0
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX13-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add(i32 1, ptr addrspace(8) %inout, i32 %lane, i32 0, i32 0, i32 0)
@@ -1191,6 +1413,33 @@ define amdgpu_kernel void @add_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v0, v2, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: add_i32_varying_offset:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX13W64-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W64-NEXT: v_mov_b32_e32 v0, 0
+; GFX13W64-NEXT: v_mov_b32_e32 v2, 1
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_add_u32 v2, v[0:1], s[0:3], null idxen offen th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v0, v2, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: add_i32_varying_offset:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX13W32-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W32-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v2, 1
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_add_u32 v2, v[0:1], s[0:3], null idxen offen th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v0, v2, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add(i32 1, ptr addrspace(8) %inout, i32 0, i32 %lane, i32 0, i32 0)
@@ -1474,6 +1723,67 @@ define amdgpu_kernel void @sub_i32_constant(ptr addrspace(1) %out, ptr addrspace
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: sub_i32_constant:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_mov_b64 s[2:3], exec
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX13W64-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W64-NEXT: s_cbranch_execz .LBB5_2
+; GFX13W64-NEXT: ; %bb.1:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX13W64-NEXT: v_mov_b32_e32 v2, 0
+; GFX13W64-NEXT: s_mul_i32 s2, s2, 5
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB5_2:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mul_u32_u24_e32 v0, 5, v0
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: sub_i32_constant:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s0, exec_lo
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v0, s1, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W32-NEXT: s_cbranch_execz .LBB5_2
+; GFX13W32-NEXT: ; %bb.1:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: s_bcnt1_i32_b32 s1, s1
+; GFX13W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: s_mul_i32 s1, s1, 5
+; GFX13W32-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB5_2:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s0
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W32-NEXT: v_mul_u32_u24_e32 v0, 5, v0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_sub_nc_u32 v0, s2, v0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.sub(i32 5, ptr addrspace(8) %inout, i32 0, i32 0, i32 0, i32 0)
store i32 %old, ptr addrspace(1) %out
@@ -1766,6 +2076,69 @@ define amdgpu_kernel void @sub_i32_uniform(ptr addrspace(1) %out, ptr addrspace(
; GFX12W32-NEXT: v_sub_nc_u32_e32 v0, s0, v0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[2:3]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: sub_i32_uniform:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_load_b32 s6, s[4:5], 0x44 nv
+; GFX13W64-NEXT: s_mov_b64 s[2:3], exec
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX13W64-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W64-NEXT: s_cbranch_execz .LBB6_2
+; GFX13W64-NEXT: ; %bb.1:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX13W64-NEXT: v_mov_b32_e32 v2, 0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: s_mul_i32 s2, s6, s2
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB6_2:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: v_mul_lo_u32 v0, s6, v0
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: sub_i32_uniform:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_load_b32 s0, s[4:5], 0x44 nv
+; GFX13W32-NEXT: s_mov_b32 s2, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_cmpx_eq_u32_e32 0, v0
+; GFX13W32-NEXT: s_cbranch_execz .LBB6_2
+; GFX13W32-NEXT: ; %bb.1:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: s_bcnt1_i32_b32 s2, s2
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: s_mul_i32 s2, s0, s2
+; GFX13W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
+; GFX13W32-NEXT: buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB6_2:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX13W32-NEXT: s_load_b64 s[2:3], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: v_mul_lo_u32 v0, s0, v0
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s0, v1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_sub_nc_u32 v0, s0, v0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[2:3]
+; GFX13W32-NEXT: s_endpgm
entry:
%old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.sub(i32 %subitive, ptr addrspace(8) %inout, i32 0, i32 0, i32 0, i32 0)
store i32 %old, ptr addrspace(1) %out
@@ -2152,6 +2525,90 @@ define amdgpu_kernel void @sub_i32_varying_vdata(ptr addrspace(1) %out, ptr addr
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: sub_i32_varying_vdata:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W64-NEXT: s_mov_b64 s[0:1], exec
+; GFX13W64-NEXT: s_mov_b32 s2, 0
+; GFX13W64-NEXT: ; implicit-def: $vgpr0
+; GFX13W64-NEXT: .LBB7_1: ; %ComputeLoop
+; GFX13W64-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W64-NEXT: s_ctz_i32_b64 s3, s[0:1]
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W64-NEXT: v_readlane_b32 s8, v1, s3
+; GFX13W64-NEXT: v_writelane_b32 v0, s2, s3
+; GFX13W64-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX13W64-NEXT: s_add_co_i32 s2, s2, s8
+; GFX13W64-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[6:7]
+; GFX13W64-NEXT: s_cbranch_scc1 .LBB7_1
+; GFX13W64-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W64-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX13W64-NEXT: v_mbcnt_hi_u32_b32 v1, exec_hi, v1
+; GFX13W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
+; GFX13W64-NEXT: ; implicit-def: $vgpr1
+; GFX13W64-NEXT: s_and_saveexec_b64 s[0:1], vcc
+; GFX13W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX13W64-NEXT: s_xor_b64 s[0:1], exec, s[0:1]
+; GFX13W64-NEXT: s_cbranch_execz .LBB7_4
+; GFX13W64-NEXT: ; %bb.3:
+; GFX13W64-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W64-NEXT: v_mov_b32_e32 v2, 0
+; GFX13W64-NEXT: v_mov_b32_e32 v1, s2
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: .LBB7_4:
+; GFX13W64-NEXT: s_or_b64 exec, exec, s[0:1]
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W64-NEXT: v_mov_b32_e32 v1, 0
+; GFX13W64-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX13W64-NEXT: v_sub_nc_u32_e32 v0, s2, v0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: sub_i32_varying_vdata:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W32-NEXT: s_mov_b32 s1, exec_lo
+; GFX13W32-NEXT: s_mov_b32 s0, 0
+; GFX13W32-NEXT: ; implicit-def: $vgpr0
+; GFX13W32-NEXT: .LBB7_1: ; %ComputeLoop
+; GFX13W32-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX13W32-NEXT: s_ctz_i32_b32 s2, s1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_readlane_b32 s3, v1, s2
+; GFX13W32-NEXT: v_writelane_b32 v0, s0, s2
+; GFX13W32-NEXT: s_lshl_b32 s2, 1, s2
+; GFX13W32-NEXT: s_add_co_i32 s0, s0, s3
+; GFX13W32-NEXT: s_and_not1_b32 s1, s1, s2
+; GFX13W32-NEXT: s_cbranch_scc1 .LBB7_1
+; GFX13W32-NEXT: ; %bb.2: ; %ComputeEnd
+; GFX13W32-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX13W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX13W32-NEXT: ; implicit-def: $vgpr1
+; GFX13W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
+; GFX13W32-NEXT: s_xor_b32 s1, exec_lo, s1
+; GFX13W32-NEXT: s_cbranch_execz .LBB7_4
+; GFX13W32-NEXT: ; %bb.3:
+; GFX13W32-NEXT: s_load_b128 s[8:11], s[4:5], 0x34 nv
+; GFX13W32-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_sub_u32 v1, v2, s[8:11], null idxen th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: .LBB7_4:
+; GFX13W32-NEXT: s_or_b32 exec_lo, exec_lo, s1
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: v_readfirstlane_b32 s2, v1
+; GFX13W32-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX13W32-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_sub_nc_u32 v0, s2, v0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.sub(i32 %lane, ptr addrspace(8) %inout, i32 0, i32 0, i32 0, i32 0)
@@ -2263,6 +2720,20 @@ define amdgpu_kernel void @sub_i32_varying_vindex(ptr addrspace(1) %out, ptr add
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13-LABEL: sub_i32_varying_vindex:
+; GFX13: ; %bb.0: ; %entry
+; GFX13-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX13-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX13-NEXT: v_mov_b32_e32 v1, 1
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: buffer_atomic_sub_u32 v1, v0, s[0:3], null idxen th:TH_ATOMIC_RETURN
+; GFX13-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13-NEXT: v_mov_b32_e32 v0, 0
+; GFX13-NEXT: s_wait_loadcnt 0x0
+; GFX13-NEXT: s_wait_kmcnt 0x0
+; GFX13-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX13-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.sub(i32 1, ptr addrspace(8) %inout, i32 %lane, i32 0, i32 0, i32 0)
@@ -2391,6 +2862,33 @@ define amdgpu_kernel void @sub_i32_varying_offset(ptr addrspace(1) %out, ptr add
; GFX12W32-NEXT: s_wait_kmcnt 0x0
; GFX12W32-NEXT: global_store_b32 v0, v2, s[0:1]
; GFX12W32-NEXT: s_endpgm
+;
+; GFX13W64-LABEL: sub_i32_varying_offset:
+; GFX13W64: ; %bb.0: ; %entry
+; GFX13W64-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX13W64-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W64-NEXT: v_mov_b32_e32 v0, 0
+; GFX13W64-NEXT: v_mov_b32_e32 v2, 1
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: buffer_atomic_sub_u32 v2, v[0:1], s[0:3], null idxen offen th:TH_ATOMIC_RETURN
+; GFX13W64-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W64-NEXT: s_wait_loadcnt 0x0
+; GFX13W64-NEXT: s_wait_kmcnt 0x0
+; GFX13W64-NEXT: global_store_b32 v0, v2, s[0:1]
+; GFX13W64-NEXT: s_endpgm
+;
+; GFX13W32-LABEL: sub_i32_varying_offset:
+; GFX13W32: ; %bb.0: ; %entry
+; GFX13W32-NEXT: s_load_b128 s[0:3], s[4:5], 0x34 nv
+; GFX13W32-NEXT: v_and_b32_e32 v1, 0x3ff, v0
+; GFX13W32-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v2, 1
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: buffer_atomic_sub_u32 v2, v[0:1], s[0:3], null idxen offen th:TH_ATOMIC_RETURN
+; GFX13W32-NEXT: s_load_b64 s[0:1], s[4:5], 0x24 nv
+; GFX13W32-NEXT: s_wait_loadcnt 0x0
+; GFX13W32-NEXT: s_wait_kmcnt 0x0
+; GFX13W32-NEXT: global_store_b32 v0, v2, s[0:1]
+; GFX13W32-NEXT: s_endpgm
entry:
%lane = call i32 @llvm.amdgcn.workitem.id.x()
%old = call i32 @llvm.amdgcn.struct.ptr.buffer.atomic.sub(i32 1, ptr addrspace(8) %inout, i32 0, i32 %lane, i32 0, i32 0)
>From d5aa0d7eba70d745aac972aa141029f4cca87445 Mon Sep 17 00:00:00 2001
From: Mariusz Sikora <mariusz.sikora at amd.com>
Date: Wed, 3 Jun 2026 07:30:56 -0400
Subject: [PATCH 2/2] Drop mattr wavefrontsize32 from RUN line
---
llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll | 2 +-
.../CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll | 4 ++--
.../test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll | 2 +-
llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll | 2 +-
llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll | 2 +-
.../test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll | 2 +-
6 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
index 1768559f26f45..9020564be9d4f 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
@@ -9,7 +9,7 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12W64 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12W32 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W64 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W32 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W32 %s
declare i32 @llvm.amdgcn.workitem.id.x()
declare i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32, ptr addrspace(8), i32, i32, i32 immarg)
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
index 6f74ad3daefd8..6c93567b7820a 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
@@ -27,8 +27,8 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1232,GFX1232-FAKE16,GFX1232_DPP,GFX1232_DPP-FAKE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1364,GFX1364-TRUE16,GFX1364_DPP,GFX1364_DPP-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -mattr=+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1364,GFX1364-FAKE16,GFX1364_DPP,GFX1364_DPP-FAKE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1332,GFX1332-TRUE16,GFX1332_DPP,GFX1332_DPP-TRUE16 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -mattr=+wavefrontsize32 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1332,GFX1332-FAKE16,GFX1332_DPP,GFX1332_DPP-FAKE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+real-true16 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1332,GFX1332-TRUE16,GFX1332_DPP,GFX1332_DPP-TRUE16 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=-real-true16 -mattr=-flat-for-global -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1332,GFX1332-FAKE16,GFX1332_DPP,GFX1332_DPP-FAKE16 %s
declare i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
index 7c336d198a9c2..01352ef04c6a0 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll
@@ -14,7 +14,7 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize64 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1164,GFX1164_DPP %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+wavefrontsize32 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1132,GFX1132_DPP %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize64 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1364,GFX1364_DPP %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize32 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1332,GFX1332_DPP %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP < %s | FileCheck -enable-var-scope -check-prefixes=GFX1332,GFX1332_DPP %s
declare i32 @llvm.amdgcn.workitem.id.x()
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
index 8dcdd6ec38420..829b393a3c47c 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll
@@ -7,7 +7,7 @@
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+wavefrontsize64 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1164 %s
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+wavefrontsize32 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1132 %s
; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1310 -mattr=+wavefrontsize64 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1364 %s
-; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1310 -mattr=+wavefrontsize32 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1332 %s
+; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1310 -mattr=-flat-for-global - -amdgpu-atomic-optimizer-strategy=DPP -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1332 %s
declare i1 @llvm.amdgcn.wqm.vote(i1)
declare i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32, ptr addrspace(8), i32, i32, i32 immarg)
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
index 29938f6c1d46a..f54dfa0bebf4e 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
@@ -9,7 +9,7 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12W64 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12W32 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W64 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W32 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W32 %s
declare i32 @llvm.amdgcn.workitem.id.x()
declare i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add(i32, ptr addrspace(8), i32, i32, i32)
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
index 3b3f555dea2f1..7b1605f8fb538 100644
--- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
+++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
@@ -9,7 +9,7 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12W64 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX12,GFX12W32 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize64 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W64 %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -mattr=+wavefrontsize32 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W32 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1310 -amdgpu-atomic-optimizer-strategy=Iterative < %s | FileCheck -enable-var-scope -check-prefixes=GFX13,GFX13W32 %s
declare i32 @llvm.amdgcn.workitem.id.x()
declare i32 @llvm.amdgcn.struct.ptr.buffer.atomic.add(i32, ptr addrspace(8), i32, i32, i32, i32)
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