[llvm] [AMDGPU] Add post-RA peephole to fuse v_lshlrev_b32 + v_or_b32 into v_lshl_or_b32 (PR #202585)

[Jay Foad via llvm-commits]

jayfoad wrote:

> Existing TableGen patterns for this fusion rarely fire because they rely on conservative SelectionDAG-level analysis. The HasOneUseBinOp predicate rejects cases where the shift has multiple DAG-level uses but only one after register allocation.

These statements sound a little bit like AI-generated overconfidence. Why would register allocation reduce the number of uses? And if was true, surely this would apply to almost every instruction selection pattern that has a one-use check.

> Constant-bus and 

On GFX10+ the constant bus limit allows for 2 of the 3 inputs to be SGPRs, which seems pretty generous. So does this patch give any benefit on GFX10+ or is it really only helpful for GFX9 and earlier?

> divergence checks are similarly conservative without final register classes.

I don't understand what this means about divergence checks being conservative, except perhaps in the rare-ish case that we end up using a VGPR for a uniform value.

https://github.com/llvm/llvm-project/pull/202585