[llvm] 057a1fe - [AMDGPU][GISel] Add register bank legalization rules for amdgcn_raw_buffer_load_async_lds (#201406)

[via llvm-commits]

Author: anjenner
Date: 2026-06-09T12:46:58+01:00
New Revision: 057a1fe9bd5b3c72ea6d65c456d1266fc20d8e33

URL: https://github.com/llvm/llvm-project/commit/057a1fe9bd5b3c72ea6d65c456d1266fc20d8e33
DIFF: https://github.com/llvm/llvm-project/commit/057a1fe9bd5b3c72ea6d65c456d1266fc20d8e33.diff

LOG: [AMDGPU][GISel] Add register bank legalization rules for amdgcn_raw_buffer_load_async_lds (#201406)

Also amdgcn_struct_buffer_load_async_lds,
amdgcn_raw_ptr_buffer_load_async_lds, and
amdgcn_struct_ptr_buffer_load_async_lds.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
    llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 74cd8b1b4b614..41aa5802ad53d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -2132,6 +2132,14 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
   addRulesForIOpcs({amdgcn_raw_buffer_load_lds})
       .Any({{_}, {{}, {IntrId, SgprV4S32, SgprP3, Imm, Vgpr32, Sgpr32}}});
 
+  addRulesForIOpcs({amdgcn_raw_buffer_load_async_lds})
+      .Any({{_}, {{}, {IntrId, SgprV4S32, SgprB32_M0, Imm, Vgpr32, Sgpr32}}});
+
+  addRulesForIOpcs({amdgcn_struct_buffer_load_async_lds})
+      .Any(
+          {{_},
+           {{}, {IntrId, SgprV4S32, SgprB32_M0, Imm, Vgpr32, Vgpr32, Sgpr32}}});
+
   addRulesForIOpcs({amdgcn_struct_buffer_load_lds})
       .Any({{_},
             {{}, {IntrId, SgprV4S32, SgprP3, Imm, Vgpr32, Vgpr32, Sgpr32}}});
@@ -2139,6 +2147,13 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
   addRulesForIOpcs({amdgcn_raw_ptr_buffer_load_lds})
       .Any({{_}, {{}, {IntrId, SgprP8, SgprP3, Imm, Vgpr32, Sgpr32}}});
 
+  addRulesForIOpcs({amdgcn_raw_ptr_buffer_load_async_lds})
+      .Any({{}, {{}, {IntrId, SgprP8, SgprB32_M0, Imm, VgprB32, SgprB32}}});
+
+  addRulesForIOpcs({amdgcn_struct_ptr_buffer_load_async_lds})
+      .Any({{_},
+            {{}, {IntrId, SgprP8, SgprB32_M0, Imm, Vgpr32, Vgpr32, Sgpr32}}});
+
   addRulesForIOpcs({amdgcn_struct_ptr_buffer_load_lds})
       .Any({{_}, {{}, {IntrId, SgprP8, SgprP3, Imm, Vgpr32, Vgpr32, Sgpr32}}});
 

diff  --git a/llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll b/llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
index 184fd61c355f0..f0367445aa6ed 100644
--- a/llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
+++ b/llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
 ; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 -new-reg-bank-select < %s | FileCheck %s
 
 define float @raw.buffer.load(<4 x i32> inreg %rsrc, ptr addrspace(3) inreg %lds) {
 ; CHECK-LABEL: raw.buffer.load:
@@ -113,3 +113,24 @@ main_body:
   %res = load float, ptr addrspace(3) %lds
   ret float %res
 }
+
+; Test divergent LDS pointer - exercises SgprB32_M0 VGPR to SGPR via readfirstlane path
+define float @struct.ptr.buffer.load.vgpr.lds(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) %lds) {
+; CHECK-LABEL: struct.ptr.buffer.load.vgpr.lds:
+; CHECK:       ; %bb.0: ; %main_body
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_readfirstlane_b32 s4, v0
+; CHECK-NEXT:    v_mov_b32_e32 v1, 8
+; CHECK-NEXT:    s_mov_b32 m0, s4
+; CHECK-NEXT:    s_nop 0
+; CHECK-NEXT:    buffer_load_dword v1, s[16:19], 0 idxen lds
+; CHECK-NEXT:    ; asyncmark
+; CHECK-NEXT:    ds_read_b32 v0, v0
+; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+main_body:
+  call void @llvm.amdgcn.struct.ptr.buffer.load.async.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 8, i32 0, i32 0, i32 0, i32 0)
+  call void @llvm.amdgcn.asyncmark()
+  %res = load float, ptr addrspace(3) %lds
+  ret float %res
+}