[llvm] [AArch64][llvm][tablegen] Restrict luti6 assembly (4 regs, 8-bit) to 0 <= Zn <= 7 (PR #200751)

[via llvm-commits]

CarolineConcatto wrote:

@jthackray  I think we can implement the ZPR3_3b as we implemented ZPRMul2_Lo and ZPRMul2_Hi in this PR:

    [LLVM][AArch64] Add register classes for Armv9.6 assembly (#111717)

My first draft it looks like you need:

def ZPR3_Lo    : ZPRClass<0,   7, 3>;
class ZPR3_MinToMaxRegOp<string Suffix, AsmOperandClass C, int  Min, int Max, ElementSizeEnum  Width, RegisterClass RC>
   : ZPRRegOp<Suffix, C, Width, RC> {
 ....
}
def ZPR3AsmOpAny_Lo   : ZPRAsmOperand<"VectorAny_Lo", 0, "3_Lo">;
def ZPR3Any_Lo   : ZPR3_MinToMaxRegOp<"", ZPR3AsmOpAny_Lo, 0, 7, ElementSizeNone, ZPR3_Lo>;

let EncoderMethod = "EncodeRegMul_MinMax<3, 0, 7>",
    DecoderMethod = "DecodeZPRMul_MinMax<3, 0, 7>" in {
  def ZZZ_Any_Lo : RegisterOperand<ZPR3_Lo, "printTypedVectorList<0,0>"> {
    let ParserMatchClass = ZPRVectorListMul<0, 3, "3_Lo">;
  }
} 

This will remove the problem we have with the tablegen and also will be able to have a proper codegen.

https://github.com/llvm/llvm-project/pull/200751