[llvm] [AArch64][TableGen] Define ZA, ZT0 and FPMR memory defvars (PR #154144)

[via llvm-commits]

CarolineConcatto wrote:

@nikic  and @Lukacma 
So, I  think s the change on how IntrReadMem and IntrWriteMem are implemented should belong to another PR, and it should not block this PR.

In my opinion, that implementation detail is unrelated to this PR. Are the reviewers ok with that?

https://github.com/llvm/llvm-project/pull/154144