[llvm] [AMDGPU][GISel] Add register bank legalization rules for amdgcn_raw_buffer_load_async_lds (PR #201406)
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Tue Jun 9 03:25:11 PDT 2026
https://github.com/anjenner updated https://github.com/llvm/llvm-project/pull/201406
>From 8034bd7e7856d986f1b5794417c711026f92818c Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Wed, 3 Jun 2026 12:39:47 -0400
Subject: [PATCH 1/5] [AMDGPU][GISel] Add register bank legalization rules for
amdgcn_raw_buffer_load_async_lds, amdgcn_struct_buffer_load_async_lds,
amdgcn_raw_ptr_buffer_load_async_lds, and
amdgcn_struct_ptr_buffer_load_async_lds.
---
.../Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp | 14 ++++++++++++++
llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll | 2 +-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index e5bab2bbdfa25..d70008d903399 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1906,6 +1906,14 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForIOpcs({amdgcn_raw_buffer_load_lds})
.Any({{_}, {{}, {IntrId, SgprV4S32, SgprP3, Imm, Vgpr32, Sgpr32}}});
+ addRulesForIOpcs({amdgcn_raw_buffer_load_async_lds})
+ .Any({{_}, {{}, {IntrId, SgprV4S32, SgprB32_M0, Imm, Vgpr32, Sgpr32}}});
+
+ addRulesForIOpcs({amdgcn_struct_buffer_load_async_lds})
+ .Any(
+ {{_},
+ {{}, {IntrId, SgprV4S32, SgprB32_M0, Imm, Vgpr32, Vgpr32, Sgpr32}}});
+
addRulesForIOpcs({amdgcn_struct_buffer_load_lds})
.Any({{_},
{{}, {IntrId, SgprV4S32, SgprP3, Imm, Vgpr32, Vgpr32, Sgpr32}}});
@@ -1913,6 +1921,12 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForIOpcs({amdgcn_raw_ptr_buffer_load_lds})
.Any({{_}, {{}, {IntrId, SgprP8, SgprP3, Imm, Vgpr32, Sgpr32}}});
+ addRulesForIOpcs({amdgcn_raw_ptr_buffer_load_async_lds})
+ .Any({{}, {{}, {IntrId, SgprP8, SgprB32_M0, Imm, VgprB32, SgprB32}}});
+
+ addRulesForIOpcs({amdgcn_struct_ptr_buffer_load_async_lds})
+ .Any({{_}, {{}, {IntrId, SgprP8, SgprP3, Imm, Vgpr32, Vgpr32, Sgpr32}}});
+
addRulesForIOpcs({amdgcn_struct_ptr_buffer_load_lds})
.Any({{_}, {{}, {IntrId, SgprP8, SgprP3, Imm, Vgpr32, Vgpr32, Sgpr32}}});
diff --git a/llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll b/llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
index 184fd61c355f0..129b4186a3fb0 100644
--- a/llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
+++ b/llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
+; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 -new-reg-bank-select < %s | FileCheck %s
define float @raw.buffer.load(<4 x i32> inreg %rsrc, ptr addrspace(3) inreg %lds) {
; CHECK-LABEL: raw.buffer.load:
>From 7d5aa41fe8e9d7a8a87ddbb6e3a532e75c5beeef Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Thu, 4 Jun 2026 05:13:00 -0400
Subject: [PATCH 2/5] Fix formatting.
---
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index d70008d903399..fde656e7c15c9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1911,8 +1911,8 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForIOpcs({amdgcn_struct_buffer_load_async_lds})
.Any(
- {{_},
- {{}, {IntrId, SgprV4S32, SgprB32_M0, Imm, Vgpr32, Vgpr32, Sgpr32}}});
+ {{_},
+ {{}, {IntrId, SgprV4S32, SgprB32_M0, Imm, Vgpr32, Vgpr32, Sgpr32}}});
addRulesForIOpcs({amdgcn_struct_buffer_load_lds})
.Any({{_},
>From 8f4b607848d21aa153559617c37866058340ff69 Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Thu, 4 Jun 2026 06:09:44 -0400
Subject: [PATCH 3/5] Use SgprB32_M0 instead of SgprP3 for
amdgcn_struct_ptr_buffer_load_async_lds.
---
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index fde656e7c15c9..8baac5f465d6b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1925,7 +1925,7 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{}, {{}, {IntrId, SgprP8, SgprB32_M0, Imm, VgprB32, SgprB32}}});
addRulesForIOpcs({amdgcn_struct_ptr_buffer_load_async_lds})
- .Any({{_}, {{}, {IntrId, SgprP8, SgprP3, Imm, Vgpr32, Vgpr32, Sgpr32}}});
+ .Any({{_}, {{}, {IntrId, SgprP8, SgprB32_M0, Imm, Vgpr32, Vgpr32, Sgpr32}}});
addRulesForIOpcs({amdgcn_struct_ptr_buffer_load_lds})
.Any({{_}, {{}, {IntrId, SgprP8, SgprP3, Imm, Vgpr32, Vgpr32, Sgpr32}}});
>From 70b831858658c460809972a23818f6daf4369701 Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Tue, 9 Jun 2026 05:54:19 -0400
Subject: [PATCH 4/5] Add test for SgprB32_M0, vgpr to sgpr via readfirstlane
path.
---
.../test/CodeGen/AMDGPU/async-buffer-loads.ll | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll b/llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
index 129b4186a3fb0..f0367445aa6ed 100644
--- a/llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
+++ b/llvm/test/CodeGen/AMDGPU/async-buffer-loads.ll
@@ -113,3 +113,24 @@ main_body:
%res = load float, ptr addrspace(3) %lds
ret float %res
}
+
+; Test divergent LDS pointer - exercises SgprB32_M0 VGPR to SGPR via readfirstlane path
+define float @struct.ptr.buffer.load.vgpr.lds(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) %lds) {
+; CHECK-LABEL: struct.ptr.buffer.load.vgpr.lds:
+; CHECK: ; %bb.0: ; %main_body
+; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT: v_readfirstlane_b32 s4, v0
+; CHECK-NEXT: v_mov_b32_e32 v1, 8
+; CHECK-NEXT: s_mov_b32 m0, s4
+; CHECK-NEXT: s_nop 0
+; CHECK-NEXT: buffer_load_dword v1, s[16:19], 0 idxen lds
+; CHECK-NEXT: ; asyncmark
+; CHECK-NEXT: ds_read_b32 v0, v0
+; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+main_body:
+ call void @llvm.amdgcn.struct.ptr.buffer.load.async.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 8, i32 0, i32 0, i32 0, i32 0)
+ call void @llvm.amdgcn.asyncmark()
+ %res = load float, ptr addrspace(3) %lds
+ ret float %res
+}
>From 2bd18a5aa731edf17c9dc1e3db8dd819037df757 Mon Sep 17 00:00:00 2001
From: Andrew Jenner <Andrew.Jenner at amd.com>
Date: Tue, 9 Jun 2026 06:32:44 -0400
Subject: [PATCH 5/5] Fix formatting.
---
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 8baac5f465d6b..e57cc4fe531d5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1925,7 +1925,8 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Any({{}, {{}, {IntrId, SgprP8, SgprB32_M0, Imm, VgprB32, SgprB32}}});
addRulesForIOpcs({amdgcn_struct_ptr_buffer_load_async_lds})
- .Any({{_}, {{}, {IntrId, SgprP8, SgprB32_M0, Imm, Vgpr32, Vgpr32, Sgpr32}}});
+ .Any({{_},
+ {{}, {IntrId, SgprP8, SgprB32_M0, Imm, Vgpr32, Vgpr32, Sgpr32}}});
addRulesForIOpcs({amdgcn_struct_ptr_buffer_load_lds})
.Any({{_}, {{}, {IntrId, SgprP8, SgprP3, Imm, Vgpr32, Vgpr32, Sgpr32}}});
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