[llvm] [AMDGPU][NFC] New tests for uncovered cases in SIInstrInfo.cpp (PR #200414)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 9 03:22:50 PDT 2026
https://github.com/ambergorzynski updated https://github.com/llvm/llvm-project/pull/200414
>From 84d4587b784014ace546d23beaf6ed8d703452d3 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Fri, 29 May 2026 09:06:22 -0500
Subject: [PATCH 1/7] [AMDGPU][NFC] Add aborts to demonstrate tests
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index ef9d184555bd6..c03f37d44bb9a 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6196,16 +6196,16 @@ unsigned SIInstrInfo::getVALUOp(unsigned Opc) const {
case AMDGPU::S_FMAAK_F32: return AMDGPU::V_FMAAK_F32;
case AMDGPU::S_CMP_LT_F32: return AMDGPU::V_CMP_LT_F32_e64;
case AMDGPU::S_CMP_EQ_F32: return AMDGPU::V_CMP_EQ_F32_e64;
- case AMDGPU::S_CMP_LE_F32: return AMDGPU::V_CMP_LE_F32_e64;
- case AMDGPU::S_CMP_GT_F32: return AMDGPU::V_CMP_GT_F32_e64;
+ case AMDGPU::S_CMP_LE_F32: {abort(); return AMDGPU::V_CMP_LE_F32_e64;}
+ case AMDGPU::S_CMP_GT_F32: {abort(); return AMDGPU::V_CMP_GT_F32_e64;}
case AMDGPU::S_CMP_LG_F32: return AMDGPU::V_CMP_LG_F32_e64;
case AMDGPU::S_CMP_GE_F32: return AMDGPU::V_CMP_GE_F32_e64;
case AMDGPU::S_CMP_O_F32: return AMDGPU::V_CMP_O_F32_e64;
case AMDGPU::S_CMP_U_F32: return AMDGPU::V_CMP_U_F32_e64;
case AMDGPU::S_CMP_NGE_F32: return AMDGPU::V_CMP_NGE_F32_e64;
- case AMDGPU::S_CMP_NLG_F32: return AMDGPU::V_CMP_NLG_F32_e64;
+ case AMDGPU::S_CMP_NLG_F32: {abort(); return AMDGPU::V_CMP_NLG_F32_e64;}
case AMDGPU::S_CMP_NGT_F32: return AMDGPU::V_CMP_NGT_F32_e64;
- case AMDGPU::S_CMP_NLE_F32: return AMDGPU::V_CMP_NLE_F32_e64;
+ case AMDGPU::S_CMP_NLE_F32: {abort(); return AMDGPU::V_CMP_NLE_F32_e64;}
case AMDGPU::S_CMP_NEQ_F32: return AMDGPU::V_CMP_NEQ_F32_e64;
case AMDGPU::S_CMP_NLT_F32: return AMDGPU::V_CMP_NLT_F32_e64;
case AMDGPU::S_CMP_LT_F16:
>From 3fd9c535c4581c36be8750bb929a009197a2d772 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Fri, 29 May 2026 09:07:43 -0500
Subject: [PATCH 2/7] [AMDGPU][NFC] New tests targeting SIInstrInfo.cpp
---
llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll | 246 ++++++++++++++++++++
1 file changed, 246 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
new file mode 100644
index 0000000000000..d9c3b781beef1
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
@@ -0,0 +1,246 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1201 < %s | FileCheck -check-prefix=CHECK %s
+
+define <8 x i1> @siinstrinfo_vector_f32_ole() {
+; CHECK-LABEL: siinstrinfo_vector_f32_ole:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-NEXT: s_clause 0x1
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-NEXT: s_wait_loadcnt 0x1
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v4
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v5
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v6
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v7
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <8 x float>, ptr addrspace(1) null, align 32
+ %C = fcmp ole <8 x float> %LGV, zeroinitializer
+ ret <8 x i1> %C
+}
+
+define <4 x i1> @siinstrinfo_vector_f32_ogt() {
+; CHECK-LABEL: siinstrinfo_vector_f32_ogt:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <4 x float>, ptr addrspace(1) null, align 16
+ %C = fcmp ogt <4 x float> %LGV, zeroinitializer
+ ret <4 x i1> %C
+}
+
+define <32 x i1> @siinstrinfo_vector_f32_ueq() {
+; CHECK-LABEL: siinstrinfo_vector_f32_ueq:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
+; CHECK-NEXT: s_clause 0x1
+; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-NEXT: global_load_b128 v[8:11], v[8:9], off
+; CHECK-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
+; CHECK-NEXT: global_load_b128 v[12:15], v[12:13], off
+; CHECK-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
+; CHECK-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
+; CHECK-NEXT: global_load_b128 v[16:19], v[16:17], off
+; CHECK-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
+; CHECK-NEXT: s_clause 0x2
+; CHECK-NEXT: global_load_b128 v[20:23], v[20:21], off
+; CHECK-NEXT: global_load_b128 v[24:27], v[24:25], off
+; CHECK-NEXT: global_load_b128 v[28:31], v[28:29], off
+; CHECK-NEXT: s_wait_loadcnt 0x7
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x6
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v4
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v5
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v6
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v7
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x5
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v8
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v9
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v10
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v11
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x4
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v12
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v13
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v14
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v15
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x3
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v16
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v17
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v18
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v19
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x2
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v20
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v21
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v22
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v23
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x1
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v24
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v25
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v26
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v26, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v27
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v27, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v28
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v28, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v29
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v29, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v30
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v30, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v31
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v31, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <32 x float>, ptr addrspace(1) null, align 128
+ %C = fcmp ueq <32 x float> %LGV, zeroinitializer
+ ret <32 x i1> %C
+}
+
+define <4 x i1> @siinstrinfo_vector_f32_ugt() {
+; CHECK-LABEL: siinstrinfo_vector_f32_ugt:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV1 = load <4 x float>, ptr addrspace(1) null, align 16
+ %C = fcmp ugt <4 x float> %LGV1, zeroinitializer
+ ret <4 x i1> %C
+}
+
>From 49b70687f25bb2547c17977cbca8f2328963faac Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Mon, 8 Jun 2026 09:47:38 -0500
Subject: [PATCH 3/7] [AMDGPU][NFC] Shorten test names
---
llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
index d9c3b781beef1..50cb6127041d6 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn -mcpu=gfx1201 < %s | FileCheck -check-prefix=CHECK %s
-define <8 x i1> @siinstrinfo_vector_f32_ole() {
-; CHECK-LABEL: siinstrinfo_vector_f32_ole:
+define <8 x i1> @vector_f32_ole() {
+; CHECK-LABEL: vector_f32_ole:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_expcnt 0x0
@@ -47,8 +47,8 @@ entry:
ret <8 x i1> %C
}
-define <4 x i1> @siinstrinfo_vector_f32_ogt() {
-; CHECK-LABEL: siinstrinfo_vector_f32_ogt:
+define <4 x i1> @vector_f32_ogt() {
+; CHECK-LABEL: vector_f32_ogt:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_expcnt 0x0
@@ -77,8 +77,8 @@ entry:
ret <4 x i1> %C
}
-define <32 x i1> @siinstrinfo_vector_f32_ueq() {
-; CHECK-LABEL: siinstrinfo_vector_f32_ueq:
+define <32 x i1> @vector_f32_ueq() {
+; CHECK-LABEL: vector_f32_ueq:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_expcnt 0x0
@@ -214,8 +214,8 @@ entry:
ret <32 x i1> %C
}
-define <4 x i1> @siinstrinfo_vector_f32_ugt() {
-; CHECK-LABEL: siinstrinfo_vector_f32_ugt:
+define <4 x i1> @vector_f32_ugt() {
+; CHECK-LABEL: vector_f32_ugt:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
; CHECK-NEXT: s_wait_expcnt 0x0
>From ccc4b6e013817783a8c37cf657fe80e13219ca91 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Mon, 8 Jun 2026 12:18:21 -0500
Subject: [PATCH 4/7] [AMDGPU][NFC] Update test checks
---
llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll | 33 ++++++++++++---------
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
index 50cb6127041d6..bf7d66d5d83c3 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
@@ -9,8 +9,9 @@ define <8 x i1> @vector_f32_ole() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 16
+; CHECK-NEXT: v_mov_b32_e32 v5, 0
; CHECK-NEXT: s_clause 0x1
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
@@ -55,7 +56,8 @@ define <4 x i1> @vector_f32_ogt() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: s_wait_loadcnt 0x0
; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
@@ -85,22 +87,24 @@ define <32 x i1> @vector_f32_ueq() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
-; CHECK-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 16
+; CHECK-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v8, 32
+; CHECK-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v12, 48
; CHECK-NEXT: s_clause 0x1
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-NEXT: v_mov_b32_e32 v13, 0
; CHECK-NEXT: global_load_b128 v[8:11], v[8:9], off
-; CHECK-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
+; CHECK-NEXT: v_mov_b32_e32 v16, 64
+; CHECK-NEXT: v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v20, 0x50
; CHECK-NEXT: global_load_b128 v[12:15], v[12:13], off
-; CHECK-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
-; CHECK-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
+; CHECK-NEXT: v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v24, 0x60
; CHECK-NEXT: global_load_b128 v[16:19], v[16:17], off
-; CHECK-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
-; CHECK-NEXT: s_clause 0x2
+; CHECK-NEXT: v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v28, 0x70
; CHECK-NEXT: global_load_b128 v[20:23], v[20:21], off
+; CHECK-NEXT: v_mov_b32_e32 v29, 0
+; CHECK-NEXT: s_clause 0x1
; CHECK-NEXT: global_load_b128 v[24:27], v[24:25], off
; CHECK-NEXT: global_load_b128 v[28:31], v[28:29], off
; CHECK-NEXT: s_wait_loadcnt 0x7
@@ -222,7 +226,8 @@ define <4 x i1> @vector_f32_ugt() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-NEXT: v_mov_b32_e32 v1, 0
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: s_wait_loadcnt 0x0
; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
>From 777eeb3f2c2d063ce50a1505368796a1c853c611 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Mon, 8 Jun 2026 12:19:44 -0500
Subject: [PATCH 5/7] [AMDGPU][NFC] Remove aborts
---
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c03f37d44bb9a..ef9d184555bd6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6196,16 +6196,16 @@ unsigned SIInstrInfo::getVALUOp(unsigned Opc) const {
case AMDGPU::S_FMAAK_F32: return AMDGPU::V_FMAAK_F32;
case AMDGPU::S_CMP_LT_F32: return AMDGPU::V_CMP_LT_F32_e64;
case AMDGPU::S_CMP_EQ_F32: return AMDGPU::V_CMP_EQ_F32_e64;
- case AMDGPU::S_CMP_LE_F32: {abort(); return AMDGPU::V_CMP_LE_F32_e64;}
- case AMDGPU::S_CMP_GT_F32: {abort(); return AMDGPU::V_CMP_GT_F32_e64;}
+ case AMDGPU::S_CMP_LE_F32: return AMDGPU::V_CMP_LE_F32_e64;
+ case AMDGPU::S_CMP_GT_F32: return AMDGPU::V_CMP_GT_F32_e64;
case AMDGPU::S_CMP_LG_F32: return AMDGPU::V_CMP_LG_F32_e64;
case AMDGPU::S_CMP_GE_F32: return AMDGPU::V_CMP_GE_F32_e64;
case AMDGPU::S_CMP_O_F32: return AMDGPU::V_CMP_O_F32_e64;
case AMDGPU::S_CMP_U_F32: return AMDGPU::V_CMP_U_F32_e64;
case AMDGPU::S_CMP_NGE_F32: return AMDGPU::V_CMP_NGE_F32_e64;
- case AMDGPU::S_CMP_NLG_F32: {abort(); return AMDGPU::V_CMP_NLG_F32_e64;}
+ case AMDGPU::S_CMP_NLG_F32: return AMDGPU::V_CMP_NLG_F32_e64;
case AMDGPU::S_CMP_NGT_F32: return AMDGPU::V_CMP_NGT_F32_e64;
- case AMDGPU::S_CMP_NLE_F32: {abort(); return AMDGPU::V_CMP_NLE_F32_e64;}
+ case AMDGPU::S_CMP_NLE_F32: return AMDGPU::V_CMP_NLE_F32_e64;
case AMDGPU::S_CMP_NEQ_F32: return AMDGPU::V_CMP_NEQ_F32_e64;
case AMDGPU::S_CMP_NLT_F32: return AMDGPU::V_CMP_NLT_F32_e64;
case AMDGPU::S_CMP_LT_F16:
>From 736cf342ae3c55b70ef2ca9195afe771f19b08ce Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Tue, 9 Jun 2026 03:21:21 -0500
Subject: [PATCH 6/7] [AMDGPU][NFC] Update autogenerated test checks
---
llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll | 33 +++++++++------------
1 file changed, 14 insertions(+), 19 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
index bf7d66d5d83c3..50cb6127041d6 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
@@ -9,9 +9,8 @@ define <8 x i1> @vector_f32_ole() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 16
-; CHECK-NEXT: v_mov_b32_e32 v5, 0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
; CHECK-NEXT: s_clause 0x1
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
@@ -56,8 +55,7 @@ define <4 x i1> @vector_f32_ogt() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: s_wait_loadcnt 0x0
; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
@@ -87,24 +85,22 @@ define <32 x i1> @vector_f32_ueq() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 16
-; CHECK-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v8, 32
-; CHECK-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v12, 48
-; CHECK-NEXT: s_clause 0x1
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
+; CHECK-NEXT: s_clause 0x1
; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
-; CHECK-NEXT: v_mov_b32_e32 v13, 0
; CHECK-NEXT: global_load_b128 v[8:11], v[8:9], off
-; CHECK-NEXT: v_mov_b32_e32 v16, 64
-; CHECK-NEXT: v_dual_mov_b32 v17, 0 :: v_dual_mov_b32 v20, 0x50
+; CHECK-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
; CHECK-NEXT: global_load_b128 v[12:15], v[12:13], off
-; CHECK-NEXT: v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v24, 0x60
+; CHECK-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
+; CHECK-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
; CHECK-NEXT: global_load_b128 v[16:19], v[16:17], off
-; CHECK-NEXT: v_dual_mov_b32 v25, 0 :: v_dual_mov_b32 v28, 0x70
+; CHECK-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
+; CHECK-NEXT: s_clause 0x2
; CHECK-NEXT: global_load_b128 v[20:23], v[20:21], off
-; CHECK-NEXT: v_mov_b32_e32 v29, 0
-; CHECK-NEXT: s_clause 0x1
; CHECK-NEXT: global_load_b128 v[24:27], v[24:25], off
; CHECK-NEXT: global_load_b128 v[28:31], v[28:29], off
; CHECK-NEXT: s_wait_loadcnt 0x7
@@ -226,8 +222,7 @@ define <4 x i1> @vector_f32_ugt() {
; CHECK-NEXT: s_wait_samplecnt 0x0
; CHECK-NEXT: s_wait_bvhcnt 0x0
; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_mov_b32_e32 v0, 0
-; CHECK-NEXT: v_mov_b32_e32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
; CHECK-NEXT: s_wait_loadcnt 0x0
; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
>From adc6f69d6b85a22c7ee0ad3c533dd2b0a1f24b98 Mon Sep 17 00:00:00 2001
From: agorzyns <amber.gorzynski at amd.com>
Date: Tue, 9 Jun 2026 05:16:17 -0500
Subject: [PATCH 7/7] [AMDGPU][NFC] Added new tests to existing fcmp test file
---
llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll | 246 --------------
llvm/test/CodeGen/AMDGPU/fcmp.ll | 343 +++++++++++++++++++-
2 files changed, 336 insertions(+), 253 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
deleted file mode 100644
index 50cb6127041d6..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
+++ /dev/null
@@ -1,246 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1201 < %s | FileCheck -check-prefix=CHECK %s
-
-define <8 x i1> @vector_f32_ole() {
-; CHECK-LABEL: vector_f32_ole:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-NEXT: s_wait_expcnt 0x0
-; CHECK-NEXT: s_wait_samplecnt 0x0
-; CHECK-NEXT: s_wait_bvhcnt 0x0
-; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
-; CHECK-NEXT: s_clause 0x1
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
-; CHECK-NEXT: s_wait_loadcnt 0x1
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v2
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v3
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x0
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v4
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v5
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v6
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v7
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; CHECK-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV = load <8 x float>, ptr addrspace(1) null, align 32
- %C = fcmp ole <8 x float> %LGV, zeroinitializer
- ret <8 x i1> %C
-}
-
-define <4 x i1> @vector_f32_ogt() {
-; CHECK-LABEL: vector_f32_ogt:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-NEXT: s_wait_expcnt 0x0
-; CHECK-NEXT: s_wait_samplecnt 0x0
-; CHECK-NEXT: s_wait_bvhcnt 0x0
-; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: s_wait_loadcnt 0x0
-; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v2
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v3
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV = load <4 x float>, ptr addrspace(1) null, align 16
- %C = fcmp ogt <4 x float> %LGV, zeroinitializer
- ret <4 x i1> %C
-}
-
-define <32 x i1> @vector_f32_ueq() {
-; CHECK-LABEL: vector_f32_ueq:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-NEXT: s_wait_expcnt 0x0
-; CHECK-NEXT: s_wait_samplecnt 0x0
-; CHECK-NEXT: s_wait_bvhcnt 0x0
-; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
-; CHECK-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
-; CHECK-NEXT: s_clause 0x1
-; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
-; CHECK-NEXT: global_load_b128 v[8:11], v[8:9], off
-; CHECK-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
-; CHECK-NEXT: global_load_b128 v[12:15], v[12:13], off
-; CHECK-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
-; CHECK-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
-; CHECK-NEXT: global_load_b128 v[16:19], v[16:17], off
-; CHECK-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
-; CHECK-NEXT: s_clause 0x2
-; CHECK-NEXT: global_load_b128 v[20:23], v[20:21], off
-; CHECK-NEXT: global_load_b128 v[24:27], v[24:25], off
-; CHECK-NEXT: global_load_b128 v[28:31], v[28:29], off
-; CHECK-NEXT: s_wait_loadcnt 0x7
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v2
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v3
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x6
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v4
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v5
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v6
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v7
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x5
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v8
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v9
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v10
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v11
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x4
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v12
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v13
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v14
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v15
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x3
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v16
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v17
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v18
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v19
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x2
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v20
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v21
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v22
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v23
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x1
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v24
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v25
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v26
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v26, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v27
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v27, 0, 1, vcc_lo
-; CHECK-NEXT: s_wait_loadcnt 0x0
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v28
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v28, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v29
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v29, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v30
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v30, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v31
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v31, 0, 1, vcc_lo
-; CHECK-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV = load <32 x float>, ptr addrspace(1) null, align 128
- %C = fcmp ueq <32 x float> %LGV, zeroinitializer
- ret <32 x i1> %C
-}
-
-define <4 x i1> @vector_f32_ugt() {
-; CHECK-LABEL: vector_f32_ugt:
-; CHECK: ; %bb.0: ; %entry
-; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
-; CHECK-NEXT: s_wait_expcnt 0x0
-; CHECK-NEXT: s_wait_samplecnt 0x0
-; CHECK-NEXT: s_wait_bvhcnt 0x0
-; CHECK-NEXT: s_wait_kmcnt 0x0
-; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
-; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
-; CHECK-NEXT: s_wait_loadcnt 0x0
-; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v1
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v2
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v3
-; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
-; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
-; CHECK-NEXT: s_setpc_b64 s[30:31]
-entry:
- %LGV1 = load <4 x float>, ptr addrspace(1) null, align 16
- %C = fcmp ugt <4 x float> %LGV1, zeroinitializer
- ret <4 x i1> %C
-}
-
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp.ll b/llvm/test/CodeGen/AMDGPU/fcmp.ll
index 5f6d5d22c61a9..ad03591ac084f 100644
--- a/llvm/test/CodeGen/AMDGPU/fcmp.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcmp.ll
@@ -1,9 +1,38 @@
-; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s
-
-; CHECK: {{^}}fcmp_sext:
-; CHECK: SETE_DX10 T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck -check-prefix=CHECK-REDWOOD %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1201 < %s | FileCheck -check-prefix=CHECK-GFX1201 %s
define amdgpu_kernel void @fcmp_sext(ptr addrspace(1) %out, ptr addrspace(1) %in) {
+; CHECK-REDWOOD-LABEL: fcmp_sext:
+; CHECK-REDWOOD: ; %bb.0: ; %entry
+; CHECK-REDWOOD-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; CHECK-REDWOOD-NEXT: TEX 0 @6
+; CHECK-REDWOOD-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; CHECK-REDWOOD-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; CHECK-REDWOOD-NEXT: CF_END
+; CHECK-REDWOOD-NEXT: PAD
+; CHECK-REDWOOD-NEXT: Fetch clause starting at 6:
+; CHECK-REDWOOD-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
+; CHECK-REDWOOD-NEXT: ALU clause starting at 8:
+; CHECK-REDWOOD-NEXT: MOV * T0.X, KC0[2].Z,
+; CHECK-REDWOOD-NEXT: ALU clause starting at 9:
+; CHECK-REDWOOD-NEXT: SETE_DX10 T0.X, T0.X, T0.Y,
+; CHECK-REDWOOD-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; CHECK-REDWOOD-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; CHECK-GFX1201-LABEL: fcmp_sext:
+; CHECK-GFX1201: ; %bb.0: ; %entry
+; CHECK-GFX1201-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; CHECK-GFX1201-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: s_cmp_eq_f32 s2, s3
+; CHECK-GFX1201-NEXT: s_cselect_b32 s2, -1, 0
+; CHECK-GFX1201-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, -1, s2
+; CHECK-GFX1201-NEXT: global_store_b32 v0, v1, s[0:1]
+; CHECK-GFX1201-NEXT: s_endpgm
entry:
%0 = load float, ptr addrspace(1) %in
%arrayidx1 = getelementptr inbounds float, ptr addrspace(1) %in, i32 1
@@ -18,11 +47,46 @@ entry:
; SET*_DX10 instruction. Previously we were lowering this to:
; SET* + FP_TO_SINT
-; CHECK: {{^}}fcmp_br:
-; CHECK: SET{{[N]*}}E_DX10 * T{{[0-9]+\.[XYZW],}}
-; CHECK-NEXT: {{[0-9]+\(5.0}}
define amdgpu_kernel void @fcmp_br(ptr addrspace(1) %out, float %in) {
+; CHECK-REDWOOD-LABEL: fcmp_br:
+; CHECK-REDWOOD: ; %bb.0: ; %entry
+; CHECK-REDWOOD-NEXT: ALU_PUSH_BEFORE 4, @8, KC0[CB0:0-32], KC1[]
+; CHECK-REDWOOD-NEXT: JUMP @5 POP:1
+; CHECK-REDWOOD-NEXT: ALU 3, @13, KC0[], KC1[]
+; CHECK-REDWOOD-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 0
+; CHECK-REDWOOD-NEXT: POP @5 POP:1
+; CHECK-REDWOOD-NEXT: ALU 1, @17, KC0[], KC1[]
+; CHECK-REDWOOD-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; CHECK-REDWOOD-NEXT: CF_END
+; CHECK-REDWOOD-NEXT: ALU clause starting at 8:
+; CHECK-REDWOOD-NEXT: MOV T0.X, literal.x,
+; CHECK-REDWOOD-NEXT: MOV T0.W, KC0[2].Y,
+; CHECK-REDWOOD-NEXT: SETNE_DX10 * T1.W, KC0[2].Z, literal.y,
+; CHECK-REDWOOD-NEXT: 0(0.000000e+00), 1084227584(5.000000e+00)
+; CHECK-REDWOOD-NEXT: PRED_SETE_INT * ExecMask,PredicateBit (MASKED), PS, 0.0,
+; CHECK-REDWOOD-NEXT: ALU clause starting at 13:
+; CHECK-REDWOOD-NEXT: ADD_INT * T1.W, T0.W, literal.x,
+; CHECK-REDWOOD-NEXT: 4(5.605194e-45), 0(0.000000e+00)
+; CHECK-REDWOOD-NEXT: LSHR * T1.X, PV.W, literal.x,
+; CHECK-REDWOOD-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; CHECK-REDWOOD-NEXT: ALU clause starting at 17:
+; CHECK-REDWOOD-NEXT: LSHR * T1.X, T0.W, literal.x,
+; CHECK-REDWOOD-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; CHECK-GFX1201-LABEL: fcmp_br:
+; CHECK-GFX1201: ; %bb.0: ; %entry
+; CHECK-GFX1201-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: s_cmp_neq_f32 s2, 0x40a00000
+; CHECK-GFX1201-NEXT: s_cbranch_scc1 .LBB1_2
+; CHECK-GFX1201-NEXT: ; %bb.1: ; %IF
+; CHECK-GFX1201-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-GFX1201-NEXT: global_store_b32 v0, v0, s[0:1] offset:4
+; CHECK-GFX1201-NEXT: .LBB1_2: ; %ENDIF
+; CHECK-GFX1201-NEXT: v_mov_b32_e32 v0, 0
+; CHECK-GFX1201-NEXT: global_store_b32 v0, v0, s[0:1]
+; CHECK-GFX1201-NEXT: s_endpgm
entry:
%0 = fcmp oeq float %in, 5.0
br i1 %0, label %IF, label %ENDIF
@@ -36,3 +100,268 @@ ENDIF:
store i32 0, ptr addrspace(1) %out
ret void
}
+
+
+define <8 x i1> @vector_f32_ole() {
+; CHECK-REDWOOD-LABEL: vector_f32_ole:
+; CHECK-REDWOOD: ; %bb.0: ; %entry
+; CHECK-REDWOOD-NEXT: CF_END
+; CHECK-REDWOOD-NEXT: PAD
+;
+; CHECK-GFX1201-LABEL: vector_f32_ole:
+; CHECK-GFX1201: ; %bb.0: ; %entry
+; CHECK-GFX1201-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_expcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_samplecnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_bvhcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-GFX1201-NEXT: s_clause 0x1
+; CHECK-GFX1201-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-GFX1201-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x1
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v0
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v2
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v3
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x0
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v4
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v5
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v6
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v7
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <8 x float>, ptr addrspace(1) null, align 32
+ %C = fcmp ole <8 x float> %LGV, zeroinitializer
+ ret <8 x i1> %C
+}
+
+define <4 x i1> @vector_f32_ogt() {
+; CHECK-REDWOOD-LABEL: vector_f32_ogt:
+; CHECK-REDWOOD: ; %bb.0: ; %entry
+; CHECK-REDWOOD-NEXT: CF_END
+; CHECK-REDWOOD-NEXT: PAD
+;
+; CHECK-GFX1201-LABEL: vector_f32_ogt:
+; CHECK-GFX1201: ; %bb.0: ; %entry
+; CHECK-GFX1201-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_expcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_samplecnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_bvhcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-GFX1201-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x0
+; CHECK-GFX1201-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v2
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v3
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <4 x float>, ptr addrspace(1) null, align 16
+ %C = fcmp ogt <4 x float> %LGV, zeroinitializer
+ ret <4 x i1> %C
+}
+
+define <32 x i1> @vector_f32_ueq() {
+; CHECK-REDWOOD-LABEL: vector_f32_ueq:
+; CHECK-REDWOOD: ; %bb.0: ; %entry
+; CHECK-REDWOOD-NEXT: CF_END
+; CHECK-REDWOOD-NEXT: PAD
+;
+; CHECK-GFX1201-LABEL: vector_f32_ueq:
+; CHECK-GFX1201: ; %bb.0: ; %entry
+; CHECK-GFX1201-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_expcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_samplecnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_bvhcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
+; CHECK-GFX1201-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
+; CHECK-GFX1201-NEXT: s_clause 0x1
+; CHECK-GFX1201-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-GFX1201-NEXT: global_load_b128 v[8:11], v[8:9], off
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
+; CHECK-GFX1201-NEXT: global_load_b128 v[12:15], v[12:13], off
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
+; CHECK-GFX1201-NEXT: global_load_b128 v[16:19], v[16:17], off
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
+; CHECK-GFX1201-NEXT: s_clause 0x2
+; CHECK-GFX1201-NEXT: global_load_b128 v[20:23], v[20:21], off
+; CHECK-GFX1201-NEXT: global_load_b128 v[24:27], v[24:25], off
+; CHECK-GFX1201-NEXT: global_load_b128 v[28:31], v[28:29], off
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x7
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v1
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v2
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v3
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x6
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v4
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v5
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v6
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v7
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x5
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v8
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v9
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v10
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v11
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x4
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v12
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v13
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v14
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v15
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x3
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v16
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v17
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v18
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v19
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x2
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v20
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v21
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v22
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v23
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x1
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v24
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v25
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v26
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v26, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v27
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v27, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x0
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v28
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v28, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v29
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v29, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v30
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v30, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v31
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v31, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <32 x float>, ptr addrspace(1) null, align 128
+ %C = fcmp ueq <32 x float> %LGV, zeroinitializer
+ ret <32 x i1> %C
+}
+
+define <4 x i1> @vector_f32_ugt() {
+; CHECK-REDWOOD-LABEL: vector_f32_ugt:
+; CHECK-REDWOOD: ; %bb.0: ; %entry
+; CHECK-REDWOOD-NEXT: CF_END
+; CHECK-REDWOOD-NEXT: PAD
+;
+; CHECK-GFX1201-LABEL: vector_f32_ugt:
+; CHECK-GFX1201: ; %bb.0: ; %entry
+; CHECK-GFX1201-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_expcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_samplecnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_bvhcnt 0x0
+; CHECK-GFX1201-NEXT: s_wait_kmcnt 0x0
+; CHECK-GFX1201-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-GFX1201-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-GFX1201-NEXT: s_wait_loadcnt 0x0
+; CHECK-GFX1201-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v1
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v2
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v3
+; CHECK-GFX1201-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-GFX1201-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-GFX1201-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV1 = load <4 x float>, ptr addrspace(1) null, align 16
+ %C = fcmp ugt <4 x float> %LGV1, zeroinitializer
+ ret <4 x i1> %C
+}
+
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