[llvm] [AMDGPU][NFC] New tests for uncovered cases in SIInstrInfo.cpp (PR #200414)
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Tue Jun 9 02:18:07 PDT 2026
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<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: ambergorzynski
<details>
<summary>Changes</summary>
Several cases in [the AMDGPU backend](https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp) are not covered by the existing tests. We are proposing a new set of tests to cover these lines.
We demonstrate that these cases are not covered by showing that no test fails when `abort` statements are included. These are removed for the final PR.
We looked for existing test files to which these could be added instead of creating a new file, but we did not find good candidates. Some test files tested different flags, or were not compatible with autogenerated assertions. Let me know if you have any ideas/suggestions for where we could add the tests.
---
Full diff: https://github.com/llvm/llvm-project/pull/200414.diff
1 Files Affected:
- (added) llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll (+246)
``````````diff
diff --git a/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
new file mode 100644
index 0000000000000..50cb6127041d6
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/fcmp-vector-f32.ll
@@ -0,0 +1,246 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1201 < %s | FileCheck -check-prefix=CHECK %s
+
+define <8 x i1> @vector_f32_ole() {
+; CHECK-LABEL: vector_f32_ole:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-NEXT: s_clause 0x1
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-NEXT: s_wait_loadcnt 0x1
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v4
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v5
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v6
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_ge_f32_e32 vcc_lo, 0, v7
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <8 x float>, ptr addrspace(1) null, align 32
+ %C = fcmp ole <8 x float> %LGV, zeroinitializer
+ ret <8 x i1> %C
+}
+
+define <4 x i1> @vector_f32_ogt() {
+; CHECK-LABEL: vector_f32_ogt:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_lt_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <4 x float>, ptr addrspace(1) null, align 16
+ %C = fcmp ogt <4 x float> %LGV, zeroinitializer
+ ret <4 x i1> %C
+}
+
+define <32 x i1> @vector_f32_ueq() {
+; CHECK-LABEL: vector_f32_ueq:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: v_dual_mov_b32 v4, 16 :: v_dual_mov_b32 v5, 0
+; CHECK-NEXT: v_dual_mov_b32 v8, 32 :: v_dual_mov_b32 v9, 0
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: v_dual_mov_b32 v12, 48 :: v_dual_mov_b32 v13, 0
+; CHECK-NEXT: s_clause 0x1
+; CHECK-NEXT: global_load_b128 v[4:7], v[4:5], off
+; CHECK-NEXT: global_load_b128 v[8:11], v[8:9], off
+; CHECK-NEXT: v_dual_mov_b32 v16, 64 :: v_dual_mov_b32 v17, 0
+; CHECK-NEXT: global_load_b128 v[12:15], v[12:13], off
+; CHECK-NEXT: v_dual_mov_b32 v20, 0x50 :: v_dual_mov_b32 v21, 0
+; CHECK-NEXT: v_dual_mov_b32 v24, 0x60 :: v_dual_mov_b32 v25, 0
+; CHECK-NEXT: global_load_b128 v[16:19], v[16:17], off
+; CHECK-NEXT: v_dual_mov_b32 v28, 0x70 :: v_dual_mov_b32 v29, 0
+; CHECK-NEXT: s_clause 0x2
+; CHECK-NEXT: global_load_b128 v[20:23], v[20:21], off
+; CHECK-NEXT: global_load_b128 v[24:27], v[24:25], off
+; CHECK-NEXT: global_load_b128 v[28:31], v[28:29], off
+; CHECK-NEXT: s_wait_loadcnt 0x7
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x6
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v4
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v5
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v6
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v7
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x5
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v8
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v9
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v10
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v11
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x4
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v12
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v13
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v14
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v15
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x3
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v16
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v17
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v18
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v19
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x2
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v20
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v21
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v22
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v22, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v23
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v23, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x1
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v24
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v25
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v25, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v26
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v26, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v27
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v27, 0, 1, vcc_lo
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v28
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v28, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v29
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v29, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v30
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v30, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nlg_f32_e32 vcc_lo, 0, v31
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v31, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV = load <32 x float>, ptr addrspace(1) null, align 128
+ %C = fcmp ueq <32 x float> %LGV, zeroinitializer
+ ret <32 x i1> %C
+}
+
+define <4 x i1> @vector_f32_ugt() {
+; CHECK-LABEL: vector_f32_ugt:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: s_wait_loadcnt_dscnt 0x0
+; CHECK-NEXT: s_wait_expcnt 0x0
+; CHECK-NEXT: s_wait_samplecnt 0x0
+; CHECK-NEXT: s_wait_bvhcnt 0x0
+; CHECK-NEXT: s_wait_kmcnt 0x0
+; CHECK-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; CHECK-NEXT: global_load_b128 v[0:3], v[0:1], off
+; CHECK-NEXT: s_wait_loadcnt 0x0
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v0
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v1
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v2
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; CHECK-NEXT: v_cmp_nge_f32_e32 vcc_lo, 0, v3
+; CHECK-NEXT: s_wait_alu depctr_va_vcc(0)
+; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
+; CHECK-NEXT: s_setpc_b64 s[30:31]
+entry:
+ %LGV1 = load <4 x float>, ptr addrspace(1) null, align 16
+ %C = fcmp ugt <4 x float> %LGV1, zeroinitializer
+ ret <4 x i1> %C
+}
+
``````````
</details>
https://github.com/llvm/llvm-project/pull/200414
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