[llvm] [VectorCombine][AMDGPU] Shrink demanded vector loads (PR #202501)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 9 02:05:48 PDT 2026
================
@@ -0,0 +1,332 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -passes=vector-combine -S -mtriple=amdgcn-amd-amdpal -mcpu=gfx1201 | FileCheck %s
+
+target triple = "amdgcn-amd-amdpal"
+
+define void @shrink_i32_load_prefix(ptr addrspace(1) %out, ptr addrspace(4) %p) {
+; CHECK-LABEL: define void @shrink_i32_load_prefix(
+; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(4) [[P:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <3 x i32>, ptr addrspace(4) [[P]], align 8
+; CHECK-NEXT: [[E0:%.*]] = extractelement <3 x i32> [[TMP0]], i32 0
+; CHECK-NEXT: [[E1:%.*]] = extractelement <3 x i32> [[TMP0]], i32 1
+; CHECK-NEXT: [[E2:%.*]] = extractelement <3 x i32> [[TMP0]], i32 2
+; CHECK-NEXT: store i32 [[E0]], ptr addrspace(1) [[OUT]], align 4
+; CHECK-NEXT: [[OUT1:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 1
+; CHECK-NEXT: store i32 [[E1]], ptr addrspace(1) [[OUT1]], align 4
+; CHECK-NEXT: [[OUT2:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 2
+; CHECK-NEXT: store i32 [[E2]], ptr addrspace(1) [[OUT2]], align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %v = load <4 x i32>, ptr addrspace(4) %p, align 8
+ %e0 = extractelement <4 x i32> %v, i32 0
+ %e1 = extractelement <4 x i32> %v, i32 1
+ %e2 = extractelement <4 x i32> %v, i32 2
+ store i32 %e0, ptr addrspace(1) %out, align 4
+ %out1 = getelementptr i32, ptr addrspace(1) %out, i32 1
+ store i32 %e1, ptr addrspace(1) %out1, align 4
+ %out2 = getelementptr i32, ptr addrspace(1) %out, i32 2
+ store i32 %e2, ptr addrspace(1) %out2, align 4
+ ret void
+}
+
+define void @shrink_i16_load_prefix(ptr addrspace(1) %out, ptr addrspace(4) %p) {
+; CHECK-LABEL: define void @shrink_i16_load_prefix(
+; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(4) [[P:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i16>, ptr addrspace(4) [[P]], align 4
+; CHECK-NEXT: [[E0:%.*]] = extractelement <2 x i16> [[TMP0]], i32 0
+; CHECK-NEXT: [[E1:%.*]] = extractelement <2 x i16> [[TMP0]], i32 1
+; CHECK-NEXT: store i16 [[E0]], ptr addrspace(1) [[OUT]], align 2
+; CHECK-NEXT: [[OUT1:%.*]] = getelementptr i16, ptr addrspace(1) [[OUT]], i32 1
+; CHECK-NEXT: store i16 [[E1]], ptr addrspace(1) [[OUT1]], align 2
+; CHECK-NEXT: ret void
+;
+entry:
+ %v = load <4 x i16>, ptr addrspace(4) %p, align 4
+ %e0 = extractelement <4 x i16> %v, i32 0
+ %e1 = extractelement <4 x i16> %v, i32 1
+ store i16 %e0, ptr addrspace(1) %out, align 2
+ %out1 = getelementptr i16, ptr addrspace(1) %out, i32 1
+ store i16 %e1, ptr addrspace(1) %out1, align 2
+ ret void
+}
+
+define void @shrink_i64_load_to_i32_chunks(ptr addrspace(1) %out, ptr addrspace(4) %p) {
+; CHECK-LABEL: define void @shrink_i64_load_to_i32_chunks(
+; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(4) [[P:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <3 x i32>, ptr addrspace(4) [[P]], align 8
+; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr addrspace(4) [[P]], i64 16
+; CHECK-NEXT: [[TMP2:%.*]] = load <3 x i32>, ptr addrspace(4) [[TMP1]], align 8
+; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr addrspace(4) [[P]], i64 32
+; CHECK-NEXT: [[TMP4:%.*]] = load <3 x i32>, ptr addrspace(4) [[TMP3]], align 8
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <3 x i32> [[TMP0]], i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <3 x i32> [[TMP0]], i32 1
+; CHECK-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
+; CHECK-NEXT: [[TMP9:%.*]] = shl i64 [[TMP8]], 32
+; CHECK-NEXT: [[E0:%.*]] = or i64 [[TMP6]], [[TMP9]]
+; CHECK-NEXT: [[TMP10:%.*]] = extractelement <3 x i32> [[TMP0]], i32 2
+; CHECK-NEXT: [[E1:%.*]] = zext i32 [[TMP10]] to i64
+; CHECK-NEXT: [[TMP11:%.*]] = extractelement <3 x i32> [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP12:%.*]] = zext i32 [[TMP11]] to i64
+; CHECK-NEXT: [[TMP13:%.*]] = extractelement <3 x i32> [[TMP2]], i32 1
+; CHECK-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
+; CHECK-NEXT: [[TMP15:%.*]] = shl i64 [[TMP14]], 32
+; CHECK-NEXT: [[E2:%.*]] = or i64 [[TMP12]], [[TMP15]]
+; CHECK-NEXT: [[TMP16:%.*]] = extractelement <3 x i32> [[TMP2]], i32 2
+; CHECK-NEXT: [[E3:%.*]] = zext i32 [[TMP16]] to i64
+; CHECK-NEXT: [[TMP17:%.*]] = extractelement <3 x i32> [[TMP4]], i32 0
+; CHECK-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
+; CHECK-NEXT: [[TMP19:%.*]] = extractelement <3 x i32> [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
+; CHECK-NEXT: [[TMP21:%.*]] = shl i64 [[TMP20]], 32
+; CHECK-NEXT: [[E4:%.*]] = or i64 [[TMP18]], [[TMP21]]
+; CHECK-NEXT: [[TMP22:%.*]] = extractelement <3 x i32> [[TMP4]], i32 2
+; CHECK-NEXT: [[E5:%.*]] = zext i32 [[TMP22]] to i64
+; CHECK-NEXT: [[D0:%.*]] = trunc i64 [[E0]] to i32
+; CHECK-NEXT: [[E0HI:%.*]] = lshr i64 [[E0]], 32
+; CHECK-NEXT: [[D1:%.*]] = trunc i64 [[E0HI]] to i32
+; CHECK-NEXT: [[D2:%.*]] = trunc i64 [[E1]] to i32
+; CHECK-NEXT: [[D4:%.*]] = trunc i64 [[E2]] to i32
+; CHECK-NEXT: [[E2HI:%.*]] = lshr i64 [[E2]], 32
+; CHECK-NEXT: [[D5:%.*]] = trunc i64 [[E2HI]] to i32
+; CHECK-NEXT: [[D6:%.*]] = trunc i64 [[E3]] to i32
+; CHECK-NEXT: [[D8:%.*]] = trunc i64 [[E4]] to i32
+; CHECK-NEXT: [[E4HI:%.*]] = lshr i64 [[E4]], 32
+; CHECK-NEXT: [[D9:%.*]] = trunc i64 [[E4HI]] to i32
+; CHECK-NEXT: [[D10:%.*]] = trunc i64 [[E5]] to i32
+; CHECK-NEXT: [[OUT0:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 0
+; CHECK-NEXT: store i32 [[D0]], ptr addrspace(1) [[OUT0]], align 4
+; CHECK-NEXT: [[OUT1:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 1
+; CHECK-NEXT: store i32 [[D1]], ptr addrspace(1) [[OUT1]], align 4
+; CHECK-NEXT: [[OUT2:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 2
+; CHECK-NEXT: store i32 [[D2]], ptr addrspace(1) [[OUT2]], align 4
+; CHECK-NEXT: [[OUT4:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 4
+; CHECK-NEXT: store i32 [[D4]], ptr addrspace(1) [[OUT4]], align 4
+; CHECK-NEXT: [[OUT5:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 5
+; CHECK-NEXT: store i32 [[D5]], ptr addrspace(1) [[OUT5]], align 4
+; CHECK-NEXT: [[OUT6:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 6
+; CHECK-NEXT: store i32 [[D6]], ptr addrspace(1) [[OUT6]], align 4
+; CHECK-NEXT: [[OUT8:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 8
+; CHECK-NEXT: store i32 [[D8]], ptr addrspace(1) [[OUT8]], align 4
+; CHECK-NEXT: [[OUT9:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 9
+; CHECK-NEXT: store i32 [[D9]], ptr addrspace(1) [[OUT9]], align 4
+; CHECK-NEXT: [[OUT10:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 10
+; CHECK-NEXT: store i32 [[D10]], ptr addrspace(1) [[OUT10]], align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %v = load <6 x i64>, ptr addrspace(4) %p, align 8, !range !0
+ %e0 = extractelement <6 x i64> %v, i32 0
+ %e1 = extractelement <6 x i64> %v, i32 1
+ %e2 = extractelement <6 x i64> %v, i32 2
+ %e3 = extractelement <6 x i64> %v, i32 3
+ %e4 = extractelement <6 x i64> %v, i32 4
+ %e5 = extractelement <6 x i64> %v, i32 5
+
+ %d0 = trunc i64 %e0 to i32
+ %e0hi = lshr i64 %e0, 32
+ %d1 = trunc i64 %e0hi to i32
+ %d2 = trunc i64 %e1 to i32
+
+ %d4 = trunc i64 %e2 to i32
+ %e2hi = lshr i64 %e2, 32
+ %d5 = trunc i64 %e2hi to i32
+ %d6 = trunc i64 %e3 to i32
+
+ %d8 = trunc i64 %e4 to i32
+ %e4hi = lshr i64 %e4, 32
+ %d9 = trunc i64 %e4hi to i32
+ %d10 = trunc i64 %e5 to i32
+
+ %out0 = getelementptr i32, ptr addrspace(1) %out, i32 0
+ store i32 %d0, ptr addrspace(1) %out0, align 4
+ %out1 = getelementptr i32, ptr addrspace(1) %out, i32 1
+ store i32 %d1, ptr addrspace(1) %out1, align 4
+ %out2 = getelementptr i32, ptr addrspace(1) %out, i32 2
+ store i32 %d2, ptr addrspace(1) %out2, align 4
+ %out4 = getelementptr i32, ptr addrspace(1) %out, i32 4
+ store i32 %d4, ptr addrspace(1) %out4, align 4
+ %out5 = getelementptr i32, ptr addrspace(1) %out, i32 5
+ store i32 %d5, ptr addrspace(1) %out5, align 4
+ %out6 = getelementptr i32, ptr addrspace(1) %out, i32 6
+ store i32 %d6, ptr addrspace(1) %out6, align 4
+ %out8 = getelementptr i32, ptr addrspace(1) %out, i32 8
+ store i32 %d8, ptr addrspace(1) %out8, align 4
+ %out9 = getelementptr i32, ptr addrspace(1) %out, i32 9
+ store i32 %d9, ptr addrspace(1) %out9, align 4
+ %out10 = getelementptr i32, ptr addrspace(1) %out, i32 10
+ store i32 %d10, ptr addrspace(1) %out10, align 4
+ ret void
+}
+
+define void @shrink_float_load_prefix(ptr addrspace(1) %out, ptr addrspace(4) %p) {
+; CHECK-LABEL: define void @shrink_float_load_prefix(
+; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(4) [[P:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <3 x float>, ptr addrspace(4) [[P]], align 8
+; CHECK-NEXT: [[E0:%.*]] = extractelement <3 x float> [[TMP0]], i32 0
+; CHECK-NEXT: [[E1:%.*]] = extractelement <3 x float> [[TMP0]], i32 1
+; CHECK-NEXT: [[E2:%.*]] = extractelement <3 x float> [[TMP0]], i32 2
+; CHECK-NEXT: store float [[E0]], ptr addrspace(1) [[OUT]], align 4
+; CHECK-NEXT: [[OUT1:%.*]] = getelementptr float, ptr addrspace(1) [[OUT]], i32 1
+; CHECK-NEXT: store float [[E1]], ptr addrspace(1) [[OUT1]], align 4
+; CHECK-NEXT: [[OUT2:%.*]] = getelementptr float, ptr addrspace(1) [[OUT]], i32 2
+; CHECK-NEXT: store float [[E2]], ptr addrspace(1) [[OUT2]], align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %v = load <4 x float>, ptr addrspace(4) %p, align 8
+ %e0 = extractelement <4 x float> %v, i32 0
+ %e1 = extractelement <4 x float> %v, i32 1
+ %e2 = extractelement <4 x float> %v, i32 2
+ store float %e0, ptr addrspace(1) %out, align 4
+ %out1 = getelementptr float, ptr addrspace(1) %out, i32 1
+ store float %e1, ptr addrspace(1) %out1, align 4
+ %out2 = getelementptr float, ptr addrspace(1) %out, i32 2
+ store float %e2, ptr addrspace(1) %out2, align 4
+ ret void
+}
+
+define void @do_not_shrink_when_all_bits_are_demanded(ptr addrspace(1) %out, ptr addrspace(4) %p) {
+; CHECK-LABEL: define void @do_not_shrink_when_all_bits_are_demanded(
+; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(4) [[P:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[V:%.*]] = load <2 x i64>, ptr addrspace(4) [[P]], align 8
+; CHECK-NEXT: [[E0:%.*]] = extractelement <2 x i64> [[V]], i32 0
+; CHECK-NEXT: [[E1:%.*]] = extractelement <2 x i64> [[V]], i32 1
+; CHECK-NEXT: [[E0LO:%.*]] = trunc i64 [[E0]] to i32
+; CHECK-NEXT: [[E0HI64:%.*]] = lshr i64 [[E0]], 32
+; CHECK-NEXT: [[E0HI:%.*]] = trunc i64 [[E0HI64]] to i32
+; CHECK-NEXT: [[E1LO:%.*]] = trunc i64 [[E1]] to i32
+; CHECK-NEXT: [[E1HI64:%.*]] = lshr i64 [[E1]], 32
+; CHECK-NEXT: [[E1HI:%.*]] = trunc i64 [[E1HI64]] to i32
+; CHECK-NEXT: store i32 [[E0LO]], ptr addrspace(1) [[OUT]], align 4
+; CHECK-NEXT: [[OUT1:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 1
+; CHECK-NEXT: store i32 [[E0HI]], ptr addrspace(1) [[OUT1]], align 4
+; CHECK-NEXT: [[OUT2:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 2
+; CHECK-NEXT: store i32 [[E1LO]], ptr addrspace(1) [[OUT2]], align 4
+; CHECK-NEXT: [[OUT3:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 3
+; CHECK-NEXT: store i32 [[E1HI]], ptr addrspace(1) [[OUT3]], align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %v = load <2 x i64>, ptr addrspace(4) %p, align 8
+ %e0 = extractelement <2 x i64> %v, i32 0
+ %e1 = extractelement <2 x i64> %v, i32 1
+ %e0lo = trunc i64 %e0 to i32
+ %e0hi64 = lshr i64 %e0, 32
+ %e0hi = trunc i64 %e0hi64 to i32
+ %e1lo = trunc i64 %e1 to i32
+ %e1hi64 = lshr i64 %e1, 32
+ %e1hi = trunc i64 %e1hi64 to i32
+ store i32 %e0lo, ptr addrspace(1) %out, align 4
+ %out1 = getelementptr i32, ptr addrspace(1) %out, i32 1
+ store i32 %e0hi, ptr addrspace(1) %out1, align 4
+ %out2 = getelementptr i32, ptr addrspace(1) %out, i32 2
+ store i32 %e1lo, ptr addrspace(1) %out2, align 4
+ %out3 = getelementptr i32, ptr addrspace(1) %out, i32 3
+ store i32 %e1hi, ptr addrspace(1) %out3, align 4
+ ret void
+}
+
+define void @do_not_shrink_to_non_b96_chunks(ptr addrspace(1) %out, ptr addrspace(4) %p) {
+; CHECK-LABEL: define void @do_not_shrink_to_non_b96_chunks(
+; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(4) [[P:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[V:%.*]] = load <2 x i64>, ptr addrspace(4) [[P]], align 8
+; CHECK-NEXT: [[E0:%.*]] = extractelement <2 x i64> [[V]], i32 0
+; CHECK-NEXT: [[E1:%.*]] = extractelement <2 x i64> [[V]], i32 1
+; CHECK-NEXT: [[E0LO:%.*]] = trunc i64 [[E0]] to i32
+; CHECK-NEXT: [[E1LO:%.*]] = trunc i64 [[E1]] to i32
+; CHECK-NEXT: store i32 [[E0LO]], ptr addrspace(1) [[OUT]], align 4
+; CHECK-NEXT: [[OUT1:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 1
+; CHECK-NEXT: store i32 [[E1LO]], ptr addrspace(1) [[OUT1]], align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %v = load <2 x i64>, ptr addrspace(4) %p, align 8
+ %e0 = extractelement <2 x i64> %v, i32 0
+ %e1 = extractelement <2 x i64> %v, i32 1
+ %e0lo = trunc i64 %e0 to i32
+ %e1lo = trunc i64 %e1 to i32
+ store i32 %e0lo, ptr addrspace(1) %out, align 4
+ %out1 = getelementptr i32, ptr addrspace(1) %out, i32 1
+ store i32 %e1lo, ptr addrspace(1) %out1, align 4
+ ret void
+}
+
+define void @shrink_to_single_b64(ptr addrspace(1) %out, ptr addrspace(4) %p) {
+; CHECK-LABEL: define void @shrink_to_single_b64(
+; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(4) [[P:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <1 x i64>, ptr addrspace(4) [[P]], align 8
+; CHECK-NEXT: [[E0:%.*]] = extractelement <1 x i64> [[TMP0]], i32 0
+; CHECK-NEXT: [[E0LO:%.*]] = trunc i64 [[E0]] to i32
+; CHECK-NEXT: [[E0HI64:%.*]] = lshr i64 [[E0]], 32
+; CHECK-NEXT: [[E0HI:%.*]] = trunc i64 [[E0HI64]] to i32
+; CHECK-NEXT: store i32 [[E0LO]], ptr addrspace(1) [[OUT]], align 4
+; CHECK-NEXT: [[OUT1:%.*]] = getelementptr i32, ptr addrspace(1) [[OUT]], i32 1
+; CHECK-NEXT: store i32 [[E0HI]], ptr addrspace(1) [[OUT1]], align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %v = load <2 x i64>, ptr addrspace(4) %p, align 8
+ %e0 = extractelement <2 x i64> %v, i32 0
+ %e0lo = trunc i64 %e0 to i32
+ %e0hi64 = lshr i64 %e0, 32
+ %e0hi = trunc i64 %e0hi64 to i32
+ store i32 %e0lo, ptr addrspace(1) %out, align 4
+ %out1 = getelementptr i32, ptr addrspace(1) %out, i32 1
+ store i32 %e0hi, ptr addrspace(1) %out1, align 4
+ ret void
+}
+
+define void @do_not_shrink_volatile_load(ptr addrspace(1) %out, ptr addrspace(4) %p) {
+; CHECK-LABEL: define void @do_not_shrink_volatile_load(
+; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(4) [[P:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[V:%.*]] = load volatile <2 x i64>, ptr addrspace(4) [[P]], align 8
+; CHECK-NEXT: [[E0:%.*]] = extractelement <2 x i64> [[V]], i32 0
+; CHECK-NEXT: [[D0:%.*]] = trunc i64 [[E0]] to i32
+; CHECK-NEXT: store i32 [[D0]], ptr addrspace(1) [[OUT]], align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %v = load volatile <2 x i64>, ptr addrspace(4) %p, align 8
+ %e0 = extractelement <2 x i64> %v, i32 0
+ %d0 = trunc i64 %e0 to i32
+ store i32 %d0, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define void @shrink_drops_range_metadata_for_shorter_vector(ptr addrspace(1) %out, ptr addrspace(4) %p) {
+; CHECK-LABEL: define void @shrink_drops_range_metadata_for_shorter_vector(
----------------
arsenm wrote:
The range should be preservable as long as the scalar type isn't changed. Same with noundef and nonnull
https://github.com/llvm/llvm-project/pull/202501
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