[llvm] [VectorCombine][AMDGPU] Shrink demanded vector loads (PR #202501)

[Matt Arsenault via llvm-commits]

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@@ -1779,6 +1779,14 @@ class TargetTransformInfo {
   getMemIntrinsicInstrCost(const MemIntrinsicCostAttributes &MICA,
                            TTI::TargetCostKind CostKind) const;
 
+  /// Return true if replacing \p Load with the narrower load plan is profitable.
+  /// \p NewLoadTys and \p NewLoadOffsets are parallel arrays; offsets are bytes
+  /// from \p Load's pointer operand. Targets should evaluate the plan as a whole.
+  LLVM_ABI bool
+  shouldReduceLoadWidth(LoadInst *Load, ArrayRef<Type *> NewLoadTys,
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arsenm wrote:

```suggestion
  shouldReduceLoadWidth(const LoadInst *Load, ArrayRef<Type *> NewLoadTys,
```

https://github.com/llvm/llvm-project/pull/202501