[llvm] [AMDGPU] Fix gfx1250 WMMA latencies (PR #202522)

[Matt Arsenault via llvm-commits]

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@@ -494,22 +495,23 @@ def : HWWriteRes<WriteSALUDummy, [HWSALU],  2>;
 
 }  // End SchedModel = GFX12SpeedModel
 
-// Check if any matrix inputs are interpreted as f8 in an f8f6f4
-// wmma instruction.
-def PredIsF8_WMMA_SCALE : SchedPredicate<[{
-  TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_a_fmt)->getImm() <= AMDGPU::WMMA::MATRIX_FMT_BF8 ||
-  TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_b_fmt)->getImm() <= AMDGPU::WMMA::MATRIX_FMT_BF8
+// Check whether the two matrix inputs of an f8f6f4 wmma instruction are
+// not both interpreted as f4. On gfx1250 an f8f6f4 wmma runs in 4 cycles
+// when both inputs are f4, and in 8 cycles when any input is f6 or f8.
+def PredIsNotBothF4_WMMA_SCALE : SchedPredicate<[{
+  TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_a_fmt)->getImm() != AMDGPU::WMMA::MATRIX_FMT_FP4 ||
+  TII->getNamedOperand(*MI, AMDGPU::OpName::matrix_b_fmt)->getImm() != AMDGPU::WMMA::MATRIX_FMT_FP4
 }]>;
 
-// If either matrix format is f8, the instruction takes 2x as many
-// cycles. TODO: This isn't reflected in MCA.
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arsenm wrote:

Isn't this TODO still true? The predicate depends on the MachineOperand checks?

https://github.com/llvm/llvm-project/pull/202522