[llvm] [SLP] Update test against const-folding (PR #202532)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 9 01:04:22 PDT 2026
https://github.com/artagnon created https://github.com/llvm/llvm-project/pull/202532
223ef1f3 ([IRBuilder] ConstFold unary intrinsics, #200496) made a lot of test updates to SLPVectorizer. The tests were written a long time ago, and it is unclear what their intent was, but at least update the one test to replace constants with arguments, where the intent is clear.
>From 0dd0eb8ca63b5b42c4297c2bbf13ccc09c1b68c7 Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: Tue, 9 Jun 2026 08:59:23 +0100
Subject: [PATCH] [SLP] Update test against const-folding
223ef1f3 ([IRBuilder] ConstFold unary intrinsics, #200496) made a lot of
test updates to SLPVectorizer. The tests were written a long time ago,
and it is unclear what their intent was, but at least update the one
test to replace constants with arguments, where the intent is clear.
---
.../revec-reduced-value-vectorized-later.ll | 44 +++++++++++++++++--
1 file changed, 40 insertions(+), 4 deletions(-)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-vectorized-later.ll b/llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-vectorized-later.ll
index 4305ad171c4b9..0e50b135afe7f 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-vectorized-later.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-vectorized-later.ll
@@ -1,13 +1,49 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -slp-revec -slp-max-reg-size=1024 -slp-threshold=-100 < %s | FileCheck %s
-define <4 x i16> @test() {
-; CHECK-LABEL: define <4 x i16> @test() {
+define <4 x i16> @test(<4 x i16> %a) {
+; CHECK-LABEL: define <4 x i16> @test(
+; CHECK-SAME: <4 x i16> [[A:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: ret <4 x i16> zeroinitializer
+; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x i16> [[A]], <4 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef>, <16 x i16> [[TMP0]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 12, i32 13, i32 14, i32 15>
+; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
+; CHECK-NEXT: [[TMP3:%.*]] = add <16 x i16> [[TMP2]], [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <16 x i16> [[TMP3]], <16 x i16> poison, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
+; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x i16> [[TMP4]], <4 x i16> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: [[TMP6:%.*]] = add <16 x i16> [[TMP5]], zeroinitializer
+; CHECK-NEXT: [[TMP7:%.*]] = add <16 x i16> [[TMP3]], zeroinitializer
+; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <16 x i16> [[TMP6]], <16 x i16> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
+; CHECK-NEXT: [[TMP9:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP8]])
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i16> poison, i16 [[TMP9]], i64 0
+; CHECK-NEXT: [[TMP11:%.*]] = shufflevector <16 x i16> [[TMP6]], <16 x i16> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
+; CHECK-NEXT: [[TMP12:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP11]])
+; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i16> [[TMP10]], i16 [[TMP12]], i64 1
+; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <16 x i16> [[TMP6]], <16 x i16> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
+; CHECK-NEXT: [[TMP15:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP14]])
+; CHECK-NEXT: [[TMP16:%.*]] = insertelement <4 x i16> [[TMP13]], i16 [[TMP15]], i64 2
+; CHECK-NEXT: [[TMP17:%.*]] = shufflevector <16 x i16> [[TMP6]], <16 x i16> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
+; CHECK-NEXT: [[TMP18:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP17]])
+; CHECK-NEXT: [[TMP19:%.*]] = insertelement <4 x i16> [[TMP16]], i16 [[TMP18]], i64 3
+; CHECK-NEXT: [[TMP20:%.*]] = shufflevector <16 x i16> [[TMP7]], <16 x i16> poison, <4 x i32> <i32 0, i32 4, i32 8, i32 12>
+; CHECK-NEXT: [[TMP21:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP20]])
+; CHECK-NEXT: [[TMP22:%.*]] = insertelement <4 x i16> poison, i16 [[TMP21]], i64 0
+; CHECK-NEXT: [[TMP23:%.*]] = shufflevector <16 x i16> [[TMP7]], <16 x i16> poison, <4 x i32> <i32 1, i32 5, i32 9, i32 13>
+; CHECK-NEXT: [[TMP24:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP23]])
+; CHECK-NEXT: [[TMP25:%.*]] = insertelement <4 x i16> [[TMP22]], i16 [[TMP24]], i64 1
+; CHECK-NEXT: [[TMP26:%.*]] = shufflevector <16 x i16> [[TMP7]], <16 x i16> poison, <4 x i32> <i32 2, i32 6, i32 10, i32 14>
+; CHECK-NEXT: [[TMP27:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP26]])
+; CHECK-NEXT: [[TMP28:%.*]] = insertelement <4 x i16> [[TMP25]], i16 [[TMP27]], i64 2
+; CHECK-NEXT: [[TMP29:%.*]] = shufflevector <16 x i16> [[TMP7]], <16 x i16> poison, <4 x i32> <i32 3, i32 7, i32 11, i32 15>
+; CHECK-NEXT: [[TMP30:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP29]])
+; CHECK-NEXT: [[TMP31:%.*]] = insertelement <4 x i16> [[TMP28]], i16 [[TMP30]], i64 3
+; CHECK-NEXT: [[OP_RDX:%.*]] = or <4 x i16> [[TMP31]], [[TMP4]]
+; CHECK-NEXT: [[OP_RDX15:%.*]] = or <4 x i16> zeroinitializer, [[TMP19]]
+; CHECK-NEXT: [[OP_RDX16:%.*]] = or <4 x i16> [[OP_RDX]], [[OP_RDX15]]
+; CHECK-NEXT: ret <4 x i16> [[OP_RDX16]]
;
entry:
- %subi = add <4 x i16> zeroinitializer, zeroinitializer
+ %subi = add <4 x i16> %a, %a
%sub40.i = add <4 x i16> %subi, zeroinitializer
%sub41.i = add <4 x i16> %subi, zeroinitializer
%sub42.i = add <4 x i16> %subi, zeroinitializer
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