[llvm] [AMDGPU] Enable WMMA256bInsts + Wave32 for gfx1200/gfx1201 + SISchedule fix + TargetParser gfx1200 propagation (PR #202093)

[Krzysztof Drewniak via llvm-commits]

================
@@ -1570,7 +1572,8 @@ def FeatureGFX12 : GCNSubtargetFeatureGeneration<"GFX12",
    FeatureIEEEMinimumMaximumInsts, FeatureSALUMinimumMaximumInsts,
    FeatureMinimum3Maximum3F32, FeatureMinimum3Maximum3F16,
    FeatureAgentScopeFineGrainedRemoteMemoryAtomics, FeatureFlatOffsetBits24,
-   FeatureFlatSignedOffset, FeatureInstCacheLineSize128
+   FeatureFlatSignedOffset, FeatureInstCacheLineSize128,
+   FeatureWMMA256bInsts
----------------
krzysz00 wrote:

"all tests pass" doesn't necessarily mean much here?

This is a claim that either
1. Some specific patch in the AMD fork never got upstreamed, causing instructions that should be supported on gfx1200/gfx1201 to not be generatable by upstream LLVM. If so, please link me the exact line of code in question
2. There exist instructions on RDNA4 that can't be generated by the compiler. In which case, can I get page numbers in / quotes from the ISA documents?

https://github.com/llvm/llvm-project/pull/202093