[llvm] [X86][Atomic] Fix bts/btr/btc regression caused by InstCombine trunc to i1 (PR #200667)

[Phoebe Wang via llvm-commits]

phoebewang wrote:

> For this particular case, the backend handles any single set bit so we won't get any simplification of the code. It seems that it now rewrites the whole pattern of `AND` + `CMP` into `TRUNC` and `AND(X,1)` itself can still appear in the backend. However, there are cases in X86ISelLowering which are explicitly handling `AND(X,1) == 0`, so these could be likely converted of `TRUNC` or removed

Do you mean backend tests have this pattern or backend opt will generate the pattern again? The former is not a problem, the latter should be updated. Anyway, for the sake of stability and independence, it's better to do it in a seperate patch.

https://github.com/llvm/llvm-project/pull/200667