[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for tensor load/store to lds (PR #202363)

[Chinmay Deshpande via llvm-commits]

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@@ -2149,6 +2149,13 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
                     amdgcn_global_store_async_from_lds_b128})
       .Any({{}, {{}, {IntrId, VgprP1, VgprP3}}});
 
+  addRulesForIOpcs({amdgcn_tensor_load_to_lds, amdgcn_tensor_store_from_lds})
+      .Any({{},
+            {{},
+             {IntrId, SgprV4S32_ReadFirstLane, SgprV8S32_ReadFirstLane,
+              SgprV4S32_ReadFirstLane, SgprV4S32_ReadFirstLane,
+              SgprV8S32_ReadFirstLane}}});
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chinmaydd wrote:

Imm argument that represents `cpol` is missing -- just for consistency as I saw it was included on the one for cvt insts 

https://github.com/llvm/llvm-project/pull/202363