[llvm] [AMDGPU][GlobalIsel] Adding new reg bank rules for amdgcn_s_quadmask, amdgcn_s_wqm (PR #201898)
Chinmay Deshpande via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 8 09:23:18 PDT 2026
https://github.com/chinmaydd updated https://github.com/llvm/llvm-project/pull/201898
>From f35b6cc120ea132fe7f343862612a62384645352 Mon Sep 17 00:00:00 2001
From: Jonathan Antenanie <jonathan03ant at gmail.com>
Date: Fri, 5 Jun 2026 17:39:01 +0000
Subject: [PATCH 1/2] [AMDGPU][GlobalIsel] Adding new reg bank rules for
amdgcn_s_quadmask
---
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp | 4 ++++
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index e5bab2bbdfa25..13e742c2119d4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1696,6 +1696,10 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForIOpcs({amdgcn_readlane}, StandardB)
.Uni(B32, {{SgprB32}, {IntrId, VgprB32, SgprB32_ReadFirstLane}});
+ addRulesForIOpcs({amdgcn_s_quadmask}, StandardB)
+ .Uni(B32, {{SgprB32}, {IntrId, SgprB32_ReadFirstLane}})
+ .Uni(B64, {{SgprB64}, {IntrId, SgprB64_ReadFirstLane}});
+
addRulesForIOpcs({amdgcn_writelane}, StandardB)
.Div(B32,
{{VgprB32},
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
index eabe746e8b38e..c932de316a00e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=0 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
declare i32 @llvm.amdgcn.s.quadmask.i32(i32)
declare i64 @llvm.amdgcn.s.quadmask.i64(i64)
>From 6e845f0d71bb91b3d403627445e848b0de9d93a4 Mon Sep 17 00:00:00 2001
From: Jonathan Antenanie <jonathan03ant at gmail.com>
Date: Fri, 5 Jun 2026 18:50:29 +0000
Subject: [PATCH 2/2] [AMDGPU][GlobalIsel] Adding new reg bank rules for
amdgcn_s_quadmask #up 2
---
.../Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp | 8 +++++---
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll | 14 +++++++-------
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll | 2 +-
3 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 13e742c2119d4..73fb1dbb952f1 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1696,9 +1696,11 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
addRulesForIOpcs({amdgcn_readlane}, StandardB)
.Uni(B32, {{SgprB32}, {IntrId, VgprB32, SgprB32_ReadFirstLane}});
- addRulesForIOpcs({amdgcn_s_quadmask}, StandardB)
- .Uni(B32, {{SgprB32}, {IntrId, SgprB32_ReadFirstLane}})
- .Uni(B64, {{SgprB64}, {IntrId, SgprB64_ReadFirstLane}});
+ addRulesForIOpcs({amdgcn_s_quadmask, amdgcn_s_wqm}, StandardB)
+ .Uni(B32, {{SgprB32}, {IntrId, SgprB32}})
+ .Div(B32, {{Sgpr32ToVgprDst}, {IntrId, SgprB32_ReadFirstLane}})
+ .Uni(B64, {{SgprB64}, {IntrId, SgprB64}})
+ .Div(B64, {{Sgpr64ToVgprDst}, {IntrId, SgprB64_ReadFirstLane}});
addRulesForIOpcs({amdgcn_writelane}, StandardB)
.Div(B32,
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
index c932de316a00e..91b99e824dc7e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.quadmask.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=0 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s
declare i32 @llvm.amdgcn.s.quadmask.i32(i32)
declare i64 @llvm.amdgcn.s.quadmask.i64(i64)
@@ -179,14 +179,15 @@ define amdgpu_kernel void @test_scc_quadmask_32(i32 %val0, i32 %val1, ptr addrsp
; GFX11-GISEL: ; %bb.0:
; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: s_and_b32 s0, s0, 1
; GFX11-GISEL-NEXT: s_quadmask_b32 s1, s1
; GFX11-GISEL-NEXT: s_cmp_eq_u32 s0, 0
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, s1
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, s1
; GFX11-GISEL-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v4, s0
-; GFX11-GISEL-NEXT: global_store_b32 v2, v3, s[2:3]
+; GFX11-GISEL-NEXT: global_store_b32 v3, v2, s[2:3]
; GFX11-GISEL-NEXT: global_store_b32 v[0:1], v4, off
; GFX11-GISEL-NEXT: s_endpgm
;
@@ -220,13 +221,12 @@ define amdgpu_kernel void @test_scc_quadmask_64(i32 %val0, i64 %val1, ptr addrsp
; GFX11-GISEL-NEXT: s_clause 0x1
; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-GISEL-NEXT: s_load_b32 s4, s[4:5], 0x24
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 0
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, 0
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: s_quadmask_b64 s[0:1], s[0:1]
; GFX11-GISEL-NEXT: s_and_b32 s4, s4, 1
-; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-GISEL-NEXT: s_cmp_eq_u32 s4, 0
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s1
; GFX11-GISEL-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, s0
; GFX11-GISEL-NEXT: global_store_b64 v4, v[0:1], s[2:3]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
index c9f4acaa20f76..096df16a8e91a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wqm.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=1 < %s | FileCheck -check-prefixes=GFX11 %s
+; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=1 -new-reg-bank-select < %s | FileCheck -check-prefixes=GFX11 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -global-isel=0 < %s | FileCheck -check-prefixes=GFX11 %s
declare i32 @llvm.amdgcn.s.wqm.i32(i32)
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