[llvm] [AArch64][GlobalISel] Fix post-legalizer observer notifications (PR #202376)

[Cullen Rhodes via llvm-commits]

https://github.com/c-rhodes created https://github.com/llvm/llvm-project/pull/202376

Assisted-by: codex

>From 099f69054b971a7ba001fd358750170a9e15af4c Mon Sep 17 00:00:00 2001
From: Cullen Rhodes <cullen.rhodes at arm.com>
Date: Mon, 8 Jun 2026 15:52:42 +0000
Subject: [PATCH] [AArch64][GlobalISel] Fix post-legalizer observer
 notifications

Assisted-by: codex
---
 llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp | 2 +-
 llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
index 3a0c0e7494f41..cd57d4dab9c8d 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
@@ -585,7 +585,7 @@ static void applySubAddMulReassoc(MachineInstr &MI, MachineInstr &Sub,
   MI.getOperand(1).setReg(Tmp);
   MI.getOperand(2).setReg(Mul2);
   Sub.eraseFromParent();
-  Observer.changingInstr(MI);
+  Observer.changedInstr(MI);
 }
 
 class AArch64PostLegalizerCombinerImpl : public Combiner {
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
index c22221724f3ec..c129266f016d4 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
@@ -1017,7 +1017,7 @@ void applySwapICmpOperands(MachineInstr &MI, GISelChangeObserver &Observer) {
   auto Pred = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
   Register LHS = MI.getOperand(2).getReg();
   Register RHS = MI.getOperand(3).getReg();
-  Observer.changedInstr(MI);
+  Observer.changingInstr(MI);
   MI.getOperand(1).setPredicate(CmpInst::getSwappedPredicate(Pred));
   MI.getOperand(2).setReg(RHS);
   MI.getOperand(3).setReg(LHS);