[llvm] [AMDGPU] Fix si-optimize-exec-masking stepping into debug values (PR #201947)
Joseph Huber via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 8 06:45:31 PDT 2026
https://github.com/jhuber6 updated https://github.com/llvm/llvm-project/pull/201947
>From 0f867c7f55c9574290691f5a98e237fbed52ff2d Mon Sep 17 00:00:00 2001
From: Joseph Huber <huberjn at outlook.com>
Date: Fri, 5 Jun 2026 16:44:28 -0500
Subject: [PATCH 1/2] [AMDGPU] Fix si-optimize-exec-masking stepping into debug
values
Summary:
This pass tries to step between register uses and would try to enter a
debug instruction if it managed to get between them.
---
.../Target/AMDGPU/SIOptimizeExecMasking.cpp | 3 +-
.../optimize-exec-masking-dbg-value.mir | 121 ++++++++++++++++++
2 files changed, 123 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/optimize-exec-masking-dbg-value.mir
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
index 47bc218ed9577..72a60f78b7348 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
@@ -416,7 +416,8 @@ bool SIOptimizeExecMasking::isRegisterInUseBetween(MachineInstr &Stop,
++A;
for (; A != Stop.getParent()->rend() && A != Stop; ++A) {
- LR.stepBackward(*A);
+ if (!A->isDebugInstr())
+ LR.stepBackward(*A);
}
return !LR.available(Reg) || MRI->isReserved(Reg);
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-dbg-value.mir
new file mode 100644
index 0000000000000..255e46894b211
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-dbg-value.mir
@@ -0,0 +1,121 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1030 -run-pass=si-optimize-exec-masking -o - %s | FileCheck %s
+
+--- |
+ define amdgpu_kernel void @dbg_value_between_cmp_and_exec_copy(ptr %ch) #0 !dbg !4 {
+ entry:
+ #dbg_value(ptr %ch, !8, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), !11)
+ %call = load i32, ptr addrspace(5) null, align 4, !dbg !12
+ %cmp.not = icmp eq i32 %call, 0
+ %0 = call { i1, i32 } @llvm.amdgcn.if.i32(i1 %cmp.not)
+ %1 = extractvalue { i1, i32 } %0, 0
+ %2 = extractvalue { i1, i32 } %0, 1
+ br i1 %1, label %if.end, label %common.ret
+
+ common.ret:
+ call void @llvm.amdgcn.end.cf.i32(i32 %2)
+ ret void
+
+ if.end:
+ %kernarg.segment = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr(), !dbg !12
+ %ch.kernarg.offset1 = bitcast ptr addrspace(4) %kernarg.segment to ptr addrspace(4), !dbg !12, !amdgpu.uniform !2
+ %ch.load = load ptr, ptr addrspace(4) %ch.kernarg.offset1, align 16, !dbg !12, !invariant.load !2, !amdgpu.uniform !2
+ %3 = load atomic i32, ptr %ch.load acquire, align 4
+ br label %common.ret
+ }
+
+ declare noundef align 4 ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #1
+ declare { i1, i32 } @llvm.amdgcn.if.i32(i1) #2
+ declare void @llvm.amdgcn.end.cf.i32(i32) #2
+
+ attributes #0 = { "target-cpu"="gfx1030" }
+ attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+ attributes #2 = { nocallback nofree nounwind willreturn }
+
+ !llvm.dbg.cu = !{!0}
+ !llvm.module.flags = !{!3}
+
+ !0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: !2, globals: !2, splitDebugInlining: false, nameTableKind: None)
+ !1 = !DIFile(filename: "test.c", directory: "/tmp")
+ !2 = !{}
+ !3 = !{i32 2, !"Debug Info Version", i32 3}
+ !4 = distinct !DISubprogram(name: "dbg_value_between_cmp_and_exec_copy", scope: !1, file: !1, line: 1, type: !6, scopeLine: 1, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2, keyInstructions: true)
+ !6 = !DISubroutineType(cc: DW_CC_LLVM_DeviceKernel, types: !7)
+ !7 = !{null}
+ !8 = !DILocalVariable(name: "ch", arg: 1, scope: !4, file: !1, line: 1, type: !9)
+ !9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64, dwarfAddressSpace: 1)
+ !10 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "S", file: !1, line: 1, size: 64, elements: !2)
+ !11 = !DILocation(line: 0, scope: !4)
+ !12 = !DILocation(line: 2, column: 1, scope: !13)
+ !13 = distinct !DILexicalBlock(scope: !4, file: !1, line: 2, column: 1)
+...
+---
+name: dbg_value_between_cmp_and_exec_copy
+alignment: 4
+tracksRegLiveness: true
+noPhis: true
+isSSA: false
+noVRegs: true
+tracksDebugUserValues: true
+liveins:
+ - { reg: '$sgpr8_sgpr9', virtual-reg: '' }
+machineFunctionInfo:
+ explicitKernArgSize: 8
+ maxKernArgAlign: 8
+ isEntryFunction: true
+ scratchRSrcReg: '$sgpr100_sgpr101_sgpr102_sgpr103'
+ stackPtrOffsetReg: '$sgpr32'
+ returnsVoid: true
+ occupancy: 16
+ sgprForEXECCopy: '$sgpr105'
+ argumentInfo:
+ kernargSegmentPtr: { reg: '$sgpr8_sgpr9' }
+body: |
+ ; CHECK-LABEL: name: dbg_value_between_cmp_and_exec_copy
+ ; CHECK: bb.0.entry:
+ ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ ; CHECK-NEXT: liveins: $sgpr8_sgpr9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr100_sgpr101_sgpr102_sgpr103, 0, 0, 0, 0, implicit $exec, debug-location !11 :: (load (s32) from `ptr addrspace(5) null`, addrspace 5)
+ ; CHECK-NEXT: DBG_VALUE $noreg, $noreg, !7, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !10
+ ; CHECK-NEXT: $sgpr0 = S_MOV_B32 $exec_lo
+ ; CHECK-NEXT: V_CMPX_EQ_U32_nosdst_e64 0, $vgpr0, implicit-def $exec, implicit $exec
+ ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
+ ; CHECK-NEXT: S_BRANCH %bb.2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1.common.ret:
+ ; CHECK-NEXT: S_ENDPGM 0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.2.if.end:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $sgpr8_sgpr9
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed renamable $sgpr8_sgpr9, 0, 0, debug-location !11 :: (dereferenceable invariant load (s64) from %ir.ch.kernarg.offset1, align 16, addrspace 4)
+ ; CHECK-NEXT: renamable $vgpr0_vgpr1 = COPY killed renamable $sgpr0_sgpr1, implicit $exec
+ ; CHECK-NEXT: dead renamable $vgpr0 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load acquire (s32) from %ir.ch.load)
+ ; CHECK-NEXT: S_BRANCH %bb.1
+ bb.0.entry:
+ successors: %bb.2(0x40000000), %bb.1(0x40000000)
+ liveins: $sgpr8_sgpr9
+
+ renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr100_sgpr101_sgpr102_sgpr103, 0, 0, 0, 0, implicit $exec, debug-location !12 :: (load (s32) from `ptr addrspace(5) null`, addrspace 5)
+ renamable $vcc_lo = V_CMP_EQ_U32_e64 0, killed $vgpr0, implicit $exec
+ DBG_VALUE $noreg, $noreg, !8, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !11
+ renamable $sgpr0 = COPY $exec_lo, implicit-def $exec_lo
+ renamable $sgpr0 = S_AND_B32 killed renamable $sgpr0, killed renamable $vcc_lo, implicit-def dead $scc
+ $exec_lo = S_MOV_B32_term killed renamable $sgpr0
+ S_CBRANCH_EXECZ %bb.1, implicit $exec
+ S_BRANCH %bb.2
+
+ bb.1.common.ret:
+ S_ENDPGM 0
+
+ bb.2.if.end:
+ successors: %bb.1(0x80000000)
+ liveins: $sgpr8_sgpr9
+
+ renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed renamable $sgpr8_sgpr9, 0, 0, debug-location !12 :: (dereferenceable invariant load (s64) from %ir.ch.kernarg.offset1, align 16, addrspace 4)
+ renamable $vgpr0_vgpr1 = COPY killed renamable $sgpr0_sgpr1, implicit $exec
+ dead renamable $vgpr0 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load acquire (s32) from %ir.ch.load)
+ S_BRANCH %bb.1
+...
>From 3b6c91c999ca73348ccb6e8426bd4b9bf99002bf Mon Sep 17 00:00:00 2001
From: Joseph Huber <huberjn at outlook.com>
Date: Mon, 8 Jun 2026 08:04:32 -0500
Subject: [PATCH 2/2] USe debugify, found more issues
---
.../Target/AMDGPU/SIOptimizeExecMasking.cpp | 16 ++-
.../optimize-exec-masking-dbg-value.mir | 121 ------------------
.../CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir | 1 +
3 files changed, 14 insertions(+), 124 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/optimize-exec-masking-dbg-value.mir
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
index 72a60f78b7348..108fb6544afa2 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
@@ -469,6 +469,8 @@ bool SIOptimizeExecMasking::optimizeExecSequence() {
auto CopyFromExecInst = findExecCopy(MBB, I);
if (CopyFromExecInst == E) {
auto PrepareExecInst = std::next(I);
+ while (PrepareExecInst != E && PrepareExecInst->isDebugInstr())
+ ++PrepareExecInst;
if (PrepareExecInst == E)
continue;
// Fold exec = COPY (S_AND_B64 reg, exec) -> exec = S_AND_B64 reg, exec
@@ -501,6 +503,9 @@ bool SIOptimizeExecMasking::optimizeExecSequence() {
J = std::next(CopyFromExecInst->getIterator()),
JE = I->getIterator();
J != JE; ++J) {
+ if (J->isDebugInstr())
+ continue;
+
if (SaveExecInst && J->readsRegister(LMC.ExecReg, TRI)) {
LLVM_DEBUG(dbgs() << "exec read prevents saveexec: " << *J << '\n');
// Make sure this is inserted after any VALU ops that may have been
@@ -759,9 +764,14 @@ void SIOptimizeExecMasking::tryRecordOrSaveexecXorSequence(MachineInstr &MI) {
XorSrc1.isReg() &&
(XorSrc0.getReg() == LMC.ExecReg || XorSrc1.getReg() == LMC.ExecReg)) {
- // Peek at the previous instruction and check if this is a relevant
- // s_or_saveexec instruction.
- MachineInstr &PossibleOrSaveexec = *MI.getPrevNode();
+ // Peek at the previous non-debug instruction and check if this is a
+ // relevant s_or_saveexec instruction.
+ MachineInstr *Prev = MI.getPrevNode();
+ while (Prev && Prev->isDebugInstr())
+ Prev = Prev->getPrevNode();
+ if (!Prev)
+ return;
+ MachineInstr &PossibleOrSaveexec = *Prev;
if (PossibleOrSaveexec.getOpcode() != LMC.OrSaveExecOpc)
return;
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-dbg-value.mir b/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-dbg-value.mir
deleted file mode 100644
index 255e46894b211..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/optimize-exec-masking-dbg-value.mir
+++ /dev/null
@@ -1,121 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1030 -run-pass=si-optimize-exec-masking -o - %s | FileCheck %s
-
---- |
- define amdgpu_kernel void @dbg_value_between_cmp_and_exec_copy(ptr %ch) #0 !dbg !4 {
- entry:
- #dbg_value(ptr %ch, !8, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), !11)
- %call = load i32, ptr addrspace(5) null, align 4, !dbg !12
- %cmp.not = icmp eq i32 %call, 0
- %0 = call { i1, i32 } @llvm.amdgcn.if.i32(i1 %cmp.not)
- %1 = extractvalue { i1, i32 } %0, 0
- %2 = extractvalue { i1, i32 } %0, 1
- br i1 %1, label %if.end, label %common.ret
-
- common.ret:
- call void @llvm.amdgcn.end.cf.i32(i32 %2)
- ret void
-
- if.end:
- %kernarg.segment = call nonnull align 16 dereferenceable(264) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr(), !dbg !12
- %ch.kernarg.offset1 = bitcast ptr addrspace(4) %kernarg.segment to ptr addrspace(4), !dbg !12, !amdgpu.uniform !2
- %ch.load = load ptr, ptr addrspace(4) %ch.kernarg.offset1, align 16, !dbg !12, !invariant.load !2, !amdgpu.uniform !2
- %3 = load atomic i32, ptr %ch.load acquire, align 4
- br label %common.ret
- }
-
- declare noundef align 4 ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #1
- declare { i1, i32 } @llvm.amdgcn.if.i32(i1) #2
- declare void @llvm.amdgcn.end.cf.i32(i32) #2
-
- attributes #0 = { "target-cpu"="gfx1030" }
- attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
- attributes #2 = { nocallback nofree nounwind willreturn }
-
- !llvm.dbg.cu = !{!0}
- !llvm.module.flags = !{!3}
-
- !0 = distinct !DICompileUnit(language: DW_LANG_C11, file: !1, producer: "clang", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, retainedTypes: !2, globals: !2, splitDebugInlining: false, nameTableKind: None)
- !1 = !DIFile(filename: "test.c", directory: "/tmp")
- !2 = !{}
- !3 = !{i32 2, !"Debug Info Version", i32 3}
- !4 = distinct !DISubprogram(name: "dbg_value_between_cmp_and_exec_copy", scope: !1, file: !1, line: 1, type: !6, scopeLine: 1, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !2, keyInstructions: true)
- !6 = !DISubroutineType(cc: DW_CC_LLVM_DeviceKernel, types: !7)
- !7 = !{null}
- !8 = !DILocalVariable(name: "ch", arg: 1, scope: !4, file: !1, line: 1, type: !9)
- !9 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !10, size: 64, dwarfAddressSpace: 1)
- !10 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "S", file: !1, line: 1, size: 64, elements: !2)
- !11 = !DILocation(line: 0, scope: !4)
- !12 = !DILocation(line: 2, column: 1, scope: !13)
- !13 = distinct !DILexicalBlock(scope: !4, file: !1, line: 2, column: 1)
-...
----
-name: dbg_value_between_cmp_and_exec_copy
-alignment: 4
-tracksRegLiveness: true
-noPhis: true
-isSSA: false
-noVRegs: true
-tracksDebugUserValues: true
-liveins:
- - { reg: '$sgpr8_sgpr9', virtual-reg: '' }
-machineFunctionInfo:
- explicitKernArgSize: 8
- maxKernArgAlign: 8
- isEntryFunction: true
- scratchRSrcReg: '$sgpr100_sgpr101_sgpr102_sgpr103'
- stackPtrOffsetReg: '$sgpr32'
- returnsVoid: true
- occupancy: 16
- sgprForEXECCopy: '$sgpr105'
- argumentInfo:
- kernargSegmentPtr: { reg: '$sgpr8_sgpr9' }
-body: |
- ; CHECK-LABEL: name: dbg_value_between_cmp_and_exec_copy
- ; CHECK: bb.0.entry:
- ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
- ; CHECK-NEXT: liveins: $sgpr8_sgpr9
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr100_sgpr101_sgpr102_sgpr103, 0, 0, 0, 0, implicit $exec, debug-location !11 :: (load (s32) from `ptr addrspace(5) null`, addrspace 5)
- ; CHECK-NEXT: DBG_VALUE $noreg, $noreg, !7, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !10
- ; CHECK-NEXT: $sgpr0 = S_MOV_B32 $exec_lo
- ; CHECK-NEXT: V_CMPX_EQ_U32_nosdst_e64 0, $vgpr0, implicit-def $exec, implicit $exec
- ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
- ; CHECK-NEXT: S_BRANCH %bb.2
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.1.common.ret:
- ; CHECK-NEXT: S_ENDPGM 0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: bb.2.if.end:
- ; CHECK-NEXT: successors: %bb.1(0x80000000)
- ; CHECK-NEXT: liveins: $sgpr8_sgpr9
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed renamable $sgpr8_sgpr9, 0, 0, debug-location !11 :: (dereferenceable invariant load (s64) from %ir.ch.kernarg.offset1, align 16, addrspace 4)
- ; CHECK-NEXT: renamable $vgpr0_vgpr1 = COPY killed renamable $sgpr0_sgpr1, implicit $exec
- ; CHECK-NEXT: dead renamable $vgpr0 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load acquire (s32) from %ir.ch.load)
- ; CHECK-NEXT: S_BRANCH %bb.1
- bb.0.entry:
- successors: %bb.2(0x40000000), %bb.1(0x40000000)
- liveins: $sgpr8_sgpr9
-
- renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr100_sgpr101_sgpr102_sgpr103, 0, 0, 0, 0, implicit $exec, debug-location !12 :: (load (s32) from `ptr addrspace(5) null`, addrspace 5)
- renamable $vcc_lo = V_CMP_EQ_U32_e64 0, killed $vgpr0, implicit $exec
- DBG_VALUE $noreg, $noreg, !8, !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef), debug-location !11
- renamable $sgpr0 = COPY $exec_lo, implicit-def $exec_lo
- renamable $sgpr0 = S_AND_B32 killed renamable $sgpr0, killed renamable $vcc_lo, implicit-def dead $scc
- $exec_lo = S_MOV_B32_term killed renamable $sgpr0
- S_CBRANCH_EXECZ %bb.1, implicit $exec
- S_BRANCH %bb.2
-
- bb.1.common.ret:
- S_ENDPGM 0
-
- bb.2.if.end:
- successors: %bb.1(0x80000000)
- liveins: $sgpr8_sgpr9
-
- renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed renamable $sgpr8_sgpr9, 0, 0, debug-location !12 :: (dereferenceable invariant load (s64) from %ir.ch.kernarg.offset1, align 16, addrspace 4)
- renamable $vgpr0_vgpr1 = COPY killed renamable $sgpr0_sgpr1, implicit $exec
- dead renamable $vgpr0 = FLAT_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr :: (load acquire (s32) from %ir.ch.load)
- S_BRANCH %bb.1
-...
diff --git a/llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir b/llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
index 47f13cb5ebe16..12cbbcb02d62a 100644
--- a/llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
+++ b/llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
@@ -1,5 +1,6 @@
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize64 -run-pass=si-optimize-exec-masking -verify-machineinstrs %s -o - | FileCheck --check-prefixes=GCN,GFX1010 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 -run-pass=si-optimize-exec-masking -verify-machineinstrs %s -o - | FileCheck --check-prefixes=GCN,GFX1030 %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -mattr=+wavefrontsize64 -run-pass=mir-debugify,si-optimize-exec-masking,mir-strip-debug -verify-machineinstrs %s -o - | FileCheck --check-prefixes=GCN,GFX1030 %s
---
# After the Optimize exec masking (post-RA) pass, there's a change of having v_cmpx instructions
More information about the llvm-commits
mailing list