[llvm] 3c49429 - AMDGPU/GlobalISel: RegBankLegalize rules for cvt_scale intrinsics (#202075)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 8 04:38:12 PDT 2026
Author: Petar Avramovic
Date: 2026-06-08T13:38:07+02:00
New Revision: 3c49429089efff48e3e1fce53682e6a954ee4cbd
URL: https://github.com/llvm/llvm-project/commit/3c49429089efff48e3e1fce53682e6a954ee4cbd
DIFF: https://github.com/llvm/llvm-project/commit/3c49429089efff48e3e1fce53682e6a954ee4cbd.diff
LOG: AMDGPU/GlobalISel: RegBankLegalize rules for cvt_scale intrinsics (#202075)
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index db5573cb08cf8..3b29b52af02fb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -1516,9 +1516,16 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
case UniInVgprV2S32:
return LLT::fixed_vector(2, 32);
case VgprV3S32:
+ case UniInVgprV3S32:
return LLT::fixed_vector(3, 32);
case VgprV4S16:
return LLT::fixed_vector(4, 16);
+ case VgprV8S16:
+ case UniInVgprV8S16:
+ return LLT::fixed_vector(8, 16);
+ case VgprV16S16:
+ case UniInVgprV16S16:
+ return LLT::fixed_vector(16, 16);
case SgprV4S32:
case SgprV4S32_WF:
case SgprV4S32_ReadFirstLane:
@@ -1526,15 +1533,22 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
case UniInVgprV4S32:
return LLT::fixed_vector(4, 32);
case VgprV8S32:
+ case UniInVgprV8S32:
return LLT::fixed_vector(8, 32);
case VgprV2S64:
case UniInVgprV2S64:
return LLT::fixed_vector(2, 64);
case VgprV6S32:
+ case UniInVgprV6S32:
return LLT::fixed_vector(6, 32);
+ case VgprV16S32:
+ case UniInVgprV16S32:
+ return LLT::fixed_vector(16, 32);
case VgprV32S16:
+ case UniInVgprV32S16:
return LLT::fixed_vector(32, 16);
case VgprV32S32:
+ case UniInVgprV32S32:
return LLT::fixed_vector(32, 32);
default:
return LLT();
@@ -1663,8 +1677,16 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case UniInVgprS64:
case UniInVgprV2S16:
case UniInVgprV2S32:
+ case UniInVgprV3S32:
case UniInVgprV4S32:
case UniInVgprV2S64:
+ case UniInVgprV6S32:
+ case UniInVgprV8S16:
+ case UniInVgprV8S32:
+ case UniInVgprV16S16:
+ case UniInVgprV16S32:
+ case UniInVgprV32S16:
+ case UniInVgprV32S32:
case UniInVgprB32:
case UniInVgprB64:
case UniInVgprB96:
@@ -1698,9 +1720,12 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case VgprV2S64:
case VgprV3S32:
case VgprV4S16:
+ case VgprV8S16:
+ case VgprV16S16:
case VgprV4S32:
case VgprV6S32:
case VgprV8S32:
+ case VgprV16S32:
case VgprV32S16:
case VgprB32:
case VgprB64:
@@ -1765,9 +1790,12 @@ bool RegBankLegalizeHelper::applyMappingDst(
case VgprV2S64:
case VgprV3S32:
case VgprV4S16:
+ case VgprV8S16:
+ case VgprV16S16:
case VgprV4S32:
case VgprV6S32:
case VgprV8S32:
+ case VgprV16S32:
case VgprV32S16: {
assert(Ty == getTyFromID(MethodIDs[OpIdx]));
assert(RB == getRegBankFromID(MethodIDs[OpIdx]));
@@ -1841,8 +1869,16 @@ bool RegBankLegalizeHelper::applyMappingDst(
case UniInVgprS64:
case UniInVgprV2S16:
case UniInVgprV2S32:
+ case UniInVgprV3S32:
case UniInVgprV4S32:
- case UniInVgprV2S64: {
+ case UniInVgprV2S64:
+ case UniInVgprV6S32:
+ case UniInVgprV8S16:
+ case UniInVgprV8S32:
+ case UniInVgprV16S16:
+ case UniInVgprV16S32:
+ case UniInVgprV32S16:
+ case UniInVgprV32S32: {
assert(Ty == getTyFromID(MethodIDs[OpIdx]));
assert(RB == SgprRB);
Register NewVgprDst = MRI.createVirtualRegister({VgprRB, Ty});
@@ -1973,9 +2009,12 @@ bool RegBankLegalizeHelper::applyMappingSrc(
case VgprV2S64:
case VgprV3S32:
case VgprV4S16:
+ case VgprV8S16:
+ case VgprV16S16:
case VgprV4S32:
case VgprV6S32:
case VgprV8S32:
+ case VgprV16S32:
case VgprV32S16:
case VgprV32S32: {
assert(Ty == getTyFromID(MethodIDs[i]));
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index 9d959f17568ee..86eb3217fa996 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -136,6 +136,30 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
case UniV2S32:
return MRI.getType(Reg) == LLT::fixed_vector(2, 32) &&
MUI.isUniformAtDef(Reg);
+ case UniV3S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(3, 32) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV6S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(6, 32) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV8S16:
+ return MRI.getType(Reg) == LLT::fixed_vector(8, 16) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV8S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(8, 32) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV16S16:
+ return MRI.getType(Reg) == LLT::fixed_vector(16, 16) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV16S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(16, 32) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV32S16:
+ return MRI.getType(Reg) == LLT::fixed_vector(32, 16) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV32S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(32, 32) &&
+ MUI.isUniformAtDef(Reg);
case UniB32:
return MRI.getType(Reg).getSizeInBits() == 32 && MUI.isUniformAtDef(Reg);
case UniB64:
@@ -201,9 +225,27 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
case DivV4S16:
return MRI.getType(Reg) == LLT::fixed_vector(4, 16) &&
MUI.isDivergentAtDef(Reg);
+ case DivV8S16:
+ return MRI.getType(Reg) == LLT::fixed_vector(8, 16) &&
+ MUI.isDivergentAtDef(Reg);
+ case DivV8S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(8, 32) &&
+ MUI.isDivergentAtDef(Reg);
+ case DivV16S16:
+ return MRI.getType(Reg) == LLT::fixed_vector(16, 16) &&
+ MUI.isDivergentAtDef(Reg);
+ case DivV16S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(16, 32) &&
+ MUI.isDivergentAtDef(Reg);
case DivV6S32:
return MRI.getType(Reg) == LLT::fixed_vector(6, 32) &&
MUI.isDivergentAtDef(Reg);
+ case DivV32S16:
+ return MRI.getType(Reg) == LLT::fixed_vector(32, 16) &&
+ MUI.isDivergentAtDef(Reg);
+ case DivV32S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(32, 32) &&
+ MUI.isDivergentAtDef(Reg);
case DivB32:
return MRI.getType(Reg).getSizeInBits() == 32 && MUI.isDivergentAtDef(Reg);
case DivB64:
@@ -1869,6 +1911,178 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, VgprV2S32, Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, VgprV2S32, Vgpr32, Vgpr32}});
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_2xpk16_fp6_f32, amdgcn_cvt_scalef32_2xpk16_bf6_f32})
+ .Any(
+ {{DivV6S32}, {{VgprV6S32}, {IntrId, VgprV16S32, VgprV16S32, Vgpr32}}})
+ .Any({{UniV6S32},
+ {{UniInVgprV6S32}, {IntrId, VgprV16S32, VgprV16S32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_f16_fp8, amdgcn_cvt_scalef32_f16_bf8},
+ Standard)
+ .Div(V2S16, {{VgprV2S16}, {IntrId, VgprV2S16, Vgpr32, Vgpr32}})
+ .Uni(V2S16, {{UniInVgprV2S16}, {IntrId, VgprV2S16, Vgpr32, Vgpr32}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_f32_fp8, amdgcn_cvt_scalef32_f32_bf8},
+ Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32}})
+ .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk16_bf6_f16, amdgcn_cvt_scalef32_pk16_fp6_f16},
+ Standard)
+ .Any({{DivV3S32}, {{VgprV3S32}, {IntrId, VgprV16S16, Vgpr32}}})
+ .Any({{UniV3S32}, {{UniInVgprV3S32}, {IntrId, VgprV16S16, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk16_bf6_f32, amdgcn_cvt_scalef32_pk16_fp6_f32},
+ Standard)
+ .Any({{DivV3S32}, {{VgprV3S32}, {IntrId, VgprV16S32, Vgpr32}}})
+ .Any({{UniV3S32}, {{UniInVgprV3S32}, {IntrId, VgprV16S32, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk8_bf8_f16, amdgcn_cvt_scalef32_pk8_fp8_f16},
+ Standard)
+ .Any({{DivV2S32}, {{VgprV2S32}, {IntrId, VgprV8S16, Vgpr32}}})
+ .Any({{UniV2S32}, {{UniInVgprV2S32}, {IntrId, VgprV8S16, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk8_bf8_f32, amdgcn_cvt_scalef32_pk8_fp8_f32},
+ Standard)
+ .Any({{DivV2S32}, {{VgprV2S32}, {IntrId, VgprV8S32, Vgpr32}}})
+ .Any({{UniV2S32}, {{UniInVgprV2S32}, {IntrId, VgprV8S32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_pk8_fp4_f16}, Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, VgprV8S16, Vgpr32}})
+ .Uni(S32, {{UniInVgprS32}, {IntrId, VgprV8S16, Vgpr32}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_pk8_fp4_f32}, Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, VgprV8S32, Vgpr32}})
+ .Uni(S32, {{UniInVgprS32}, {IntrId, VgprV8S32, Vgpr32}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_sr_pk16_bf6_f16,
+ amdgcn_cvt_scalef32_sr_pk16_fp6_f16},
+ Standard)
+ .Any({{DivV3S32}, {{VgprV3S32}, {IntrId, VgprV16S16, Vgpr32, Vgpr32}}})
+ .Any({{UniV3S32},
+ {{UniInVgprV3S32}, {IntrId, VgprV16S16, Vgpr32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_sr_pk16_bf6_f32,
+ amdgcn_cvt_scalef32_sr_pk16_fp6_f32},
+ Standard)
+ .Any({{DivV3S32}, {{VgprV3S32}, {IntrId, VgprV16S32, Vgpr32, Vgpr32}}})
+ .Any({{UniV3S32},
+ {{UniInVgprV3S32}, {IntrId, VgprV16S32, Vgpr32, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_sr_pk8_bf8_f16, amdgcn_cvt_scalef32_sr_pk8_fp8_f16},
+ Standard)
+ .Any({{DivV2S32}, {{VgprV2S32}, {IntrId, VgprV8S16, Vgpr32, Vgpr32}}})
+ .Any({{UniV2S32},
+ {{UniInVgprV2S32}, {IntrId, VgprV8S16, Vgpr32, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_sr_pk8_bf8_f32, amdgcn_cvt_scalef32_sr_pk8_fp8_f32},
+ Standard)
+ .Any({{DivV2S32}, {{VgprV2S32}, {IntrId, VgprV8S32, Vgpr32, Vgpr32}}})
+ .Any({{UniV2S32},
+ {{UniInVgprV2S32}, {IntrId, VgprV8S32, Vgpr32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_sr_pk8_fp4_f16}, Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, VgprV8S16, Vgpr32, Vgpr32}})
+ .Uni(S32, {{UniInVgprS32}, {IntrId, VgprV8S16, Vgpr32, Vgpr32}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_sr_pk8_fp4_f32}, Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, VgprV8S32, Vgpr32, Vgpr32}})
+ .Uni(S32, {{UniInVgprS32}, {IntrId, VgprV8S32, Vgpr32, Vgpr32}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scale_pk16_f16_bf6, amdgcn_cvt_scale_pk16_f16_fp6}, Standard)
+ .Any({{DivV16S16}, {{VgprV16S16}, {IntrId, VgprV3S32, Vgpr32}}})
+ .Any({{UniV16S16}, {{UniInVgprV16S16}, {IntrId, VgprV3S32, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scale_pk16_f32_bf6, amdgcn_cvt_scale_pk16_f32_fp6}, Standard)
+ .Any({{DivV16S32}, {{VgprV16S32}, {IntrId, VgprV3S32, Vgpr32}}})
+ .Any({{UniV16S32}, {{UniInVgprV16S32}, {IntrId, VgprV3S32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scale_pk8_f16_bf8, amdgcn_cvt_scale_pk8_f16_fp8},
+ Standard)
+ .Any({{DivV8S16}, {{VgprV8S16}, {IntrId, VgprV2S32, Vgpr32}}})
+ .Any({{UniV8S16}, {{UniInVgprV8S16}, {IntrId, VgprV2S32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scale_pk8_f16_fp4}, Standard)
+ .Any({{DivV8S16}, {{VgprV8S16}, {IntrId, Vgpr32, Vgpr32}}})
+ .Any({{UniV8S16}, {{UniInVgprV8S16}, {IntrId, Vgpr32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scale_pk8_f32_bf8, amdgcn_cvt_scale_pk8_f32_fp8},
+ Standard)
+ .Any({{DivV8S32}, {{VgprV8S32}, {IntrId, VgprV2S32, Vgpr32}}})
+ .Any({{UniV8S32}, {{UniInVgprV8S32}, {IntrId, VgprV2S32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scale_pk8_f32_fp4}, Standard)
+ .Any({{DivV8S32}, {{VgprV8S32}, {IntrId, Vgpr32, Vgpr32}}})
+ .Any({{UniV8S32}, {{UniInVgprV8S32}, {IntrId, Vgpr32, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk32_bf6_f16, amdgcn_cvt_scalef32_pk32_fp6_f16},
+ Standard)
+ .Any({{DivV6S32}, {{VgprV6S32}, {IntrId, VgprV32S16, Vgpr32}}})
+ .Any({{UniV6S32}, {{UniInVgprV6S32}, {IntrId, VgprV32S16, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk_fp8_f32, amdgcn_cvt_scalef32_pk_bf8_f32},
+ Standard)
+ .Div(V2S16,
+ {{VgprV2S16}, {IntrId, VgprV2S16, Vgpr32, Vgpr32, Vgpr32, Imm}})
+ .Uni(V2S16, {{UniInVgprV2S16},
+ {IntrId, VgprV2S16, Vgpr32, Vgpr32, Vgpr32, Imm}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk_f32_fp8, amdgcn_cvt_scalef32_pk_f32_bf8},
+ Standard)
+ .Any({{DivV2S32}, {{VgprV2S32}, {IntrId, Vgpr32, Vgpr32, Imm}}})
+ .Any({{UniV2S32}, {{UniInVgprV2S32}, {IntrId, Vgpr32, Vgpr32, Imm}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk_fp8_f16, amdgcn_cvt_scalef32_pk_bf8_f16},
+ Standard)
+ .Div(V2S16, {{VgprV2S16}, {IntrId, VgprV2S16, VgprV2S16, Vgpr32, Imm}})
+ .Uni(V2S16,
+ {{UniInVgprV2S16}, {IntrId, VgprV2S16, VgprV2S16, Vgpr32, Imm}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_pk_f32_fp4}, Standard)
+ .Any({{DivV2S32}, {{VgprV2S32}, {IntrId, Vgpr32, Vgpr32, Imm}}})
+ .Any({{UniV2S32}, {{UniInVgprV2S32}, {IntrId, Vgpr32, Vgpr32, Imm}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_pk_fp4_f32}, Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Imm}})
+ .Uni(S32,
+ {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Imm}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_pk_f16_fp4,
+ amdgcn_cvt_scalef32_pk_f16_fp8,
+ amdgcn_cvt_scalef32_pk_f16_bf8},
+ Standard)
+ .Div(V2S16, {{VgprV2S16}, {IntrId, Vgpr32, Vgpr32, Imm}})
+ .Uni(V2S16, {{UniInVgprV2S16}, {IntrId, Vgpr32, Vgpr32, Imm}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk32_f32_fp6, amdgcn_cvt_scalef32_pk32_f32_bf6},
+ Standard)
+ .Any({{DivV32S32}, {{VgprV32S32}, {IntrId, VgprV6S32, Vgpr32}}})
+ .Any({{UniV32S32}, {{UniInVgprV32S32}, {IntrId, VgprV6S32, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk32_f16_fp6, amdgcn_cvt_scalef32_pk32_f16_bf6},
+ Standard)
+ .Any({{DivV32S16}, {{VgprV32S16}, {IntrId, VgprV6S32, Vgpr32}}})
+ .Any({{UniV32S16}, {{UniInVgprV32S16}, {IntrId, VgprV6S32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_pk_fp4_f16}, Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, Vgpr32, VgprV2S16, Vgpr32, Imm}})
+ .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, VgprV2S16, Vgpr32, Imm}});
+
addRulesForIOpcs({amdgcn_global_load_tr_b64})
.Any({{DivB64, _, UniP1}, {{VgprB64}, {IntrId, SgprP1}}})
.Any({{DivB64, _, DivP1}, {{VgprB64}, {IntrId, VgprP1}}})
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index d7684d16676a0..d9b1dd6289376 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -100,17 +100,32 @@ enum UniformityLLTOpPredicateID {
V2S64,
V3S32,
V4S32,
+ V32S32,
UniV2S16,
UniV2S32,
UniV2S64,
+ UniV3S32,
+ UniV6S32,
+ UniV8S16,
+ UniV8S32,
+ UniV16S16,
+ UniV16S32,
+ UniV32S16,
+ UniV32S32,
DivV2S16,
DivV2S32,
DivV2S64,
DivV3S32,
DivV4S16,
+ DivV8S16,
+ DivV8S32,
+ DivV16S16,
+ DivV16S32,
DivV6S32,
+ DivV32S16,
+ DivV32S32,
// B types
B32,
@@ -208,6 +223,8 @@ enum RegBankLLTMappingApplyID {
VgprB512,
VgprBRC,
VgprV4S16,
+ VgprV8S16,
+ VgprV16S16,
VgprV4S32,
VgprV8S32,
VgprV2S64,
@@ -219,8 +236,16 @@ enum RegBankLLTMappingApplyID {
UniInVgprS64,
UniInVgprV2S16,
UniInVgprV2S32,
+ UniInVgprV3S32,
UniInVgprV4S32,
UniInVgprV2S64,
+ UniInVgprV6S32,
+ UniInVgprV8S16,
+ UniInVgprV8S32,
+ UniInVgprV16S16,
+ UniInVgprV16S32,
+ UniInVgprV32S16,
+ UniInVgprV32S32,
UniInVgprB32,
UniInVgprB64,
UniInVgprB96,
@@ -265,6 +290,7 @@ enum RegBankLLTMappingApplyID {
Vgpr32ZExt,
VgprV6S32,
+ VgprV16S32,
VgprV32S16,
VgprV32S32,
};
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
index 651917bf240ea..8193fec395eb2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
declare <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp8(<2 x i32> %src, i32 %scale, i32 %scale_sel)
declare <8 x bfloat> @llvm.amdgcn.cvt.scale.pk8.bf16.fp8(<2 x i32> %src, i32 %scale, i32 %scale_sel)
@@ -39,6 +39,29 @@ define amdgpu_ps void @test_cvt_scale_pk8_f16_fp8_vv(<2 x i32> %src, i32 %scale,
ret void
}
+define amdgpu_ps void @test_cvt_scale_pk8_f16_fp8_ss(<2 x i32> inreg %src, i32 inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f16_fp8_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f16_fp8 v[2:5], v[6:7], s2 scale_sel:1
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f16_fp8_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f16_fp8 v[2:5], v[6:7], s2 scale_sel:1
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp8(<2 x i32> %src, i32 %scale, i32 1)
+ store <8 x half> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_cvt_scale_pk8_f16_bf8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f16_bf8_vv:
; GFX1250-SDAG: ; %bb.0:
@@ -60,6 +83,29 @@ define amdgpu_ps void @test_cvt_scale_pk8_f16_bf8_vv(<2 x i32> %src, i32 %scale,
ret void
}
+define amdgpu_ps void @test_cvt_scale_pk8_f16_bf8_ss(<2 x i32> inreg %src, i32 inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f16_bf8_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f16_bf8 v[2:5], v[6:7], s2
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f16_bf8_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f16_bf8 v[2:5], v[6:7], s2
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.bf8(<2 x i32> %src, i32 %scale, i32 0)
+ store <8 x half> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_cvt_scale_pk8_bf16_fp8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_cvt_scale_pk8_bf16_fp8_vv:
; GFX1250: ; %bb.0:
@@ -98,6 +144,20 @@ define amdgpu_ps void @test_cvt_scale_pk8_f16_fp4_vv(i32 %src, i32 %scale, ptr a
ret void
}
+define amdgpu_ps void @test_cvt_scale_pk8_f16_fp4_ss(i32 inreg %src, i32 inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-LABEL: test_cvt_scale_pk8_f16_fp4_ss:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: v_mov_b32_e32 v2, s0
+; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-NEXT: v_cvt_scale_pk8_f16_fp4 v[2:5], v2, s1 scale_sel:3
+; GFX1250-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-NEXT: s_endpgm
+ %cvt = tail call <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp4(i32 %src, i32 %scale, i32 3)
+ store <8 x half> %cvt, ptr addrspace(1) %out, align 16
+ ret void
+}
+
define amdgpu_ps void @test_cvt_scale_pk8_bf16_fp4_vv(i32 %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_cvt_scale_pk8_bf16_fp4_vv:
; GFX1250: ; %bb.0:
@@ -135,6 +195,48 @@ define amdgpu_ps void @test_cvt_scale_pk8_f32_fp8_vv(<2 x i32> %src, i32 %scale,
ret void
}
+define amdgpu_ps void @test_cvt_scale_pk8_f32_fp8_ss(<2 x i32> inreg %src, i32 inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f32_fp8_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f32_fp8 v[2:9], v[10:11], s2 scale_sel:8
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f32_fp8_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f32_fp8 v[2:9], v[10:11], s2 scale_sel:8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: s_clause 0x1
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <8 x float> @llvm.amdgcn.cvt.scale.pk8.f32.fp8(<2 x i32> %src, i32 %scale, i32 8)
+ store <8 x float> %cvt, ptr addrspace(1) %out, align 16
+ ret void
+}
+
define amdgpu_ps void @test_cvt_scale_pk8_f32_bf8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f32_bf8_vv:
; GFX1250-SDAG: ; %bb.0:
@@ -160,6 +262,48 @@ define amdgpu_ps void @test_cvt_scale_pk8_f32_bf8_vv(<2 x i32> %src, i32 %scale,
ret void
}
+define amdgpu_ps void @test_cvt_scale_pk8_f32_bf8_ss(<2 x i32> inreg %src, i32 inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f32_bf8_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f32_bf8 v[2:9], v[10:11], s2
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f32_bf8_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f32_bf8 v[2:9], v[10:11], s2
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: s_clause 0x1
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <8 x float> @llvm.amdgcn.cvt.scale.pk8.f32.bf8(<2 x i32> %src, i32 %scale, i32 0)
+ store <8 x float> %cvt, ptr addrspace(1) %out, align 16
+ ret void
+}
+
define amdgpu_ps void @test_cvt_scale_pk8_f32_fp4_vv(i32 %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f32_fp4_vv:
; GFX1250-SDAG: ; %bb.0:
@@ -183,6 +327,48 @@ define amdgpu_ps void @test_cvt_scale_pk8_f32_fp4_vv(i32 %src, i32 %scale, ptr a
ret void
}
+define amdgpu_ps void @test_cvt_scale_pk8_f32_fp4_ss(i32 inreg %src, i32 inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f32_fp4_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f32_fp4 v[2:9], v2, s1 scale_sel:1
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f32_fp4_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f32_fp4 v[2:9], v2, s1 scale_sel:1
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: s_clause 0x1
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <8 x float> @llvm.amdgcn.cvt.scale.pk8.f32.fp4(i32 %src, i32 %scale, i32 1)
+ store <8 x float> %cvt, ptr addrspace(1) %out, align 32
+ ret void
+}
+
define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_fp6_vv:
; GFX1250-SDAG: ; %bb.0:
@@ -206,6 +392,50 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_vv(<3 x i32> %src, i32 %scale
ret void
}
+define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_ss(<3 x i32> inreg %src, i32 inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_fp6_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v12, s2
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f16_fp6 v[2:9], v[10:12], s3
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_fp6_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_fp6 v[2:9], v[10:12], s3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: s_clause 0x1
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.fp6(<3 x i32> %src, i32 %scale, i32 0)
+ store <16 x half> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_fp6_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -224,8 +454,23 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_fp6_sl(<3 x i32> inreg %src, ptr
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_fp6 v[2:9], v[10:12], 0x64 scale_sel:1
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
@@ -289,6 +534,50 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_vv(<3 x i32> %src, i32 %scale
ret void
}
+define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_ss(<3 x i32> inreg %src, i32 inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_bf6_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s0 :: v_dual_mov_b32 v11, s1
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v12, s2
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f16_bf6 v[2:9], v[10:12], s3 scale_sel:4
+; GFX1250-SDAG-NEXT: s_clause 0x1
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f16_bf6_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_bf6 v[2:9], v[10:12], s3 scale_sel:4
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: s_clause 0x1
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <16 x half> @llvm.amdgcn.cvt.scale.pk16.f16.bf6(<3 x i32> %src, i32 %scale, i32 4)
+ store <16 x half> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_sl(<3 x i32> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f16_bf6_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -307,8 +596,23 @@ define amdgpu_ps void @test_cvt_scale_pk16_f16_bf6_sl(<3 x i32> inreg %src, ptr
; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-NEXT: v_dual_mov_b32 v12, s2 :: v_dual_mov_b32 v11, s1
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v10, s0
-; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f16_bf6 v[2:9], v[10:12], 0x64 scale_sel:5
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
; GFX1250-GISEL-NEXT: s_clause 0x1
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
@@ -376,6 +680,65 @@ define amdgpu_ps void @test_cvt_scale_pk16_f32_fp6_vv(<3 x i32> %src, i32 %scale
ret void
}
+define amdgpu_ps void @test_cvt_scale_pk16_f32_fp6_ss(<3 x i32> inreg %src, i32 inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f32_fp6_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v18, s0 :: v_dual_mov_b32 v19, s1
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v20, s2
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f32_fp6 v[2:17], v[18:20], s3 scale_sel:5
+; GFX1250-SDAG-NEXT: s_clause 0x3
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[14:17], off offset:48
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[10:13], off offset:32
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f32_fp6_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v20, s2 :: v_dual_mov_b32 v19, s1
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v18, s0
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f32_fp6 v[2:17], v[18:20], s3 scale_sel:5
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v12
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v13
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v10
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v11
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s14, v16
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s15, v17
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s12, v14
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s13, v15
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
+; GFX1250-GISEL-NEXT: s_clause 0x3
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[10:13], off offset:32
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[14:17], off offset:48
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <16 x float> @llvm.amdgcn.cvt.scale.pk16.f32.fp6(<3 x i32> %src, i32 %scale, i32 5)
+ store <16 x float> %cvt, ptr addrspace(1) %out, align 16
+ ret void
+}
+
define amdgpu_ps void @test_cvt_scale_pk16_f32_bf6_vv(<3 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f32_bf6_vv:
; GFX1250-SDAG: ; %bb.0:
@@ -402,3 +765,62 @@ define amdgpu_ps void @test_cvt_scale_pk16_f32_bf6_vv(<3 x i32> %src, i32 %scale
store <16 x float> %cvt, ptr addrspace(1) %out, align 16
ret void
}
+
+define amdgpu_ps void @test_cvt_scale_pk16_f32_bf6_ss(<3 x i32> inreg %src, i32 inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_cvt_scale_pk16_f32_bf6_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v18, s0 :: v_dual_mov_b32 v19, s1
+; GFX1250-SDAG-NEXT: v_mov_b32_e32 v20, s2
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scale_pk16_f32_bf6 v[2:17], v[18:20], s3 scale_sel:6
+; GFX1250-SDAG-NEXT: s_clause 0x3
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[14:17], off offset:48
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[10:13], off offset:32
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_cvt_scale_pk16_f32_bf6_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_dual_mov_b32 v20, s2 :: v_dual_mov_b32 v19, s1
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v18, s0
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scale_pk16_f32_bf6 v[2:17], v[18:20], s3 scale_sel:6
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v4
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v5
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s6, v8
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s7, v9
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v6
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v7
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s10, v12
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s11, v13
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s8, v10
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s9, v11
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s14, v16
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s15, v17
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s12, v14
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s13, v15
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
+; GFX1250-GISEL-NEXT: s_clause 0x3
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[6:9], off offset:16
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[10:13], off offset:32
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[14:17], off offset:48
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <16 x float> @llvm.amdgcn.cvt.scale.pk16.f32.bf6(<3 x i32> %src, i32 %scale, i32 6)
+ store <16 x float> %cvt, ptr addrspace(1) %out, align 16
+ ret void
+}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
index d6ab24646d784..39141ffecf484 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefixes=GCN,GFX950-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefixes=GCN,GFX950-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck --check-prefixes=GCN,GFX950-GISEL %s
declare <6 x i32> @llvm.amdgcn.cvt.scalef32.2xpk16.bf6.f32(<16 x float> %src0, <16 x float> %src1, float %scale)
declare <6 x i32> @llvm.amdgcn.cvt.scalef32.2xpk16.fp6.f32(<16 x float> %src0, <16 x float> %src1, float %scale)
@@ -85,8 +85,19 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f32_sl(<16 x float> inreg %src, pt
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_2xpk16_fp6_f32 v[18:23], v[2:17], v[2:17], v24
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX950-GISEL-NEXT: s_nop 1
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:16
; GFX950-GISEL-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.2xpk16.fp6.f32(<16 x float> %src, <16 x float> %src, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
@@ -145,8 +156,19 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f32_sl(<16 x float> inreg %src, pt
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_2xpk16_bf6_f32 v[18:23], v[2:17], v[2:17], v24
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX950-GISEL-NEXT: s_nop 1
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:16
; GFX950-GISEL-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.2xpk16.bf6.f32(<16 x float> %src, <16 x float> %src, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
@@ -962,61 +984,35 @@ define <2 x bfloat> @test_cvt_scale_bf16_fp4_byte3(i32 %src, float %scale) {
}
define <32 x float> @test_cvt_scale_pk32_f32_fp6(<6 x i32> %src, float %scale) {
-; GFX950-SDAG-LABEL: test_cvt_scale_pk32_f32_fp6:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v38, v6
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v37, v5
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v36, v4
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v35, v3
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v34, v2
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v33, v1
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v32, v0
-; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_f32_fp6 v[0:31], v[32:37], v38
-; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX950-GISEL-LABEL: test_cvt_scale_pk32_f32_fp6:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v32, v0
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v33, v1
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v34, v2
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v35, v3
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v36, v4
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v37, v5
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v38, v6
-; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_f32_fp6 v[0:31], v[32:37], v38
-; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: test_cvt_scale_pk32_f32_fp6:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v38, v6
+; GCN-NEXT: v_mov_b32_e32 v37, v5
+; GCN-NEXT: v_mov_b32_e32 v36, v4
+; GCN-NEXT: v_mov_b32_e32 v35, v3
+; GCN-NEXT: v_mov_b32_e32 v34, v2
+; GCN-NEXT: v_mov_b32_e32 v33, v1
+; GCN-NEXT: v_mov_b32_e32 v32, v0
+; GCN-NEXT: v_cvt_scalef32_pk32_f32_fp6 v[0:31], v[32:37], v38
+; GCN-NEXT: s_setpc_b64 s[30:31]
%ret = tail call <32 x float> @llvm.amdgcn.cvt.scalef32.pk32.f32.fp6(<6 x i32> %src, float %scale)
ret <32 x float> %ret
}
define <32 x float> @test_cvt_scale_pk32_f32_bf6(<6 x i32> %src, float %scale) {
-; GFX950-SDAG-LABEL: test_cvt_scale_pk32_f32_bf6:
-; GFX950-SDAG: ; %bb.0:
-; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v38, v6
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v37, v5
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v36, v4
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v35, v3
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v34, v2
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v33, v1
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v32, v0
-; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_f32_bf6 v[0:31], v[32:37], v38
-; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX950-GISEL-LABEL: test_cvt_scale_pk32_f32_bf6:
-; GFX950-GISEL: ; %bb.0:
-; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v32, v0
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v33, v1
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v34, v2
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v35, v3
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v36, v4
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v37, v5
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v38, v6
-; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_f32_bf6 v[0:31], v[32:37], v38
-; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GCN-LABEL: test_cvt_scale_pk32_f32_bf6:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v38, v6
+; GCN-NEXT: v_mov_b32_e32 v37, v5
+; GCN-NEXT: v_mov_b32_e32 v36, v4
+; GCN-NEXT: v_mov_b32_e32 v35, v3
+; GCN-NEXT: v_mov_b32_e32 v34, v2
+; GCN-NEXT: v_mov_b32_e32 v33, v1
+; GCN-NEXT: v_mov_b32_e32 v32, v0
+; GCN-NEXT: v_cvt_scalef32_pk32_f32_bf6 v[0:31], v[32:37], v38
+; GCN-NEXT: s_setpc_b64 s[30:31]
%ret = tail call <32 x float> @llvm.amdgcn.cvt.scalef32.pk32.f32.bf6(<6 x i32> %src, float %scale)
ret <32 x float> %ret
}
@@ -1474,6 +1470,52 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f32_vv_inreg_src(<16 x float> inre
ret void
}
+define amdgpu_ps void @test_scalef32_pk32_fp6_f32_ss(<16 x float> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_f32_ss:
+; GFX950-SDAG: ; %bb.0:
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-SDAG-NEXT: v_cvt_scalef32_2xpk16_fp6_f32 v[18:23], v[2:17], v[2:17], s16
+; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
+; GFX950-SDAG-NEXT: s_endpgm
+;
+; GFX950-GISEL-LABEL: test_scalef32_pk32_fp6_f32_ss:
+; GFX950-GISEL: ; %bb.0:
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: v_cvt_scalef32_2xpk16_fp6_f32 v[18:23], v[2:17], v[2:17], s16
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX950-GISEL-NEXT: s_nop 1
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:16
+; GFX950-GISEL-NEXT: s_endpgm
+ %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.2xpk16.fp6.f32(<16 x float> %src, <16 x float> %src, float %scale)
+ store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk32_fp6_f32_sl_inreg_src(<16 x float> inreg %src, ptr addrspace(1) %out) {
; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_f32_sl_inreg_src:
; GFX950-SDAG: ; %bb.0:
@@ -1503,8 +1545,19 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f32_sl_inreg_src(<16 x float> inre
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_2xpk16_fp6_f32 v[18:23], v[2:17], v[2:17], v24
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX950-GISEL-NEXT: s_nop 1
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:16
; GFX950-GISEL-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.2xpk16.fp6.f32(<16 x float> %src, <16 x float> %src, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
@@ -1550,6 +1603,52 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f32_vv_inreg_src(<16 x float> inre
ret void
}
+define amdgpu_ps void @test_scalef32_pk32_bf6_f32_ss(<16 x float> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_f32_ss:
+; GFX950-SDAG: ; %bb.0:
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-SDAG-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-SDAG-NEXT: v_cvt_scalef32_2xpk16_bf6_f32 v[18:23], v[2:17], v[2:17], s16
+; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
+; GFX950-SDAG-NEXT: s_endpgm
+;
+; GFX950-GISEL-LABEL: test_scalef32_pk32_bf6_f32_ss:
+; GFX950-GISEL: ; %bb.0:
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: v_cvt_scalef32_2xpk16_bf6_f32 v[18:23], v[2:17], v[2:17], s16
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX950-GISEL-NEXT: s_nop 1
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:16
+; GFX950-GISEL-NEXT: s_endpgm
+ %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.2xpk16.bf6.f32(<16 x float> %src, <16 x float> %src, float %scale)
+ store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk32_bf6_f32_sl_inreg_src(<16 x float> inreg inreg %src, ptr addrspace(1) %out) {
; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_f32_sl_inreg_src:
; GFX950-SDAG: ; %bb.0:
@@ -1579,8 +1678,19 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f32_sl_inreg_src(<16 x float> inre
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_2xpk16_bf6_f32 v[18:23], v[2:17], v[2:17], v24
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX950-GISEL-NEXT: s_nop 1
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:16
; GFX950-GISEL-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.2xpk16.bf6.f32(<16 x float> %src, <16 x float> %src, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
@@ -1598,6 +1708,18 @@ define <2 x half> @test_cvt_scalef32_f16_fp8_byte0_dst_lo_inreg_src(i32 inreg %s
ret <2 x half> %ret
}
+define <2 x half> @test_cvt_scalef32_f16_fp8_byte0_dst_lo_ss(i32 inreg %src, float inreg %scale, <2 x half> inreg %old) {
+; GCN-LABEL: test_cvt_scalef32_f16_fp8_byte0_dst_lo_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_cvt_scalef32_f16_fp8 v0, s0, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <2 x half> @llvm.amdgcn.cvt.scalef32.f16.fp8(<2 x half> %old, i32 %src, float %scale, i32 0, i1 false)
+ ret <2 x half> %ret
+}
+
define <2 x half> @test_cvt_scalef32_f16_fp8_byte1_dst_lo_inreg_src(i32 inreg %src, float %scale, <2 x half> %old) {
; GCN-LABEL: test_cvt_scalef32_f16_fp8_byte1_dst_lo_inreg_src:
; GCN: ; %bb.0:
@@ -1689,6 +1811,17 @@ define float @test_cvt_scalef32_f32_fp8_byte0_inreg_src(i32 inreg %src, float %s
ret float %ret
}
+define float @test_cvt_scalef32_f32_fp8_byte0_ss(i32 inreg %src, float inreg %scale) {
+; GCN-LABEL: test_cvt_scalef32_f32_fp8_byte0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_cvt_scalef32_f32_fp8 v0, s0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call float @llvm.amdgcn.cvt.scalef32.f32.fp8(i32 %src, float %scale, i32 0)
+ ret float %ret
+}
+
define float @test_cvt_scalef32_f32_fp8_byte1_inreg_src(i32 inreg %src, float %scale) {
; GCN-LABEL: test_cvt_scalef32_f32_fp8_byte1_inreg_src:
; GCN: ; %bb.0:
@@ -1730,6 +1863,18 @@ define <2 x half> @test_cvt_scalef32_f16_bf8_byte0_dst_lo_inreg_src(i32 inreg %s
ret <2 x half> %ret
}
+define <2 x half> @test_cvt_scalef32_f16_bf8_byte0_dst_lo_ss(i32 inreg %src, float inreg %scale, <2 x half> inreg %old) {
+; GCN-LABEL: test_cvt_scalef32_f16_bf8_byte0_dst_lo_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_cvt_scalef32_f16_bf8 v0, s0, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <2 x half> @llvm.amdgcn.cvt.scalef32.f16.bf8(<2 x half> %old, i32 %src, float %scale, i32 0, i1 false)
+ ret <2 x half> %ret
+}
+
define <2 x half> @test_cvt_scalef32_f16_bf8_byte1_dst_lo_inreg_src(i32 inreg %src, float %scale, <2 x half> %old) {
; GCN-LABEL: test_cvt_scalef32_f16_bf8_byte1_dst_lo_inreg_src:
; GCN: ; %bb.0:
@@ -1821,6 +1966,17 @@ define float @test_cvt_scalef32_f32_bf8_byte0_inreg_src(i32 inreg %src, float %s
ret float %ret
}
+define float @test_cvt_scalef32_f32_bf8_byte0_ss(i32 inreg %src, float inreg %scale) {
+; GCN-LABEL: test_cvt_scalef32_f32_bf8_byte0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_cvt_scalef32_f32_bf8 v0, s0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call float @llvm.amdgcn.cvt.scalef32.f32.bf8(i32 %src, float %scale, i32 0)
+ ret float %ret
+}
+
define float @test_cvt_scalef32_f32_bf8_byte1_inreg_src(i32 inreg %src, float %scale) {
; GCN-LABEL: test_cvt_scalef32_f32_bf8_byte1_inreg_src:
; GCN: ; %bb.0:
@@ -1863,6 +2019,19 @@ define <2 x i16> @test_cvt_scalef32_pk_fp8_f32_word0_inreg_src(<2 x i16> inreg %
ret <2 x i16> %ret
}
+define <2 x i16> @test_cvt_scalef32_pk_fp8_f32_word0_ss(<2 x i16> inreg %old, float inreg %src0, float inreg %src1, float inreg %scale) {
+; GCN-LABEL: test_cvt_scalef32_pk_fp8_f32_word0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_mov_b32_e32 v2, s3
+; GCN-NEXT: v_cvt_scalef32_pk_fp8_f32 v0, s1, v1, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <2 x i16> @llvm.amdgcn.cvt.scalef32.pk.fp8.f32(<2 x i16> %old, float %src0, float %src1, float %scale, i1 false)
+ ret <2 x i16> %ret
+}
+
define <2 x i16> @test_cvt_scalef32_pk_fp8_f32_word1_inreg_src(<2 x i16> inreg %old, float %src0, float %src1, float %scale) {
; GCN-LABEL: test_cvt_scalef32_pk_fp8_f32_word1_inreg_src:
; GCN: ; %bb.0:
@@ -1888,6 +2057,19 @@ define <2 x i16> @test_cvt_scalef32_pk_bf8_f32_word0_inreg_src(<2 x i16> inreg %
ret <2 x i16> %ret
}
+define <2 x i16> @test_cvt_scalef32_pk_bf8_f32_word0_ss(<2 x i16> inreg %old, float inreg %src0, float inreg %src1, float inreg %scale) {
+; GCN-LABEL: test_cvt_scalef32_pk_bf8_f32_word0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_mov_b32_e32 v2, s3
+; GCN-NEXT: v_cvt_scalef32_pk_bf8_f32 v0, s1, v1, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <2 x i16> @llvm.amdgcn.cvt.scalef32.pk.bf8.f32(<2 x i16> %old, float %src0, float %src1, float %scale, i1 false)
+ ret <2 x i16> %ret
+}
+
define <2 x i16> @test_cvt_scalef32_pk_bf8_f32_word1_inreg_src(<2 x i16> %old, float inreg %src0, float %src1, float %scale) {
; GCN-LABEL: test_cvt_scalef32_pk_bf8_f32_word1_inreg_src:
; GCN: ; %bb.0:
@@ -1908,6 +2090,17 @@ define <2 x float> @test_cvt_scalef32_pk_f32_fp8_word0_inreg_src(i32 inreg %src,
ret <2 x float> %ret
}
+define <2 x float> @test_cvt_scalef32_pk_f32_fp8_word0_ss(i32 inreg %src, float inreg %scale) {
+; GCN-LABEL: test_cvt_scalef32_pk_f32_fp8_word0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_cvt_scalef32_pk_f32_fp8 v[0:1], s0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <2 x float> @llvm.amdgcn.cvt.scalef32.pk.f32.fp8(i32 %src, float %scale, i1 false)
+ ret <2 x float> %ret
+}
+
define <2 x float> @test_cvt_scalef32_pk_f32_fp8_word1_inreg_src(i32 inreg %src, float %scale) {
; GCN-LABEL: test_cvt_scalef32_pk_f32_fp8_word1_inreg_src:
; GCN: ; %bb.0:
@@ -1928,6 +2121,17 @@ define <2 x float> @test_cvt_scalef32_pk_f32_bf8_word0_inreg_src(i32 inreg %src,
ret <2 x float> %ret
}
+define <2 x float> @test_cvt_scalef32_pk_f32_bf8_word0_ss(i32 inreg %src, float inreg %scale) {
+; GCN-LABEL: test_cvt_scalef32_pk_f32_bf8_word0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_cvt_scalef32_pk_f32_bf8 v[0:1], s0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <2 x float> @llvm.amdgcn.cvt.scalef32.pk.f32.bf8(i32 %src, float %scale, i1 false)
+ ret <2 x float> %ret
+}
+
define <2 x float> @test_cvt_scalef32_pk_f32_bf8_word1_inreg_src(i32 inreg %src, float %scale) {
; GCN-LABEL: test_cvt_scalef32_pk_f32_bf8_word1_inreg_src:
; GCN: ; %bb.0:
@@ -1948,6 +2152,18 @@ define <2 x i16> @test_cvt_scalef32_pk_fp8_f16_word0_inreg_src(<2 x i16> %old, <
ret <2 x i16> %ret
}
+define <2 x i16> @test_cvt_scalef32_pk_fp8_f16_word0_ss(<2 x i16> inreg %old, <2 x half> inreg %src, float inreg %scale) {
+; GCN-LABEL: test_cvt_scalef32_pk_fp8_f16_word0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_cvt_scalef32_pk_fp8_f16 v0, s1, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <2 x i16> @llvm.amdgcn.cvt.scalef32.pk.fp8.f16(<2 x i16> %old, <2 x half> %src, float %scale, i1 false)
+ ret <2 x i16> %ret
+}
+
define <2 x i16> @test_cvt_scalef32_pk_fp8_f16_word1_inreg_src(<2 x i16> %old, <2 x half> inreg %src, float %scale) {
; GCN-LABEL: test_cvt_scalef32_pk_fp8_f16_word1_inreg_src:
; GCN: ; %bb.0:
@@ -1988,6 +2204,18 @@ define <2 x i16> @test_cvt_scalef32_pk_bf8_f16_word0_inreg_src(<2 x i16> %old, <
ret <2 x i16> %ret
}
+define <2 x i16> @test_cvt_scalef32_pk_bf8_f16_word0_ss(<2 x i16> inreg %old, <2 x half> inreg %src, float inreg %scale) {
+; GCN-LABEL: test_cvt_scalef32_pk_bf8_f16_word0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_cvt_scalef32_pk_bf8_f16 v0, s1, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <2 x i16> @llvm.amdgcn.cvt.scalef32.pk.bf8.f16(<2 x i16> %old, <2 x half> %src, float %scale, i1 false)
+ ret <2 x i16> %ret
+}
+
define <2 x i16> @test_cvt_scalef32_pk_bf8_f16_word1_inreg_src(<2 x i16> %old, <2 x half> inreg %src, float %scale) {
; GCN-LABEL: test_cvt_scalef32_pk_bf8_f16_word1_inreg_src:
; GCN: ; %bb.0:
@@ -2028,6 +2256,17 @@ define <2 x float> @test_cvt_scale_f32_fp4_byte0_inreg_src(i32 inreg %src, float
ret <2 x float> %ret
}
+define <2 x float> @test_cvt_scale_f32_fp4_byte0_ss(i32 inreg %src, float inreg %scale) {
+; GCN-LABEL: test_cvt_scale_f32_fp4_byte0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_cvt_scalef32_pk_f32_fp4 v[0:1], s0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <2 x float> @llvm.amdgcn.cvt.scalef32.pk.f32.fp4(i32 %src, float %scale, i32 0)
+ ret <2 x float> %ret
+}
+
define <2 x float> @test_cvt_scale_f32_fp4_byte1_inreg_src(i32 inreg %src, float %scale) {
; GCN-LABEL: test_cvt_scale_f32_fp4_byte1_inreg_src:
; GCN: ; %bb.0:
@@ -2068,6 +2307,19 @@ define i32 @test_cvt_scale_fp4_f32_byte0_inreg_src(i32 %old, float inreg %src0,
ret i32 %ret
}
+define i32 @test_cvt_scale_fp4_f32_byte0_ss(i32 inreg %old, float inreg %src0, float inreg %src1, float inreg %scale) {
+; GCN-LABEL: test_cvt_scale_fp4_f32_byte0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NEXT: v_mov_b32_e32 v1, s2
+; GCN-NEXT: v_mov_b32_e32 v2, s3
+; GCN-NEXT: v_cvt_scalef32_pk_fp4_f32 v0, s1, v1, v2
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call i32 @llvm.amdgcn.cvt.scalef32.pk.fp4.f32(i32 %old, float %src0, float %src1, float %scale, i32 0)
+ ret i32 %ret
+}
+
define i32 @test_cvt_scale_fp4_f32_byte1_inreg_src(i32 %old, float inreg %src0, float %src1, float %scale) {
; GCN-LABEL: test_cvt_scale_fp4_f32_byte1_inreg_src:
; GCN: ; %bb.0:
@@ -2108,6 +2360,17 @@ define <2 x half> @test_cvt_scale_f16_fp4_byte0_inreg_src(i32 inreg %src, float
ret <2 x half> %ret
}
+define <2 x half> @test_cvt_scale_f16_fp4_byte0_ss(i32 inreg %src, float inreg %scale) {
+; GCN-LABEL: test_cvt_scale_f16_fp4_byte0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_cvt_scalef32_pk_f16_fp4 v0, s0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <2 x half> @llvm.amdgcn.cvt.scalef32.pk.f16.fp4(i32 %src, float %scale, i32 0)
+ ret <2 x half> %ret
+}
+
define <2 x half> @test_cvt_scale_f16_fp4_byte1_inreg_src(i32 inreg %src, float %scale) {
; GCN-LABEL: test_cvt_scale_f16_fp4_byte1_inreg_src:
; GCN: ; %bb.0:
@@ -2179,58 +2442,88 @@ define <2 x bfloat> @test_cvt_scale_bf16_fp4_byte3_inreg_src(i32 inreg %src, flo
}
define <32 x float> @test_cvt_scale_pk32_f32_fp6_inreg_src(<6 x i32> inreg %src, float %scale) {
-; GFX950-SDAG-LABEL: test_cvt_scale_pk32_f32_fp6_inreg_src:
+; GCN-LABEL: test_cvt_scale_pk32_f32_fp6_inreg_src:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v32, v0
+; GCN-NEXT: v_mov_b32_e32 v34, s0
+; GCN-NEXT: v_mov_b32_e32 v35, s1
+; GCN-NEXT: v_mov_b32_e32 v36, s2
+; GCN-NEXT: v_mov_b32_e32 v37, s3
+; GCN-NEXT: v_mov_b32_e32 v38, s16
+; GCN-NEXT: v_mov_b32_e32 v39, s17
+; GCN-NEXT: v_cvt_scalef32_pk32_f32_fp6 v[0:31], v[34:39], v32
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <32 x float> @llvm.amdgcn.cvt.scalef32.pk32.f32.fp6(<6 x i32> %src, float %scale)
+ ret <32 x float> %ret
+}
+
+define <32 x float> @test_cvt_scale_pk32_f32_fp6_ss(<6 x i32> inreg %src, float inreg %scale) {
+; GFX950-SDAG-LABEL: test_cvt_scale_pk32_f32_fp6_ss:
; GFX950-SDAG: ; %bb.0:
; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v32, v0
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v34, s0
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v35, s1
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v36, s2
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v37, s3
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v38, s16
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v39, s17
-; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_f32_fp6 v[0:31], v[34:39], v32
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v32, s0
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v33, s1
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v34, s2
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v35, s3
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v36, s16
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v37, s17
+; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_f32_fp6 v[0:31], v[32:37], s18
; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX950-GISEL-LABEL: test_cvt_scale_pk32_f32_fp6_inreg_src:
+; GFX950-GISEL-LABEL: test_cvt_scale_pk32_f32_fp6_ss:
; GFX950-GISEL: ; %bb.0:
; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT: s_mov_b32 s4, s16
; GFX950-GISEL-NEXT: s_mov_b32 s5, s17
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v32, v0
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
-; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_f32_fp6 v[0:31], v[34:39], v32
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[36:37], s[4:5]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[34:35], s[2:3]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[32:33], s[0:1]
+; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_f32_fp6 v[0:31], v[32:37], s18
; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
%ret = tail call <32 x float> @llvm.amdgcn.cvt.scalef32.pk32.f32.fp6(<6 x i32> %src, float %scale)
ret <32 x float> %ret
}
define <32 x float> @test_cvt_scale_pk32_f32_bf6_inreg_src(<6 x i32> inreg %src, float %scale) {
-; GFX950-SDAG-LABEL: test_cvt_scale_pk32_f32_bf6_inreg_src:
+; GCN-LABEL: test_cvt_scale_pk32_f32_bf6_inreg_src:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v32, v0
+; GCN-NEXT: v_mov_b32_e32 v34, s0
+; GCN-NEXT: v_mov_b32_e32 v35, s1
+; GCN-NEXT: v_mov_b32_e32 v36, s2
+; GCN-NEXT: v_mov_b32_e32 v37, s3
+; GCN-NEXT: v_mov_b32_e32 v38, s16
+; GCN-NEXT: v_mov_b32_e32 v39, s17
+; GCN-NEXT: v_cvt_scalef32_pk32_f32_bf6 v[0:31], v[34:39], v32
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <32 x float> @llvm.amdgcn.cvt.scalef32.pk32.f32.bf6(<6 x i32> %src, float %scale)
+ ret <32 x float> %ret
+}
+
+define <32 x float> @test_cvt_scale_pk32_f32_bf6_ss(<6 x i32> inreg %src, float inreg %scale) {
+; GFX950-SDAG-LABEL: test_cvt_scale_pk32_f32_bf6_ss:
; GFX950-SDAG: ; %bb.0:
; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v32, v0
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v34, s0
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v35, s1
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v36, s2
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v37, s3
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v38, s16
-; GFX950-SDAG-NEXT: v_mov_b32_e32 v39, s17
-; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_f32_bf6 v[0:31], v[34:39], v32
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v32, s0
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v33, s1
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v34, s2
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v35, s3
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v36, s16
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v37, s17
+; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_f32_bf6 v[0:31], v[32:37], s18
; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
;
-; GFX950-GISEL-LABEL: test_cvt_scale_pk32_f32_bf6_inreg_src:
+; GFX950-GISEL-LABEL: test_cvt_scale_pk32_f32_bf6_ss:
; GFX950-GISEL: ; %bb.0:
; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX950-GISEL-NEXT: s_mov_b32 s4, s16
; GFX950-GISEL-NEXT: s_mov_b32 s5, s17
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[38:39], s[4:5]
-; GFX950-GISEL-NEXT: v_mov_b32_e32 v32, v0
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[36:37], s[2:3]
-; GFX950-GISEL-NEXT: v_mov_b64_e32 v[34:35], s[0:1]
-; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_f32_bf6 v[0:31], v[34:39], v32
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[36:37], s[4:5]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[34:35], s[2:3]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[32:33], s[0:1]
+; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_f32_bf6 v[0:31], v[32:37], s18
; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
%ret = tail call <32 x float> @llvm.amdgcn.cvt.scalef32.pk32.f32.bf6(<6 x i32> %src, float %scale)
ret <32 x float> %ret
@@ -2265,6 +2558,33 @@ define <32 x half> @test_cvt_scalef32_pk32_f16_fp6_vv_inreg_src(<6 x i32> inreg
ret <32 x half> %ret
}
+define <32 x half> @test_cvt_scalef32_pk32_f16_fp6_ss(<6 x i32> inreg %src, float inreg %scale) {
+; GFX950-SDAG-LABEL: test_cvt_scalef32_pk32_f16_fp6_ss:
+; GFX950-SDAG: ; %bb.0:
+; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s0
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s1
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v18, s2
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v19, s3
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v20, s16
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v21, s17
+; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_f16_fp6 v[0:15], v[16:21], s18
+; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-GISEL-LABEL: test_cvt_scalef32_pk32_f16_fp6_ss:
+; GFX950-GISEL: ; %bb.0:
+; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-GISEL-NEXT: s_mov_b32 s4, s16
+; GFX950-GISEL-NEXT: s_mov_b32 s5, s17
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[20:21], s[4:5]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
+; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_f16_fp6 v[0:15], v[16:21], s18
+; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <32 x half> @llvm.amdgcn.cvt.scalef32.pk32.f16.fp6(<6 x i32> %src, float %scale)
+ ret <32 x half> %ret
+}
+
define <32 x half> @test_cvt_scalef32_pk32_f16_fp6_sl_inreg_src(<6 x i32> inreg inreg %src) {
; GFX950-SDAG-LABEL: test_cvt_scalef32_pk32_f16_fp6_sl_inreg_src:
; GFX950-SDAG: ; %bb.0:
@@ -2357,6 +2677,33 @@ define <32 x half> @test_cvt_scalef32_pk32_f16_bf6_vv_inreg_src(<6 x i32> inreg
ret <32 x half> %ret
}
+define <32 x half> @test_cvt_scalef32_pk32_f16_bf6_ss(<6 x i32> inreg %src, float inreg %scale) {
+; GFX950-SDAG-LABEL: test_cvt_scalef32_pk32_f16_bf6_ss:
+; GFX950-SDAG: ; %bb.0:
+; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s0
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s1
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v18, s2
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v19, s3
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v20, s16
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v21, s17
+; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_f16_bf6 v[0:15], v[16:21], s18
+; GFX950-SDAG-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX950-GISEL-LABEL: test_cvt_scalef32_pk32_f16_bf6_ss:
+; GFX950-GISEL: ; %bb.0:
+; GFX950-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX950-GISEL-NEXT: s_mov_b32 s4, s16
+; GFX950-GISEL-NEXT: s_mov_b32 s5, s17
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[20:21], s[4:5]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[18:19], s[2:3]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[0:1]
+; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_f16_bf6 v[0:15], v[16:21], s18
+; GFX950-GISEL-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <32 x half> @llvm.amdgcn.cvt.scalef32.pk32.f16.bf6(<6 x i32> %src, float %scale)
+ ret <32 x half> %ret
+}
+
define <32 x half> @test_cvt_scalef32_pk32_f16_bf6_sl_inreg_src(<6 x i32> inreg inreg %src) {
; GFX950-SDAG-LABEL: test_cvt_scalef32_pk32_f16_bf6_sl_inreg_src:
; GFX950-SDAG: ; %bb.0:
@@ -2430,6 +2777,17 @@ define <2 x half> @test_cvt_scalef32_pk_f16_fp8_word0_inreg_src(i32 inreg %src,
ret <2 x half> %ret
}
+define <2 x half> @test_cvt_scalef32_pk_f16_fp8_word0_ss(i32 inreg %src, float inreg %scale) {
+; GCN-LABEL: test_cvt_scalef32_pk_f16_fp8_word0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_cvt_scalef32_pk_f16_fp8 v0, s0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <2 x half> @llvm.amdgcn.cvt.scalef32.pk.f16.fp8(i32 %src, float %scale, i1 false)
+ ret <2 x half> %ret
+}
+
define <2 x half> @test_cvt_scalef32_pk_f16_fp8_word1_inreg_src(i32 inreg %src, float %scale) {
; GCN-LABEL: test_cvt_scalef32_pk_f16_fp8_word1_inreg_src:
; GCN: ; %bb.0:
@@ -2450,6 +2808,17 @@ define <2 x half> @test_cvt_scalef32_pk_f16_bf8_word0_inreg_src(i32 inreg %src,
ret <2 x half> %ret
}
+define <2 x half> @test_cvt_scalef32_pk_f16_bf8_word0_ss(i32 inreg %src, float inreg %scale) {
+; GCN-LABEL: test_cvt_scalef32_pk_f16_bf8_word0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NEXT: v_cvt_scalef32_pk_f16_bf8 v0, s0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call <2 x half> @llvm.amdgcn.cvt.scalef32.pk.f16.bf8(i32 %src, float %scale, i1 false)
+ ret <2 x half> %ret
+}
+
define <2 x half> @test_cvt_scalef32_pk_f16_bf8_word1_inreg_src(i32 inreg %src, float %scale) {
; GCN-LABEL: test_cvt_scalef32_pk_f16_bf8_word1_inreg_src:
; GCN: ; %bb.0:
@@ -2511,6 +2880,18 @@ define i32 @test_cvt_scalef32_fp4_f16_byte0_inreg_src(<2 x half> inreg %src0, fl
ret i32 %ret
}
+define i32 @test_cvt_scalef32_fp4_f16_byte0_ss(<2 x half> inreg %src0, float inreg %scale, i32 inreg %old) {
+; GCN-LABEL: test_cvt_scalef32_fp4_f16_byte0_ss:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NEXT: v_cvt_scalef32_pk_fp4_f16 v0, s0, v1
+; GCN-NEXT: s_setpc_b64 s[30:31]
+ %ret = tail call i32 @llvm.amdgcn.cvt.scalef32.pk.fp4.f16(i32 %old, <2 x half> %src0, float %scale, i32 0)
+ ret i32 %ret
+}
+
define i32 @test_cvt_scalef32_fp4_f16_byte1_inreg_src(<2 x half> inreg %src0, float %scale, i32 %old) {
; GCN-LABEL: test_cvt_scalef32_fp4_f16_byte1_inreg_src:
; GCN: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
index 70674961b87fb..d4076a83c01d9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx950 < %s | FileCheck -check-prefix=GFX950-GISEL %s
declare <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.bf16(<32 x bfloat> %src, float %scale)
declare <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.f16(<32 x half> %src, float %scale)
@@ -143,8 +143,19 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f16_sl(<32 x half> inreg %src, ptr
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[2:17], v24
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX950-GISEL-NEXT: s_nop 1
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:16
; GFX950-GISEL-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.f16(<32 x half> %src, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
@@ -287,8 +298,19 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f16_sl(<32 x half> inreg %src, ptr
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[2:17], v24
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX950-GISEL-NEXT: s_nop 1
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:16
; GFX950-GISEL-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.fp6.f16(<32 x half> %src, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
@@ -450,6 +472,60 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f16_vv_inreg_src(<32 x half> inreg
ret void
}
+define amdgpu_ps void @test_scalef32_pk32_bf6_f16_ss(<32 x half> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_f16_ss:
+; GFX950-SDAG: ; %bb.0:
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15
+; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[2:17], s16
+; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
+; GFX950-SDAG-NEXT: s_endpgm
+;
+; GFX950-GISEL-LABEL: test_scalef32_pk32_bf6_f16_ss:
+; GFX950-GISEL: ; %bb.0:
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[2:17], s16
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX950-GISEL-NEXT: s_nop 1
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:16
+; GFX950-GISEL-NEXT: s_endpgm
+ %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.f16(<32 x half> %src, float %scale)
+ store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk32_bf6_f16_sl_inreg_src(<32 x half> inreg %src, ptr addrspace(1) %out) {
; GFX950-SDAG-LABEL: test_scalef32_pk32_bf6_f16_sl_inreg_src:
; GFX950-SDAG: ; %bb.0:
@@ -487,8 +563,19 @@ define amdgpu_ps void @test_scalef32_pk32_bf6_f16_sl_inreg_src(<32 x half> inreg
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_bf6_f16 v[18:23], v[2:17], v24
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX950-GISEL-NEXT: s_nop 1
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:16
; GFX950-GISEL-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.bf6.f16(<32 x half> %src, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
@@ -650,6 +737,60 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f16_vv_inreg_src(<32 x half> inreg
ret void
}
+define amdgpu_ps void @test_scalef32_pk32_fp6_f16_ss(<32 x half> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_f16_ss:
+; GFX950-SDAG: ; %bb.0:
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, s0
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, s1
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, s2
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, s3
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, s4
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, s5
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v8, s6
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v9, s7
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v10, s8
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v11, s9
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v12, s10
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v13, s11
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v14, s12
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v15, s13
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v16, s14
+; GFX950-SDAG-NEXT: v_mov_b32_e32 v17, s15
+; GFX950-SDAG-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[2:17], s16
+; GFX950-SDAG-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GFX950-SDAG-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
+; GFX950-SDAG-NEXT: s_endpgm
+;
+; GFX950-GISEL-LABEL: test_scalef32_pk32_fp6_f16_ss:
+; GFX950-GISEL: ; %bb.0:
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[2:17], s16
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX950-GISEL-NEXT: s_nop 1
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:16
+; GFX950-GISEL-NEXT: s_endpgm
+ %cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.fp6.f16(<32 x half> %src, float %scale)
+ store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk32_fp6_f16_sl_inreg_src(<32 x half> inreg %src, ptr addrspace(1) %out) {
; GFX950-SDAG-LABEL: test_scalef32_pk32_fp6_f16_sl_inreg_src:
; GFX950-SDAG: ; %bb.0:
@@ -687,8 +828,19 @@ define amdgpu_ps void @test_scalef32_pk32_fp6_f16_sl_inreg_src(<32 x half> inreg
; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
; GFX950-GISEL-NEXT: v_mov_b32_e32 v24, 0x42c80000
; GFX950-GISEL-NEXT: v_cvt_scalef32_pk32_fp6_f16 v[18:23], v[2:17], v24
-; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[18:21], off
-; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[22:23], off offset:16
+; GFX950-GISEL-NEXT: s_nop 0
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s2, v20
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s3, v21
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s0, v18
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s1, v19
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s4, v22
+; GFX950-GISEL-NEXT: v_readfirstlane_b32 s5, v23
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX950-GISEL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX950-GISEL-NEXT: s_nop 1
+; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
+; GFX950-GISEL-NEXT: global_store_dwordx2 v[0:1], v[2:3], off offset:16
; GFX950-GISEL-NEXT: s_endpgm
%cvt = tail call <6 x i32> @llvm.amdgcn.cvt.scalef32.pk32.fp6.f16(<32 x half> %src, float 100.0)
store <6 x i32> %cvt, ptr addrspace(1) %out, align 8
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
index cba6dff663617..0eb511a4e7891 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s
declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f32(<16 x float> %src, float %scale)
declare <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f32(<16 x float> %src, float %scale)
@@ -31,6 +31,43 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_f32_vv(<16 x float> %src, float %s
ret void
}
+define amdgpu_ps void @test_scalef32_pk16_bf6_f32_ss(<16 x float> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f32_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[2:17], s16
+; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f32_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f32 v[18:20], v[2:17], s16
+; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f32(<16 x float> %src, float %scale)
+ store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk16_bf6_f32_sl(<16 x float> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f32_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -89,6 +126,43 @@ define amdgpu_ps void @test_scalef32_pk16_fp6_f32_vv(<16 x float> %src, float %s
ret void
}
+define amdgpu_ps void @test_scalef32_pk16_fp6_f32_ss(<16 x float> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f32_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[2:17], s16
+; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f32_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f32 v[18:20], v[2:17], s16
+; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f32(<16 x float> %src, float %scale)
+ store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk16_fp6_f32_sl(<16 x float> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f32_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -197,6 +271,35 @@ define amdgpu_ps void @test_scalef32_pk16_bf6_f16_vv(<16 x half> %src, float %sc
ret void
}
+define amdgpu_ps void @test_scalef32_pk16_bf6_f16_ss(<16 x half> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f16_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[2:9], s8
+; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_pk16_bf6_f16_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_bf6_f16 v[10:12], v[2:9], s8
+; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.bf6.f16(<16 x half> %src, float %scale)
+ store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk16_bf6_f16_sl(<16 x half> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_bf6_f16_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -297,6 +400,35 @@ define amdgpu_ps void @test_scalef32_pk16_fp6_f16_vv(<16 x half> %src, float %sc
ret void
}
+define amdgpu_ps void @test_scalef32_pk16_fp6_f16_ss(<16 x half> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f16_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[2:9], s8
+; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_pk16_fp6_f16_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk16_fp6_f16 v[10:12], v[2:9], s8
+; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.pk16.fp6.f16(<16 x half> %src, float %scale)
+ store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk16_fp6_f16_sl(<16 x half> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk16_fp6_f16_sl:
; GFX1250-SDAG: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
index ebdabab78424e..1e367813375f0 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s
declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.bf16(<8 x bfloat> %src, float %scale)
declare <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.bf16(<8 x bfloat> %src, float %scale)
@@ -125,6 +125,31 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_f16_vv(<8 x half> %src, float %scal
ret void
}
+define amdgpu_ps void @test_scalef32_pk8_fp8_f16_ss(<8 x half> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f16_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_f16 v[6:7], v[2:5], s4
+; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f16_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_f16 v[6:7], v[2:5], s4
+; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f16(<8 x half> %src, float %scale)
+ store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk8_fp8_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f16_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -171,6 +196,31 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_f16_vv(<8 x half> %src, float %scal
ret void
}
+define amdgpu_ps void @test_scalef32_pk8_bf8_f16_ss(<8 x half> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f16_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_f16 v[6:7], v[2:5], s4
+; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f16_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_f16 v[6:7], v[2:5], s4
+; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f16(<8 x half> %src, float %scale)
+ store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk8_bf8_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f16_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -217,6 +267,35 @@ define amdgpu_ps void @test_scalef32_pk8_bf8_f32_vv(<8 x float> %src, float %sca
ret void
}
+define amdgpu_ps void @test_scalef32_pk8_bf8_f32_ss(<8 x float> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f32_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[2:9], s8
+; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[10:11], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_pk8_bf8_f32_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_bf8_f32 v[10:11], v[2:9], s8
+; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[10:11], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.bf8.f32(<8 x float> %src, float %scale)
+ store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk8_bf8_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_bf8_f32_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -267,6 +346,35 @@ define amdgpu_ps void @test_scalef32_pk8_fp8_f32_vv(<8 x float> %src, float %sca
ret void
}
+define amdgpu_ps void @test_scalef32_pk8_fp8_f32_ss(<8 x float> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f32_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[2:9], s8
+; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[10:11], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp8_f32_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp8_f32 v[10:11], v[2:9], s8
+; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[10:11], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.pk8.fp8.f32(<8 x float> %src, float %scale)
+ store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk8_fp8_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp8_f32_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -317,6 +425,35 @@ define amdgpu_ps void @test_scalef32_pk8_fp4_f32_vv(<8 x float> %src, float %sca
ret void
}
+define amdgpu_ps void @test_scalef32_pk8_fp4_f32_ss(<8 x float> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f32_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_f32 v10, v[2:9], s8
+; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v10, off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f32_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_f32 v10, v[2:9], s8
+; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v10, off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f32(<8 x float> %src, float %scale)
+ store i32 %cvt, ptr addrspace(1) %out, align 4
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk8_fp4_f32_sl(<8 x float> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f32_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -367,6 +504,31 @@ define amdgpu_ps void @test_scalef32_pk8_fp4_f16_vv(<8 x half> %src, float %scal
ret void
}
+define amdgpu_ps void @test_scalef32_pk8_fp4_f16_ss(<8 x half> inreg %src, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f16_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_pk8_fp4_f16 v6, v[2:5], s4
+; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v6, off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_pk8_fp4_f16_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_pk8_fp4_f16 v6, v[2:5], s4
+; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v6, off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.pk8.fp4.f16(<8 x half> %src, float %scale)
+ store i32 %cvt, ptr addrspace(1) %out, align 4
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_pk8_fp4_f16_sl(<8 x half> inreg %src, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_pk8_fp4_f16_sl:
; GFX1250-SDAG: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
index dbbbdd8932bc9..44029cd388edc 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-GISEL %s
declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.bf16(<8 x bfloat> %src, i32 %sr, float %scale)
declare <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.bf16(<8 x bfloat> %src, i32 %sr, float %scale)
@@ -119,6 +119,31 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f16_vv(<8 x half> %src, i32 %sr,
ret void
}
+define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f16_ss(<8 x half> inreg %src, i32 inreg %sr, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f16_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_f16 v[6:7], v[2:5], s4, s5
+; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f16_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_f16 v[6:7], v[2:5], s4, s5
+; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f16(<8 x half> %src, i32 %sr, float %scale)
+ store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f16_sl(<8 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f16_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -163,6 +188,31 @@ define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f16_vv(<8 x half> %src, i32 %sr,
ret void
}
+define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f16_ss(<8 x half> inreg %src, i32 inreg %sr, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f16_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_f16 v[6:7], v[2:5], s4, s5
+; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f16_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_f16 v[6:7], v[2:5], s4, s5
+; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[6:7], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f16(<8 x half> %src, i32 %sr, float %scale)
+ store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f16_sl(<8 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f16_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -207,6 +257,35 @@ define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f32_vv(<8 x float> %src, i32 %sr
ret void
}
+define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f32_ss(<8 x float> inreg %src, i32 inreg %sr, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f32_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[2:9], s8, s9
+; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[10:11], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_bf8_f32_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_bf8_f32 v[10:11], v[2:9], s8, s9
+; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[10:11], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.bf8.f32(<8 x float> %src, i32 %sr, float %scale)
+ store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_sr_pk8_bf8_f32_sl(<8 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_bf8_f32_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -255,6 +334,35 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f32_vv(<8 x float> %src, i32 %sr
ret void
}
+define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f32_ss(<8 x float> inreg %src, i32 inreg %sr, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f32_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[2:9], s8, s9
+; GFX1250-SDAG-NEXT: global_store_b64 v[0:1], v[10:11], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp8_f32_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp8_f32 v[10:11], v[2:9], s8, s9
+; GFX1250-GISEL-NEXT: global_store_b64 v[0:1], v[10:11], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <2 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk8.fp8.f32(<8 x float> %src, i32 %sr, float %scale)
+ store <2 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_sr_pk8_fp8_f32_sl(<8 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp8_f32_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -303,6 +411,35 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f32_vv(<8 x float> %src, i32 %sr
ret void
}
+define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f32_ss(<8 x float> inreg %src, i32 inreg %sr, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f32_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[2:9], s8, s9
+; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v10, off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f32_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_f32 v10, v[2:9], s8, s9
+; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v10, off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f32(<8 x float> %src, i32 %sr, float %scale)
+ store i32 %cvt, ptr addrspace(1) %out, align 4
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f32_sl(<8 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f32_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -351,6 +488,31 @@ define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f16_vv(<8 x half> %src, i32 %sr,
ret void
}
+define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f16_ss(<8 x half> inreg %src, i32 inreg %sr, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f16_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk8_fp4_f16 v6, v[2:5], s4, s5
+; GFX1250-SDAG-NEXT: global_store_b32 v[0:1], v6, off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_sr_pk8_fp4_f16_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk8_fp4_f16 v6, v[2:5], s4, s5
+; GFX1250-GISEL-NEXT: global_store_b32 v[0:1], v6, off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call i32 @llvm.amdgcn.cvt.scalef32.sr.pk8.fp4.f16(<8 x half> %src, i32 %sr, float %scale)
+ store i32 %cvt, ptr addrspace(1) %out, align 4
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_sr_pk8_fp4_f16_sl(<8 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk8_fp4_f16_sl:
; GFX1250-SDAG: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
index d8ba1f40f3c08..0b40a633353b7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.bf16(<16 x bfloat> %src, i32 %sr, float %scale)
declare <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f16(<16 x half> %src, i32 %sr, float %scale)
@@ -50,6 +50,35 @@ define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_vv(<16 x half> %src, i32 %s
ret void
}
+define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_ss(<16 x half> inreg %src, i32 inreg %sr, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_bf6_f16_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[2:9], s8, s9
+; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_bf6_f16_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk16_bf6_f16 v[10:12], v[2:9], s8, s9
+; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f16(<16 x half> %src, i32 %sr, float %scale)
+ store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f16_sl(<16 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_bf6_f16_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -120,6 +149,35 @@ define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_vv(<16 x half> %src, i32 %s
ret void
}
+define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_ss(<16 x half> inreg %src, i32 inreg %sr, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_fp6_f16_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[2:9], s8, s9
+; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[10:12], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_fp6_f16_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk16_fp6_f16 v[10:12], v[2:9], s8, s9
+; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[10:12], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f16(<16 x half> %src, i32 %sr, float %scale)
+ store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f16_sl(<16 x half> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_fp6_f16_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -161,6 +219,43 @@ define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_vv(<16 x float> %src, i32 %
ret void
}
+define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_ss(<16 x float> inreg %src, i32 inreg %sr, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_bf6_f32_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk16_bf6_f32 v[18:20], v[2:17], s16, s17
+; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_bf6_f32_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk16_bf6_f32 v[18:20], v[2:17], s16, s17
+; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.bf6.f32(<16 x float> %src, i32 %sr, float %scale)
+ store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_sr_pk16_bf6_f32_sl(<16 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_bf6_f32_sl:
; GFX1250-SDAG: ; %bb.0:
@@ -210,6 +305,43 @@ define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f32_vv(<16 x float> %src, i32 %
ret void
}
+define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f32_ss(<16 x float> inreg %src, i32 inreg %sr, float inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_fp6_f32_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, s2 :: v_dual_mov_b32 v5, s3
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s5
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v8, s6 :: v_dual_mov_b32 v9, s7
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v10, s8 :: v_dual_mov_b32 v11, s9
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v12, s10 :: v_dual_mov_b32 v13, s11
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scalef32_sr_pk16_fp6_f32 v[18:20], v[2:17], s16, s17
+; GFX1250-SDAG-NEXT: global_store_b96 v[0:1], v[18:20], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_scalef32_sr_pk16_fp6_f32_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[16:17], s[14:15]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[14:15], s[12:13]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[12:13], s[10:11]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[10:11], s[8:9]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[8:9], s[6:7]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[4:5]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3]
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scalef32_sr_pk16_fp6_f32 v[18:20], v[2:17], s16, s17
+; GFX1250-GISEL-NEXT: global_store_b96 v[0:1], v[18:20], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <3 x i32> @llvm.amdgcn.cvt.scalef32.sr.pk16.fp6.f32(<16 x float> %src, i32 %sr, float %scale)
+ store <3 x i32> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_scalef32_sr_pk16_fp6_f32_sl(<16 x float> inreg %src, i32 inreg %sr, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_scalef32_sr_pk16_fp6_f32_sl:
; GFX1250-SDAG: ; %bb.0:
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