[llvm] [AArch64][SVE] add missing instcombine x+1 -> x (PR #201851)

[Paul Walker via llvm-commits]

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@@ -2511,6 +2515,28 @@ instCombineSVEVectorBinOp(InstCombiner &IC, IntrinsicInst &II) {
   return IC.replaceInstUsesWith(II, BinOp);
 }
 
+static std::optional<Instruction *> instCombineSVEVectorMla(InstCombiner &IC,
+                                                            IntrinsicInst &II) {
+  bool InactiveLanesAreUndefined =
+      II.getIntrinsicID() == Intrinsic::aarch64_sve_mla_u;
+  Value *Pred = II.getOperand(0);
+  if (!InactiveLanesAreUndefined && !isAllActivePredicate(Pred))
+    return std::nullopt;
+
+  Value *Acc = II.getArgOperand(1);
+  Value *MulOp0 = II.getArgOperand(2);
+  Value *MulOp1 = II.getArgOperand(3);
+
+  // For all-active predicates, mla(acc, x, 1) is add(acc, x). For mla_u,
+  // inactive lanes are undefined, so it is also valid to drop the predicate.
+  if (match(MulOp0, m_One()))
+    return IC.replaceInstUsesWith(II, IC.Builder.CreateAdd(Acc, MulOp1));
+  if (match(MulOp1, m_One()))
+    return IC.replaceInstUsesWith(II, IC.Builder.CreateAdd(Acc, MulOp0));
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paulwalker-arm wrote:

Perhaps worth adding the equivalent m_AllOnes() -> Sub transformation?

https://github.com/llvm/llvm-project/pull/201851