[llvm] AMDGPU/UniformityAnalysis: Test MIR uniformity analysis for INLINEASM (PR #201956)

[Pankaj Dwivedi via llvm-commits]

================
@@ -0,0 +1,60 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+
+# CHECK-LABEL: MachineUniformityInfo for function:  @inlineasm_s
+# CHECK-LABEL: BLOCK bb.0
+# CHECK-NOT: DIVERGENT: %0: INLINEASM
+---
+name:            inlineasm_s
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    INLINEASM &"s_mov_b32 $0, 7", attdialect, regdef:SReg_32, def %0:sreg_32
+    $sgpr0 = COPY %0
+    SI_RETURN implicit $sgpr0
+...
+
+# CHECK-LABEL: MachineUniformityInfo for function:  @inlineasm_v
+# CHECK-LABEL: BLOCK bb.0
+# CHECK-NOT: DIVERGENT: %0: INLINEASM
+---
+name:            inlineasm_v
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    INLINEASM &"v_mov_b32 $0, 8", attdialect, regdef:VGPR_32, def %0:vgpr_32
+    $vgpr0 = COPY %0
+    SI_RETURN implicit $vgpr0
+...
+
+# CHECK-LABEL: MachineUniformityInfo for function:  @inlineasm_sv
+# CHECK-LABEL: BLOCK bb.0
+# CHECK-NOT: DIVERGENT: %0: INLINEASM
+# CHECK-NOT: DIVERGENT: %1: INLINEASM
+---
+name:            inlineasm_sv
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    INLINEASM &"s_mov_b32 $0, 7\0Av_mov_b32 $1, 8", attdialect, regdef:SReg_32, def %0:sreg_32, regdef:VGPR_32, def %1:vgpr_32
+    $sgpr0 = COPY %0
+    $vgpr0 = COPY %1
+    SI_RETURN implicit $sgpr0, implicit $vgpr0
+...
+
+# CHECK-LABEL: MachineUniformityInfo for function:  @inlineasm_svs
+# CHECK-LABEL: BLOCK bb.0
+# CHECK-NOT: DIVERGENT: %0: INLINEASM
+# CHECK-NOT: DIVERGENT: %1: INLINEASM
----------------
PankajDwivedi-25 wrote:

Yes its looks good logically in the current form.

all i ment here is; currently getValueUniformity query is on whole instruction, instead this can be per def. That is part of another refactoring which earlier I tried but didn't work because of MIR can have multiple def(values) per instruction and the enum ValueUniformity is per value which is fine for IR but its doesn't fit for MIR.

May be we can go ahead with the current state as of now.

 

https://github.com/llvm/llvm-project/pull/201956