[llvm] [AArch64] SME definitions for C1-Ultra scheduling model (PR #194850)

[David Green via llvm-commits]

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@@ -93,9 +117,194 @@ def : WriteRes<WriteLDHi,    []> { let Latency = 4; }
 // Define customized scheduler read/write types specific to C1 Ultra.
 //===----------------------------------------------------------------------===//
 
+// The approach for modelling SME instructions should not be taken as accurate.
+// This is largely due to the limitations of tablegen and the way that SME
+// works. Fundamentally, modelling SME instructions accurately requires
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davemgreen wrote:

Can you more prominently call out that separate execution engines will not be modelled by llvm and is probably the larger issue.

https://github.com/llvm/llvm-project/pull/194850