[llvm] [AMDGPU] Enable WMMA256bInsts + Wave32 for gfx1200/gfx1201 + SISchedule fix + TargetParser gfx1200 propagation (PR #202093)

[Alexandra Munkes via llvm-commits]

Malexandra-de wrote:

> RDNA4 gfx1200 SWMMAC theoretical peak: ~5770 TOPs (26 pipelines × dual-issue) AMD official documentation: 820 TOPs (SWMMAC performance figure) Our measured result (K0 baseline): 518 TOPs (9%) Our optimized result (K9): 4326 TOPs (75%)
> 
> 75% represents the benchmark for data-center-grade optimization (Google TPU achieves 70–80%; NVIDIA H100 achieves 72–78%). AMD official INT4 figure: 820 TOPs Our K0 baseline: 518 TOPs (63% — exceeding the official figure) Our K9 optimization: 4326 TOPs (527% — 5.27x the official figure)
> 
> Theoretical peak ≈ 5770: 75% utilization
> 
> This demonstrates that AMD's official drivers fail to fully unlock the hardware's capabilities. Our SISchedule + StaggeredPipeline approach is the solution that truly saturates the 26-stage pipeline.

Question, where are you getting "26 pipelines" from. gfx1200, which is used in the 9060XT has 16WGPs, or more speficically 64 SIMDs/Matrix Units. 

https://github.com/llvm/llvm-project/pull/202093