[llvm] [AMDGPU] Capping max number of registers for indirect calls (PR #199765)

[Janek van Oirschot via llvm-commits]

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@@ -316,11 +323,27 @@ void MCResourceInfo::gatherResourceInfo(
     } else {
       const MCExpr *SymRef = MCSymbolRefExpr::create(MaxSym, OutContext);
       MCSymbol *LocalNumSym = getSymbol(FnSym->getName(), RIK, OutContext);
-      const MCExpr *MaxWithLocal = AMDGPUMCExpr::createMax(
+      const MCExpr *RegExpr = AMDGPUMCExpr::createMax(
           {MCConstantExpr::create(numRegs, OutContext), SymRef}, OutContext);
-      LocalNumSym->setVariableValue(MaxWithLocal);
-      LLVM_DEBUG(dbgs() << "MCResUse:   " << LocalNumSym->getName()
-                        << ": Indirect callee within, using module maximum\n");
+      if (RIK == RIK_NumVGPR) {
+        RegExpr = AMDGPUMCExpr::createMin(
+            {MCConstantExpr::create(MaxAllowedVGPRs, OutContext), RegExpr},
+            OutContext);
+      } else if (RIK == RIK_NumAGPR) {
+        RegExpr = AMDGPUMCExpr::createMin(
+            {MCConstantExpr::create(MaxAllowedAGPRs, OutContext), RegExpr},
+            OutContext);
+      } else if (RIK == RIK_NumSGPR) {
+        RegExpr = AMDGPUMCExpr::createMin(
+            {MCConstantExpr::create(MaxAllowedSGPRs, OutContext), RegExpr},
+            OutContext);
+      }
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JanekvO wrote:

Sorry, I'm still wondering: do the named barriers also need to be capped? (I don't think they're occupancy constrained but I don't know if they might end up needing a hard limit as well)

https://github.com/llvm/llvm-project/pull/199765