[llvm] [PowerPC] Custom Lower ABDU using branchless carry (PR #182704)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 7 09:22:28 PDT 2026
https://github.com/mike-goutokuji updated https://github.com/llvm/llvm-project/pull/182704
>From 264e74ead7315920de1854fe38b7b00e619f3f94 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 21 Feb 2026 16:44:56 -0500
Subject: [PATCH 1/3] Pre-commit tests
---
llvm/test/CodeGen/PowerPC/abdu-neg.ll | 931 ++++++++++++++++++++++++
llvm/test/CodeGen/PowerPC/abdu.ll | 982 ++++++++++++++++++++++++++
2 files changed, 1913 insertions(+)
create mode 100644 llvm/test/CodeGen/PowerPC/abdu-neg.ll
create mode 100644 llvm/test/CodeGen/PowerPC/abdu.ll
diff --git a/llvm/test/CodeGen/PowerPC/abdu-neg.ll b/llvm/test/CodeGen/PowerPC/abdu-neg.ll
new file mode 100644
index 0000000000000..bfd656bd0f56f
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/abdu-neg.ll
@@ -0,0 +1,931 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,PPC32
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,PPC64
+
+;
+; trunc(nabs(sub(zext(a),zext(b)))) -> nabdu(a,b)
+;
+
+define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
+; PPC32-LABEL: abd_ext_i8:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: clrlwi 4, 4, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i8:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 56
+; PPC64-NEXT: clrldi 4, 4, 56
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i8 %a to i64
+ %bext = zext i8 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i8
+ ret i8 %trunc
+}
+
+define i8 @abd_ext_i8_i16(i8 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i8_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i8_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 56
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i8 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i8
+ ret i8 %trunc
+}
+
+define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
+; PPC32-LABEL: abd_ext_i8_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: clrlwi 4, 4, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i8_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 56
+; PPC64-NEXT: clrldi 4, 4, 56
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i8 %a to i64
+ %bext = zext i8 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i8
+ ret i8 %trunc
+}
+
+define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i16 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i16
+ ret i16 %trunc
+}
+
+define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_ext_i16_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB4_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB4_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i16_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i16 %a to i64
+ %bext = zext i32 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i16
+ ret i16 %trunc
+}
+
+define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i16_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i16_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i16 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i16
+ ret i16 %trunc
+}
+
+define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_ext_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB6_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB6_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i32 %a to i64
+ %bext = zext i32 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i32
+ ret i32 %trunc
+}
+
+define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i32_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB7_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB7_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i32_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i32 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i32
+ ret i32 %trunc
+}
+
+define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_ext_i32_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB8_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB8_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: neg 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i32_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+ %aext = zext i32 %a to i64
+ %bext = zext i32 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
+ %nabs = sub i64 0, %abs
+ %trunc = trunc i64 %nabs to i32
+ ret i32 %trunc
+}
+
+define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_ext_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB9_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB9_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: subfic 4, 4, 0
+; PPC32-NEXT: subfze 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB9_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: neg 3, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB9_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: neg 3, 3
+; PPC64-NEXT: blr
+ %aext = zext i64 %a to i128
+ %bext = zext i64 %b to i128
+ %sub = sub i128 %aext, %bext
+ %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)
+ %nabs = sub i128 0, %abs
+ %trunc = trunc i128 %nabs to i64
+ ret i64 %trunc
+}
+
+define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_ext_i64_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB10_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB10_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: subfic 4, 4, 0
+; PPC32-NEXT: subfze 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i64_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB10_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: neg 3, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB10_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: neg 3, 3
+; PPC64-NEXT: blr
+ %aext = zext i64 %a to i128
+ %bext = zext i64 %b to i128
+ %sub = sub i128 %aext, %bext
+ %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)
+ %nabs = sub i128 0, %abs
+ %trunc = trunc i128 %nabs to i64
+ ret i64 %trunc
+}
+
+define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_ext_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB11_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB11_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: subfic 6, 6, 0
+; PPC32-NEXT: subfze 5, 5
+; PPC32-NEXT: subfze 4, 4
+; PPC32-NEXT: subfze 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: subfic 4, 4, 0
+; PPC64-NEXT: subfze 3, 3
+; PPC64-NEXT: blr
+ %aext = zext i128 %a to i256
+ %bext = zext i128 %b to i256
+ %sub = sub i256 %aext, %bext
+ %abs = call i256 @llvm.abs.i256(i256 %sub, i1 false)
+ %nabs = sub i256 0, %abs
+ %trunc = trunc i256 %nabs to i128
+ ret i128 %trunc
+}
+
+define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_ext_i128_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB12_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB12_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: subfic 6, 6, 0
+; PPC32-NEXT: subfze 5, 5
+; PPC32-NEXT: subfze 4, 4
+; PPC32-NEXT: subfze 3, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i128_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: subfic 4, 4, 0
+; PPC64-NEXT: subfze 3, 3
+; PPC64-NEXT: blr
+ %aext = zext i128 %a to i256
+ %bext = zext i128 %b to i256
+ %sub = sub i256 %aext, %bext
+ %abs = call i256 @llvm.abs.i256(i256 %sub, i1 true)
+ %nabs = sub i256 0, %abs
+ %trunc = trunc i256 %nabs to i128
+ ret i128 %trunc
+}
+
+;
+; sub(umin(a,b),umax(a,b)) -> nabdu(a,b)
+;
+
+define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_minmax_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 4, 4, 24
+; CHECK-NEXT: clrlwi 3, 3, 24
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: mr 5, 3
+; CHECK-NEXT: bge 0, .LBB13_3
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ble 0, .LBB13_4
+; CHECK-NEXT: .LBB13_2:
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB13_3:
+; CHECK-NEXT: mr 5, 4
+; CHECK-NEXT: bgt 0, .LBB13_2
+; CHECK-NEXT: .LBB13_4:
+; CHECK-NEXT: mr 3, 4
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+ %min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
+ %max = call i8 @llvm.umax.i8(i8 %a, i8 %b)
+ %sub = sub i8 %min, %max
+ ret i8 %sub
+}
+
+define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
+; CHECK-LABEL: abd_minmax_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 4, 4, 16
+; CHECK-NEXT: clrlwi 3, 3, 16
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: mr 5, 3
+; CHECK-NEXT: bge 0, .LBB14_3
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ble 0, .LBB14_4
+; CHECK-NEXT: .LBB14_2:
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB14_3:
+; CHECK-NEXT: mr 5, 4
+; CHECK-NEXT: bgt 0, .LBB14_2
+; CHECK-NEXT: .LBB14_4:
+; CHECK-NEXT: mr 3, 4
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+ %min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
+ %max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
+ %sub = sub i16 %min, %max
+ ret i16 %sub
+}
+
+define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: abd_minmax_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: mr 5, 3
+; CHECK-NEXT: bge 0, .LBB15_3
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: ble 0, .LBB15_4
+; CHECK-NEXT: .LBB15_2:
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB15_3:
+; CHECK-NEXT: mr 5, 4
+; CHECK-NEXT: bgt 0, .LBB15_2
+; CHECK-NEXT: .LBB15_4:
+; CHECK-NEXT: mr 3, 4
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+ %min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+ %max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+ %sub = sub i32 %min, %max
+ ret i32 %sub
+}
+
+define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_minmax_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: cmplw 3, 5
+; PPC32-NEXT: cmplw 1, 4, 6
+; PPC32-NEXT: crandc 20, 0, 2
+; PPC32-NEXT: crand 21, 2, 4
+; PPC32-NEXT: cror 20, 21, 20
+; PPC32-NEXT: mr 7, 3
+; PPC32-NEXT: bc 12, 20, .LBB16_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: mr 7, 5
+; PPC32-NEXT: .LBB16_2:
+; PPC32-NEXT: mr 8, 4
+; PPC32-NEXT: bc 12, 20, .LBB16_4
+; PPC32-NEXT: # %bb.3:
+; PPC32-NEXT: mr 8, 6
+; PPC32-NEXT: .LBB16_4:
+; PPC32-NEXT: crandc 20, 1, 2
+; PPC32-NEXT: crand 21, 2, 5
+; PPC32-NEXT: cror 20, 21, 20
+; PPC32-NEXT: bc 12, 20, .LBB16_6
+; PPC32-NEXT: # %bb.5:
+; PPC32-NEXT: mr 3, 5
+; PPC32-NEXT: .LBB16_6:
+; PPC32-NEXT: bc 12, 20, .LBB16_8
+; PPC32-NEXT: # %bb.7:
+; PPC32-NEXT: mr 4, 6
+; PPC32-NEXT: .LBB16_8:
+; PPC32-NEXT: subc 4, 8, 4
+; PPC32-NEXT: subfe 3, 3, 7
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: mr 5, 3
+; PPC64-NEXT: bge 0, .LBB16_3
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: ble 0, .LBB16_4
+; PPC64-NEXT: .LBB16_2:
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB16_3:
+; PPC64-NEXT: mr 5, 4
+; PPC64-NEXT: bgt 0, .LBB16_2
+; PPC64-NEXT: .LBB16_4:
+; PPC64-NEXT: mr 3, 4
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
+ %min = call i64 @llvm.umin.i64(i64 %a, i64 %b)
+ %max = call i64 @llvm.umax.i64(i64 %a, i64 %b)
+ %sub = sub i64 %min, %max
+ ret i64 %sub
+}
+
+define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_minmax_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: stwu 1, -16(1)
+; PPC32-NEXT: cmplw 3, 7
+; PPC32-NEXT: cmplw 1, 4, 8
+; PPC32-NEXT: xor 11, 3, 7
+; PPC32-NEXT: xor 12, 4, 8
+; PPC32-NEXT: cmplw 5, 5, 9
+; PPC32-NEXT: cmplw 6, 6, 10
+; PPC32-NEXT: crandc 23, 0, 2
+; PPC32-NEXT: crand 26, 2, 4
+; PPC32-NEXT: or 11, 12, 11
+; PPC32-NEXT: crandc 20, 20, 22
+; PPC32-NEXT: crand 24, 22, 24
+; PPC32-NEXT: cror 23, 26, 23
+; PPC32-NEXT: cmplwi 7, 11, 0
+; PPC32-NEXT: cror 20, 24, 20
+; PPC32-NEXT: crandc 23, 23, 30
+; PPC32-NEXT: crand 20, 30, 20
+; PPC32-NEXT: cror 20, 20, 23
+; PPC32-NEXT: mr 11, 3
+; PPC32-NEXT: stw 30, 8(1) # 4-byte Folded Spill
+; PPC32-NEXT: bc 4, 20, .LBB17_11
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: mr 12, 4
+; PPC32-NEXT: bc 4, 20, .LBB17_12
+; PPC32-NEXT: .LBB17_2:
+; PPC32-NEXT: mr 0, 5
+; PPC32-NEXT: bc 4, 20, .LBB17_13
+; PPC32-NEXT: .LBB17_3:
+; PPC32-NEXT: mr 30, 6
+; PPC32-NEXT: bc 12, 20, .LBB17_5
+; PPC32-NEXT: .LBB17_4:
+; PPC32-NEXT: mr 30, 10
+; PPC32-NEXT: .LBB17_5:
+; PPC32-NEXT: crandc 20, 1, 2
+; PPC32-NEXT: crand 23, 2, 5
+; PPC32-NEXT: crandc 21, 21, 22
+; PPC32-NEXT: crand 22, 22, 25
+; PPC32-NEXT: cror 20, 23, 20
+; PPC32-NEXT: cror 21, 22, 21
+; PPC32-NEXT: crandc 20, 20, 30
+; PPC32-NEXT: crand 21, 30, 21
+; PPC32-NEXT: cror 20, 21, 20
+; PPC32-NEXT: bc 4, 20, .LBB17_14
+; PPC32-NEXT: # %bb.6:
+; PPC32-NEXT: bc 4, 20, .LBB17_15
+; PPC32-NEXT: .LBB17_7:
+; PPC32-NEXT: bc 4, 20, .LBB17_16
+; PPC32-NEXT: .LBB17_8:
+; PPC32-NEXT: bc 12, 20, .LBB17_10
+; PPC32-NEXT: .LBB17_9:
+; PPC32-NEXT: mr 6, 10
+; PPC32-NEXT: .LBB17_10:
+; PPC32-NEXT: subc 6, 30, 6
+; PPC32-NEXT: subfe 5, 5, 0
+; PPC32-NEXT: subfe 4, 4, 12
+; PPC32-NEXT: subfe 3, 3, 11
+; PPC32-NEXT: lwz 30, 8(1) # 4-byte Folded Reload
+; PPC32-NEXT: addi 1, 1, 16
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB17_11:
+; PPC32-NEXT: mr 11, 7
+; PPC32-NEXT: mr 12, 4
+; PPC32-NEXT: bc 12, 20, .LBB17_2
+; PPC32-NEXT: .LBB17_12:
+; PPC32-NEXT: mr 12, 8
+; PPC32-NEXT: mr 0, 5
+; PPC32-NEXT: bc 12, 20, .LBB17_3
+; PPC32-NEXT: .LBB17_13:
+; PPC32-NEXT: mr 0, 9
+; PPC32-NEXT: mr 30, 6
+; PPC32-NEXT: bc 4, 20, .LBB17_4
+; PPC32-NEXT: b .LBB17_5
+; PPC32-NEXT: .LBB17_14:
+; PPC32-NEXT: mr 3, 7
+; PPC32-NEXT: bc 12, 20, .LBB17_7
+; PPC32-NEXT: .LBB17_15:
+; PPC32-NEXT: mr 4, 8
+; PPC32-NEXT: bc 12, 20, .LBB17_8
+; PPC32-NEXT: .LBB17_16:
+; PPC32-NEXT: mr 5, 9
+; PPC32-NEXT: bc 4, 20, .LBB17_9
+; PPC32-NEXT: b .LBB17_10
+;
+; PPC64-LABEL: abd_minmax_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 5
+; PPC64-NEXT: cmpld 1, 4, 6
+; PPC64-NEXT: crandc 20, 0, 2
+; PPC64-NEXT: mr 7, 3
+; PPC64-NEXT: crand 21, 2, 4
+; PPC64-NEXT: cror 20, 21, 20
+; PPC64-NEXT: bc 12, 20, .LBB17_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: mr 7, 5
+; PPC64-NEXT: .LBB17_2:
+; PPC64-NEXT: mr 8, 4
+; PPC64-NEXT: bc 12, 20, .LBB17_4
+; PPC64-NEXT: # %bb.3:
+; PPC64-NEXT: mr 8, 6
+; PPC64-NEXT: .LBB17_4:
+; PPC64-NEXT: crandc 20, 1, 2
+; PPC64-NEXT: crand 21, 2, 5
+; PPC64-NEXT: cror 20, 21, 20
+; PPC64-NEXT: bc 12, 20, .LBB17_6
+; PPC64-NEXT: # %bb.5:
+; PPC64-NEXT: mr 3, 5
+; PPC64-NEXT: .LBB17_6:
+; PPC64-NEXT: bc 12, 20, .LBB17_8
+; PPC64-NEXT: # %bb.7:
+; PPC64-NEXT: mr 4, 6
+; PPC64-NEXT: .LBB17_8:
+; PPC64-NEXT: subc 4, 8, 4
+; PPC64-NEXT: subfe 3, 3, 7
+; PPC64-NEXT: blr
+ %min = call i128 @llvm.umin.i128(i128 %a, i128 %b)
+ %max = call i128 @llvm.umax.i128(i128 %a, i128 %b)
+ %sub = sub i128 %min, %max
+ ret i128 %sub
+}
+
+;
+; select(icmp(a,b),sub(a,b),sub(b,a)) -> nabdu(a,b)
+;
+
+define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_cmp_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 5, 4, 24
+; CHECK-NEXT: clrlwi 6, 3, 24
+; CHECK-NEXT: cmplw 6, 5
+; CHECK-NEXT: ble 0, .LBB18_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 4, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB18_2:
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ule i8 %a, %b
+ %ab = sub i8 %a, %b
+ %ba = sub i8 %b, %a
+ %sel = select i1 %cmp, i8 %ab, i8 %ba
+ ret i8 %sel
+}
+
+define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
+; CHECK-LABEL: abd_cmp_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 5, 4, 16
+; CHECK-NEXT: clrlwi 6, 3, 16
+; CHECK-NEXT: cmplw 6, 5
+; CHECK-NEXT: blt 0, .LBB19_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 4, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB19_2:
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ult i16 %a, %b
+ %ab = sub i16 %a, %b
+ %ba = sub i16 %b, %a
+ %sel = select i1 %cmp, i16 %ab, i16 %ba
+ ret i16 %sel
+}
+
+define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: abd_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: bge 0, .LBB20_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB20_2:
+; CHECK-NEXT: sub 3, 4, 3
+; CHECK-NEXT: blr
+ %cmp = icmp uge i32 %a, %b
+ %ab = sub i32 %a, %b
+ %ba = sub i32 %b, %a
+ %sel = select i1 %cmp, i32 %ba, i32 %ab
+ ret i32 %sel
+}
+
+define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_cmp_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: mr 7, 4
+; PPC32-NEXT: cmplw 1, 4, 6
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: mr 8, 3
+; PPC32-NEXT: cmplw 3, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: crandc 20, 0, 2
+; PPC32-NEXT: crand 21, 2, 4
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: cror 20, 21, 20
+; PPC32-NEXT: subfe 5, 8, 5
+; PPC32-NEXT: bc 12, 20, .LBB21_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: mr 3, 5
+; PPC32-NEXT: .LBB21_2:
+; PPC32-NEXT: bclr 12, 20, 0
+; PPC32-NEXT: # %bb.3:
+; PPC32-NEXT: mr 4, 6
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: blt 0, .LBB21_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB21_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
+ %cmp = icmp ult i64 %a, %b
+ %ab = sub i64 %a, %b
+ %ba = sub i64 %b, %a
+ %sel = select i1 %cmp, i64 %ab, i64 %ba
+ ret i64 %sel
+}
+
+define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_cmp_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: stwu 1, -16(1)
+; PPC32-NEXT: cmplw 3, 7
+; PPC32-NEXT: cmplw 1, 4, 8
+; PPC32-NEXT: cmplw 5, 5, 9
+; PPC32-NEXT: mr 11, 6
+; PPC32-NEXT: crand 21, 2, 4
+; PPC32-NEXT: cmplw 1, 6, 10
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: stw 30, 8(1) # 4-byte Folded Spill
+; PPC32-NEXT: mr 12, 5
+; PPC32-NEXT: mr 0, 4
+; PPC32-NEXT: mr 30, 3
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: xor 4, 4, 8
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: or 3, 4, 3
+; PPC32-NEXT: subfe 4, 8, 0
+; PPC32-NEXT: crandc 23, 0, 2
+; PPC32-NEXT: cmplwi 3, 0
+; PPC32-NEXT: subfe 3, 7, 30
+; PPC32-NEXT: crandc 20, 20, 22
+; PPC32-NEXT: crand 22, 22, 4
+; PPC32-NEXT: subc 10, 10, 11
+; PPC32-NEXT: cror 21, 21, 23
+; PPC32-NEXT: cror 20, 22, 20
+; PPC32-NEXT: subfe 9, 12, 9
+; PPC32-NEXT: crandc 21, 21, 2
+; PPC32-NEXT: crand 20, 2, 20
+; PPC32-NEXT: subfe 8, 0, 8
+; PPC32-NEXT: cror 20, 20, 21
+; PPC32-NEXT: subfe 7, 30, 7
+; PPC32-NEXT: bc 4, 20, .LBB22_6
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: bc 4, 20, .LBB22_7
+; PPC32-NEXT: .LBB22_2:
+; PPC32-NEXT: bc 4, 20, .LBB22_8
+; PPC32-NEXT: .LBB22_3:
+; PPC32-NEXT: bc 12, 20, .LBB22_5
+; PPC32-NEXT: .LBB22_4:
+; PPC32-NEXT: mr 6, 10
+; PPC32-NEXT: .LBB22_5:
+; PPC32-NEXT: lwz 30, 8(1) # 4-byte Folded Reload
+; PPC32-NEXT: addi 1, 1, 16
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB22_6:
+; PPC32-NEXT: mr 3, 7
+; PPC32-NEXT: bc 12, 20, .LBB22_2
+; PPC32-NEXT: .LBB22_7:
+; PPC32-NEXT: mr 4, 8
+; PPC32-NEXT: bc 12, 20, .LBB22_3
+; PPC32-NEXT: .LBB22_8:
+; PPC32-NEXT: mr 5, 9
+; PPC32-NEXT: bc 4, 20, .LBB22_4
+; PPC32-NEXT: b .LBB22_5
+;
+; PPC64-LABEL: abd_cmp_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: mr 7, 4
+; PPC64-NEXT: cmpld 1, 4, 6
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: mr 8, 3
+; PPC64-NEXT: cmpld 3, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: crandc 20, 0, 2
+; PPC64-NEXT: subc 6, 6, 7
+; PPC64-NEXT: subfe 5, 8, 5
+; PPC64-NEXT: crand 21, 2, 4
+; PPC64-NEXT: cror 20, 21, 20
+; PPC64-NEXT: bc 12, 20, .LBB22_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: mr 3, 5
+; PPC64-NEXT: .LBB22_2:
+; PPC64-NEXT: bclr 12, 20, 0
+; PPC64-NEXT: # %bb.3:
+; PPC64-NEXT: mr 4, 6
+; PPC64-NEXT: blr
+ %cmp = icmp ult i128 %a, %b
+ %ab = sub i128 %a, %b
+ %ba = sub i128 %b, %a
+ %sel = select i1 %cmp, i128 %ab, i128 %ba
+ ret i128 %sel
+}
+
+declare i8 @llvm.abs.i8(i8, i1)
+declare i16 @llvm.abs.i16(i16, i1)
+declare i32 @llvm.abs.i32(i32, i1)
+declare i64 @llvm.abs.i64(i64, i1)
+declare i128 @llvm.abs.i128(i128, i1)
+
+declare i8 @llvm.umax.i8(i8, i8)
+declare i16 @llvm.umax.i16(i16, i16)
+declare i32 @llvm.umax.i32(i32, i32)
+declare i64 @llvm.umax.i64(i64, i64)
+
+declare i8 @llvm.umin.i8(i8, i8)
+declare i16 @llvm.umin.i16(i16, i16)
+declare i32 @llvm.umin.i32(i32, i32)
+declare i64 @llvm.umin.i64(i64, i64)
diff --git a/llvm/test/CodeGen/PowerPC/abdu.ll b/llvm/test/CodeGen/PowerPC/abdu.ll
new file mode 100644
index 0000000000000..b4ae1954d3d59
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/abdu.ll
@@ -0,0 +1,982 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc-unknown-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,PPC32
+; RUN: llc -mtriple=powerpc64-unknown-linux-gnu %s -o - | FileCheck %s --check-prefixes=CHECK,PPC64
+
+;
+; trunc(abs(sub(zext(a),zext(b)))) -> abdu(a,b)
+;
+
+define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
+; PPC32-LABEL: abd_ext_i8:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: clrlwi 4, 4, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i8:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 3, 3, 24
+; PPC64-NEXT: clrlwi 4, 4, 24
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: srawi 4, 3, 31
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i8 %a to i64
+ %bext = zext i8 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i8
+ ret i8 %trunc
+}
+
+define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
+; PPC32-LABEL: abd_ext_i8_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: clrlwi 4, 4, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i8_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 3, 3, 24
+; PPC64-NEXT: clrlwi 4, 4, 24
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: srawi 4, 3, 31
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i8 %a to i64
+ %bext = zext i8 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
+ %trunc = trunc i64 %abs to i8
+ ret i8 %trunc
+}
+
+define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 3, 3, 16
+; PPC64-NEXT: clrlwi 4, 4, 16
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: srawi 4, 3, 31
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i16 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i16
+ ret i16 %trunc
+}
+
+define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_ext_i16_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB3_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB3_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i16_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 3, 3, 16
+; PPC64-NEXT: cmplw 3, 4
+; PPC64-NEXT: bgt 0, .LBB3_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB3_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i16 %a to i64
+ %bext = zext i32 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i16
+ ret i16 %trunc
+}
+
+define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i16_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i16_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 3, 3, 16
+; PPC64-NEXT: clrlwi 4, 4, 16
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: srawi 4, 3, 31
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i16 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
+ %trunc = trunc i64 %abs to i16
+ ret i16 %trunc
+}
+
+define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_ext_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB5_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB5_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmplw 3, 4
+; PPC64-NEXT: bgt 0, .LBB5_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB5_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i32 %a to i64
+ %bext = zext i32 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i32
+ ret i32 %trunc
+}
+
+define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
+; PPC32-LABEL: abd_ext_i32_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB6_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB6_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i32_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 4, 4, 16
+; PPC64-NEXT: cmplw 3, 4
+; PPC64-NEXT: bgt 0, .LBB6_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB6_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i32 %a to i64
+ %bext = zext i16 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i32
+ ret i32 %trunc
+}
+
+define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_ext_i32_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: cmplw 3, 4
+; PPC32-NEXT: bgt 0, .LBB7_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB7_2:
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i32_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmplw 3, 4
+; PPC64-NEXT: bgt 0, .LBB7_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB7_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %aext = zext i32 %a to i64
+ %bext = zext i32 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 true)
+ %trunc = trunc i64 %abs to i32
+ ret i32 %trunc
+}
+
+define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_ext_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB8_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB8_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB8_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB8_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
+ %aext = zext i64 %a to i128
+ %bext = zext i64 %b to i128
+ %sub = sub i128 %aext, %bext
+ %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)
+ %trunc = trunc i128 %abs to i64
+ ret i64 %trunc
+}
+
+define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_ext_i64_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB9_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB9_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i64_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB9_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB9_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
+ %aext = zext i64 %a to i128
+ %bext = zext i64 %b to i128
+ %sub = sub i128 %aext, %bext
+ %abs = call i128 @llvm.abs.i128(i128 %sub, i1 true)
+ %trunc = trunc i128 %abs to i64
+ ret i64 %trunc
+}
+
+define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_ext_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB10_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB10_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: blr
+ %aext = zext i128 %a to i256
+ %bext = zext i128 %b to i256
+ %sub = sub i256 %aext, %bext
+ %abs = call i256 @llvm.abs.i256(i256 %sub, i1 false)
+ %trunc = trunc i256 %abs to i128
+ ret i128 %trunc
+}
+
+define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_ext_i128_undef:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB11_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB11_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_ext_i128_undef:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: blr
+ %aext = zext i128 %a to i256
+ %bext = zext i128 %b to i256
+ %sub = sub i256 %aext, %bext
+ %abs = call i256 @llvm.abs.i256(i256 %sub, i1 true)
+ %trunc = trunc i256 %abs to i128
+ ret i128 %trunc
+}
+
+;
+; sub(umax(a,b),umin(a,b)) -> abdu(a,b)
+;
+
+define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_minmax_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 3, 3, 24
+; CHECK-NEXT: clrlwi 4, 4, 24
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
+ %max = call i8 @llvm.umax.i8(i8 %a, i8 %b)
+ %sub = sub i8 %max, %min
+ ret i8 %sub
+}
+
+define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
+; CHECK-LABEL: abd_minmax_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 3, 3, 16
+; CHECK-NEXT: clrlwi 4, 4, 16
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
+ %max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
+ %sub = sub i16 %max, %min
+ ret i16 %sub
+}
+
+define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: abd_minmax_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: bgt 0, .LBB14_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 4, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB14_2:
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
+ %max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
+ %sub = sub i32 %max, %min
+ ret i32 %sub
+}
+
+define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_minmax_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB15_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB15_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB15_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB15_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
+ %min = call i64 @llvm.umin.i64(i64 %a, i64 %b)
+ %max = call i64 @llvm.umax.i64(i64 %a, i64 %b)
+ %sub = sub i64 %max, %min
+ ret i64 %sub
+}
+
+define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_minmax_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB16_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB16_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: blr
+ %min = call i128 @llvm.umin.i128(i128 %a, i128 %b)
+ %max = call i128 @llvm.umax.i128(i128 %a, i128 %b)
+ %sub = sub i128 %max, %min
+ ret i128 %sub
+}
+
+;
+; select(icmp(a,b),sub(a,b),sub(b,a)) -> abdu(a,b)
+;
+
+define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_cmp_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 3, 3, 24
+; CHECK-NEXT: clrlwi 4, 4, 24
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ugt i8 %a, %b
+ %ab = sub i8 %a, %b
+ %ba = sub i8 %b, %a
+ %sel = select i1 %cmp, i8 %ab, i8 %ba
+ ret i8 %sel
+}
+
+define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
+; CHECK-LABEL: abd_cmp_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 3, 3, 16
+; CHECK-NEXT: clrlwi 4, 4, 16
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp uge i16 %a, %b
+ %ab = sub i16 %a, %b
+ %ba = sub i16 %b, %a
+ %sel = select i1 %cmp, i16 %ab, i16 %ba
+ ret i16 %sel
+}
+
+define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: abd_cmp_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: bgt 0, .LBB19_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 4, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB19_2:
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ult i32 %a, %b
+ %ab = sub i32 %a, %b
+ %ba = sub i32 %b, %a
+ %sel = select i1 %cmp, i32 %ba, i32 %ab
+ ret i32 %sel
+}
+
+define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_cmp_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB20_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB20_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB20_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB20_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
+ %cmp = icmp uge i64 %a, %b
+ %ab = sub i64 %a, %b
+ %ba = sub i64 %b, %a
+ %sel = select i1 %cmp, i64 %ab, i64 %ba
+ ret i64 %sel
+}
+
+define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_cmp_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB21_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB21_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: blr
+ %cmp = icmp uge i128 %a, %b
+ %ab = sub i128 %a, %b
+ %ba = sub i128 %b, %a
+ %sel = select i1 %cmp, i128 %ab, i128 %ba
+ ret i128 %sel
+}
+
+;
+; sub(select(icmp(a,b),a,b),select(icmp(a,b),b,a)) -> abdu(a,b)
+;
+
+define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_select_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 3, 3, 24
+; CHECK-NEXT: clrlwi 4, 4, 24
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ult i8 %a, %b
+ %ab = select i1 %cmp, i8 %a, i8 %b
+ %ba = select i1 %cmp, i8 %b, i8 %a
+ %sub = sub i8 %ba, %ab
+ ret i8 %sub
+}
+
+define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
+; CHECK-LABEL: abd_select_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: clrlwi 3, 3, 16
+; CHECK-NEXT: clrlwi 4, 4, 16
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: srawi 4, 3, 31
+; CHECK-NEXT: xor 3, 3, 4
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ule i16 %a, %b
+ %ab = select i1 %cmp, i16 %a, i16 %b
+ %ba = select i1 %cmp, i16 %b, i16 %a
+ %sub = sub i16 %ba, %ab
+ ret i16 %sub
+}
+
+define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: abd_select_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: cmplw 3, 4
+; CHECK-NEXT: bgt 0, .LBB24_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 4, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB24_2:
+; CHECK-NEXT: sub 3, 3, 4
+; CHECK-NEXT: blr
+ %cmp = icmp ugt i32 %a, %b
+ %ab = select i1 %cmp, i32 %a, i32 %b
+ %ba = select i1 %cmp, i32 %b, i32 %a
+ %sub = sub i32 %ab, %ba
+ ret i32 %sub
+}
+
+define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_select_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB25_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB25_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_select_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmpld 3, 4
+; PPC64-NEXT: bgt 0, .LBB25_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 4, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB25_2:
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
+ %cmp = icmp uge i64 %a, %b
+ %ab = select i1 %cmp, i64 %a, i64 %b
+ %ba = select i1 %cmp, i64 %b, i64 %a
+ %sub = sub i64 %ab, %ba
+ ret i64 %sub
+}
+
+define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
+; PPC32-LABEL: abd_select_i128:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 6, 6, 10
+; PPC32-NEXT: subfe 5, 9, 5
+; PPC32-NEXT: subfe 4, 8, 4
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: addze. 7, 11
+; PPC32-NEXT: li 7, -1
+; PPC32-NEXT: bc 12, 2, .LBB26_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: .LBB26_2:
+; PPC32-NEXT: xor 6, 6, 7
+; PPC32-NEXT: xor 5, 5, 7
+; PPC32-NEXT: subc 6, 6, 7
+; PPC32-NEXT: xor 4, 4, 7
+; PPC32-NEXT: subfe 5, 7, 5
+; PPC32-NEXT: xor 3, 3, 7
+; PPC32-NEXT: subfe 4, 7, 4
+; PPC32-NEXT: subfe 3, 7, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_select_i128:
+; PPC64: # %bb.0:
+; PPC64-NEXT: subc 4, 4, 6
+; PPC64-NEXT: li 7, 0
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: addze 5, 7
+; PPC64-NEXT: addic 5, 5, -1
+; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: xor 4, 4, 5
+; PPC64-NEXT: xor 3, 3, 5
+; PPC64-NEXT: subc 4, 4, 5
+; PPC64-NEXT: subfe 3, 5, 3
+; PPC64-NEXT: blr
+ %cmp = icmp ult i128 %a, %b
+ %ab = select i1 %cmp, i128 %a, i128 %b
+ %ba = select i1 %cmp, i128 %b, i128 %a
+ %sub = sub i128 %ba, %ab
+ ret i128 %sub
+}
+
+;
+; Operand is guaranteed non-zero: -(x | 1) cannot be 0
+;
+
+define i32 @abd_nonzero_rhs_i32(i32 %a, i32 %b) nounwind {
+; PPC32-LABEL: abd_nonzero_rhs_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: ori 4, 4, 1
+; PPC32-NEXT: neg 5, 4
+; PPC32-NEXT: cmplw 5, 3
+; PPC32-NEXT: blt 0, .LBB27_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: sub 3, 5, 3
+; PPC32-NEXT: blr
+; PPC32-NEXT: .LBB27_2:
+; PPC32-NEXT: add 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_nonzero_rhs_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: ori 4, 4, 1
+; PPC64-NEXT: neg 5, 4
+; PPC64-NEXT: cmplw 5, 3
+; PPC64-NEXT: blt 0, .LBB27_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB27_2:
+; PPC64-NEXT: add 3, 3, 4
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: blr
+ %b1 = or i32 %b, 1
+ %nb = sub i32 0, %b1
+ %aext = zext i32 %a to i64
+ %bext = zext i32 %nb to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i32
+ ret i32 %trunc
+}
+
+define i64 @abd_nonzero_rhs_i64(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_nonzero_rhs_i64:
+; PPC32: # %bb.0:
+; PPC32-NEXT: ori 6, 6, 1
+; PPC32-NEXT: subfic 6, 6, 0
+; PPC32-NEXT: subfze 5, 5
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB28_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB28_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_nonzero_rhs_i64:
+; PPC64: # %bb.0:
+; PPC64-NEXT: ori 4, 4, 1
+; PPC64-NEXT: neg 5, 4
+; PPC64-NEXT: cmpld 5, 3
+; PPC64-NEXT: blt 0, .LBB28_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB28_2:
+; PPC64-NEXT: add 3, 3, 4
+; PPC64-NEXT: blr
+ %b1 = or i64 %b, 1
+ %nb = sub i64 0, %b1
+ %aext = zext i64 %a to i128
+ %bext = zext i64 %nb to i128
+ %sub = sub i128 %aext, %bext
+ %abs = call i128 @llvm.abs.i128(i128 %sub, i1 false)
+ %trunc = trunc i128 %abs to i64
+ ret i64 %trunc
+}
+
+define i32 @abd_nonzero_rhs_i32_select(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: abd_nonzero_rhs_i32_select:
+; CHECK: # %bb.0:
+; CHECK-NEXT: ori 4, 4, 1
+; CHECK-NEXT: neg 5, 4
+; CHECK-NEXT: cmplw 5, 3
+; CHECK-NEXT: blt 0, .LBB29_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: sub 3, 5, 3
+; CHECK-NEXT: blr
+; CHECK-NEXT: .LBB29_2:
+; CHECK-NEXT: add 3, 3, 4
+; CHECK-NEXT: blr
+ %b1 = or i32 %b, 1
+ %nb = sub i32 0, %b1
+ %cmp = icmp ugt i32 %a, %nb
+ %ab = sub i32 %a, %nb
+ %ba = sub i32 %nb, %a
+ %sel = select i1 %cmp, i32 %ab, i32 %ba
+ ret i32 %sel
+}
+
+define i64 @abd_nonzero_rhs_i64_select(i64 %a, i64 %b) nounwind {
+; PPC32-LABEL: abd_nonzero_rhs_i64_select:
+; PPC32: # %bb.0:
+; PPC32-NEXT: ori 6, 6, 1
+; PPC32-NEXT: subfic 6, 6, 0
+; PPC32-NEXT: subfze 5, 5
+; PPC32-NEXT: subc 4, 4, 6
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: addze. 5, 7
+; PPC32-NEXT: li 5, -1
+; PPC32-NEXT: bc 12, 2, .LBB30_2
+; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: li 5, 0
+; PPC32-NEXT: .LBB30_2:
+; PPC32-NEXT: xor 4, 4, 5
+; PPC32-NEXT: xor 3, 3, 5
+; PPC32-NEXT: subc 4, 4, 5
+; PPC32-NEXT: subfe 3, 5, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_nonzero_rhs_i64_select:
+; PPC64: # %bb.0:
+; PPC64-NEXT: ori 4, 4, 1
+; PPC64-NEXT: neg 5, 4
+; PPC64-NEXT: cmpld 5, 3
+; PPC64-NEXT: blt 0, .LBB30_2
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB30_2:
+; PPC64-NEXT: add 3, 3, 4
+; PPC64-NEXT: blr
+ %b1 = or i64 %b, 1
+ %nb = sub i64 0, %b1
+ %cmp = icmp ugt i64 %a, %nb
+ %ab = sub i64 %a, %nb
+ %ba = sub i64 %nb, %a
+ %sel = select i1 %cmp, i64 %ab, i64 %ba
+ ret i64 %sel
+}
+
+declare i8 @llvm.abs.i8(i8, i1)
+declare i16 @llvm.abs.i16(i16, i1)
+declare i32 @llvm.abs.i32(i32, i1)
+declare i64 @llvm.abs.i64(i64, i1)
+declare i128 @llvm.abs.i128(i128, i1)
+
+declare i8 @llvm.umax.i8(i8, i8)
+declare i16 @llvm.umax.i16(i16, i16)
+declare i32 @llvm.umax.i32(i32, i32)
+declare i64 @llvm.umax.i64(i64, i64)
+
+declare i8 @llvm.umin.i8(i8, i8)
+declare i16 @llvm.umin.i16(i16, i16)
+declare i32 @llvm.umin.i32(i32, i32)
+declare i64 @llvm.umin.i64(i64, i64)
>From bfd1e2639fc942529992b1d9d417c146fd4cf730 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 21 Feb 2026 15:27:36 -0500
Subject: [PATCH 2/3] [PowerPC] Custom Lower ABDU using branchless carry
In normal abs, we already do this but with asr 31 instead of sbc, which we can get directly from the subtraction.
---
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 10 +
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 65 +-
llvm/lib/Target/PowerPC/PPCISelLowering.h | 1 +
llvm/test/CodeGen/PowerPC/abdu-neg.ll | 393 ++---
llvm/test/CodeGen/PowerPC/abdu.ll | 678 ++++----
.../test/CodeGen/PowerPC/fast-isel-cmp-imm.ll | 1391 +++++++++++++++--
6 files changed, 1921 insertions(+), 617 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 3db2b0e8e5d5a..16cb183dbd5e4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -5675,6 +5675,16 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
break;
}
+ case ISD::ABDU:
+ case ISD::ABDS: {
+ unsigned ExtOp =
+ Node->getOpcode() == ISD::ABDU ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;
+ Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
+ Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
+ Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
+ Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
+ break;
+ }
case ISD::UMUL_LOHI:
case ISD::SMUL_LOHI: {
// Promote to a multiply in a wider integer type.
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 22d17edf2915f..64be294e75053 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -603,10 +603,19 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
- // Custom handling for PowerPC ucmp instruction
+ // Custom handling for ucmp
setOperationAction(ISD::UCMP, MVT::i32, Custom);
setOperationAction(ISD::UCMP, MVT::i64, isPPC64 ? Custom : Expand);
+ // Custom handling for abdu
+ if (isPPC64) {
+ setOperationAction(ISD::ABDU, MVT::i32, Promote);
+ setOperationAction(ISD::ABDU, MVT::i64, Custom);
+ } else {
+ setOperationAction(ISD::ABDU, MVT::i32, Custom);
+ setOperationAction(ISD::ABDU, MVT::i64, Expand);
+ }
+
// NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
// SjLj exception handling but a light-weight setjmp/longjmp replacement to
// support continuation, user-level threading, and etc.. As a result, no
@@ -12748,6 +12757,58 @@ SDValue PPCTargetLowering::LowerSADDO(SDValue Op, SelectionDAG &DAG) const {
return DAG.getMergeValues({Sum, OverflowTrunc}, dl);
}
+SDValue PPCTargetLowering::LowerABDU(SDValue Op, SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ SDValue LHS = Op.getOperand(0);
+ SDValue RHS = Op.getOperand(1);
+ EVT OpVT = LHS.getValueType();
+ EVT VT = Op.getValueType();
+ bool IsNonNegative = DAG.SignBitIsZero(LHS) && DAG.SignBitIsZero(RHS);
+
+ // If the subtract doesn't overflow then just use abs(sub()).
+ if (DAG.willNotOverflowSub(IsNonNegative, LHS, RHS))
+ return DAG.getNode(ISD::ABS, DL, VT,
+ DAG.getNode(ISD::SUB, DL, VT, LHS, RHS));
+
+ if (DAG.willNotOverflowSub(IsNonNegative, RHS, LHS))
+ return DAG.getNode(ISD::ABS, DL, VT,
+ DAG.getNode(ISD::SUB, DL, VT, RHS, LHS));
+
+ // General path: use SUBC (or ADDC when RHS is 0-X) to get
+ // subtract-with-flags, then CMOV to select a-b or b-a. ADDC/SUBC produce the
+ // flags we need.
+ unsigned Opcode = PPCISD::SUBC;
+
+ // Check if RHS is a negation (0 - X). If so, we can use ADDC instead of SUBC:
+ // a - (0 - x) = a + x (mod 2^n)
+ // Same semantics as in LowerCMP; apply same safety checks.
+ if (RHS.getOpcode() == ISD::SUB) {
+ SDValue SubLHS = RHS.getOperand(0);
+ SDValue SubRHS = RHS.getOperand(1);
+
+ if (isNullConstant(SubLHS) && DAG.isKnownNeverZero(SubRHS)) {
+ Opcode = PPCISD::ADDC;
+ RHS = SubRHS;
+ }
+ }
+
+ // Calculate LHS - RHS and capture the carry (CA)
+ SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
+
+ SDValue Res = DAG.getNode(Opcode, DL, VTs, LHS, RHS);
+
+ SDValue CA0 = Res.getValue(1);
+
+ // t2 = A - B + CA0 using SUBE.
+ SDValue ZeroOrNeg1 = DAG.getNode(PPCISD::SUBE, DL, VTs, Res, Res, CA0);
+
+ SDValue Xor = DAG.getNode(ISD::XOR, DL, OpVT, Res, ZeroOrNeg1);
+
+ Res = DAG.getNode(ISD::SUB, DL, OpVT, Xor, ZeroOrNeg1);
+
+ return Res;
+}
+
// Lower unsigned 3-way compare producing -1/0/1.
SDValue PPCTargetLowering::LowerUCMP(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op);
@@ -12894,6 +12955,8 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
return LowerADDSUBO_CARRY(Op, DAG);
case ISD::UCMP:
return LowerUCMP(Op, DAG);
+ case ISD::ABDU:
+ return LowerABDU(Op, DAG);
case ISD::STRICT_LRINT:
case ISD::STRICT_LLRINT:
case ISD::STRICT_LROUND:
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index ed47ca96d5953..c30ee80224deb 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -741,6 +741,7 @@ namespace llvm {
SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerADDSUBO(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerABDU(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerUCMP(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerToLibCall(const char *LibCallName, SDValue Op,
SelectionDAG &DAG) const;
diff --git a/llvm/test/CodeGen/PowerPC/abdu-neg.ll b/llvm/test/CodeGen/PowerPC/abdu-neg.ll
index bfd656bd0f56f..d7ac27ec079e8 100644
--- a/llvm/test/CodeGen/PowerPC/abdu-neg.ll
+++ b/llvm/test/CodeGen/PowerPC/abdu-neg.ll
@@ -126,15 +126,10 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_ext_i16_i32:
; PPC32: # %bb.0:
; PPC32-NEXT: clrlwi 3, 3, 16
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB4_2
-; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: neg 3, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB4_2:
-; PPC32-NEXT: sub 3, 3, 4
-; PPC32-NEXT: neg 3, 3
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i16_i32:
@@ -187,15 +182,10 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_ext_i32:
; PPC32: # %bb.0:
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB6_2
-; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: neg 3, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB6_2:
-; PPC32-NEXT: sub 3, 3, 4
-; PPC32-NEXT: neg 3, 3
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i32:
@@ -220,15 +210,10 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
; PPC32-LABEL: abd_ext_i32_i16:
; PPC32: # %bb.0:
; PPC32-NEXT: clrlwi 4, 4, 16
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB7_2
-; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: neg 3, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB7_2:
-; PPC32-NEXT: sub 3, 3, 4
-; PPC32-NEXT: neg 3, 3
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i32_i16:
@@ -252,15 +237,10 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_ext_i32_undef:
; PPC32: # %bb.0:
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB8_2
-; PPC32-NEXT: # %bb.1:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: neg 3, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB8_2:
-; PPC32-NEXT: sub 3, 3, 4
-; PPC32-NEXT: neg 3, 3
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i32_undef:
@@ -285,14 +265,13 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
; PPC32-LABEL: abd_ext_i64:
; PPC32: # %bb.0:
; PPC32-NEXT: subc 4, 4, 6
-; PPC32-NEXT: li 7, 0
; PPC32-NEXT: subfe 3, 5, 3
-; PPC32-NEXT: addze. 5, 7
-; PPC32-NEXT: li 5, -1
-; PPC32-NEXT: bc 12, 2, .LBB9_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 5, 0
-; PPC32-NEXT: .LBB9_2:
+; PPC32-NEXT: mfxer 5
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: addze 6, 7
+; PPC32-NEXT: addic 6, 6, -1
+; PPC32-NEXT: mtxer 5
+; PPC32-NEXT: subfe 5, 6, 6
; PPC32-NEXT: xor 4, 4, 5
; PPC32-NEXT: xor 3, 3, 5
; PPC32-NEXT: subc 4, 4, 5
@@ -303,15 +282,10 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_ext_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB9_2
-; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: neg 3, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB9_2:
-; PPC64-NEXT: sub 3, 3, 4
-; PPC64-NEXT: neg 3, 3
; PPC64-NEXT: blr
%aext = zext i64 %a to i128
%bext = zext i64 %b to i128
@@ -326,14 +300,13 @@ define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
; PPC32-LABEL: abd_ext_i64_undef:
; PPC32: # %bb.0:
; PPC32-NEXT: subc 4, 4, 6
-; PPC32-NEXT: li 7, 0
; PPC32-NEXT: subfe 3, 5, 3
-; PPC32-NEXT: addze. 5, 7
-; PPC32-NEXT: li 5, -1
-; PPC32-NEXT: bc 12, 2, .LBB10_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 5, 0
-; PPC32-NEXT: .LBB10_2:
+; PPC32-NEXT: mfxer 5
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: addze 6, 7
+; PPC32-NEXT: addic 6, 6, -1
+; PPC32-NEXT: mtxer 5
+; PPC32-NEXT: subfe 5, 6, 6
; PPC32-NEXT: xor 4, 4, 5
; PPC32-NEXT: xor 3, 3, 5
; PPC32-NEXT: subc 4, 4, 5
@@ -344,15 +317,10 @@ define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_ext_i64_undef:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB10_2
-; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: neg 3, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB10_2:
-; PPC64-NEXT: sub 3, 3, 4
-; PPC64-NEXT: neg 3, 3
; PPC64-NEXT: blr
%aext = zext i64 %a to i128
%bext = zext i64 %b to i128
@@ -369,14 +337,13 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; PPC32-NEXT: subc 6, 6, 10
; PPC32-NEXT: subfe 5, 9, 5
; PPC32-NEXT: subfe 4, 8, 4
-; PPC32-NEXT: li 11, 0
; PPC32-NEXT: subfe 3, 7, 3
-; PPC32-NEXT: addze. 7, 11
-; PPC32-NEXT: li 7, -1
-; PPC32-NEXT: bc 12, 2, .LBB11_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 7, 0
-; PPC32-NEXT: .LBB11_2:
+; PPC32-NEXT: mfxer 7
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: addze 8, 11
+; PPC32-NEXT: addic 8, 8, -1
+; PPC32-NEXT: mtxer 7
+; PPC32-NEXT: subfe 7, 8, 8
; PPC32-NEXT: xor 6, 6, 7
; PPC32-NEXT: xor 5, 5, 7
; PPC32-NEXT: subc 6, 6, 7
@@ -396,9 +363,11 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; PPC64-NEXT: subc 4, 4, 6
; PPC64-NEXT: li 7, 0
; PPC64-NEXT: subfe 3, 5, 3
-; PPC64-NEXT: addze 5, 7
-; PPC64-NEXT: addic 5, 5, -1
-; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: mfxer 5
+; PPC64-NEXT: addze 6, 7
+; PPC64-NEXT: addic 6, 6, -1
+; PPC64-NEXT: mtxer 5
+; PPC64-NEXT: subfe 5, 6, 6
; PPC64-NEXT: xor 4, 4, 5
; PPC64-NEXT: xor 3, 3, 5
; PPC64-NEXT: subc 4, 4, 5
@@ -421,14 +390,13 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; PPC32-NEXT: subc 6, 6, 10
; PPC32-NEXT: subfe 5, 9, 5
; PPC32-NEXT: subfe 4, 8, 4
-; PPC32-NEXT: li 11, 0
; PPC32-NEXT: subfe 3, 7, 3
-; PPC32-NEXT: addze. 7, 11
-; PPC32-NEXT: li 7, -1
-; PPC32-NEXT: bc 12, 2, .LBB12_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 7, 0
-; PPC32-NEXT: .LBB12_2:
+; PPC32-NEXT: mfxer 7
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: addze 8, 11
+; PPC32-NEXT: addic 8, 8, -1
+; PPC32-NEXT: mtxer 7
+; PPC32-NEXT: subfe 7, 8, 8
; PPC32-NEXT: xor 6, 6, 7
; PPC32-NEXT: xor 5, 5, 7
; PPC32-NEXT: subc 6, 6, 7
@@ -448,9 +416,11 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; PPC64-NEXT: subc 4, 4, 6
; PPC64-NEXT: li 7, 0
; PPC64-NEXT: subfe 3, 5, 3
-; PPC64-NEXT: addze 5, 7
-; PPC64-NEXT: addic 5, 5, -1
-; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: mfxer 5
+; PPC64-NEXT: addze 6, 7
+; PPC64-NEXT: addic 6, 6, -1
+; PPC64-NEXT: mtxer 5
+; PPC64-NEXT: subfe 5, 6, 6
; PPC64-NEXT: xor 4, 4, 5
; PPC64-NEXT: xor 3, 3, 5
; PPC64-NEXT: subc 4, 4, 5
@@ -472,25 +442,35 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
;
define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
-; CHECK-LABEL: abd_minmax_i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 4, 4, 24
-; CHECK-NEXT: clrlwi 3, 3, 24
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: mr 5, 3
-; CHECK-NEXT: bge 0, .LBB13_3
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: ble 0, .LBB13_4
-; CHECK-NEXT: .LBB13_2:
-; CHECK-NEXT: sub 3, 5, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB13_3:
-; CHECK-NEXT: mr 5, 4
-; CHECK-NEXT: bgt 0, .LBB13_2
-; CHECK-NEXT: .LBB13_4:
-; CHECK-NEXT: mr 3, 4
-; CHECK-NEXT: sub 3, 5, 3
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_minmax_i8:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: clrlwi 4, 4, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i8:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 4, 4, 24
+; PPC64-NEXT: clrlwi 3, 3, 24
+; PPC64-NEXT: cmplw 3, 4
+; PPC64-NEXT: mr 5, 3
+; PPC64-NEXT: bge 0, .LBB13_3
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: ble 0, .LBB13_4
+; PPC64-NEXT: .LBB13_2:
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB13_3:
+; PPC64-NEXT: mr 5, 4
+; PPC64-NEXT: bgt 0, .LBB13_2
+; PPC64-NEXT: .LBB13_4:
+; PPC64-NEXT: mr 3, 4
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
%min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
%max = call i8 @llvm.umax.i8(i8 %a, i8 %b)
%sub = sub i8 %min, %max
@@ -498,25 +478,35 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
}
define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
-; CHECK-LABEL: abd_minmax_i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 4, 4, 16
-; CHECK-NEXT: clrlwi 3, 3, 16
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: mr 5, 3
-; CHECK-NEXT: bge 0, .LBB14_3
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: ble 0, .LBB14_4
-; CHECK-NEXT: .LBB14_2:
-; CHECK-NEXT: sub 3, 5, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB14_3:
-; CHECK-NEXT: mr 5, 4
-; CHECK-NEXT: bgt 0, .LBB14_2
-; CHECK-NEXT: .LBB14_4:
-; CHECK-NEXT: mr 3, 4
-; CHECK-NEXT: sub 3, 5, 3
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_minmax_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrlwi 4, 4, 16
+; PPC64-NEXT: clrlwi 3, 3, 16
+; PPC64-NEXT: cmplw 3, 4
+; PPC64-NEXT: mr 5, 3
+; PPC64-NEXT: bge 0, .LBB14_3
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: ble 0, .LBB14_4
+; PPC64-NEXT: .LBB14_2:
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB14_3:
+; PPC64-NEXT: mr 5, 4
+; PPC64-NEXT: bgt 0, .LBB14_2
+; PPC64-NEXT: .LBB14_4:
+; PPC64-NEXT: mr 3, 4
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
%min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
%max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
%sub = sub i16 %min, %max
@@ -524,23 +514,31 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
}
define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: abd_minmax_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: mr 5, 3
-; CHECK-NEXT: bge 0, .LBB15_3
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: ble 0, .LBB15_4
-; CHECK-NEXT: .LBB15_2:
-; CHECK-NEXT: sub 3, 5, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB15_3:
-; CHECK-NEXT: mr 5, 4
-; CHECK-NEXT: bgt 0, .LBB15_2
-; CHECK-NEXT: .LBB15_4:
-; CHECK-NEXT: mr 3, 4
-; CHECK-NEXT: sub 3, 5, 3
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_minmax_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: cmplw 3, 4
+; PPC64-NEXT: mr 5, 3
+; PPC64-NEXT: bge 0, .LBB15_3
+; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: ble 0, .LBB15_4
+; PPC64-NEXT: .LBB15_2:
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
+; PPC64-NEXT: .LBB15_3:
+; PPC64-NEXT: mr 5, 4
+; PPC64-NEXT: bgt 0, .LBB15_2
+; PPC64-NEXT: .LBB15_4:
+; PPC64-NEXT: mr 3, 4
+; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: blr
%min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
%max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
%sub = sub i32 %min, %max
@@ -582,20 +580,10 @@ define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_minmax_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: mr 5, 3
-; PPC64-NEXT: bge 0, .LBB16_3
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: ble 0, .LBB16_4
-; PPC64-NEXT: .LBB16_2:
-; PPC64-NEXT: sub 3, 5, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB16_3:
-; PPC64-NEXT: mr 5, 4
-; PPC64-NEXT: bgt 0, .LBB16_2
-; PPC64-NEXT: .LBB16_4:
-; PPC64-NEXT: mr 3, 4
-; PPC64-NEXT: sub 3, 5, 3
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 4, 3
; PPC64-NEXT: blr
%min = call i64 @llvm.umin.i64(i64 %a, i64 %b)
%max = call i64 @llvm.umax.i64(i64 %a, i64 %b)
@@ -731,18 +719,26 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
;
define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
-; CHECK-LABEL: abd_cmp_i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 5, 4, 24
-; CHECK-NEXT: clrlwi 6, 3, 24
-; CHECK-NEXT: cmplw 6, 5
-; CHECK-NEXT: ble 0, .LBB18_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: sub 3, 4, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB18_2:
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_cmp_i8:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: clrlwi 4, 4, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i8:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 56
+; PPC64-NEXT: clrldi 4, 4, 56
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: neg 3, 3
+; PPC64-NEXT: blr
%cmp = icmp ule i8 %a, %b
%ab = sub i8 %a, %b
%ba = sub i8 %b, %a
@@ -751,18 +747,26 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
}
define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
-; CHECK-LABEL: abd_cmp_i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 5, 4, 16
-; CHECK-NEXT: clrlwi 6, 3, 16
-; CHECK-NEXT: cmplw 6, 5
-; CHECK-NEXT: blt 0, .LBB19_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: sub 3, 4, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB19_2:
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_cmp_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: neg 3, 3
+; PPC64-NEXT: blr
%cmp = icmp ult i16 %a, %b
%ab = sub i16 %a, %b
%ba = sub i16 %b, %a
@@ -771,16 +775,24 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
}
define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: abd_cmp_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: bge 0, .LBB20_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB20_2:
-; CHECK-NEXT: sub 3, 4, 3
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_cmp_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 4, 3
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: neg 3, 3
+; PPC64-NEXT: blr
%cmp = icmp uge i32 %a, %b
%ab = sub i32 %a, %b
%ba = sub i32 %b, %a
@@ -813,13 +825,10 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_cmp_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: blt 0, .LBB21_2
-; PPC64-NEXT: # %bb.1:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB21_2:
-; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%cmp = icmp ult i64 %a, %b
%ab = sub i64 %a, %b
@@ -929,3 +938,5 @@ declare i8 @llvm.umin.i8(i8, i8)
declare i16 @llvm.umin.i16(i16, i16)
declare i32 @llvm.umin.i32(i32, i32)
declare i64 @llvm.umin.i64(i64, i64)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/PowerPC/abdu.ll b/llvm/test/CodeGen/PowerPC/abdu.ll
index b4ae1954d3d59..732c44bd1588f 100644
--- a/llvm/test/CodeGen/PowerPC/abdu.ll
+++ b/llvm/test/CodeGen/PowerPC/abdu.ll
@@ -19,10 +19,10 @@ define i8 @abd_ext_i8(i8 %a, i8 %b) nounwind {
;
; PPC64-LABEL: abd_ext_i8:
; PPC64: # %bb.0:
-; PPC64-NEXT: clrlwi 3, 3, 24
-; PPC64-NEXT: clrlwi 4, 4, 24
+; PPC64-NEXT: clrldi 3, 3, 56
+; PPC64-NEXT: clrldi 4, 4, 56
; PPC64-NEXT: sub 3, 3, 4
-; PPC64-NEXT: srawi 4, 3, 31
+; PPC64-NEXT: sradi 4, 3, 63
; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
@@ -48,10 +48,10 @@ define i8 @abd_ext_i8_undef(i8 %a, i8 %b) nounwind {
;
; PPC64-LABEL: abd_ext_i8_undef:
; PPC64: # %bb.0:
-; PPC64-NEXT: clrlwi 3, 3, 24
-; PPC64-NEXT: clrlwi 4, 4, 24
+; PPC64-NEXT: clrldi 3, 3, 56
+; PPC64-NEXT: clrldi 4, 4, 56
; PPC64-NEXT: sub 3, 3, 4
-; PPC64-NEXT: srawi 4, 3, 31
+; PPC64-NEXT: sradi 4, 3, 63
; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
@@ -77,10 +77,10 @@ define i16 @abd_ext_i16(i16 %a, i16 %b) nounwind {
;
; PPC64-LABEL: abd_ext_i16:
; PPC64: # %bb.0:
-; PPC64-NEXT: clrlwi 3, 3, 16
-; PPC64-NEXT: clrlwi 4, 4, 16
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 48
; PPC64-NEXT: sub 3, 3, 4
-; PPC64-NEXT: srawi 4, 3, 31
+; PPC64-NEXT: sradi 4, 3, 63
; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
@@ -97,25 +97,19 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_ext_i16_i32:
; PPC32: # %bb.0:
; PPC32-NEXT: clrlwi 3, 3, 16
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB3_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB3_2:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 3, 4
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i16_i32:
; PPC64: # %bb.0:
-; PPC64-NEXT: clrlwi 3, 3, 16
-; PPC64-NEXT: cmplw 3, 4
-; PPC64-NEXT: bgt 0, .LBB3_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: clrldi 3, 3, 32
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB3_2:
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
; PPC64-NEXT: blr
@@ -140,10 +134,10 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
;
; PPC64-LABEL: abd_ext_i16_undef:
; PPC64: # %bb.0:
-; PPC64-NEXT: clrlwi 3, 3, 16
-; PPC64-NEXT: clrlwi 4, 4, 16
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 48
; PPC64-NEXT: sub 3, 3, 4
-; PPC64-NEXT: srawi 4, 3, 31
+; PPC64-NEXT: sradi 4, 3, 63
; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
@@ -159,24 +153,19 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_ext_i32:
; PPC32: # %bb.0:
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB5_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB5_2:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 3, 4
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i32:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmplw 3, 4
-; PPC64-NEXT: bgt 0, .LBB5_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
; PPC64-NEXT: clrldi 3, 3, 32
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB5_2:
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
; PPC64-NEXT: blr
@@ -192,25 +181,19 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
; PPC32-LABEL: abd_ext_i32_i16:
; PPC32: # %bb.0:
; PPC32-NEXT: clrlwi 4, 4, 16
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB6_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB6_2:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 3, 4
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i32_i16:
; PPC64: # %bb.0:
-; PPC64-NEXT: clrlwi 4, 4, 16
-; PPC64-NEXT: cmplw 3, 4
-; PPC64-NEXT: bgt 0, .LBB6_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
; PPC64-NEXT: clrldi 3, 3, 32
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB6_2:
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
; PPC64-NEXT: blr
@@ -225,24 +208,19 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_ext_i32_undef:
; PPC32: # %bb.0:
-; PPC32-NEXT: cmplw 3, 4
-; PPC32-NEXT: bgt 0, .LBB7_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: sub 3, 4, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB7_2:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
; PPC32-NEXT: sub 3, 3, 4
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_ext_i32_undef:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmplw 3, 4
-; PPC64-NEXT: bgt 0, .LBB7_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
; PPC64-NEXT: clrldi 3, 3, 32
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB7_2:
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
; PPC64-NEXT: blr
@@ -258,14 +236,13 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
; PPC32-LABEL: abd_ext_i64:
; PPC32: # %bb.0:
; PPC32-NEXT: subc 4, 4, 6
-; PPC32-NEXT: li 7, 0
; PPC32-NEXT: subfe 3, 5, 3
-; PPC32-NEXT: addze. 5, 7
-; PPC32-NEXT: li 5, -1
-; PPC32-NEXT: bc 12, 2, .LBB8_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 5, 0
-; PPC32-NEXT: .LBB8_2:
+; PPC32-NEXT: mfxer 5
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: addze 6, 7
+; PPC32-NEXT: addic 6, 6, -1
+; PPC32-NEXT: mtxer 5
+; PPC32-NEXT: subfe 5, 6, 6
; PPC32-NEXT: xor 4, 4, 5
; PPC32-NEXT: xor 3, 3, 5
; PPC32-NEXT: subc 4, 4, 5
@@ -274,12 +251,9 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_ext_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB8_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB8_2:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%aext = zext i64 %a to i128
@@ -294,14 +268,13 @@ define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
; PPC32-LABEL: abd_ext_i64_undef:
; PPC32: # %bb.0:
; PPC32-NEXT: subc 4, 4, 6
-; PPC32-NEXT: li 7, 0
; PPC32-NEXT: subfe 3, 5, 3
-; PPC32-NEXT: addze. 5, 7
-; PPC32-NEXT: li 5, -1
-; PPC32-NEXT: bc 12, 2, .LBB9_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 5, 0
-; PPC32-NEXT: .LBB9_2:
+; PPC32-NEXT: mfxer 5
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: addze 6, 7
+; PPC32-NEXT: addic 6, 6, -1
+; PPC32-NEXT: mtxer 5
+; PPC32-NEXT: subfe 5, 6, 6
; PPC32-NEXT: xor 4, 4, 5
; PPC32-NEXT: xor 3, 3, 5
; PPC32-NEXT: subc 4, 4, 5
@@ -310,12 +283,9 @@ define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_ext_i64_undef:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB9_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB9_2:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%aext = zext i64 %a to i128
@@ -332,14 +302,13 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; PPC32-NEXT: subc 6, 6, 10
; PPC32-NEXT: subfe 5, 9, 5
; PPC32-NEXT: subfe 4, 8, 4
-; PPC32-NEXT: li 11, 0
; PPC32-NEXT: subfe 3, 7, 3
-; PPC32-NEXT: addze. 7, 11
-; PPC32-NEXT: li 7, -1
-; PPC32-NEXT: bc 12, 2, .LBB10_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 7, 0
-; PPC32-NEXT: .LBB10_2:
+; PPC32-NEXT: mfxer 7
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: addze 8, 11
+; PPC32-NEXT: addic 8, 8, -1
+; PPC32-NEXT: mtxer 7
+; PPC32-NEXT: subfe 7, 8, 8
; PPC32-NEXT: xor 6, 6, 7
; PPC32-NEXT: xor 5, 5, 7
; PPC32-NEXT: subc 6, 6, 7
@@ -355,9 +324,11 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; PPC64-NEXT: subc 4, 4, 6
; PPC64-NEXT: li 7, 0
; PPC64-NEXT: subfe 3, 5, 3
-; PPC64-NEXT: addze 5, 7
-; PPC64-NEXT: addic 5, 5, -1
-; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: mfxer 5
+; PPC64-NEXT: addze 6, 7
+; PPC64-NEXT: addic 6, 6, -1
+; PPC64-NEXT: mtxer 5
+; PPC64-NEXT: subfe 5, 6, 6
; PPC64-NEXT: xor 4, 4, 5
; PPC64-NEXT: xor 3, 3, 5
; PPC64-NEXT: subc 4, 4, 5
@@ -377,14 +348,13 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; PPC32-NEXT: subc 6, 6, 10
; PPC32-NEXT: subfe 5, 9, 5
; PPC32-NEXT: subfe 4, 8, 4
-; PPC32-NEXT: li 11, 0
; PPC32-NEXT: subfe 3, 7, 3
-; PPC32-NEXT: addze. 7, 11
-; PPC32-NEXT: li 7, -1
-; PPC32-NEXT: bc 12, 2, .LBB11_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 7, 0
-; PPC32-NEXT: .LBB11_2:
+; PPC32-NEXT: mfxer 7
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: addze 8, 11
+; PPC32-NEXT: addic 8, 8, -1
+; PPC32-NEXT: mtxer 7
+; PPC32-NEXT: subfe 7, 8, 8
; PPC32-NEXT: xor 6, 6, 7
; PPC32-NEXT: xor 5, 5, 7
; PPC32-NEXT: subc 6, 6, 7
@@ -400,9 +370,11 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; PPC64-NEXT: subc 4, 4, 6
; PPC64-NEXT: li 7, 0
; PPC64-NEXT: subfe 3, 5, 3
-; PPC64-NEXT: addze 5, 7
-; PPC64-NEXT: addic 5, 5, -1
-; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: mfxer 5
+; PPC64-NEXT: addze 6, 7
+; PPC64-NEXT: addic 6, 6, -1
+; PPC64-NEXT: mtxer 5
+; PPC64-NEXT: subfe 5, 6, 6
; PPC64-NEXT: xor 4, 4, 5
; PPC64-NEXT: xor 3, 3, 5
; PPC64-NEXT: subc 4, 4, 5
@@ -421,15 +393,25 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
;
define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
-; CHECK-LABEL: abd_minmax_i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 3, 3, 24
-; CHECK-NEXT: clrlwi 4, 4, 24
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: srawi 4, 3, 31
-; CHECK-NEXT: xor 3, 3, 4
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_minmax_i8:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: clrlwi 4, 4, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i8:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 56
+; PPC64-NEXT: clrldi 4, 4, 56
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%min = call i8 @llvm.umin.i8(i8 %a, i8 %b)
%max = call i8 @llvm.umax.i8(i8 %a, i8 %b)
%sub = sub i8 %max, %min
@@ -437,15 +419,25 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
}
define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
-; CHECK-LABEL: abd_minmax_i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 3, 3, 16
-; CHECK-NEXT: clrlwi 4, 4, 16
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: srawi 4, 3, 31
-; CHECK-NEXT: xor 3, 3, 4
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_minmax_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%min = call i16 @llvm.umin.i16(i16 %a, i16 %b)
%max = call i16 @llvm.umax.i16(i16 %a, i16 %b)
%sub = sub i16 %max, %min
@@ -453,16 +445,23 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
}
define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: abd_minmax_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: bgt 0, .LBB14_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: sub 3, 4, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB14_2:
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_minmax_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_minmax_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%min = call i32 @llvm.umin.i32(i32 %a, i32 %b)
%max = call i32 @llvm.umax.i32(i32 %a, i32 %b)
%sub = sub i32 %max, %min
@@ -473,14 +472,13 @@ define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
; PPC32-LABEL: abd_minmax_i64:
; PPC32: # %bb.0:
; PPC32-NEXT: subc 4, 4, 6
-; PPC32-NEXT: li 7, 0
; PPC32-NEXT: subfe 3, 5, 3
-; PPC32-NEXT: addze. 5, 7
-; PPC32-NEXT: li 5, -1
-; PPC32-NEXT: bc 12, 2, .LBB15_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 5, 0
-; PPC32-NEXT: .LBB15_2:
+; PPC32-NEXT: mfxer 5
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: addze 6, 7
+; PPC32-NEXT: addic 6, 6, -1
+; PPC32-NEXT: mtxer 5
+; PPC32-NEXT: subfe 5, 6, 6
; PPC32-NEXT: xor 4, 4, 5
; PPC32-NEXT: xor 3, 3, 5
; PPC32-NEXT: subc 4, 4, 5
@@ -489,12 +487,9 @@ define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_minmax_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB15_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB15_2:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%min = call i64 @llvm.umin.i64(i64 %a, i64 %b)
@@ -509,14 +504,13 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
; PPC32-NEXT: subc 6, 6, 10
; PPC32-NEXT: subfe 5, 9, 5
; PPC32-NEXT: subfe 4, 8, 4
-; PPC32-NEXT: li 11, 0
; PPC32-NEXT: subfe 3, 7, 3
-; PPC32-NEXT: addze. 7, 11
-; PPC32-NEXT: li 7, -1
-; PPC32-NEXT: bc 12, 2, .LBB16_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 7, 0
-; PPC32-NEXT: .LBB16_2:
+; PPC32-NEXT: mfxer 7
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: addze 8, 11
+; PPC32-NEXT: addic 8, 8, -1
+; PPC32-NEXT: mtxer 7
+; PPC32-NEXT: subfe 7, 8, 8
; PPC32-NEXT: xor 6, 6, 7
; PPC32-NEXT: xor 5, 5, 7
; PPC32-NEXT: subc 6, 6, 7
@@ -532,9 +526,11 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
; PPC64-NEXT: subc 4, 4, 6
; PPC64-NEXT: li 7, 0
; PPC64-NEXT: subfe 3, 5, 3
-; PPC64-NEXT: addze 5, 7
-; PPC64-NEXT: addic 5, 5, -1
-; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: mfxer 5
+; PPC64-NEXT: addze 6, 7
+; PPC64-NEXT: addic 6, 6, -1
+; PPC64-NEXT: mtxer 5
+; PPC64-NEXT: subfe 5, 6, 6
; PPC64-NEXT: xor 4, 4, 5
; PPC64-NEXT: xor 3, 3, 5
; PPC64-NEXT: subc 4, 4, 5
@@ -551,15 +547,25 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
;
define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
-; CHECK-LABEL: abd_cmp_i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 3, 3, 24
-; CHECK-NEXT: clrlwi 4, 4, 24
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: srawi 4, 3, 31
-; CHECK-NEXT: xor 3, 3, 4
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_cmp_i8:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: clrlwi 4, 4, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i8:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 56
+; PPC64-NEXT: clrldi 4, 4, 56
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%cmp = icmp ugt i8 %a, %b
%ab = sub i8 %a, %b
%ba = sub i8 %b, %a
@@ -568,15 +574,25 @@ define i8 @abd_cmp_i8(i8 %a, i8 %b) nounwind {
}
define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
-; CHECK-LABEL: abd_cmp_i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 3, 3, 16
-; CHECK-NEXT: clrlwi 4, 4, 16
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: srawi 4, 3, 31
-; CHECK-NEXT: xor 3, 3, 4
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_cmp_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%cmp = icmp uge i16 %a, %b
%ab = sub i16 %a, %b
%ba = sub i16 %b, %a
@@ -585,16 +601,23 @@ define i16 @abd_cmp_i16(i16 %a, i16 %b) nounwind {
}
define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: abd_cmp_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: bgt 0, .LBB19_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: sub 3, 4, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB19_2:
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_cmp_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_cmp_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%cmp = icmp ult i32 %a, %b
%ab = sub i32 %a, %b
%ba = sub i32 %b, %a
@@ -606,14 +629,13 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
; PPC32-LABEL: abd_cmp_i64:
; PPC32: # %bb.0:
; PPC32-NEXT: subc 4, 4, 6
-; PPC32-NEXT: li 7, 0
; PPC32-NEXT: subfe 3, 5, 3
-; PPC32-NEXT: addze. 5, 7
-; PPC32-NEXT: li 5, -1
-; PPC32-NEXT: bc 12, 2, .LBB20_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 5, 0
-; PPC32-NEXT: .LBB20_2:
+; PPC32-NEXT: mfxer 5
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: addze 6, 7
+; PPC32-NEXT: addic 6, 6, -1
+; PPC32-NEXT: mtxer 5
+; PPC32-NEXT: subfe 5, 6, 6
; PPC32-NEXT: xor 4, 4, 5
; PPC32-NEXT: xor 3, 3, 5
; PPC32-NEXT: subc 4, 4, 5
@@ -622,12 +644,9 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_cmp_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB20_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB20_2:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%cmp = icmp uge i64 %a, %b
@@ -643,14 +662,13 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; PPC32-NEXT: subc 6, 6, 10
; PPC32-NEXT: subfe 5, 9, 5
; PPC32-NEXT: subfe 4, 8, 4
-; PPC32-NEXT: li 11, 0
; PPC32-NEXT: subfe 3, 7, 3
-; PPC32-NEXT: addze. 7, 11
-; PPC32-NEXT: li 7, -1
-; PPC32-NEXT: bc 12, 2, .LBB21_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 7, 0
-; PPC32-NEXT: .LBB21_2:
+; PPC32-NEXT: mfxer 7
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: addze 8, 11
+; PPC32-NEXT: addic 8, 8, -1
+; PPC32-NEXT: mtxer 7
+; PPC32-NEXT: subfe 7, 8, 8
; PPC32-NEXT: xor 6, 6, 7
; PPC32-NEXT: xor 5, 5, 7
; PPC32-NEXT: subc 6, 6, 7
@@ -666,9 +684,11 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; PPC64-NEXT: subc 4, 4, 6
; PPC64-NEXT: li 7, 0
; PPC64-NEXT: subfe 3, 5, 3
-; PPC64-NEXT: addze 5, 7
-; PPC64-NEXT: addic 5, 5, -1
-; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: mfxer 5
+; PPC64-NEXT: addze 6, 7
+; PPC64-NEXT: addic 6, 6, -1
+; PPC64-NEXT: mtxer 5
+; PPC64-NEXT: subfe 5, 6, 6
; PPC64-NEXT: xor 4, 4, 5
; PPC64-NEXT: xor 3, 3, 5
; PPC64-NEXT: subc 4, 4, 5
@@ -686,15 +706,25 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
;
define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
-; CHECK-LABEL: abd_select_i8:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 3, 3, 24
-; CHECK-NEXT: clrlwi 4, 4, 24
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: srawi 4, 3, 31
-; CHECK-NEXT: xor 3, 3, 4
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_select_i8:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 24
+; PPC32-NEXT: clrlwi 4, 4, 24
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_select_i8:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 56
+; PPC64-NEXT: clrldi 4, 4, 56
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%cmp = icmp ult i8 %a, %b
%ab = select i1 %cmp, i8 %a, i8 %b
%ba = select i1 %cmp, i8 %b, i8 %a
@@ -703,15 +733,25 @@ define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
}
define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
-; CHECK-LABEL: abd_select_i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 3, 3, 16
-; CHECK-NEXT: clrlwi 4, 4, 16
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: srawi 4, 3, 31
-; CHECK-NEXT: xor 3, 3, 4
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_select_i16:
+; PPC32: # %bb.0:
+; PPC32-NEXT: clrlwi 3, 3, 16
+; PPC32-NEXT: clrlwi 4, 4, 16
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: srawi 4, 3, 31
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_select_i16:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 48
+; PPC64-NEXT: clrldi 4, 4, 48
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%cmp = icmp ule i16 %a, %b
%ab = select i1 %cmp, i16 %a, i16 %b
%ba = select i1 %cmp, i16 %b, i16 %a
@@ -720,16 +760,23 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
}
define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: abd_select_i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: cmplw 3, 4
-; CHECK-NEXT: bgt 0, .LBB24_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: sub 3, 4, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB24_2:
-; CHECK-NEXT: sub 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_select_i32:
+; PPC32: # %bb.0:
+; PPC32-NEXT: subc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_select_i32:
+; PPC64: # %bb.0:
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%cmp = icmp ugt i32 %a, %b
%ab = select i1 %cmp, i32 %a, i32 %b
%ba = select i1 %cmp, i32 %b, i32 %a
@@ -741,14 +788,13 @@ define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
; PPC32-LABEL: abd_select_i64:
; PPC32: # %bb.0:
; PPC32-NEXT: subc 4, 4, 6
-; PPC32-NEXT: li 7, 0
; PPC32-NEXT: subfe 3, 5, 3
-; PPC32-NEXT: addze. 5, 7
-; PPC32-NEXT: li 5, -1
-; PPC32-NEXT: bc 12, 2, .LBB25_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 5, 0
-; PPC32-NEXT: .LBB25_2:
+; PPC32-NEXT: mfxer 5
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: addze 6, 7
+; PPC32-NEXT: addic 6, 6, -1
+; PPC32-NEXT: mtxer 5
+; PPC32-NEXT: subfe 5, 6, 6
; PPC32-NEXT: xor 4, 4, 5
; PPC32-NEXT: xor 3, 3, 5
; PPC32-NEXT: subc 4, 4, 5
@@ -757,12 +803,9 @@ define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
;
; PPC64-LABEL: abd_select_i64:
; PPC64: # %bb.0:
-; PPC64-NEXT: cmpld 3, 4
-; PPC64-NEXT: bgt 0, .LBB25_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 4, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB25_2:
+; PPC64-NEXT: subc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%cmp = icmp uge i64 %a, %b
@@ -778,14 +821,13 @@ define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
; PPC32-NEXT: subc 6, 6, 10
; PPC32-NEXT: subfe 5, 9, 5
; PPC32-NEXT: subfe 4, 8, 4
-; PPC32-NEXT: li 11, 0
; PPC32-NEXT: subfe 3, 7, 3
-; PPC32-NEXT: addze. 7, 11
-; PPC32-NEXT: li 7, -1
-; PPC32-NEXT: bc 12, 2, .LBB26_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 7, 0
-; PPC32-NEXT: .LBB26_2:
+; PPC32-NEXT: mfxer 7
+; PPC32-NEXT: li 11, 0
+; PPC32-NEXT: addze 8, 11
+; PPC32-NEXT: addic 8, 8, -1
+; PPC32-NEXT: mtxer 7
+; PPC32-NEXT: subfe 7, 8, 8
; PPC32-NEXT: xor 6, 6, 7
; PPC32-NEXT: xor 5, 5, 7
; PPC32-NEXT: subc 6, 6, 7
@@ -801,9 +843,11 @@ define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
; PPC64-NEXT: subc 4, 4, 6
; PPC64-NEXT: li 7, 0
; PPC64-NEXT: subfe 3, 5, 3
-; PPC64-NEXT: addze 5, 7
-; PPC64-NEXT: addic 5, 5, -1
-; PPC64-NEXT: subfe 5, 5, 5
+; PPC64-NEXT: mfxer 5
+; PPC64-NEXT: addze 6, 7
+; PPC64-NEXT: addic 6, 6, -1
+; PPC64-NEXT: mtxer 5
+; PPC64-NEXT: subfe 5, 6, 6
; PPC64-NEXT: xor 4, 4, 5
; PPC64-NEXT: xor 3, 3, 5
; PPC64-NEXT: subc 4, 4, 5
@@ -824,28 +868,22 @@ define i32 @abd_nonzero_rhs_i32(i32 %a, i32 %b) nounwind {
; PPC32-LABEL: abd_nonzero_rhs_i32:
; PPC32: # %bb.0:
; PPC32-NEXT: ori 4, 4, 1
-; PPC32-NEXT: neg 5, 4
-; PPC32-NEXT: cmplw 5, 3
-; PPC32-NEXT: blt 0, .LBB27_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: sub 3, 5, 3
-; PPC32-NEXT: blr
-; PPC32-NEXT: .LBB27_2:
-; PPC32-NEXT: add 3, 3, 4
+; PPC32-NEXT: addc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
; PPC32-NEXT: blr
;
; PPC64-LABEL: abd_nonzero_rhs_i32:
; PPC64: # %bb.0:
; PPC64-NEXT: ori 4, 4, 1
-; PPC64-NEXT: neg 5, 4
-; PPC64-NEXT: cmplw 5, 3
-; PPC64-NEXT: blt 0, .LBB27_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 5, 3
; PPC64-NEXT: clrldi 3, 3, 32
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB27_2:
-; PPC64-NEXT: add 3, 3, 4
+; PPC64-NEXT: neg 4, 4
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: clrldi 3, 3, 32
; PPC64-NEXT: blr
%b1 = or i32 %b, 1
@@ -865,14 +903,13 @@ define i64 @abd_nonzero_rhs_i64(i64 %a, i64 %b) nounwind {
; PPC32-NEXT: subfic 6, 6, 0
; PPC32-NEXT: subfze 5, 5
; PPC32-NEXT: subc 4, 4, 6
-; PPC32-NEXT: li 7, 0
; PPC32-NEXT: subfe 3, 5, 3
-; PPC32-NEXT: addze. 5, 7
-; PPC32-NEXT: li 5, -1
-; PPC32-NEXT: bc 12, 2, .LBB28_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 5, 0
-; PPC32-NEXT: .LBB28_2:
+; PPC32-NEXT: mfxer 5
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: addze 6, 7
+; PPC32-NEXT: addic 6, 6, -1
+; PPC32-NEXT: mtxer 5
+; PPC32-NEXT: subfe 5, 6, 6
; PPC32-NEXT: xor 4, 4, 5
; PPC32-NEXT: xor 3, 3, 5
; PPC32-NEXT: subc 4, 4, 5
@@ -882,14 +919,10 @@ define i64 @abd_nonzero_rhs_i64(i64 %a, i64 %b) nounwind {
; PPC64-LABEL: abd_nonzero_rhs_i64:
; PPC64: # %bb.0:
; PPC64-NEXT: ori 4, 4, 1
-; PPC64-NEXT: neg 5, 4
-; PPC64-NEXT: cmpld 5, 3
-; PPC64-NEXT: blt 0, .LBB28_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 5, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB28_2:
-; PPC64-NEXT: add 3, 3, 4
+; PPC64-NEXT: addc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%b1 = or i64 %b, 1
%nb = sub i64 0, %b1
@@ -902,18 +935,26 @@ define i64 @abd_nonzero_rhs_i64(i64 %a, i64 %b) nounwind {
}
define i32 @abd_nonzero_rhs_i32_select(i32 %a, i32 %b) nounwind {
-; CHECK-LABEL: abd_nonzero_rhs_i32_select:
-; CHECK: # %bb.0:
-; CHECK-NEXT: ori 4, 4, 1
-; CHECK-NEXT: neg 5, 4
-; CHECK-NEXT: cmplw 5, 3
-; CHECK-NEXT: blt 0, .LBB29_2
-; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: sub 3, 5, 3
-; CHECK-NEXT: blr
-; CHECK-NEXT: .LBB29_2:
-; CHECK-NEXT: add 3, 3, 4
-; CHECK-NEXT: blr
+; PPC32-LABEL: abd_nonzero_rhs_i32_select:
+; PPC32: # %bb.0:
+; PPC32-NEXT: ori 4, 4, 1
+; PPC32-NEXT: addc 3, 3, 4
+; PPC32-NEXT: subfe 4, 3, 3
+; PPC32-NEXT: xor 3, 3, 4
+; PPC32-NEXT: sub 3, 3, 4
+; PPC32-NEXT: blr
+;
+; PPC64-LABEL: abd_nonzero_rhs_i32_select:
+; PPC64: # %bb.0:
+; PPC64-NEXT: ori 4, 4, 1
+; PPC64-NEXT: clrldi 3, 3, 32
+; PPC64-NEXT: neg 4, 4
+; PPC64-NEXT: clrldi 4, 4, 32
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: sradi 4, 3, 63
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
+; PPC64-NEXT: blr
%b1 = or i32 %b, 1
%nb = sub i32 0, %b1
%cmp = icmp ugt i32 %a, %nb
@@ -930,14 +971,13 @@ define i64 @abd_nonzero_rhs_i64_select(i64 %a, i64 %b) nounwind {
; PPC32-NEXT: subfic 6, 6, 0
; PPC32-NEXT: subfze 5, 5
; PPC32-NEXT: subc 4, 4, 6
-; PPC32-NEXT: li 7, 0
; PPC32-NEXT: subfe 3, 5, 3
-; PPC32-NEXT: addze. 5, 7
-; PPC32-NEXT: li 5, -1
-; PPC32-NEXT: bc 12, 2, .LBB30_2
-; PPC32-NEXT: # %bb.1:
-; PPC32-NEXT: li 5, 0
-; PPC32-NEXT: .LBB30_2:
+; PPC32-NEXT: mfxer 5
+; PPC32-NEXT: li 7, 0
+; PPC32-NEXT: addze 6, 7
+; PPC32-NEXT: addic 6, 6, -1
+; PPC32-NEXT: mtxer 5
+; PPC32-NEXT: subfe 5, 6, 6
; PPC32-NEXT: xor 4, 4, 5
; PPC32-NEXT: xor 3, 3, 5
; PPC32-NEXT: subc 4, 4, 5
@@ -947,14 +987,10 @@ define i64 @abd_nonzero_rhs_i64_select(i64 %a, i64 %b) nounwind {
; PPC64-LABEL: abd_nonzero_rhs_i64_select:
; PPC64: # %bb.0:
; PPC64-NEXT: ori 4, 4, 1
-; PPC64-NEXT: neg 5, 4
-; PPC64-NEXT: cmpld 5, 3
-; PPC64-NEXT: blt 0, .LBB30_2
-; PPC64-NEXT: # %bb.1:
-; PPC64-NEXT: sub 3, 5, 3
-; PPC64-NEXT: blr
-; PPC64-NEXT: .LBB30_2:
-; PPC64-NEXT: add 3, 3, 4
+; PPC64-NEXT: addc 3, 3, 4
+; PPC64-NEXT: subfe 4, 3, 3
+; PPC64-NEXT: xor 3, 3, 4
+; PPC64-NEXT: sub 3, 3, 4
; PPC64-NEXT: blr
%b1 = or i64 %b, 1
%nb = sub i64 0, %b1
@@ -980,3 +1016,5 @@ declare i8 @llvm.umin.i8(i8, i8)
declare i16 @llvm.umin.i16(i16, i16)
declare i32 @llvm.umin.i32(i32, i32)
declare i64 @llvm.umin.i64(i64, i64)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll b/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
index bb708be393562..92adf341d5706 100644
--- a/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
+++ b/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mattr=+vsx | FileCheck %s --check-prefix=VSX
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 -mattr=spe | FileCheck %s --check-prefix=SPE
@@ -5,18 +6,63 @@
declare void @foo()
define void @t1a(float %a) nounwind {
+; ELF64-LABEL: t1a:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: addis 3, 2, .LCPI0_0 at toc@ha
+; ELF64-NEXT: lfs 0, .LCPI0_0 at toc@l(3)
+; ELF64-NEXT: fcmpu 0, 1, 0
+; ELF64-NEXT: bne 0, .LBB0_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB0_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t1a:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: addis 3, 2, .LCPI0_0 at toc@ha
+; VSX-NEXT: lfs 0, .LCPI0_0 at toc@l(3)
+; VSX-NEXT: fcmpu 0, 1, 0
+; VSX-NEXT: bne 0, .LBB0_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB0_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t1a:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: lis 4, .LCPI0_0 at ha
+; SPE-NEXT: lwz 4, .LCPI0_0 at l(4)
+; SPE-NEXT: bl __nesf2
+; SPE-NEXT: cmplwi 3, 0
+; SPE-NEXT: bne 0, .LBB0_2
+; SPE-NEXT: b .LBB0_1
+; SPE-NEXT: .LBB0_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB0_2
+; SPE-NEXT: .LBB0_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t1a
-; SPE-LABEL: @t1a
-; VSX-LABEL: @t1a
%cmp = fcmp nnan ninf oeq float %a, 0.000000e+00
-; ELF64: addis
-; ELF64: lfs
-; ELF64: fcmpu
-; VSX: addis
-; VSX: lfs
-; VSX: fcmpu
-; SPE: efscmpeq
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -28,18 +74,63 @@ if.end: ; preds = %if.then, %entry
}
define void @t1b(float %a) nounwind {
+; ELF64-LABEL: t1b:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: addis 3, 2, .LCPI1_0 at toc@ha
+; ELF64-NEXT: lfs 0, .LCPI1_0 at toc@l(3)
+; ELF64-NEXT: fcmpu 0, 1, 0
+; ELF64-NEXT: bne 0, .LBB1_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB1_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t1b:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: addis 3, 2, .LCPI1_0 at toc@ha
+; VSX-NEXT: lfs 0, .LCPI1_0 at toc@l(3)
+; VSX-NEXT: fcmpu 0, 1, 0
+; VSX-NEXT: bne 0, .LBB1_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB1_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t1b:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: lis 4, .LCPI1_0 at ha
+; SPE-NEXT: lwz 4, .LCPI1_0 at l(4)
+; SPE-NEXT: bl __nesf2
+; SPE-NEXT: cmplwi 3, 0
+; SPE-NEXT: bne 0, .LBB1_2
+; SPE-NEXT: b .LBB1_1
+; SPE-NEXT: .LBB1_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB1_2
+; SPE-NEXT: .LBB1_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t1b
-; SPE-LABEL: @t1b
-; VSX-LABEL: @t1b
%cmp = fcmp nnan ninf oeq float %a, -0.000000e+00
-; ELF64: addis
-; ELF64: lfs
-; ELF64: fcmpu
-; VSX: addis
-; VSX: lfs
-; VSX: fcmpu
-; SPE: efscmpeq
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -51,18 +142,63 @@ if.end: ; preds = %if.then, %entry
}
define void @t1c(float %a) nounwind {
+; ELF64-LABEL: t1c:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: addis 3, 2, .LCPI2_0 at toc@ha
+; ELF64-NEXT: lfs 0, .LCPI2_0 at toc@l(3)
+; ELF64-NEXT: fcmpu 0, 0, 1
+; ELF64-NEXT: bne 0, .LBB2_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB2_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t1c:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: addis 3, 2, .LCPI2_0 at toc@ha
+; VSX-NEXT: lfs 0, .LCPI2_0 at toc@l(3)
+; VSX-NEXT: fcmpu 0, 0, 1
+; VSX-NEXT: bne 0, .LBB2_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB2_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t1c:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: lis 4, .LCPI2_0 at ha
+; SPE-NEXT: lwz 4, .LCPI2_0 at l(4)
+; SPE-NEXT: bl __nesf2
+; SPE-NEXT: cmplwi 3, 0
+; SPE-NEXT: bne 0, .LBB2_2
+; SPE-NEXT: b .LBB2_1
+; SPE-NEXT: .LBB2_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB2_2
+; SPE-NEXT: .LBB2_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t1c
-; SPE-LABEL: @t1c
-; VSX-LABEL: @t1c
%cmp = fcmp nnan ninf oeq float -0.000000e+00, %a
-; ELF64: addis
-; ELF64: lfs
-; ELF64: fcmpu
-; VSX: addis
-; VSX: lfs
-; VSX: fcmpu
-; SPE: efscmpeq
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -74,18 +210,71 @@ if.end: ; preds = %if.then, %entry
}
define void @t2a(double %a) nounwind {
+; ELF64-LABEL: t2a:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
+; ELF64-NEXT: lfd 0, .LCPI3_0 at toc@l(3)
+; ELF64-NEXT: fcmpu 0, 1, 0
+; ELF64-NEXT: bne 0, .LBB3_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB3_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t2a:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: addis 3, 2, .LCPI3_0 at toc@ha
+; VSX-NEXT: lfd 0, .LCPI3_0 at toc@l(3)
+; VSX-NEXT: xscmpudp 0, 1, 0
+; VSX-NEXT: bne 0, .LBB3_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB3_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t2a:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: evmergelo 3, 3, 4
+; SPE-NEXT: li 5, .LCPI3_0 at l
+; SPE-NEXT: lis 4, .LCPI3_0 at ha
+; SPE-NEXT: evlddx 5, 4, 5
+; SPE-NEXT: mr 6, 5
+; SPE-NEXT: mr 4, 3
+; SPE-NEXT: evmergehi 5, 5, 5
+; SPE-NEXT: # kill: def $r5 killed $r5 killed $s5
+; SPE-NEXT: evmergehi 3, 3, 3
+; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
+; SPE-NEXT: bl __nedf2
+; SPE-NEXT: cmplwi 3, 0
+; SPE-NEXT: bne 0, .LBB3_2
+; SPE-NEXT: b .LBB3_1
+; SPE-NEXT: .LBB3_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB3_2
+; SPE-NEXT: .LBB3_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t2a
-; SPE-LABEL: @t2a
-; VSX-LABEL: @t2a
%cmp = fcmp nnan ninf oeq double %a, 0.000000e+00
-; ELF64: addis
-; ELF64: lfd
-; ELF64: fcmpu
-; VSX: addis
-; VSX: lfd
-; VSX: xscmpudp
-; SPE: efdcmpeq
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -97,18 +286,71 @@ if.end: ; preds = %if.then, %entry
}
define void @t2b(double %a) nounwind {
+; ELF64-LABEL: t2b:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: addis 3, 2, .LCPI4_0 at toc@ha
+; ELF64-NEXT: lfd 0, .LCPI4_0 at toc@l(3)
+; ELF64-NEXT: fcmpu 0, 1, 0
+; ELF64-NEXT: bne 0, .LBB4_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB4_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t2b:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: addis 3, 2, .LCPI4_0 at toc@ha
+; VSX-NEXT: lfd 0, .LCPI4_0 at toc@l(3)
+; VSX-NEXT: xscmpudp 0, 1, 0
+; VSX-NEXT: bne 0, .LBB4_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB4_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t2b:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: evmergelo 3, 3, 4
+; SPE-NEXT: li 5, .LCPI4_0 at l
+; SPE-NEXT: lis 4, .LCPI4_0 at ha
+; SPE-NEXT: evlddx 5, 4, 5
+; SPE-NEXT: mr 6, 5
+; SPE-NEXT: mr 4, 3
+; SPE-NEXT: evmergehi 5, 5, 5
+; SPE-NEXT: # kill: def $r5 killed $r5 killed $s5
+; SPE-NEXT: evmergehi 3, 3, 3
+; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
+; SPE-NEXT: bl __nedf2
+; SPE-NEXT: cmplwi 3, 0
+; SPE-NEXT: bne 0, .LBB4_2
+; SPE-NEXT: b .LBB4_1
+; SPE-NEXT: .LBB4_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB4_2
+; SPE-NEXT: .LBB4_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t2b
-; SPE-LABEL: @t2b
-; VSX-LABEL: @t2b
%cmp = fcmp nnan ninf oeq double %a, -0.000000e+00
-; ELF64: addis
-; ELF64: lfd
-; ELF64: fcmpu
-; VSX: addis
-; VSX: lfd
-; VSX: xscmpudp
-; SPE: efdcmpeq
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -120,18 +362,71 @@ if.end: ; preds = %if.then, %entry
}
define void @t2c(double %a) nounwind {
+; ELF64-LABEL: t2c:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: addis 3, 2, .LCPI5_0 at toc@ha
+; ELF64-NEXT: lfd 0, .LCPI5_0 at toc@l(3)
+; ELF64-NEXT: fcmpu 0, 0, 1
+; ELF64-NEXT: bne 0, .LBB5_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB5_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t2c:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: addis 3, 2, .LCPI5_0 at toc@ha
+; VSX-NEXT: lfd 0, .LCPI5_0 at toc@l(3)
+; VSX-NEXT: xscmpudp 0, 0, 1
+; VSX-NEXT: bne 0, .LBB5_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB5_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t2c:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: evmergelo 3, 3, 4
+; SPE-NEXT: li 5, .LCPI5_0 at l
+; SPE-NEXT: lis 4, .LCPI5_0 at ha
+; SPE-NEXT: evlddx 5, 4, 5
+; SPE-NEXT: mr 6, 5
+; SPE-NEXT: mr 4, 3
+; SPE-NEXT: evmergehi 5, 5, 5
+; SPE-NEXT: # kill: def $r5 killed $r5 killed $s5
+; SPE-NEXT: evmergehi 3, 3, 3
+; SPE-NEXT: # kill: def $r3 killed $r3 killed $s3
+; SPE-NEXT: bl __nedf2
+; SPE-NEXT: cmplwi 3, 0
+; SPE-NEXT: bne 0, .LBB5_2
+; SPE-NEXT: b .LBB5_1
+; SPE-NEXT: .LBB5_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB5_2
+; SPE-NEXT: .LBB5_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t2c
-; SPE-LABEL: @t2c
-; VSX-LABEL: @t2c
%cmp = fcmp nnan ninf oeq double -0.000000e+00, %a
-; ELF64: addis
-; ELF64: lfd
-; ELF64: fcmpu
-; VSX: addis
-; VSX: lfd
-; VSX: xscmpudp
-; SPE: efdcmpeq
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -143,11 +438,60 @@ if.end: ; preds = %if.then, %entry
}
define void @t4(i8 signext %a) nounwind {
+; ELF64-LABEL: t4:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: # kill: def $r3 killed $r3 killed $x3
+; ELF64-NEXT: extsb 3, 3
+; ELF64-NEXT: cmpwi 3, -1
+; ELF64-NEXT: bne 0, .LBB6_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB6_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t4:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: # kill: def $r3 killed $r3 killed $x3
+; VSX-NEXT: extsb 3, 3
+; VSX-NEXT: cmpwi 3, -1
+; VSX-NEXT: bne 0, .LBB6_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB6_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t4:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: cmpwi 3, -1
+; SPE-NEXT: bne 0, .LBB6_2
+; SPE-NEXT: b .LBB6_1
+; SPE-NEXT: .LBB6_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB6_2
+; SPE-NEXT: .LBB6_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t4
%cmp = icmp eq i8 %a, -1
-; ELF64: extsb
-; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -159,11 +503,60 @@ if.end: ; preds = %if.then, %entry
}
define void @t5(i8 zeroext %a) nounwind {
+; ELF64-LABEL: t5:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: # kill: def $r3 killed $r3 killed $x3
+; ELF64-NEXT: extsb 3, 3
+; ELF64-NEXT: cmpwi 3, 1
+; ELF64-NEXT: bne 0, .LBB7_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB7_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t5:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: # kill: def $r3 killed $r3 killed $x3
+; VSX-NEXT: extsb 3, 3
+; VSX-NEXT: cmpwi 3, 1
+; VSX-NEXT: bne 0, .LBB7_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB7_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t5:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: cmplwi 3, 1
+; SPE-NEXT: bne 0, .LBB7_2
+; SPE-NEXT: b .LBB7_1
+; SPE-NEXT: .LBB7_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB7_2
+; SPE-NEXT: .LBB7_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t5
%cmp = icmp eq i8 %a, 1
-; ELF64: extsb
-; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -175,11 +568,64 @@ if.end: ; preds = %if.then, %entry
}
define void @t5a(i8 zeroext %a) nounwind {
+; ELF64-LABEL: t5a:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: mr 4, 3
+; ELF64-NEXT: li 3, 1
+; ELF64-NEXT: extsb 3, 3
+; ELF64-NEXT: extsb 4, 4
+; ELF64-NEXT: cmpw 3, 4
+; ELF64-NEXT: bne 0, .LBB8_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB8_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t5a:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: mr 4, 3
+; VSX-NEXT: li 3, 1
+; VSX-NEXT: extsb 3, 3
+; VSX-NEXT: extsb 4, 4
+; VSX-NEXT: cmpw 3, 4
+; VSX-NEXT: bne 0, .LBB8_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB8_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t5a:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: cmplwi 3, 1
+; SPE-NEXT: bne 0, .LBB8_2
+; SPE-NEXT: b .LBB8_1
+; SPE-NEXT: .LBB8_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB8_2
+; SPE-NEXT: .LBB8_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t5a
%cmp = icmp eq i8 1, %a
-; ELF64: extsb
-; ELF64: cmpw
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -191,11 +637,60 @@ if.end: ; preds = %if.then, %entry
}
define void @t6(i16 signext %a) nounwind {
+; ELF64-LABEL: t6:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: # kill: def $r3 killed $r3 killed $x3
+; ELF64-NEXT: extsh 3, 3
+; ELF64-NEXT: cmpwi 3, -1
+; ELF64-NEXT: bne 0, .LBB9_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB9_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t6:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: # kill: def $r3 killed $r3 killed $x3
+; VSX-NEXT: extsh 3, 3
+; VSX-NEXT: cmpwi 3, -1
+; VSX-NEXT: bne 0, .LBB9_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB9_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t6:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: cmpwi 3, -1
+; SPE-NEXT: bne 0, .LBB9_2
+; SPE-NEXT: b .LBB9_1
+; SPE-NEXT: .LBB9_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB9_2
+; SPE-NEXT: .LBB9_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t6
%cmp = icmp eq i16 %a, -1
-; ELF64: extsh
-; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -207,11 +702,60 @@ if.end: ; preds = %if.then, %entry
}
define void @t7(i16 zeroext %a) nounwind {
+; ELF64-LABEL: t7:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: # kill: def $r3 killed $r3 killed $x3
+; ELF64-NEXT: extsh 3, 3
+; ELF64-NEXT: cmpwi 3, 1
+; ELF64-NEXT: bne 0, .LBB10_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB10_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t7:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: # kill: def $r3 killed $r3 killed $x3
+; VSX-NEXT: extsh 3, 3
+; VSX-NEXT: cmpwi 3, 1
+; VSX-NEXT: bne 0, .LBB10_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB10_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t7:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: cmplwi 3, 1
+; SPE-NEXT: bne 0, .LBB10_2
+; SPE-NEXT: b .LBB10_1
+; SPE-NEXT: .LBB10_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB10_2
+; SPE-NEXT: .LBB10_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t7
%cmp = icmp eq i16 %a, 1
-; ELF64: extsh
-; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -223,11 +767,64 @@ if.end: ; preds = %if.then, %entry
}
define void @t7a(i16 zeroext %a) nounwind {
+; ELF64-LABEL: t7a:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: mr 4, 3
+; ELF64-NEXT: li 3, 1
+; ELF64-NEXT: extsh 3, 3
+; ELF64-NEXT: extsh 4, 4
+; ELF64-NEXT: cmpw 3, 4
+; ELF64-NEXT: bne 0, .LBB11_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB11_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t7a:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: mr 4, 3
+; VSX-NEXT: li 3, 1
+; VSX-NEXT: extsh 3, 3
+; VSX-NEXT: extsh 4, 4
+; VSX-NEXT: cmpw 3, 4
+; VSX-NEXT: bne 0, .LBB11_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB11_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t7a:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: cmplwi 3, 1
+; SPE-NEXT: bne 0, .LBB11_2
+; SPE-NEXT: b .LBB11_1
+; SPE-NEXT: .LBB11_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB11_2
+; SPE-NEXT: .LBB11_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t7a
%cmp = icmp eq i16 1, %a
-; ELF64: extsh
-; ELF64: cmpw
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -239,10 +836,58 @@ if.end: ; preds = %if.then, %entry
}
define void @t8(i32 %a) nounwind {
+; ELF64-LABEL: t8:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: # kill: def $r3 killed $r3 killed $x3
+; ELF64-NEXT: cmpwi 3, -1
+; ELF64-NEXT: bne 0, .LBB12_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB12_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t8:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: # kill: def $r3 killed $r3 killed $x3
+; VSX-NEXT: cmpwi 3, -1
+; VSX-NEXT: bne 0, .LBB12_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB12_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t8:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: cmpwi 3, -1
+; SPE-NEXT: bne 0, .LBB12_2
+; SPE-NEXT: b .LBB12_1
+; SPE-NEXT: .LBB12_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB12_2
+; SPE-NEXT: .LBB12_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t8
%cmp = icmp eq i32 %a, -1
-; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -254,10 +899,58 @@ if.end: ; preds = %if.then, %entry
}
define void @t9(i32 %a) nounwind {
+; ELF64-LABEL: t9:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: # kill: def $r3 killed $r3 killed $x3
+; ELF64-NEXT: cmpwi 3, 1
+; ELF64-NEXT: bne 0, .LBB13_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB13_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t9:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: # kill: def $r3 killed $r3 killed $x3
+; VSX-NEXT: cmpwi 3, 1
+; VSX-NEXT: bne 0, .LBB13_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB13_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t9:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: cmplwi 3, 1
+; SPE-NEXT: bne 0, .LBB13_2
+; SPE-NEXT: b .LBB13_1
+; SPE-NEXT: .LBB13_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB13_2
+; SPE-NEXT: .LBB13_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t9
%cmp = icmp eq i32 %a, 1
-; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -269,10 +962,58 @@ if.end: ; preds = %if.then, %entry
}
define void @t10(i32 %a) nounwind {
+; ELF64-LABEL: t10:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: # kill: def $r3 killed $r3 killed $x3
+; ELF64-NEXT: cmpwi 3, 384
+; ELF64-NEXT: bne 0, .LBB14_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB14_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t10:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: # kill: def $r3 killed $r3 killed $x3
+; VSX-NEXT: cmpwi 3, 384
+; VSX-NEXT: bne 0, .LBB14_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB14_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t10:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: cmplwi 3, 384
+; SPE-NEXT: bne 0, .LBB14_2
+; SPE-NEXT: b .LBB14_1
+; SPE-NEXT: .LBB14_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB14_2
+; SPE-NEXT: .LBB14_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t10
%cmp = icmp eq i32 %a, 384
-; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -284,10 +1025,58 @@ if.end: ; preds = %if.then, %entry
}
define void @t11(i32 %a) nounwind {
+; ELF64-LABEL: t11:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: # kill: def $r3 killed $r3 killed $x3
+; ELF64-NEXT: cmpwi 3, 4096
+; ELF64-NEXT: bne 0, .LBB15_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB15_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t11:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: # kill: def $r3 killed $r3 killed $x3
+; VSX-NEXT: cmpwi 3, 4096
+; VSX-NEXT: bne 0, .LBB15_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB15_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t11:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: cmplwi 3, 4096
+; SPE-NEXT: bne 0, .LBB15_2
+; SPE-NEXT: b .LBB15_1
+; SPE-NEXT: .LBB15_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB15_2
+; SPE-NEXT: .LBB15_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t11
%cmp = icmp eq i32 %a, 4096
-; ELF64: cmpwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -299,10 +1088,60 @@ if.end: ; preds = %if.then, %entry
}
define void @t11a(i32 %a) nounwind {
+; ELF64-LABEL: t11a:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: mr 4, 3
+; ELF64-NEXT: li 3, 4096
+; ELF64-NEXT: cmpw 3, 4
+; ELF64-NEXT: bne 0, .LBB16_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB16_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t11a:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: mr 4, 3
+; VSX-NEXT: li 3, 4096
+; VSX-NEXT: cmpw 3, 4
+; VSX-NEXT: bne 0, .LBB16_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB16_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t11a:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: cmplwi 3, 4096
+; SPE-NEXT: bne 0, .LBB16_2
+; SPE-NEXT: b .LBB16_1
+; SPE-NEXT: .LBB16_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB16_2
+; SPE-NEXT: .LBB16_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t11a
%cmp = icmp eq i32 4096, %a
-; ELF64: cmpw
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -314,11 +1153,62 @@ if.end: ; preds = %if.then, %entry
}
define void @t12(i8 %a) nounwind {
+; ELF64-LABEL: t12:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: # kill: def $r3 killed $r3 killed $x3
+; ELF64-NEXT: clrlwi 3, 3, 24
+; ELF64-NEXT: cmplwi 3, 143
+; ELF64-NEXT: ble 0, .LBB17_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB17_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t12:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: # kill: def $r3 killed $r3 killed $x3
+; VSX-NEXT: clrlwi 3, 3, 24
+; VSX-NEXT: cmplwi 3, 143
+; VSX-NEXT: ble 0, .LBB17_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB17_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t12:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: mr 4, 3
+; SPE-NEXT: clrlwi 3, 4, 24
+; SPE-NEXT: cmplwi 3, 144
+; SPE-NEXT: blt 0, .LBB17_2
+; SPE-NEXT: b .LBB17_1
+; SPE-NEXT: .LBB17_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB17_2
+; SPE-NEXT: .LBB17_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t12
%cmp = icmp ugt i8 %a, -113
-; ELF64: clrlwi
-; ELF64: cmplwi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -330,12 +1220,42 @@ if.end: ; preds = %if.then, %entry
}
define void @t13() nounwind ssp {
+; ELF64-LABEL: t13:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: lis 3, -1
+; ELF64-NEXT: ori 3, 3, 65413
+; ELF64-NEXT: lis 4, -32768
+; ELF64-NEXT: cmpw 3, 4
+; ELF64-NEXT: bge 0, .LBB18_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: blr
+; ELF64-NEXT: .LBB18_2: # %if.end
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t13:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: lis 3, -1
+; VSX-NEXT: ori 3, 3, 65413
+; VSX-NEXT: lis 4, -32768
+; VSX-NEXT: cmpw 3, 4
+; VSX-NEXT: bge 0, .LBB18_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: blr
+; VSX-NEXT: .LBB18_2: # %if.end
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t13:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: li 3, 1
+; SPE-NEXT: cmplwi 3, 0
+; SPE-NEXT: bne 0, .LBB18_2
+; SPE-NEXT: b .LBB18_1
+; SPE-NEXT: .LBB18_1: # %if.then
+; SPE-NEXT: blr
+; SPE-NEXT: .LBB18_2: # %if.end
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t13
%cmp = icmp slt i32 -123, -2147483648
-; ELF64: li
-; ELF64: lis
-; ELF64: cmpw
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -346,10 +1266,57 @@ if.end: ; preds = %entry
}
define void @t14(i64 %a) nounwind {
+; ELF64-LABEL: t14:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: cmpdi 3, -1
+; ELF64-NEXT: bne 0, .LBB19_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB19_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t14:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: cmpdi 3, -1
+; VSX-NEXT: bne 0, .LBB19_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB19_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t14:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: and 3, 4, 3
+; SPE-NEXT: cmpwi 3, -1
+; SPE-NEXT: bne 0, .LBB19_2
+; SPE-NEXT: b .LBB19_1
+; SPE-NEXT: .LBB19_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB19_2
+; SPE-NEXT: .LBB19_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t14
%cmp = icmp eq i64 %a, -1
-; ELF64: cmpdi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -361,10 +1328,61 @@ if.end: ; preds = %if.then, %entry
}
define void @t15(i64 %a) nounwind {
+; ELF64-LABEL: t15:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: cmpdi 3, 1
+; ELF64-NEXT: bne 0, .LBB20_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB20_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t15:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: cmpdi 3, 1
+; VSX-NEXT: bne 0, .LBB20_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB20_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t15:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: stw 4, 12(1) # 4-byte Folded Spill
+; SPE-NEXT: mr 4, 3
+; SPE-NEXT: lwz 3, 12(1) # 4-byte Folded Reload
+; SPE-NEXT: xori 3, 3, 1
+; SPE-NEXT: or 3, 3, 4
+; SPE-NEXT: cmplwi 3, 0
+; SPE-NEXT: bne 0, .LBB20_2
+; SPE-NEXT: b .LBB20_1
+; SPE-NEXT: .LBB20_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB20_2
+; SPE-NEXT: .LBB20_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t15
%cmp = icmp eq i64 %a, 1
-; ELF64: cmpdi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -376,10 +1394,61 @@ if.end: ; preds = %if.then, %entry
}
define void @t16(i64 %a) nounwind {
+; ELF64-LABEL: t16:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: cmpdi 3, 384
+; ELF64-NEXT: bne 0, .LBB21_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB21_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t16:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: cmpdi 3, 384
+; VSX-NEXT: bne 0, .LBB21_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB21_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t16:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: stw 4, 12(1) # 4-byte Folded Spill
+; SPE-NEXT: mr 4, 3
+; SPE-NEXT: lwz 3, 12(1) # 4-byte Folded Reload
+; SPE-NEXT: xori 3, 3, 384
+; SPE-NEXT: or 3, 3, 4
+; SPE-NEXT: cmplwi 3, 0
+; SPE-NEXT: bne 0, .LBB21_2
+; SPE-NEXT: b .LBB21_1
+; SPE-NEXT: .LBB21_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB21_2
+; SPE-NEXT: .LBB21_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t16
%cmp = icmp eq i64 %a, 384
-; ELF64: cmpdi
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -391,11 +1460,66 @@ if.end: ; preds = %if.then, %entry
}
define void @t17(i64 %a) nounwind {
+; ELF64-LABEL: t17:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: lis 4, 0
+; ELF64-NEXT: ori 4, 4, 32768
+; ELF64-NEXT: cmpd 3, 4
+; ELF64-NEXT: bne 0, .LBB22_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB22_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t17:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: lis 4, 0
+; VSX-NEXT: ori 4, 4, 32768
+; VSX-NEXT: cmpd 3, 4
+; VSX-NEXT: bne 0, .LBB22_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB22_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t17:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: stw 4, 12(1) # 4-byte Folded Spill
+; SPE-NEXT: mr 4, 3
+; SPE-NEXT: lwz 3, 12(1) # 4-byte Folded Reload
+; SPE-NEXT: xori 3, 3, 32768
+; SPE-NEXT: or 3, 3, 4
+; SPE-NEXT: cmplwi 3, 0
+; SPE-NEXT: bne 0, .LBB22_2
+; SPE-NEXT: b .LBB22_1
+; SPE-NEXT: .LBB22_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB22_2
+; SPE-NEXT: .LBB22_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t17
%cmp = icmp eq i64 %a, 32768
; Extra operand so we don't match on cmpdi.
-; ELF64: cmpd {{[0-9]+}}
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
@@ -407,11 +1531,68 @@ if.end: ; preds = %if.then, %entry
}
define void @t17a(i64 %a) nounwind {
+; ELF64-LABEL: t17a:
+; ELF64: # %bb.0: # %entry
+; ELF64-NEXT: mflr 0
+; ELF64-NEXT: stdu 1, -112(1)
+; ELF64-NEXT: std 0, 128(1)
+; ELF64-NEXT: mr 4, 3
+; ELF64-NEXT: lis 3, 0
+; ELF64-NEXT: ori 3, 3, 32768
+; ELF64-NEXT: cmpd 3, 4
+; ELF64-NEXT: bne 0, .LBB23_2
+; ELF64-NEXT: # %bb.1: # %if.then
+; ELF64-NEXT: bl foo
+; ELF64-NEXT: nop
+; ELF64-NEXT: .LBB23_2: # %if.end
+; ELF64-NEXT: addi 1, 1, 112
+; ELF64-NEXT: ld 0, 16(1)
+; ELF64-NEXT: mtlr 0
+; ELF64-NEXT: blr
+;
+; VSX-LABEL: t17a:
+; VSX: # %bb.0: # %entry
+; VSX-NEXT: mflr 0
+; VSX-NEXT: stdu 1, -96(1)
+; VSX-NEXT: std 0, 112(1)
+; VSX-NEXT: mr 4, 3
+; VSX-NEXT: lis 3, 0
+; VSX-NEXT: ori 3, 3, 32768
+; VSX-NEXT: cmpd 3, 4
+; VSX-NEXT: bne 0, .LBB23_2
+; VSX-NEXT: # %bb.1: # %if.then
+; VSX-NEXT: bl foo
+; VSX-NEXT: nop
+; VSX-NEXT: .LBB23_2: # %if.end
+; VSX-NEXT: addi 1, 1, 96
+; VSX-NEXT: ld 0, 16(1)
+; VSX-NEXT: mtlr 0
+; VSX-NEXT: blr
+;
+; SPE-LABEL: t17a:
+; SPE: # %bb.0: # %entry
+; SPE-NEXT: mflr 0
+; SPE-NEXT: stwu 1, -16(1)
+; SPE-NEXT: stw 0, 20(1)
+; SPE-NEXT: stw 4, 12(1) # 4-byte Folded Spill
+; SPE-NEXT: mr 4, 3
+; SPE-NEXT: lwz 3, 12(1) # 4-byte Folded Reload
+; SPE-NEXT: xori 3, 3, 32768
+; SPE-NEXT: or 3, 3, 4
+; SPE-NEXT: cmplwi 3, 0
+; SPE-NEXT: bne 0, .LBB23_2
+; SPE-NEXT: b .LBB23_1
+; SPE-NEXT: .LBB23_1: # %if.then
+; SPE-NEXT: bl foo
+; SPE-NEXT: b .LBB23_2
+; SPE-NEXT: .LBB23_2: # %if.end
+; SPE-NEXT: lwz 0, 20(1)
+; SPE-NEXT: addi 1, 1, 16
+; SPE-NEXT: mtlr 0
+; SPE-NEXT: blr
entry:
-; ELF64-LABEL: @t17a
%cmp = icmp eq i64 32768, %a
; Extra operand so we don't match on cmpdi.
-; ELF64: cmpd {{[0-9]+}}
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
>From 2fe84aeffc440c25b22996d77d8fb584c353c51f Mon Sep 17 00:00:00 2001
From: mike-goutokuji <gfunni234 at gmail.com>
Date: Sun, 7 Jun 2026 12:22:19 -0400
Subject: [PATCH 3/3] Apply suggestion from @lei137
Co-authored-by: Lei Huang <lei at ca.ibm.com>
---
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 64be294e75053..747a3aba2f105 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -12793,6 +12793,7 @@ SDValue PPCTargetLowering::LowerABDU(SDValue Op, SelectionDAG &DAG) const {
}
// Calculate LHS - RHS and capture the carry (CA)
+ // Create value list for result and carry flag (i32)
SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);
SDValue Res = DAG.getNode(Opcode, DL, VTs, LHS, RHS);
More information about the llvm-commits
mailing list