[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for cvt_scale intrinsics (PR #202075)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 6 12:18:03 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Petar Avramovic (petar-avramovic)
<details>
<summary>Changes</summary>
---
Patch is 138.08 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/202075.diff
10 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp (+40-1)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+216)
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h (+26)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll (+425-3)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.gfx950.ll (+470-89)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk.ll (+161-9)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk16.gfx1250.ll (+133-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.pk8.ll (+163-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk.gfx1250.ll (+163-1)
- (modified) llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scalef32.sr.pk16.ll (+133-1)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
index db5573cb08cf8..3b29b52af02fb 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeHelper.cpp
@@ -1516,9 +1516,16 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
case UniInVgprV2S32:
return LLT::fixed_vector(2, 32);
case VgprV3S32:
+ case UniInVgprV3S32:
return LLT::fixed_vector(3, 32);
case VgprV4S16:
return LLT::fixed_vector(4, 16);
+ case VgprV8S16:
+ case UniInVgprV8S16:
+ return LLT::fixed_vector(8, 16);
+ case VgprV16S16:
+ case UniInVgprV16S16:
+ return LLT::fixed_vector(16, 16);
case SgprV4S32:
case SgprV4S32_WF:
case SgprV4S32_ReadFirstLane:
@@ -1526,15 +1533,22 @@ LLT RegBankLegalizeHelper::getTyFromID(RegBankLLTMappingApplyID ID) {
case UniInVgprV4S32:
return LLT::fixed_vector(4, 32);
case VgprV8S32:
+ case UniInVgprV8S32:
return LLT::fixed_vector(8, 32);
case VgprV2S64:
case UniInVgprV2S64:
return LLT::fixed_vector(2, 64);
case VgprV6S32:
+ case UniInVgprV6S32:
return LLT::fixed_vector(6, 32);
+ case VgprV16S32:
+ case UniInVgprV16S32:
+ return LLT::fixed_vector(16, 32);
case VgprV32S16:
+ case UniInVgprV32S16:
return LLT::fixed_vector(32, 16);
case VgprV32S32:
+ case UniInVgprV32S32:
return LLT::fixed_vector(32, 32);
default:
return LLT();
@@ -1663,8 +1677,16 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case UniInVgprS64:
case UniInVgprV2S16:
case UniInVgprV2S32:
+ case UniInVgprV3S32:
case UniInVgprV4S32:
case UniInVgprV2S64:
+ case UniInVgprV6S32:
+ case UniInVgprV8S16:
+ case UniInVgprV8S32:
+ case UniInVgprV16S16:
+ case UniInVgprV16S32:
+ case UniInVgprV32S16:
+ case UniInVgprV32S32:
case UniInVgprB32:
case UniInVgprB64:
case UniInVgprB96:
@@ -1698,9 +1720,12 @@ RegBankLegalizeHelper::getRegBankFromID(RegBankLLTMappingApplyID ID) {
case VgprV2S64:
case VgprV3S32:
case VgprV4S16:
+ case VgprV8S16:
+ case VgprV16S16:
case VgprV4S32:
case VgprV6S32:
case VgprV8S32:
+ case VgprV16S32:
case VgprV32S16:
case VgprB32:
case VgprB64:
@@ -1765,9 +1790,12 @@ bool RegBankLegalizeHelper::applyMappingDst(
case VgprV2S64:
case VgprV3S32:
case VgprV4S16:
+ case VgprV8S16:
+ case VgprV16S16:
case VgprV4S32:
case VgprV6S32:
case VgprV8S32:
+ case VgprV16S32:
case VgprV32S16: {
assert(Ty == getTyFromID(MethodIDs[OpIdx]));
assert(RB == getRegBankFromID(MethodIDs[OpIdx]));
@@ -1841,8 +1869,16 @@ bool RegBankLegalizeHelper::applyMappingDst(
case UniInVgprS64:
case UniInVgprV2S16:
case UniInVgprV2S32:
+ case UniInVgprV3S32:
case UniInVgprV4S32:
- case UniInVgprV2S64: {
+ case UniInVgprV2S64:
+ case UniInVgprV6S32:
+ case UniInVgprV8S16:
+ case UniInVgprV8S32:
+ case UniInVgprV16S16:
+ case UniInVgprV16S32:
+ case UniInVgprV32S16:
+ case UniInVgprV32S32: {
assert(Ty == getTyFromID(MethodIDs[OpIdx]));
assert(RB == SgprRB);
Register NewVgprDst = MRI.createVirtualRegister({VgprRB, Ty});
@@ -1973,9 +2009,12 @@ bool RegBankLegalizeHelper::applyMappingSrc(
case VgprV2S64:
case VgprV3S32:
case VgprV4S16:
+ case VgprV8S16:
+ case VgprV16S16:
case VgprV4S32:
case VgprV6S32:
case VgprV8S32:
+ case VgprV16S32:
case VgprV32S16:
case VgprV32S32: {
assert(Ty == getTyFromID(MethodIDs[i]));
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index e5bab2bbdfa25..ac097c45ce902 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -136,6 +136,30 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
case UniV2S32:
return MRI.getType(Reg) == LLT::fixed_vector(2, 32) &&
MUI.isUniformAtDef(Reg);
+ case UniV3S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(3, 32) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV6S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(6, 32) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV8S16:
+ return MRI.getType(Reg) == LLT::fixed_vector(8, 16) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV8S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(8, 32) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV16S16:
+ return MRI.getType(Reg) == LLT::fixed_vector(16, 16) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV16S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(16, 32) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV32S16:
+ return MRI.getType(Reg) == LLT::fixed_vector(32, 16) &&
+ MUI.isUniformAtDef(Reg);
+ case UniV32S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(32, 32) &&
+ MUI.isUniformAtDef(Reg);
case UniB32:
return MRI.getType(Reg).getSizeInBits() == 32 && MUI.isUniformAtDef(Reg);
case UniB64:
@@ -201,9 +225,29 @@ bool matchUniformityAndLLT(Register Reg, UniformityLLTOpPredicateID UniID,
case DivV4S16:
return MRI.getType(Reg) == LLT::fixed_vector(4, 16) &&
MUI.isDivergentAtDef(Reg);
+ case DivV8S16:
+ return MRI.getType(Reg) == LLT::fixed_vector(8, 16) &&
+ MUI.isDivergentAtDef(Reg);
+ case DivV8S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(8, 32) &&
+ MUI.isDivergentAtDef(Reg);
+ case DivV16S16:
+ return MRI.getType(Reg) == LLT::fixed_vector(16, 16) &&
+ MUI.isDivergentAtDef(Reg);
+ case DivV16S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(16, 32) &&
+ MUI.isDivergentAtDef(Reg);
case DivV6S32:
return MRI.getType(Reg) == LLT::fixed_vector(6, 32) &&
MUI.isDivergentAtDef(Reg);
+ case DivV32S16:
+ return MRI.getType(Reg) == LLT::fixed_vector(32, 16) &&
+ MUI.isDivergentAtDef(Reg);
+ case DivV32S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(32, 32) &&
+ MUI.isDivergentAtDef(Reg);
+ case V32S32:
+ return MRI.getType(Reg) == LLT::fixed_vector(32, 32);
case DivB32:
return MRI.getType(Reg).getSizeInBits() == 32 && MUI.isDivergentAtDef(Reg);
case DivB64:
@@ -1863,6 +1907,178 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, VgprV2S32, Vgpr32, Vgpr32}})
.Div(S32, {{Vgpr32}, {IntrId, Vgpr32, VgprV2S32, Vgpr32, Vgpr32}});
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_2xpk16_fp6_f32, amdgcn_cvt_scalef32_2xpk16_bf6_f32})
+ .Any(
+ {{DivV6S32}, {{VgprV6S32}, {IntrId, VgprV16S32, VgprV16S32, Vgpr32}}})
+ .Any({{UniV6S32},
+ {{UniInVgprV6S32}, {IntrId, VgprV16S32, VgprV16S32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_f16_fp8, amdgcn_cvt_scalef32_f16_bf8},
+ Standard)
+ .Div(V2S16, {{VgprV2S16}, {IntrId, VgprV2S16, Vgpr32, Vgpr32}})
+ .Uni(V2S16, {{UniInVgprV2S16}, {IntrId, VgprV2S16, Vgpr32, Vgpr32}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_f32_fp8, amdgcn_cvt_scalef32_f32_bf8},
+ Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32}})
+ .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk16_bf6_f16, amdgcn_cvt_scalef32_pk16_fp6_f16},
+ Standard)
+ .Any({{DivV3S32}, {{VgprV3S32}, {IntrId, VgprV16S16, Vgpr32}}})
+ .Any({{UniV3S32}, {{UniInVgprV3S32}, {IntrId, VgprV16S16, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk16_bf6_f32, amdgcn_cvt_scalef32_pk16_fp6_f32},
+ Standard)
+ .Any({{DivV3S32}, {{VgprV3S32}, {IntrId, VgprV16S32, Vgpr32}}})
+ .Any({{UniV3S32}, {{UniInVgprV3S32}, {IntrId, VgprV16S32, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk8_bf8_f16, amdgcn_cvt_scalef32_pk8_fp8_f16},
+ Standard)
+ .Any({{DivV2S32}, {{VgprV2S32}, {IntrId, VgprV8S16, Vgpr32}}})
+ .Any({{UniV2S32}, {{UniInVgprV2S32}, {IntrId, VgprV8S16, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk8_bf8_f32, amdgcn_cvt_scalef32_pk8_fp8_f32},
+ Standard)
+ .Any({{DivV2S32}, {{VgprV2S32}, {IntrId, VgprV8S32, Vgpr32}}})
+ .Any({{UniV2S32}, {{UniInVgprV2S32}, {IntrId, VgprV8S32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_pk8_fp4_f16}, Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, VgprV8S16, Vgpr32}})
+ .Uni(S32, {{UniInVgprS32}, {IntrId, VgprV8S16, Vgpr32}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_pk8_fp4_f32}, Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, VgprV8S32, Vgpr32}})
+ .Uni(S32, {{UniInVgprS32}, {IntrId, VgprV8S32, Vgpr32}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_sr_pk16_bf6_f16,
+ amdgcn_cvt_scalef32_sr_pk16_fp6_f16},
+ Standard)
+ .Any({{DivV3S32}, {{VgprV3S32}, {IntrId, VgprV16S16, Vgpr32, Vgpr32}}})
+ .Any({{UniV3S32},
+ {{UniInVgprV3S32}, {IntrId, VgprV16S16, Vgpr32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_sr_pk16_bf6_f32,
+ amdgcn_cvt_scalef32_sr_pk16_fp6_f32},
+ Standard)
+ .Any({{DivV3S32}, {{VgprV3S32}, {IntrId, VgprV16S32, Vgpr32, Vgpr32}}})
+ .Any({{UniV3S32},
+ {{UniInVgprV3S32}, {IntrId, VgprV16S32, Vgpr32, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_sr_pk8_bf8_f16, amdgcn_cvt_scalef32_sr_pk8_fp8_f16},
+ Standard)
+ .Any({{DivV2S32}, {{VgprV2S32}, {IntrId, VgprV8S16, Vgpr32, Vgpr32}}})
+ .Any({{UniV2S32},
+ {{UniInVgprV2S32}, {IntrId, VgprV8S16, Vgpr32, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_sr_pk8_bf8_f32, amdgcn_cvt_scalef32_sr_pk8_fp8_f32},
+ Standard)
+ .Any({{DivV2S32}, {{VgprV2S32}, {IntrId, VgprV8S32, Vgpr32, Vgpr32}}})
+ .Any({{UniV2S32},
+ {{UniInVgprV2S32}, {IntrId, VgprV8S32, Vgpr32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_sr_pk8_fp4_f16}, Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, VgprV8S16, Vgpr32, Vgpr32}})
+ .Uni(S32, {{UniInVgprS32}, {IntrId, VgprV8S16, Vgpr32, Vgpr32}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_sr_pk8_fp4_f32}, Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, VgprV8S32, Vgpr32, Vgpr32}})
+ .Uni(S32, {{UniInVgprS32}, {IntrId, VgprV8S32, Vgpr32, Vgpr32}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scale_pk16_f16_bf6, amdgcn_cvt_scale_pk16_f16_fp6}, Standard)
+ .Any({{DivV16S16}, {{VgprV16S16}, {IntrId, VgprV3S32, Vgpr32}}})
+ .Any({{UniV16S16}, {{UniInVgprV16S16}, {IntrId, VgprV3S32, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scale_pk16_f32_bf6, amdgcn_cvt_scale_pk16_f32_fp6}, Standard)
+ .Any({{DivV16S32}, {{VgprV16S32}, {IntrId, VgprV3S32, Vgpr32}}})
+ .Any({{UniV16S32}, {{UniInVgprV16S32}, {IntrId, VgprV3S32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scale_pk8_f16_bf8, amdgcn_cvt_scale_pk8_f16_fp8},
+ Standard)
+ .Any({{DivV8S16}, {{VgprV8S16}, {IntrId, VgprV2S32, Vgpr32}}})
+ .Any({{UniV8S16}, {{UniInVgprV8S16}, {IntrId, VgprV2S32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scale_pk8_f16_fp4}, Standard)
+ .Any({{DivV8S16}, {{VgprV8S16}, {IntrId, Vgpr32, Vgpr32}}})
+ .Any({{UniV8S16}, {{UniInVgprV8S16}, {IntrId, Vgpr32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scale_pk8_f32_bf8, amdgcn_cvt_scale_pk8_f32_fp8},
+ Standard)
+ .Any({{DivV8S32}, {{VgprV8S32}, {IntrId, VgprV2S32, Vgpr32}}})
+ .Any({{UniV8S32}, {{UniInVgprV8S32}, {IntrId, VgprV2S32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scale_pk8_f32_fp4}, Standard)
+ .Any({{DivV8S32}, {{VgprV8S32}, {IntrId, Vgpr32, Vgpr32}}})
+ .Any({{UniV8S32}, {{UniInVgprV8S32}, {IntrId, Vgpr32, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk32_bf6_f16, amdgcn_cvt_scalef32_pk32_fp6_f16},
+ Standard)
+ .Any({{DivV6S32}, {{VgprV6S32}, {IntrId, VgprV32S16, Vgpr32}}})
+ .Any({{UniV6S32}, {{UniInVgprV6S32}, {IntrId, VgprV32S16, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk_fp8_f32, amdgcn_cvt_scalef32_pk_bf8_f32},
+ Standard)
+ .Div(V2S16,
+ {{VgprV2S16}, {IntrId, VgprV2S16, Vgpr32, Vgpr32, Vgpr32, Imm}})
+ .Uni(V2S16, {{UniInVgprV2S16},
+ {IntrId, VgprV2S16, Vgpr32, Vgpr32, Vgpr32, Imm}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk_f32_fp8, amdgcn_cvt_scalef32_pk_f32_bf8},
+ Standard)
+ .Any({{DivV2S32}, {{VgprV2S32}, {IntrId, Vgpr32, Vgpr32, Imm}}})
+ .Any({{UniV2S32}, {{UniInVgprV2S32}, {IntrId, Vgpr32, Vgpr32, Imm}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk_fp8_f16, amdgcn_cvt_scalef32_pk_bf8_f16},
+ Standard)
+ .Div(V2S16, {{VgprV2S16}, {IntrId, VgprV2S16, VgprV2S16, Vgpr32, Imm}})
+ .Uni(V2S16,
+ {{UniInVgprV2S16}, {IntrId, VgprV2S16, VgprV2S16, Vgpr32, Imm}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_pk_f32_fp4}, Standard)
+ .Any({{DivV2S32}, {{VgprV2S32}, {IntrId, Vgpr32, Vgpr32, Imm}}})
+ .Any({{UniV2S32}, {{UniInVgprV2S32}, {IntrId, Vgpr32, Vgpr32, Imm}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_pk_fp4_f32}, Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Imm}})
+ .Uni(S32,
+ {{UniInVgprS32}, {IntrId, Vgpr32, Vgpr32, Vgpr32, Vgpr32, Imm}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_pk_f16_fp4,
+ amdgcn_cvt_scalef32_pk_f16_fp8,
+ amdgcn_cvt_scalef32_pk_f16_bf8},
+ Standard)
+ .Div(V2S16, {{VgprV2S16}, {IntrId, Vgpr32, Vgpr32, Imm}})
+ .Uni(V2S16, {{UniInVgprV2S16}, {IntrId, Vgpr32, Vgpr32, Imm}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk32_f32_fp6, amdgcn_cvt_scalef32_pk32_f32_bf6},
+ Standard)
+ .Any({{DivV32S32}, {{VgprV32S32}, {IntrId, VgprV6S32, Vgpr32}}})
+ .Any({{UniV32S32}, {{UniInVgprV32S32}, {IntrId, VgprV6S32, Vgpr32}}});
+
+ addRulesForIOpcs(
+ {amdgcn_cvt_scalef32_pk32_f16_fp6, amdgcn_cvt_scalef32_pk32_f16_bf6},
+ Standard)
+ .Any({{DivV32S16}, {{VgprV32S16}, {IntrId, VgprV6S32, Vgpr32}}})
+ .Any({{UniV32S16}, {{UniInVgprV32S16}, {IntrId, VgprV6S32, Vgpr32}}});
+
+ addRulesForIOpcs({amdgcn_cvt_scalef32_pk_fp4_f16}, Standard)
+ .Div(S32, {{Vgpr32}, {IntrId, Vgpr32, VgprV2S16, Vgpr32, Imm}})
+ .Uni(S32, {{UniInVgprS32}, {IntrId, Vgpr32, VgprV2S16, Vgpr32, Imm}});
+
addRulesForIOpcs({amdgcn_global_load_tr_b64})
.Any({{DivB64, _, UniP1}, {{VgprB64}, {IntrId, SgprP1}}})
.Any({{DivB64, _, DivP1}, {{VgprB64}, {IntrId, VgprP1}}})
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
index d7684d16676a0..d9b1dd6289376 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.h
@@ -100,17 +100,32 @@ enum UniformityLLTOpPredicateID {
V2S64,
V3S32,
V4S32,
+ V32S32,
UniV2S16,
UniV2S32,
UniV2S64,
+ UniV3S32,
+ UniV6S32,
+ UniV8S16,
+ UniV8S32,
+ UniV16S16,
+ UniV16S32,
+ UniV32S16,
+ UniV32S32,
DivV2S16,
DivV2S32,
DivV2S64,
DivV3S32,
DivV4S16,
+ DivV8S16,
+ DivV8S32,
+ DivV16S16,
+ DivV16S32,
DivV6S32,
+ DivV32S16,
+ DivV32S32,
// B types
B32,
@@ -208,6 +223,8 @@ enum RegBankLLTMappingApplyID {
VgprB512,
VgprBRC,
VgprV4S16,
+ VgprV8S16,
+ VgprV16S16,
VgprV4S32,
VgprV8S32,
VgprV2S64,
@@ -219,8 +236,16 @@ enum RegBankLLTMappingApplyID {
UniInVgprS64,
UniInVgprV2S16,
UniInVgprV2S32,
+ UniInVgprV3S32,
UniInVgprV4S32,
UniInVgprV2S64,
+ UniInVgprV6S32,
+ UniInVgprV8S16,
+ UniInVgprV8S32,
+ UniInVgprV16S16,
+ UniInVgprV16S32,
+ UniInVgprV32S16,
+ UniInVgprV32S32,
UniInVgprB32,
UniInVgprB64,
UniInVgprB96,
@@ -265,6 +290,7 @@ enum RegBankLLTMappingApplyID {
Vgpr32ZExt,
VgprV6S32,
+ VgprV16S32,
VgprV32S16,
VgprV32S32,
};
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
index 651917bf240ea..8193fec395eb2 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.scale.pk.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -global-isel-abort=2 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s
declare <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp8(<2 x i32> %src, i32 %scale, i32 %scale_sel)
declare <8 x bfloat> @llvm.amdgcn.cvt.scale.pk8.bf16.fp8(<2 x i32> %src, i32 %scale, i32 %scale_sel)
@@ -39,6 +39,29 @@ define amdgpu_ps void @test_cvt_scale_pk8_f16_fp8_vv(<2 x i32> %src, i32 %scale,
ret void
}
+define amdgpu_ps void @test_cvt_scale_pk8_f16_fp8_ss(<2 x i32> inreg %src, i32 inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f16_fp8_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f16_fp8 v[2:5], v[6:7], s2 scale_sel:1
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f16_fp8_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f16_fp8 v[2:5], v[6:7], s2 scale_sel:1
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.fp8(<2 x i32> %src, i32 %scale, i32 1)
+ store <8 x half> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_cvt_scale_pk8_f16_bf8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f16_bf8_vv:
; GFX1250-SDAG: ; %bb.0:
@@ -60,6 +83,29 @@ define amdgpu_ps void @test_cvt_scale_pk8_f16_bf8_vv(<2 x i32> %src, i32 %scale,
ret void
}
+define amdgpu_ps void @test_cvt_scale_pk8_f16_bf8_ss(<2 x i32> inreg %src, i32 inreg %scale, ptr addrspace(1) %out) {
+; GFX1250-SDAG-LABEL: test_cvt_scale_pk8_f16_bf8_ss:
+; GFX1250-SDAG: ; %bb.0:
+; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-SDAG-NEXT: v_dual_mov_b32 v6, s0 :: v_dual_mov_b32 v7, s1
+; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-SDAG-NEXT: v_cvt_scale_pk8_f16_bf8 v[2:5], v[6:7], s2
+; GFX1250-SDAG-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-SDAG-NEXT: s_endpgm
+;
+; GFX1250-GISEL-LABEL: test_cvt_scale_pk8_f16_bf8_ss:
+; GFX1250-GISEL: ; %bb.0:
+; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[6:7], s[0:1]
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_cvt_scale_pk8_f16_bf8 v[2:5], v[6:7], s2
+; GFX1250-GISEL-NEXT: global_store_b128 v[0:1], v[2:5], off
+; GFX1250-GISEL-NEXT: s_endpgm
+ %cvt = tail call <8 x half> @llvm.amdgcn.cvt.scale.pk8.f16.bf8(<2 x i32> %src, i32 %scale, i32 0)
+ store <8 x half> %cvt, ptr addrspace(1) %out, align 8
+ ret void
+}
+
define amdgpu_ps void @test_cvt_scale_pk8_bf16_fp8_vv(<2 x i32> %src, i32 %scale, ptr addrspace(1) %out) {
; GFX1250-LABEL: test_cvt_scale_pk8_bf16_fp8_vv:
; GFX1250: ; %bb.0:
@@ -98,6 +144,20 @@ define amdgpu_ps void @test_cvt_scale_pk8_f16_fp4_vv(i32 %src, i32 %scale, ptr a
ret void
}
+define...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/202075
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