[llvm] AMDGPU/GlobalISel: RegBankLegalize rules for v_pk_add/mul_f32 (PR #202074)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 6 12:16:27 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Petar Avramovic (petar-avramovic)
<details>
<summary>Changes</summary>
---
Patch is 39.78 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/202074.diff
2 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp (+3-1)
- (modified) llvm/test/CodeGen/AMDGPU/packed-fp32.ll (+449-132)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
index e5bab2bbdfa25..926a0941a83a9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp
@@ -1350,7 +1350,9 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
.Uni(V2S16, {{UniInVgprV2S16}, {VgprV2S16, VgprV2S16}}, !hasSALUFloat)
.Uni(V2S16, {{SgprV2S16}, {SgprV2S16, SgprV2S16}, ScalarizeToS16},
hasSALUFloat)
- .Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}});
+ .Div(V2S16, {{VgprV2S16}, {VgprV2S16, VgprV2S16}})
+ .Any({{UniV2S32}, {{UniInVgprV2S32}, {VgprV2S32, VgprV2S32}}})
+ .Any({{DivV2S32}, {{VgprV2S32}, {VgprV2S32, VgprV2S32}}});
addRulesForGOpcs({G_FSUB, G_STRICT_FSUB}, Standard)
.Div(S16, {{Vgpr16}, {Vgpr16, Vgpr16}})
diff --git a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
index 27ea6f344796f..5dd8e45a5d895 100644
--- a/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
+++ b/llvm/test/CodeGen/AMDGPU/packed-fp32.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GFX900 %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -enable-var-scope -check-prefixes=PACKED,PACKED-SDAG,GFX90A-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -enable-var-scope -check-prefixes=PACKED,PACKED-GISEL,GFX90A-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx90a < %s | FileCheck -enable-var-scope -check-prefixes=PACKED,PACKED-GISEL,GFX90A-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -enable-var-scope -check-prefixes=PACKED,PACKED-SDAG,GFX942-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -enable-var-scope -check-prefixes=PACKED,PACKED-GISEL,GFX942-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck -enable-var-scope -check-prefixes=PACKED,PACKED-GISEL,GFX942-GISEL %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,GFX1250-SDAG %s
-; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,GFX1250-GISEL %s
+; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -enable-var-scope -check-prefixes=GFX1250,GFX1250-GISEL %s
define amdgpu_kernel void @fadd_v2_vv(ptr addrspace(1) %a) {
; GFX900-LABEL: fadd_v2_vv:
@@ -1007,20 +1007,37 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo(ptr addrspace(1) %a, float %x) {
; PACKED-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; PACKED-SDAG-NEXT: s_endpgm
;
-; PACKED-GISEL-LABEL: fadd_v2_v_fneg_lo:
-; PACKED-GISEL: ; %bb.0:
-; PACKED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; PACKED-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; PACKED-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; PACKED-GISEL-NEXT: v_lshlrev_b32_e32 v4, 3, v0
-; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; PACKED-GISEL-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]
-; PACKED-GISEL-NEXT: v_mov_b32_e32 v3, s2
-; PACKED-GISEL-NEXT: v_max_f32_e64 v2, -s2, -s2
-; PACKED-GISEL-NEXT: s_waitcnt vmcnt(0)
-; PACKED-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3]
-; PACKED-GISEL-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
-; PACKED-GISEL-NEXT: s_endpgm
+; GFX90A-GISEL-LABEL: fadd_v2_v_fneg_lo:
+; GFX90A-GISEL: ; %bb.0:
+; GFX90A-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-GISEL-NEXT: s_load_dword s3, s[4:5], 0x2c
+; GFX90A-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX90A-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
+; GFX90A-GISEL-NEXT: v_max_f32_e64 v3, -s3, -s3
+; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s2, v3
+; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX90A-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3]
+; GFX90A-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX90A-GISEL-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: fadd_v2_v_fneg_lo:
+; GFX942-GISEL: ; %bb.0:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX942-GISEL-NEXT: s_load_dword s3, s[4:5], 0x2c
+; GFX942-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
+; GFX942-GISEL-NEXT: v_max_f32_e64 v3, -s3, -s3
+; GFX942-GISEL-NEXT: s_nop 0
+; GFX942-GISEL-NEXT: v_readfirstlane_b32 s2, v3
+; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX942-GISEL-NEXT: s_nop 0
+; GFX942-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3]
+; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX942-GISEL-NEXT: s_endpgm
;
; GFX1250-SDAG-LABEL: fadd_v2_v_fneg_lo:
; GFX1250-SDAG: ; %bb.0:
@@ -1041,8 +1058,11 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo(ptr addrspace(1) %a, float %x) {
; GFX1250-GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v0
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT: global_load_b64 v[0:1], v4, s[0:1] scale_offset
-; GFX1250-GISEL-NEXT: v_mov_b32_e32 v3, s2
; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v2, -s2, -s2
+; GFX1250-GISEL-NEXT: s_mov_b32 s5, s2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s4, v2
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3]
@@ -1086,20 +1106,37 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi(ptr addrspace(1) %a, float %x) {
; PACKED-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; PACKED-SDAG-NEXT: s_endpgm
;
-; PACKED-GISEL-LABEL: fadd_v2_v_fneg_hi:
-; PACKED-GISEL: ; %bb.0:
-; PACKED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; PACKED-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
-; PACKED-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; PACKED-GISEL-NEXT: v_lshlrev_b32_e32 v4, 3, v0
-; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; PACKED-GISEL-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]
-; PACKED-GISEL-NEXT: v_mov_b32_e32 v2, s2
-; PACKED-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2
-; PACKED-GISEL-NEXT: s_waitcnt vmcnt(0)
-; PACKED-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3]
-; PACKED-GISEL-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
-; PACKED-GISEL-NEXT: s_endpgm
+; GFX90A-GISEL-LABEL: fadd_v2_v_fneg_hi:
+; GFX90A-GISEL: ; %bb.0:
+; GFX90A-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX90A-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX90A-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
+; GFX90A-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2
+; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX90A-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3]
+; GFX90A-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX90A-GISEL-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: fadd_v2_v_fneg_hi:
+; GFX942-GISEL: ; %bb.0:
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX942-GISEL-NEXT: s_load_dword s2, s[4:5], 0x2c
+; GFX942-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
+; GFX942-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2
+; GFX942-GISEL-NEXT: s_nop 0
+; GFX942-GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX942-GISEL-NEXT: s_nop 0
+; GFX942-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3]
+; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX942-GISEL-NEXT: s_endpgm
;
; GFX1250-SDAG-LABEL: fadd_v2_v_fneg_hi:
; GFX1250-SDAG: ; %bb.0:
@@ -1120,8 +1157,10 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi(ptr addrspace(1) %a, float %x) {
; GFX1250-GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v0
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT: global_load_b64 v[0:1], v4, s[0:1] scale_offset
-; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s2
-; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v3, -s2, -s2
+; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v2, -s2, -s2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3]
@@ -1163,19 +1202,35 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo2(ptr addrspace(1) %a, float %x, flo
; PACKED-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; PACKED-SDAG-NEXT: s_endpgm
;
-; PACKED-GISEL-LABEL: fadd_v2_v_fneg_lo2:
-; PACKED-GISEL: ; %bb.0:
-; PACKED-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; PACKED-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; PACKED-GISEL-NEXT: v_lshlrev_b32_e32 v4, 3, v0
-; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; PACKED-GISEL-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]
-; PACKED-GISEL-NEXT: v_max_f32_e64 v2, -s2, -s2
-; PACKED-GISEL-NEXT: v_mov_b32_e32 v3, s3
-; PACKED-GISEL-NEXT: s_waitcnt vmcnt(0)
-; PACKED-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3]
-; PACKED-GISEL-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
-; PACKED-GISEL-NEXT: s_endpgm
+; GFX90A-GISEL-LABEL: fadd_v2_v_fneg_lo2:
+; GFX90A-GISEL: ; %bb.0:
+; GFX90A-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX90A-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX90A-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
+; GFX90A-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2
+; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s2, v3
+; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX90A-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3]
+; GFX90A-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX90A-GISEL-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: fadd_v2_v_fneg_lo2:
+; GFX942-GISEL: ; %bb.0:
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX942-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
+; GFX942-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2
+; GFX942-GISEL-NEXT: s_nop 0
+; GFX942-GISEL-NEXT: v_readfirstlane_b32 s2, v3
+; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX942-GISEL-NEXT: s_nop 0
+; GFX942-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3]
+; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX942-GISEL-NEXT: s_endpgm
;
; GFX1250-SDAG-LABEL: fadd_v2_v_fneg_lo2:
; GFX1250-SDAG: ; %bb.0:
@@ -1199,7 +1254,9 @@ define amdgpu_kernel void @fadd_v2_v_fneg_lo2(ptr addrspace(1) %a, float %x, flo
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT: global_load_b64 v[0:1], v4, s[0:1] scale_offset
; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v2, -s2, -s2
-; GFX1250-GISEL-NEXT: v_mov_b32_e32 v3, s3
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3]
@@ -1241,19 +1298,36 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi2(ptr addrspace(1) %a, float %x, flo
; PACKED-SDAG-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; PACKED-SDAG-NEXT: s_endpgm
;
-; PACKED-GISEL-LABEL: fadd_v2_v_fneg_hi2:
-; PACKED-GISEL: ; %bb.0:
-; PACKED-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
-; PACKED-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
-; PACKED-GISEL-NEXT: v_lshlrev_b32_e32 v4, 3, v0
-; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; PACKED-GISEL-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1]
-; PACKED-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2
-; PACKED-GISEL-NEXT: v_mov_b32_e32 v2, s3
-; PACKED-GISEL-NEXT: s_waitcnt vmcnt(0)
-; PACKED-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3]
-; PACKED-GISEL-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
-; PACKED-GISEL-NEXT: s_endpgm
+; GFX90A-GISEL-LABEL: fadd_v2_v_fneg_hi2:
+; GFX90A-GISEL: ; %bb.0:
+; GFX90A-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX90A-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX90A-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
+; GFX90A-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2
+; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX90A-GISEL-NEXT: s_mov_b32 s4, s3
+; GFX90A-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX90A-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[4:5]
+; GFX90A-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX90A-GISEL-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: fadd_v2_v_fneg_hi2:
+; GFX942-GISEL: ; %bb.0:
+; GFX942-GISEL-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
+; GFX942-GISEL-NEXT: v_and_b32_e32 v0, 0x3ff, v0
+; GFX942-GISEL-NEXT: v_lshlrev_b32_e32 v2, 3, v0
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: global_load_dwordx2 v[0:1], v2, s[0:1]
+; GFX942-GISEL-NEXT: v_max_f32_e64 v3, -s2, -s2
+; GFX942-GISEL-NEXT: s_mov_b32 s4, s3
+; GFX942-GISEL-NEXT: v_readfirstlane_b32 s5, v3
+; GFX942-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX942-GISEL-NEXT: s_nop 0
+; GFX942-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[4:5]
+; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX942-GISEL-NEXT: s_endpgm
;
; GFX1250-SDAG-LABEL: fadd_v2_v_fneg_hi2:
; GFX1250-SDAG: ; %bb.0:
@@ -1276,8 +1350,11 @@ define amdgpu_kernel void @fadd_v2_v_fneg_hi2(ptr addrspace(1) %a, float %x, flo
; GFX1250-GISEL-NEXT: v_and_b32_e32 v4, 0x3ff, v0
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT: global_load_b64 v[0:1], v4, s[0:1] scale_offset
-; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v3, -s2, -s2
-; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s3
+; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v2, -s2, -s2
+; GFX1250-GISEL-NEXT: s_mov_b32 s4, s3
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s5, v2
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[4:5]
; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3]
@@ -3150,9 +3227,11 @@ define amdgpu_kernel void @add_vector_neg_bitcast_scalar_lo(ptr addrspace(1) %ou
; GFX1250-GISEL-NEXT: ds_load_2addr_b32 v[0:1], v0 offset1:1
; GFX1250-GISEL-NEXT: ds_load_b32 v2, v2
; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v2, -v2, -v2
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v2
; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_max_num_f32_e64 v2, -s2, -s2
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v3, v2
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3]
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
@@ -3304,19 +3383,38 @@ define amdgpu_kernel void @shuffle_add_f32(ptr addrspace(1) %out, ptr addrspace(
; PACKED-SDAG-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; PACKED-SDAG-NEXT: s_endpgm
;
-; PACKED-GISEL-LABEL: shuffle_add_f32:
-; PACKED-GISEL: ; %bb.0: ; %bb
-; PACKED-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
-; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; PACKED-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; PACKED-GISEL-NEXT: ds_read_b64 v[0:1], v2
-; PACKED-GISEL-NEXT: ds_read_b64 v[2:3], v2 offset:8
-; PACKED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; PACKED-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3] op_sel:[0,1] op_sel_hi:[1,0]
-; PACKED-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; PACKED-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
-; PACKED-GISEL-NEXT: s_endpgm
+; GFX90A-GISEL-LABEL: shuffle_add_f32:
+; GFX90A-GISEL: ; %bb.0: ; %bb
+; GFX90A-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX90A-GISEL-NEXT: ds_read_b64 v[0:1], v2
+; GFX90A-GISEL-NEXT: ds_read_b64 v[2:3], v2 offset:8
+; GFX90A-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX90A-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; GFX90A-GISEL-NEXT: v_readfirstlane_b32 s2, v3
+; GFX90A-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3]
+; GFX90A-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX90A-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX90A-GISEL-NEXT: s_endpgm
+;
+; GFX942-GISEL-LABEL: shuffle_add_f32:
+; GFX942-GISEL: ; %bb.0: ; %bb
+; GFX942-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX942-GISEL-NEXT: ds_read_b64 v[0:1], v2
+; GFX942-GISEL-NEXT: ds_read_b64 v[2:3], v2 offset:8
+; GFX942-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
+; GFX942-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX942-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; GFX942-GISEL-NEXT: v_readfirstlane_b32 s2, v3
+; GFX942-GISEL-NEXT: v_mov_b32_e32 v2, 0
+; GFX942-GISEL-NEXT: s_nop 0
+; GFX942-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], s[2:3]
+; GFX942-GISEL-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX942-GISEL-NEXT: s_endpgm
;
; GFX1250-SDAG-LABEL: shuffle_add_f32:
; GFX1250-SDAG: ; %bb.0: ; %bb
@@ -3340,7 +3438,11 @@ define amdgpu_kernel void @shuffle_add_f32(ptr addrspace(1) %out, ptr addrspace(
; GFX1250-GISEL-NEXT: ds_load_b64 v[0:1], v2
; GFX1250-GISEL-NEXT: ds_load_b64 v[2:3], v2 offset:8
; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0
-; GFX1250-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3] op_sel:[0,1] op_sel_hi:[1,0]
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s3, v2
+; GFX1250-GISEL-NEXT: v_readfirstlane_b32 s2, v3
+; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
+; GFX1250-GISEL-NEXT: v_pk_add_f32 v[0:1], v[0:1], v[2:3]
; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 0
; GFX1250-GISEL-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX1250-GISEL-NEXT: s_endpgm
@@ -3390,23 +3492,47 @@ define amdgpu_kernel void @shuffle_neg_add_f32(ptr addrspace(1) %out, ptr addrsp
; PACKED-SDAG-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; PACKED-SDAG-NEXT: s_endpgm
;
-; PACKED-GISEL-LABEL: shuffle_neg_add_f32:
-; PACKED-GISEL: ; %bb.0: ; %bb
-; PACKED-GISEL-NEXT: s_load_dword s0, s[4:5], 0x2c
-; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; PACKED-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; PACKED-GISEL-NEXT: ds_read_b64 v[0:1], v2
-; PACKED-GISEL-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
-; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; PACKED-GISEL-NEXT: ds_read_b32 v3, v0
-; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; PACKED-GISEL-NEXT: ds_read_b64 v[2:3], v2 offset:8
-; PACKED-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; PACKED-GISEL-NEXT: v_pk_mul_f32...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/202074
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