[llvm] [SelectionDAG] Fold saturations into min/max (PR #202067)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 6 11:22:46 PDT 2026
https://github.com/mike-goutokuji created https://github.com/llvm/llvm-project/pull/202067
This is similar to what we do in Instcombine.
>From 96bf7b8bd99cc85ee3fc487a7b6da4f917fb958b Mon Sep 17 00:00:00 2001
From: Mike-Goutokuji <gfunni234 at gmail.com>
Date: Fri, 5 Jun 2026 13:25:45 -0400
Subject: [PATCH] [SelectionDAG] Fold saturations into min/max
Otherwise, there are some cases that rely on manual checking in ARM, when we can move that to DAG.
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 108 +-
llvm/lib/Target/ARM/ARMISelLowering.cpp | 6 +-
.../AArch64/Atomics/aarch64-atomicrmw-lse2.ll | 660 +--
.../Atomics/aarch64-atomicrmw-lse2_lse128.ll | 260 +-
.../aarch64-atomicrmw-outline_atomics.ll | 660 +--
.../AArch64/Atomics/aarch64-atomicrmw-rcpc.ll | 660 +--
.../Atomics/aarch64-atomicrmw-rcpc3.ll | 660 +--
.../Atomics/aarch64-atomicrmw-v8_1a.ll | 260 +-
.../AArch64/Atomics/aarch64-atomicrmw-v8a.ll | 660 +--
.../Atomics/aarch64_be-atomicrmw-lse2.ll | 1360 +++---
.../aarch64_be-atomicrmw-lse2_lse128.ll | 560 +--
.../aarch64_be-atomicrmw-outline_atomics.ll | 1420 +++---
.../Atomics/aarch64_be-atomicrmw-rcpc.ll | 1360 +++---
.../Atomics/aarch64_be-atomicrmw-rcpc3.ll | 1360 +++---
.../Atomics/aarch64_be-atomicrmw-v8_1a.ll | 560 +--
.../Atomics/aarch64_be-atomicrmw-v8a.ll | 1360 +++---
llvm/test/CodeGen/AArch64/arm64-atomic-128.ll | 56 +-
llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll | 3 +-
llvm/test/CodeGen/AArch64/arm64-fmax.ll | 3 +-
llvm/test/CodeGen/AArch64/atomic-ops-lse.ll | 624 +--
llvm/test/CodeGen/AArch64/atomic-ops.ll | 176 +-
llvm/test/CodeGen/AArch64/cond-sel.ll | 414 +-
llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll | 294 +-
llvm/test/CodeGen/AArch64/sat-add.ll | 28 +-
.../test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll | 32 +-
.../test/CodeGen/AMDGPU/flat-saddr-atomics.ll | 16 +-
llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll | 96 +-
.../AMDGPU/flat_atomics_i64_noprivate.ll | 64 +-
.../CodeGen/AMDGPU/flat_atomics_i64_system.ll | 264 +-
.../flat_atomics_i64_system_noprivate.ll | 120 +-
.../global-saddr-atomics-min-max-system.ll | 64 +-
.../AMDGPU/global_atomics_i64_system.ll | 120 +-
llvm/test/CodeGen/AMDGPU/max.ll | 4 +-
llvm/test/CodeGen/AMDGPU/min.ll | 172 +-
llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll | 154 +-
llvm/test/CodeGen/ARM/atomic-64bit.ll | 1235 +++--
llvm/test/CodeGen/ARM/atomic-ops-v8.ll | 2781 ++++++++----
.../ARM/atomicrmw_exclusive_monitor_ints.ll | 529 ++-
llvm/test/CodeGen/ARM/atomicrmw_minmax.ll | 35 +-
llvm/test/CodeGen/ARM/commute-movcc.ll | 8 +-
llvm/test/CodeGen/ARM/fpclamptosat.ll | 385 +-
llvm/test/CodeGen/ARM/fpclamptosat_vec.ll | 1406 +++---
llvm/test/CodeGen/ARM/sadd_sat.ll | 195 +-
llvm/test/CodeGen/ARM/sat-to-bitop.ll | 90 +-
llvm/test/CodeGen/ARM/ssat.ll | 143 +-
llvm/test/CodeGen/ARM/usat-with-shift.ll | 47 +-
llvm/test/CodeGen/ARM/usat.ll | 154 +-
.../ir-instruction/atomicrmw-lamcas.ll | 1320 +++---
.../ir-instruction/atomicrmw-minmax.ll | 50 +-
.../CodeGen/LoongArch/select-to-shiftand.ll | 72 +-
llvm/test/CodeGen/NVPTX/i8x4-instructions.ll | 132 +-
llvm/test/CodeGen/PowerPC/optcmp.ll | 4 +-
llvm/test/CodeGen/PowerPC/sat-add.ll | 33 +-
llvm/test/CodeGen/RISCV/atomic-rmw.ll | 3960 ++++++++---------
llvm/test/CodeGen/RISCV/atomic-signext.ll | 875 ++--
llvm/test/CodeGen/RISCV/compress.ll | 9 +-
llvm/test/CodeGen/RISCV/forced-atomics.ll | 148 +-
llvm/test/CodeGen/RISCV/fpclamptosat.ll | 354 +-
llvm/test/CodeGen/RISCV/pr148084.ll | 22 +-
.../CodeGen/RISCV/rvv/fpclamptosat_vec.ll | 372 +-
llvm/test/CodeGen/RISCV/select-cc.ll | 49 +-
.../CodeGen/SystemZ/atomicrmw-minmax-03.ll | 22 +-
.../CodeGen/SystemZ/atomicrmw-minmax-04.ll | 16 +-
.../CodeGen/SystemZ/atomicrmw-ops-i128.ll | 12 +-
llvm/test/CodeGen/SystemZ/int-max-01.ll | 40 +-
llvm/test/CodeGen/SystemZ/int-min-01.ll | 40 +-
.../Thumb2/LowOverheadLoops/minloop.ll | 21 +-
.../test/CodeGen/Thumb2/mve-blockplacement.ll | 36 +-
.../CodeGen/Thumb2/mve-vecreduce-loops.ll | 109 +-
.../CodeGen/Thumb2/mve-vmaxv-vminv-scalar.ll | 245 +-
llvm/test/CodeGen/Thumb2/mve-vmaxv.ll | 77 +-
llvm/test/CodeGen/Thumb2/v8_IT_4.ll | 12 +-
llvm/test/CodeGen/VE/Scalar/atomic.ll | 3 +-
llvm/test/CodeGen/VE/Scalar/max.ll | 4 +-
llvm/test/CodeGen/VE/Scalar/min.ll | 4 +-
llvm/test/CodeGen/VE/Scalar/smin.ll | 4 +-
llvm/test/CodeGen/WebAssembly/fpclamptosat.ll | 36 +-
.../X86/8bit_cmov_of_trunc_promotion.ll | 22 +-
llvm/test/CodeGen/X86/apx/cfcmov.ll | 8 +-
llvm/test/CodeGen/X86/atomic-minmax-i6432.ll | 60 +-
llvm/test/CodeGen/X86/atomic128.ll | 20 +-
llvm/test/CodeGen/X86/atomic32.ll | 16 +-
llvm/test/CodeGen/X86/atomic64.ll | 36 +-
llvm/test/CodeGen/X86/atomic6432.ll | 24 +-
llvm/test/CodeGen/X86/cmov.ll | 14 +-
llvm/test/CodeGen/X86/fpclamptosat_vec.ll | 2159 +++++----
llvm/test/CodeGen/X86/jump_sign.ll | 36 +-
llvm/test/CodeGen/X86/mul-constant-result.ll | 178 +-
llvm/test/CodeGen/X86/pr5145.ll | 36 +-
llvm/test/CodeGen/X86/sat-add.ll | 40 +-
llvm/test/CodeGen/X86/select.ll | 40 +-
llvm/test/CodeGen/X86/selectcc-to-shiftand.ll | 7 +-
llvm/test/CodeGen/X86/tail-opts.ll | 4 +-
93 files changed, 17359 insertions(+), 15048 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 7b2a35b10c318..b8c796a78b138 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -614,6 +614,9 @@ namespace {
SDValue False, ISD::CondCode CC, const SDLoc &DL);
SDValue foldSelectToUMin(SDValue LHS, SDValue RHS, SDValue True,
SDValue False, ISD::CondCode CC, const SDLoc &DL);
+ SDValue foldSelectToMinMax(const SDLoc &DL, EVT VT, SDValue LHS,
+ SDValue RHS, SDValue TrueVal, SDValue FalseVal,
+ ISD::CondCode CC);
SDValue unfoldMaskedMerge(SDNode *N);
SDValue unfoldExtremeBitClearingToShifts(SDNode *N);
SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
@@ -6264,6 +6267,22 @@ static SDValue PerformUMinFpToSatCombine(SDValue N0, SDValue N1, SDValue N2,
return DAG.getZExtOrTrunc(Sat, SDLoc(N0), N3.getValueType());
}
+static bool getMinMaxOperands(SDValue Op, SDValue &X, APInt &C) {
+ SDValue Op0 = Op.getOperand(0);
+ SDValue Op1 = Op.getOperand(1);
+ if (ConstantSDNode *C0 = isConstOrConstSplat(Op0)) {
+ X = Op1;
+ C = C0->getAPIntValue();
+ return true;
+ }
+ if (ConstantSDNode *C1 = isConstOrConstSplat(Op1)) {
+ X = Op0;
+ C = C1->getAPIntValue();
+ return true;
+ }
+ return false;
+}
+
SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
@@ -6284,6 +6303,36 @@ SDValue DAGCombiner::visitIMINMAX(SDNode *N) {
!DAG.isConstantIntBuildVectorOrConstantInt(N1))
return DAG.getNode(Opcode, DL, VT, N1, N0);
+ // Canonicalize max(min(X, HiC), LoC) -> min(max(X, LoC), HiC) when HiC > LoC.
+ // This matches InstCombine and is required for good saturation codegen on
+ // targets that lower min(max(X, 0), K) more efficiently than max(min(X, K), 0).
+ auto CanonicalizeClampForm = [&](unsigned OuterOpc, unsigned InnerOpc,
+ unsigned NewInnerOpc, unsigned NewOuterOpc,
+ auto CompareHiLo) -> SDValue {
+ if (Opcode != OuterOpc || N0.getOpcode() != InnerOpc || !N0.hasOneUse())
+ return SDValue();
+ SDValue X;
+ APInt HiC;
+ if (!getMinMaxOperands(N0, X, HiC))
+ return SDValue();
+ ConstantSDNode *LoCN = isConstOrConstSplat(N1);
+ if (!LoCN || !CompareHiLo(HiC, LoCN->getAPIntValue()))
+ return SDValue();
+ SDValue NewInner = DAG.getNode(NewInnerOpc, DL, VT, X, N1);
+ SDValue HiOp = N0.getOperand(N0.getOperand(0) == X ? 1 : 0);
+ return DAG.getNode(NewOuterOpc, DL, VT, NewInner, HiOp);
+ };
+ if (SDValue S = CanonicalizeClampForm(ISD::SMAX, ISD::SMIN, ISD::SMAX, ISD::SMIN,
+ [](const APInt &Hi, const APInt &Lo) {
+ return Hi.sgt(Lo);
+ }))
+ return S;
+ if (SDValue U = CanonicalizeClampForm(ISD::UMAX, ISD::UMIN, ISD::UMAX, ISD::UMIN,
+ [](const APInt &Hi, const APInt &Lo) {
+ return Hi.ugt(Lo);
+ }))
+ return U;
+
// fold vector ops
if (VT.isVector())
if (SDValue FoldedVOp = SimplifyVBinOp(N, DL))
@@ -12994,6 +13043,47 @@ SDValue DAGCombiner::foldSelectToUMin(SDValue LHS, SDValue RHS, SDValue True,
return SDValue();
}
+/// Fold (cmp X, Y) ? X : Y to min/max.
+SDValue DAGCombiner::foldSelectToMinMax(const SDLoc &DL, EVT VT, SDValue LHS,
+ SDValue RHS, SDValue TrueVal,
+ SDValue FalseVal, ISD::CondCode CC) {
+ if (!VT.isScalarInteger())
+ return SDValue();
+
+ if (TrueVal == RHS && FalseVal == LHS) {
+ std::swap(LHS, RHS);
+ CC = ISD::getSetCCSwappedOperands(CC);
+ }
+ if (TrueVal != LHS || FalseVal != RHS)
+ return SDValue();
+
+ unsigned Opc = 0;
+ switch (CC) {
+ case ISD::SETGT:
+ case ISD::SETGE:
+ Opc = ISD::SMAX;
+ break;
+ case ISD::SETLT:
+ case ISD::SETLE:
+ Opc = ISD::SMIN;
+ break;
+ case ISD::SETUGT:
+ case ISD::SETUGE:
+ Opc = ISD::UMAX;
+ break;
+ case ISD::SETULT:
+ case ISD::SETULE:
+ Opc = ISD::UMIN;
+ break;
+ default:
+ return SDValue();
+ }
+
+ if (!LegalOperations || hasOperation(Opc, VT))
+ return DAG.getNode(Opc, DL, VT, LHS, RHS);
+ return SDValue();
+}
+
SDValue DAGCombiner::visitSELECT(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
@@ -13121,6 +13211,9 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
SDValue Cond0 = N0.getOperand(0), Cond1 = N0.getOperand(1);
ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get();
+ if (SDValue MinMax = foldSelectToMinMax(DL, VT, Cond0, Cond1, N1, N2, CC))
+ return MinMax;
+
// select (fcmp lt x, y), x, y -> fminnum x, y
// select (fcmp gt x, y), x, y -> fmaxnum x, y
//
@@ -14390,6 +14483,10 @@ SDValue DAGCombiner::visitSELECT_CC(SDNode *N) {
if (N2 == N3)
return N2;
+ if (SDValue MinMax =
+ foldSelectToMinMax(DL, N->getValueType(0), N0, N1, N2, N3, CC))
+ return MinMax;
+
// select_cc bool, 0, x, y, seteq -> select bool, y, x
if (CC == ISD::SETEQ && !LegalTypes && N0.getValueType() == MVT::i1 &&
isNullConstant(N1))
@@ -17054,9 +17151,6 @@ static SDValue detectUSatUPattern(SDValue In, EVT VT) {
/// Detect patterns of truncation with signed saturation:
/// (truncate (smin (smax (x, signed_min_of_dest_type),
/// signed_max_of_dest_type)) to dest_type)
-/// or:
-/// (truncate (smax (smin (x, signed_max_of_dest_type),
-/// signed_min_of_dest_type)) to dest_type).
///
/// Return the source value to be truncated or SDValue() if the pattern was not
/// matched.
@@ -17092,14 +17186,14 @@ static SDValue detectSSatUPattern(SDValue In, EVT VT, SelectionDAG &DAG,
SDValue Val;
APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
// Min == 0, Max is unsigned max of destination type.
- if (sd_match(In, m_SMax(m_SMin(m_Value(Val), m_SpecificInt(UnsignedMax)),
- m_Zero())))
- return Val;
-
if (sd_match(In, m_SMin(m_SMax(m_Value(Val), m_Zero()),
m_SpecificInt(UnsignedMax))))
return Val;
+ if (sd_match(In, m_SMax(m_SMin(m_Value(Val), m_SpecificInt(UnsignedMax)),
+ m_Zero())))
+ return Val;
+
if (sd_match(In, m_UMin(m_SMax(m_Value(Val), m_Zero()),
m_SpecificInt(UnsignedMax))))
return Val;
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index e08a4f5ebda08..b05a48be026d1 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -18085,7 +18085,8 @@ static SDValue PerformMinMaxToSatCombine(SDValue Op, SelectionDAG &DAG,
SDValue Op0 = Op.getOperand(0);
if (VT != MVT::i32 ||
- (Op0.getOpcode() != ISD::SMIN && Op0.getOpcode() != ISD::SMAX) ||
+ (Op0.getOpcode() != ISD::SMIN && Op0.getOpcode() != ISD::SMAX &&
+ Op0.getOpcode() != ISD::UMIN) ||
!isa<ConstantSDNode>(Op.getOperand(1)) ||
!isa<ConstantSDNode>(Op0.getOperand(1)))
return SDValue();
@@ -18099,7 +18100,8 @@ static SDValue PerformMinMaxToSatCombine(SDValue Op, SelectionDAG &DAG,
APInt MinC = Min.getConstantOperandAPInt(1);
APInt MaxC = Max.getConstantOperandAPInt(1);
- if (Min.getOpcode() != ISD::SMIN || Max.getOpcode() != ISD::SMAX ||
+ if ((Min.getOpcode() != ISD::SMIN && Min.getOpcode() != ISD::UMIN) ||
+ Max.getOpcode() != ISD::SMAX ||
!(MinC + 1).isPowerOf2())
return SDValue();
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
index dfce1fbe0d30f..880f3d5d4220b 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2.ll
@@ -5345,11 +5345,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -5366,11 +5367,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -5387,11 +5389,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -5408,11 +5411,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -5429,11 +5433,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -5449,11 +5454,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
@@ -5469,11 +5475,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
@@ -5489,11 +5496,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value release, align 2
ret i16 %r
}
@@ -5509,11 +5517,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
@@ -5529,11 +5538,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -5875,11 +5885,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -5896,11 +5907,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -5917,11 +5929,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -5938,11 +5951,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -5959,11 +5973,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -5976,9 +5991,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5992,9 +6008,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6008,9 +6025,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6024,9 +6042,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -6040,9 +6059,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6310,11 +6330,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -6331,11 +6352,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -6352,11 +6374,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -6373,11 +6396,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -6394,11 +6418,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -6414,11 +6439,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
@@ -6434,11 +6460,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
@@ -6454,11 +6481,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value release, align 2
ret i16 %r
}
@@ -6474,11 +6502,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
@@ -6494,11 +6523,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -6515,7 +6545,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -6533,7 +6563,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -6551,7 +6581,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -6569,7 +6599,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -6587,7 +6617,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -6605,7 +6635,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -6623,7 +6653,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -6641,7 +6671,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -6659,7 +6689,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -6677,7 +6707,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -6704,9 +6734,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -6733,9 +6763,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -6762,9 +6792,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -6791,9 +6821,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -6820,9 +6850,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -6840,11 +6870,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -6861,11 +6892,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -6882,11 +6914,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -6903,11 +6936,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -6924,11 +6958,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -6941,9 +6976,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -6957,9 +6993,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6973,9 +7010,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6989,9 +7027,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7005,9 +7044,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -7021,7 +7061,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -7035,7 +7075,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -7049,7 +7089,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -7063,7 +7103,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -7077,7 +7117,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -7091,7 +7131,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -7105,7 +7145,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -7119,7 +7159,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -7133,7 +7173,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -7147,7 +7187,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -7167,9 +7207,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -7189,9 +7229,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -7211,9 +7251,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -7233,9 +7273,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -7255,9 +7295,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -7900,9 +7940,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -7915,9 +7956,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -7930,9 +7972,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -7945,9 +7988,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7960,9 +8004,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -8233,7 +8278,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -8254,7 +8299,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -8275,7 +8320,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -8296,7 +8341,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8317,7 +8362,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8336,7 +8381,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
@@ -8355,7 +8400,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 2
ret i16 %r
@@ -8374,7 +8419,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value release, align 2
ret i16 %r
@@ -8393,7 +8438,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
@@ -8412,7 +8457,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
@@ -8430,7 +8475,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -8448,7 +8493,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -8466,7 +8511,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -8484,7 +8529,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -8502,7 +8547,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -8520,7 +8565,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -8538,7 +8583,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -8556,7 +8601,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -8574,7 +8619,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -8592,7 +8637,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -8619,9 +8664,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -8648,9 +8693,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -8677,9 +8722,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -8706,9 +8751,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -8735,9 +8780,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -8758,7 +8803,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -8779,7 +8824,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -8800,7 +8845,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -8821,7 +8866,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8842,7 +8887,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8855,9 +8900,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -8870,9 +8916,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -8885,9 +8932,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -8900,9 +8948,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -8915,9 +8964,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -8931,7 +8981,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -8945,7 +8995,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -8959,7 +9009,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -8973,7 +9023,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -8987,7 +9037,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -9001,7 +9051,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -9015,7 +9065,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -9029,7 +9079,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -9043,7 +9093,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -9057,7 +9107,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -9077,9 +9127,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -9099,9 +9149,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -9121,9 +9171,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -9143,9 +9193,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -9165,9 +9215,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
index a939581680ab0..6e8ab037b16f1 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-lse2_lse128.ll
@@ -4086,9 +4086,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -4102,9 +4103,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -4118,9 +4120,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -4134,9 +4137,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -4150,9 +4154,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -4565,9 +4570,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -4592,9 +4597,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -4619,9 +4624,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -4646,9 +4651,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -4673,9 +4678,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -4726,9 +4731,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -4742,9 +4748,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -4758,9 +4765,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -4774,9 +4782,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -4790,9 +4799,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -4806,7 +4816,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -4820,7 +4830,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -4834,7 +4844,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -4848,7 +4858,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -4862,7 +4872,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -4876,7 +4886,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -4890,7 +4900,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -4904,7 +4914,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -4918,7 +4928,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -4932,7 +4942,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -4952,9 +4962,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -4974,9 +4984,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -4996,9 +5006,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -5018,9 +5028,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -5040,9 +5050,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -5365,9 +5375,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5380,9 +5391,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -5395,9 +5407,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -5410,9 +5423,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -5425,9 +5439,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -5840,9 +5855,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -5867,9 +5882,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -5894,9 +5909,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -5921,9 +5936,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -5948,9 +5963,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -6000,9 +6015,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -6015,9 +6031,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6030,9 +6047,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6045,9 +6063,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -6060,9 +6079,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6076,7 +6096,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -6090,7 +6110,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -6104,7 +6124,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -6118,7 +6138,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -6132,7 +6152,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -6146,7 +6166,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -6160,7 +6180,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -6174,7 +6194,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -6188,7 +6208,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -6202,7 +6222,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -6222,9 +6242,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -6244,9 +6264,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -6266,9 +6286,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -6288,9 +6308,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -6310,9 +6330,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
index f91e54be0bca6..d943827cfa452 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-outline_atomics.ll
@@ -4018,11 +4018,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -4037,11 +4038,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -4056,11 +4058,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -4075,11 +4078,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -4094,11 +4098,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -4112,11 +4117,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
@@ -4130,11 +4136,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
@@ -4148,11 +4155,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value release, align 2
ret i16 %r
}
@@ -4166,11 +4174,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
@@ -4184,11 +4193,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -4488,11 +4498,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -4507,11 +4518,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -4526,11 +4538,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -4545,11 +4558,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -4564,11 +4578,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -4581,9 +4596,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -4597,9 +4613,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -4613,9 +4630,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -4629,9 +4647,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -4645,9 +4664,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -4913,11 +4933,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -4932,11 +4953,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -4951,11 +4973,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -4970,11 +4993,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -4989,11 +5013,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -5007,11 +5032,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
@@ -5025,11 +5051,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
@@ -5043,11 +5070,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value release, align 2
ret i16 %r
}
@@ -5061,11 +5089,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
@@ -5079,11 +5108,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w8, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -5098,7 +5128,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -5114,7 +5144,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -5130,7 +5160,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -5146,7 +5176,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -5162,7 +5192,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -5178,7 +5208,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -5194,7 +5224,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -5210,7 +5240,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -5226,7 +5256,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -5242,7 +5272,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -5265,9 +5295,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -5290,9 +5320,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -5315,9 +5345,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -5340,9 +5370,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -5365,9 +5395,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -5383,11 +5413,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -5402,11 +5433,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -5421,11 +5453,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -5440,11 +5473,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -5459,11 +5493,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w8, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -5476,9 +5511,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5492,9 +5528,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -5508,9 +5545,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -5524,9 +5562,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -5540,9 +5579,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -5556,7 +5596,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -5570,7 +5610,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -5584,7 +5624,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -5598,7 +5638,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -5612,7 +5652,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -5626,7 +5666,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -5640,7 +5680,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -5654,7 +5694,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -5668,7 +5708,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -5682,7 +5722,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -5702,9 +5742,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -5724,9 +5764,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -5746,9 +5786,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -5768,9 +5808,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -5790,9 +5830,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -6365,9 +6405,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -6380,9 +6421,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6395,9 +6437,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6410,9 +6453,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -6425,9 +6469,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6696,7 +6741,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -6715,7 +6760,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -6734,7 +6779,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -6753,7 +6798,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -6772,7 +6817,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -6789,7 +6834,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
@@ -6806,7 +6851,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 2
ret i16 %r
@@ -6823,7 +6868,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value release, align 2
ret i16 %r
@@ -6840,7 +6885,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
@@ -6857,7 +6902,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
@@ -6873,7 +6918,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -6889,7 +6934,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -6905,7 +6950,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -6921,7 +6966,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -6937,7 +6982,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -6953,7 +6998,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -6969,7 +7014,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -6985,7 +7030,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -7001,7 +7046,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -7017,7 +7062,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -7040,9 +7085,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -7065,9 +7110,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -7090,9 +7135,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -7115,9 +7160,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -7140,9 +7185,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -7161,7 +7206,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -7180,7 +7225,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -7199,7 +7244,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -7218,7 +7263,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -7237,7 +7282,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -7250,9 +7295,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -7265,9 +7311,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -7280,9 +7327,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -7295,9 +7343,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7310,9 +7359,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -7326,7 +7376,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -7340,7 +7390,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -7354,7 +7404,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -7368,7 +7418,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -7382,7 +7432,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -7396,7 +7446,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -7410,7 +7460,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -7424,7 +7474,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -7438,7 +7488,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -7452,7 +7502,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -7472,9 +7522,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -7494,9 +7544,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -7516,9 +7566,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -7538,9 +7588,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -7560,9 +7610,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
index 22bfedb7adaa4..fca31e02df853 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc.ll
@@ -5345,11 +5345,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -5366,11 +5367,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -5387,11 +5389,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -5408,11 +5411,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -5429,11 +5433,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -5449,11 +5454,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
@@ -5469,11 +5475,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
@@ -5489,11 +5496,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value release, align 2
ret i16 %r
}
@@ -5509,11 +5517,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
@@ -5529,11 +5538,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -5875,11 +5885,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -5896,11 +5907,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -5917,11 +5929,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -5938,11 +5951,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -5959,11 +5973,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -5976,9 +5991,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5992,9 +6008,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6008,9 +6025,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6024,9 +6042,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -6040,9 +6059,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6310,11 +6330,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -6331,11 +6352,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -6352,11 +6374,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -6373,11 +6396,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -6394,11 +6418,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -6414,11 +6439,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
@@ -6434,11 +6460,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
@@ -6454,11 +6481,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value release, align 2
ret i16 %r
}
@@ -6474,11 +6502,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
@@ -6494,11 +6523,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -6515,7 +6545,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -6533,7 +6563,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -6551,7 +6581,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -6569,7 +6599,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -6587,7 +6617,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -6605,7 +6635,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -6623,7 +6653,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -6641,7 +6671,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -6659,7 +6689,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -6677,7 +6707,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -6704,9 +6734,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -6733,9 +6763,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -6762,9 +6792,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -6791,9 +6821,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -6820,9 +6850,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -6840,11 +6870,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -6861,11 +6892,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -6882,11 +6914,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -6903,11 +6936,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -6924,11 +6958,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -6941,9 +6976,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -6957,9 +6993,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6973,9 +7010,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6989,9 +7027,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7005,9 +7044,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -7021,7 +7061,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -7035,7 +7075,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -7049,7 +7089,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -7063,7 +7103,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -7077,7 +7117,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -7091,7 +7131,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -7105,7 +7145,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -7119,7 +7159,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -7133,7 +7173,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -7147,7 +7187,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -7167,9 +7207,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -7189,9 +7229,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -7211,9 +7251,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -7233,9 +7273,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -7255,9 +7295,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -7900,9 +7940,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -7915,9 +7956,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -7930,9 +7972,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -7945,9 +7988,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7960,9 +8004,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -8233,7 +8278,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -8254,7 +8299,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -8275,7 +8320,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -8296,7 +8341,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8317,7 +8362,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8336,7 +8381,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
@@ -8355,7 +8400,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 2
ret i16 %r
@@ -8374,7 +8419,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value release, align 2
ret i16 %r
@@ -8393,7 +8438,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
@@ -8412,7 +8457,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
@@ -8430,7 +8475,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -8448,7 +8493,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -8466,7 +8511,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -8484,7 +8529,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -8502,7 +8547,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -8520,7 +8565,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -8538,7 +8583,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -8556,7 +8601,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -8574,7 +8619,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -8592,7 +8637,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -8619,9 +8664,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -8648,9 +8693,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -8677,9 +8722,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -8706,9 +8751,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -8735,9 +8780,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -8758,7 +8803,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -8779,7 +8824,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -8800,7 +8845,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -8821,7 +8866,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8842,7 +8887,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8855,9 +8900,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -8870,9 +8916,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -8885,9 +8932,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -8900,9 +8948,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -8915,9 +8964,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -8931,7 +8981,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -8945,7 +8995,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -8959,7 +9009,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -8973,7 +9023,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -8987,7 +9037,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -9001,7 +9051,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -9015,7 +9065,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -9029,7 +9079,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -9043,7 +9093,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -9057,7 +9107,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -9077,9 +9127,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -9099,9 +9149,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -9121,9 +9171,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -9143,9 +9193,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -9165,9 +9215,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
index 2b2ca83652df9..fceda992da642 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-rcpc3.ll
@@ -5345,11 +5345,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -5366,11 +5367,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -5387,11 +5389,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -5408,11 +5411,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -5429,11 +5433,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -5449,11 +5454,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
@@ -5469,11 +5475,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
@@ -5489,11 +5496,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value release, align 2
ret i16 %r
}
@@ -5509,11 +5517,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
@@ -5529,11 +5538,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -5875,11 +5885,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -5896,11 +5907,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -5917,11 +5929,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -5938,11 +5951,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -5959,11 +5973,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -5976,9 +5991,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5992,9 +6008,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6008,9 +6025,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6024,9 +6042,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -6040,9 +6059,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6310,11 +6330,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -6331,11 +6352,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -6352,11 +6374,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -6373,11 +6396,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -6394,11 +6418,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -6414,11 +6439,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
@@ -6434,11 +6460,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
@@ -6454,11 +6481,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value release, align 2
ret i16 %r
}
@@ -6474,11 +6502,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
@@ -6494,11 +6523,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -6515,7 +6545,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -6533,7 +6563,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -6551,7 +6581,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -6569,7 +6599,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -6587,7 +6617,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -6605,7 +6635,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -6623,7 +6653,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -6641,7 +6671,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -6659,7 +6689,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -6677,7 +6707,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -6704,9 +6734,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -6733,9 +6763,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -6762,9 +6792,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -6791,9 +6821,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -6820,9 +6850,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -6840,11 +6870,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -6861,11 +6892,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -6882,11 +6914,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -6903,11 +6936,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -6924,11 +6958,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -6941,9 +6976,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -6957,9 +6993,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6973,9 +7010,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6989,9 +7027,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7005,9 +7044,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -7021,7 +7061,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -7035,7 +7075,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -7049,7 +7089,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -7063,7 +7103,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -7077,7 +7117,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -7091,7 +7131,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -7105,7 +7145,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -7119,7 +7159,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -7133,7 +7173,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -7147,7 +7187,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -7167,9 +7207,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -7189,9 +7229,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -7211,9 +7251,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -7233,9 +7273,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -7255,9 +7295,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -7900,9 +7940,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -7915,9 +7956,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -7930,9 +7972,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -7945,9 +7988,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7960,9 +8004,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -8233,7 +8278,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -8254,7 +8299,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -8275,7 +8320,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -8296,7 +8341,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8317,7 +8362,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8336,7 +8381,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
@@ -8355,7 +8400,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 2
ret i16 %r
@@ -8374,7 +8419,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value release, align 2
ret i16 %r
@@ -8393,7 +8438,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
@@ -8412,7 +8457,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
@@ -8430,7 +8475,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -8448,7 +8493,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -8466,7 +8511,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -8484,7 +8529,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -8502,7 +8547,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -8520,7 +8565,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -8538,7 +8583,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -8556,7 +8601,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -8574,7 +8619,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -8592,7 +8637,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -8619,9 +8664,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -8648,9 +8693,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -8677,9 +8722,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -8706,9 +8751,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -8735,9 +8780,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -8758,7 +8803,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -8779,7 +8824,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -8800,7 +8845,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -8821,7 +8866,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8842,7 +8887,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8855,9 +8900,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -8870,9 +8916,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -8885,9 +8932,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -8900,9 +8948,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -8915,9 +8964,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -8931,7 +8981,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -8945,7 +8995,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -8959,7 +9009,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -8973,7 +9023,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -8987,7 +9037,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -9001,7 +9051,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -9015,7 +9065,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -9029,7 +9079,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -9043,7 +9093,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -9057,7 +9107,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -9077,9 +9127,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -9099,9 +9149,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -9121,9 +9171,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -9143,9 +9193,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -9165,9 +9215,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
index 2066946da96b1..1aa36ddde794a 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8_1a.ll
@@ -4196,9 +4196,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -4212,9 +4213,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -4228,9 +4230,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -4244,9 +4247,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -4260,9 +4264,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -4675,9 +4680,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -4702,9 +4707,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -4729,9 +4734,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -4756,9 +4761,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -4783,9 +4788,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -4836,9 +4841,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -4852,9 +4858,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -4868,9 +4875,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -4884,9 +4892,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -4900,9 +4909,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -4916,7 +4926,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -4930,7 +4940,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -4944,7 +4954,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -4958,7 +4968,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -4972,7 +4982,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -4986,7 +4996,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -5000,7 +5010,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -5014,7 +5024,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -5028,7 +5038,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -5042,7 +5052,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -5062,9 +5072,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -5084,9 +5094,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -5106,9 +5116,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -5128,9 +5138,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -5150,9 +5160,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -5475,9 +5485,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5490,9 +5501,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -5505,9 +5517,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -5520,9 +5533,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -5535,9 +5549,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -5950,9 +5965,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -5977,9 +5992,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -6004,9 +6019,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -6031,9 +6046,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -6058,9 +6073,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x2, x4
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x4, x2
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x5, x7
; -O1: ccmp x4, x6, #0, eq
@@ -6110,9 +6125,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -6125,9 +6141,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6140,9 +6157,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6155,9 +6173,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -6170,9 +6189,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6186,7 +6206,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -6200,7 +6220,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -6214,7 +6234,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -6228,7 +6248,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -6242,7 +6262,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -6256,7 +6276,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -6270,7 +6290,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -6284,7 +6304,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -6298,7 +6318,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -6312,7 +6332,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -6332,9 +6352,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -6354,9 +6374,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -6376,9 +6396,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -6398,9 +6418,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -6420,9 +6440,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
index 8f4b30bd90638..c18e8c7485a89 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64-atomicrmw-v8a.ll
@@ -5345,11 +5345,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -5366,11 +5367,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -5387,11 +5389,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -5408,11 +5411,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -5429,11 +5433,12 @@ define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -5449,11 +5454,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
@@ -5469,11 +5475,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
@@ -5489,11 +5496,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value release, align 2
ret i16 %r
}
@@ -5509,11 +5517,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
@@ -5529,11 +5538,12 @@ define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -5875,11 +5885,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -5896,11 +5907,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -5917,11 +5929,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -5938,11 +5951,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -5959,11 +5973,12 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -5976,9 +5991,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5992,9 +6008,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6008,9 +6025,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6024,9 +6042,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -6040,9 +6059,10 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6310,11 +6330,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -6331,11 +6352,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -6352,11 +6374,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -6373,11 +6396,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -6394,11 +6418,12 @@ define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -6414,11 +6439,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
@@ -6434,11 +6460,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
@@ -6454,11 +6481,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value release, align 2
ret i16 %r
}
@@ -6474,11 +6502,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
@@ -6494,11 +6523,12 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0: subs w9, w9, w10, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -6515,7 +6545,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -6533,7 +6563,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -6551,7 +6581,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -6569,7 +6599,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -6587,7 +6617,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -6605,7 +6635,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -6623,7 +6653,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -6641,7 +6671,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -6659,7 +6689,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -6677,7 +6707,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -6704,9 +6734,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -6733,9 +6763,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -6762,9 +6792,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -6791,9 +6821,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -6820,9 +6850,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, ge
-; -O1: csel x10, x0, x2, ge
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lt
+; -O1: csel x10, x0, x2, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -6840,11 +6870,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
@@ -6861,11 +6892,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
@@ -6882,11 +6914,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
@@ -6903,11 +6936,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
@@ -6924,11 +6958,12 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0: subs w9, w9, w10, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
@@ -6941,9 +6976,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -6957,9 +6993,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6973,9 +7010,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6989,9 +7027,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7005,9 +7044,10 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -7021,7 +7061,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -7035,7 +7075,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -7049,7 +7089,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -7063,7 +7103,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -7077,7 +7117,7 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -7091,7 +7131,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -7105,7 +7145,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -7119,7 +7159,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -7133,7 +7173,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -7147,7 +7187,7 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -7167,9 +7207,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -7189,9 +7229,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -7211,9 +7251,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -7233,9 +7273,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -7255,9 +7295,9 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -7900,9 +7940,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -7915,9 +7956,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -7930,9 +7972,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -7945,9 +7988,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7960,9 +8004,10 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -8233,7 +8278,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -8254,7 +8299,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -8275,7 +8320,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -8296,7 +8341,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8317,7 +8362,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8336,7 +8381,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
@@ -8355,7 +8400,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 2
ret i16 %r
@@ -8374,7 +8419,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value release, align 2
ret i16 %r
@@ -8393,7 +8438,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
@@ -8412,7 +8457,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
@@ -8430,7 +8475,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -8448,7 +8493,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -8466,7 +8511,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -8484,7 +8529,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -8502,7 +8547,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -8520,7 +8565,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -8538,7 +8583,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -8556,7 +8601,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -8574,7 +8619,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -8592,7 +8637,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -8619,9 +8664,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -8648,9 +8693,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -8677,9 +8722,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -8706,9 +8751,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -8735,9 +8780,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldaxp x0, x1, [x8]
-; -O1: cmp x2, x0
-; -O1: csel x9, x1, x3, hs
-; -O1: csel x10, x0, x2, hs
+; -O1: cmp x0, x2
+; -O1: csel x9, x1, x3, lo
+; -O1: csel x10, x0, x2, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -8758,7 +8803,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -8779,7 +8824,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -8800,7 +8845,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -8821,7 +8866,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8842,7 +8887,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8855,9 +8900,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -8870,9 +8916,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -8885,9 +8932,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -8900,9 +8948,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -8915,9 +8964,10 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -8931,7 +8981,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -8945,7 +8995,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -8959,7 +9009,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -8973,7 +9023,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -8987,7 +9037,7 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -9001,7 +9051,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -9015,7 +9065,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -9029,7 +9079,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -9043,7 +9093,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -9057,7 +9107,7 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -9077,9 +9127,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -9099,9 +9149,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -9121,9 +9171,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -9143,9 +9193,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -9165,9 +9215,9 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x21, x0
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x0, x21
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll
index ea6ebe08936f5..5ba04453369ef 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2.ll
@@ -5220,200 +5220,220 @@ define dso_local i128 @atomicrmw_xor_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value release, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -5715,115 +5735,127 @@ define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value)
define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5831,15 +5863,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -5847,15 +5881,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -5863,15 +5899,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -5879,15 +5917,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6120,200 +6160,220 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value release, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -6321,7 +6381,7 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6330,7 +6390,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -6339,7 +6399,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6348,7 +6408,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -6357,7 +6417,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6366,7 +6426,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -6375,7 +6435,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6384,7 +6444,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -6393,7 +6453,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6402,7 +6462,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -6411,7 +6471,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6420,7 +6480,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -6429,7 +6489,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6438,7 +6498,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -6447,7 +6507,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6456,7 +6516,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -6465,7 +6525,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6474,7 +6534,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -6483,7 +6543,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6492,7 +6552,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -6500,9 +6560,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6513,9 +6573,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -6523,9 +6583,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6536,9 +6596,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -6546,9 +6606,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6559,9 +6619,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -6569,9 +6629,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6582,9 +6642,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -6592,9 +6652,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6605,9 +6665,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -6615,115 +6675,127 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -6731,15 +6803,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6747,15 +6821,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6763,15 +6839,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -6779,15 +6857,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6796,12 +6876,12 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -6810,12 +6890,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -6824,12 +6904,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -6838,12 +6918,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -6852,12 +6932,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -6866,12 +6946,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -6880,12 +6960,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -6894,12 +6974,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -6908,12 +6988,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -6922,12 +7002,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -6935,16 +7015,16 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -6952,16 +7032,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -6969,16 +7049,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -6986,16 +7066,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -7003,16 +7083,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -7020,9 +7100,10 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7040,9 +7121,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7060,9 +7142,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7080,9 +7163,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7100,9 +7184,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7120,9 +7205,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7140,9 +7226,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7160,9 +7247,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7180,9 +7268,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7200,9 +7289,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7515,9 +7605,10 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value
define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7535,9 +7626,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value)
define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7555,9 +7647,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7575,9 +7668,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7595,9 +7689,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7615,15 +7710,17 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -7631,15 +7728,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -7647,15 +7746,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -7663,15 +7764,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7679,15 +7782,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -7920,9 +8025,10 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %val
define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7932,7 +8038,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -7940,9 +8046,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7952,7 +8059,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -7960,9 +8067,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7972,7 +8080,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -7980,9 +8088,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7992,7 +8101,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8000,9 +8109,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8012,7 +8122,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8020,9 +8130,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8032,7 +8143,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
@@ -8040,9 +8151,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8052,7 +8164,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 2
ret i16 %r
@@ -8060,9 +8172,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8072,7 +8185,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value release, align 2
ret i16 %r
@@ -8080,9 +8193,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8092,7 +8206,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
@@ -8100,9 +8214,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8112,7 +8227,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
@@ -8121,7 +8236,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8130,7 +8245,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -8139,7 +8254,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8148,7 +8263,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -8157,7 +8272,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8166,7 +8281,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -8175,7 +8290,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8184,7 +8299,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -8193,7 +8308,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8202,7 +8317,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -8211,7 +8326,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8220,7 +8335,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -8229,7 +8344,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8238,7 +8353,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -8247,7 +8362,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8256,7 +8371,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -8265,7 +8380,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8274,7 +8389,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -8283,7 +8398,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8292,7 +8407,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -8300,9 +8415,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8313,9 +8428,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -8323,9 +8438,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8336,9 +8451,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -8346,9 +8461,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8359,9 +8474,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -8369,9 +8484,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8382,9 +8497,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -8392,9 +8507,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8405,9 +8520,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -8415,9 +8530,10 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8427,7 +8543,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -8435,9 +8551,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8447,7 +8564,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -8455,9 +8572,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8467,7 +8585,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -8475,9 +8593,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8487,7 +8606,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8495,9 +8614,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8507,7 +8627,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8515,15 +8635,17 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -8531,15 +8653,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -8547,15 +8671,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -8563,15 +8689,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -8579,15 +8707,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -8596,12 +8726,12 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -8610,12 +8740,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -8624,12 +8754,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -8638,12 +8768,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -8652,12 +8782,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -8666,12 +8796,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -8680,12 +8810,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -8694,12 +8824,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -8708,12 +8838,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -8722,12 +8852,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -8735,16 +8865,16 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -8752,16 +8882,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -8769,16 +8899,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -8786,16 +8916,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -8803,16 +8933,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll
index 29663f2633852..c651c9572e53f 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-lse2_lse128.ll
@@ -4110,15 +4110,17 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -4126,15 +4128,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -4142,15 +4146,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -4158,15 +4164,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -4174,15 +4182,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -4555,18 +4565,18 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, ge
-; -O0: csel x2, x11, x12, ge
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lt
+; -O0: csel x2, x11, x12, lt
; -O0: casp x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -4576,18 +4586,18 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, ge
-; -O0: csel x2, x11, x12, ge
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lt
+; -O0: csel x2, x11, x12, lt
; -O0: caspa x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -4597,18 +4607,18 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, ge
-; -O0: csel x2, x11, x12, ge
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lt
+; -O0: csel x2, x11, x12, lt
; -O0: caspl x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -4618,18 +4628,18 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, ge
-; -O0: csel x2, x11, x12, ge
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lt
+; -O0: csel x2, x11, x12, lt
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -4639,18 +4649,18 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, ge
-; -O0: csel x2, x11, x12, ge
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lt
+; -O0: csel x2, x11, x12, lt
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -4695,15 +4705,17 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -4711,15 +4723,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -4727,15 +4741,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -4743,15 +4759,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -4759,15 +4777,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -4776,12 +4796,12 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -4790,12 +4810,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -4804,12 +4824,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -4818,12 +4838,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -4832,12 +4852,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -4846,12 +4866,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -4860,12 +4880,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -4874,12 +4894,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -4888,12 +4908,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -4902,12 +4922,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -4915,16 +4935,16 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -4932,16 +4952,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -4949,16 +4969,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -4966,16 +4986,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -4983,16 +5003,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -5280,15 +5300,17 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5296,15 +5318,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -5312,15 +5336,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -5328,15 +5354,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -5344,15 +5372,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -5725,18 +5755,18 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, hs
-; -O0: csel x2, x11, x12, hs
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lo
+; -O0: csel x2, x11, x12, lo
; -O0: casp x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -5746,18 +5776,18 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, hs
-; -O0: csel x2, x11, x12, hs
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lo
+; -O0: csel x2, x11, x12, lo
; -O0: caspa x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -5767,18 +5797,18 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, hs
-; -O0: csel x2, x11, x12, hs
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lo
+; -O0: csel x2, x11, x12, lo
; -O0: caspl x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -5788,18 +5818,18 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, hs
-; -O0: csel x2, x11, x12, hs
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lo
+; -O0: csel x2, x11, x12, lo
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -5809,18 +5839,18 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, hs
-; -O0: csel x2, x11, x12, hs
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lo
+; -O0: csel x2, x11, x12, lo
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -5865,15 +5895,17 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5881,15 +5913,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -5897,15 +5931,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -5913,15 +5949,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -5929,15 +5967,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -5946,12 +5986,12 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -5960,12 +6000,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -5974,12 +6014,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -5988,12 +6028,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -6002,12 +6042,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -6016,12 +6056,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -6030,12 +6070,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -6044,12 +6084,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -6058,12 +6098,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -6072,12 +6112,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -6085,16 +6125,16 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -6102,16 +6142,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -6119,16 +6159,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -6136,16 +6176,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -6153,16 +6193,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-outline_atomics.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-outline_atomics.ll
index 45737a1ae6be4..3650a2f1ec1b4 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-outline_atomics.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-outline_atomics.ll
@@ -3955,180 +3955,200 @@ define dso_local i128 @atomicrmw_xor_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, gt
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas1_relax
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, gt
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas1_acq
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_release:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, gt
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas1_rel
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, gt
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, gt
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O0: sxth w9, w0
-; -O0: subs w9, w9, w8, sxth
-; -O0: csel w1, w0, w8, gt
+; -O0: sxth w9, w8
+; -O0: sxth w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas2_relax
; -O0: subs w8, w0, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O0: sxth w9, w0
-; -O0: subs w9, w9, w8, sxth
-; -O0: csel w1, w0, w8, gt
+; -O0: sxth w9, w8
+; -O0: sxth w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas2_acq
; -O0: subs w8, w0, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
-; -O0: sxth w9, w0
-; -O0: subs w9, w9, w8, sxth
-; -O0: csel w1, w0, w8, gt
+; -O0: sxth w9, w8
+; -O0: sxth w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas2_rel
; -O0: subs w8, w0, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value release, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O0: sxth w9, w0
-; -O0: subs w9, w9, w8, sxth
-; -O0: csel w1, w0, w8, gt
+; -O0: sxth w9, w8
+; -O0: sxth w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas2_acq_rel
; -O0: subs w8, w0, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O0: sxth w9, w0
-; -O0: subs w9, w9, w8, sxth
-; -O0: csel w1, w0, w8, gt
+; -O0: sxth w9, w8
+; -O0: sxth w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas2_acq_rel
; -O0: subs w8, w0, w8, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -4390,105 +4410,117 @@ define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value)
define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, gt
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas1_relax
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, gt
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas1_acq
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, gt
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas1_rel
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, gt
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, gt
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, gt
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -4496,15 +4528,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -4512,15 +4546,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -4528,15 +4564,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -4544,15 +4582,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -4785,180 +4825,200 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, le
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas1_relax
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, le
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas1_acq
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_release:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, le
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas1_rel
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, le
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, le
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O0: sxth w9, w0
-; -O0: subs w9, w9, w8, sxth
-; -O0: csel w1, w0, w8, le
+; -O0: sxth w9, w8
+; -O0: sxth w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas2_relax
; -O0: subs w8, w0, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O0: sxth w9, w0
-; -O0: subs w9, w9, w8, sxth
-; -O0: csel w1, w0, w8, le
+; -O0: sxth w9, w8
+; -O0: sxth w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas2_acq
; -O0: subs w8, w0, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
-; -O0: sxth w9, w0
-; -O0: subs w9, w9, w8, sxth
-; -O0: csel w1, w0, w8, le
+; -O0: sxth w9, w8
+; -O0: sxth w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas2_rel
; -O0: subs w8, w0, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value release, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O0: sxth w9, w0
-; -O0: subs w9, w9, w8, sxth
-; -O0: csel w1, w0, w8, le
+; -O0: sxth w9, w8
+; -O0: sxth w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas2_acq_rel
; -O0: subs w8, w0, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O0: sxth w9, w0
-; -O0: subs w9, w9, w8, sxth
-; -O0: csel w1, w0, w8, le
+; -O0: sxth w9, w8
+; -O0: sxth w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas2_acq_rel
; -O0: subs w8, w0, w8, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -4966,14 +5026,14 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O0: subs w9, w0, w8
-; -O0: csel w1, w0, w8, le
+; -O0: csel w1, w0, w8, lt
; -O0: bl __aarch64_cas4_relax
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -4982,14 +5042,14 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O0: subs w9, w0, w8
-; -O0: csel w1, w0, w8, le
+; -O0: csel w1, w0, w8, lt
; -O0: bl __aarch64_cas4_acq
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -4998,14 +5058,14 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
; -O0: subs w9, w0, w8
-; -O0: csel w1, w0, w8, le
+; -O0: csel w1, w0, w8, lt
; -O0: bl __aarch64_cas4_rel
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -5014,14 +5074,14 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O0: subs w9, w0, w8
-; -O0: csel w1, w0, w8, le
+; -O0: csel w1, w0, w8, lt
; -O0: bl __aarch64_cas4_acq_rel
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -5030,14 +5090,14 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O0: subs w9, w0, w8
-; -O0: csel w1, w0, w8, le
+; -O0: csel w1, w0, w8, lt
; -O0: bl __aarch64_cas4_acq_rel
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -5046,14 +5106,14 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O0: subs x9, x0, x8
-; -O0: csel x1, x0, x8, le
+; -O0: csel x1, x0, x8, lt
; -O0: bl __aarch64_cas8_relax
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -5062,14 +5122,14 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O0: subs x9, x0, x8
-; -O0: csel x1, x0, x8, le
+; -O0: csel x1, x0, x8, lt
; -O0: bl __aarch64_cas8_acq
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -5078,14 +5138,14 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
; -O0: subs x9, x0, x8
-; -O0: csel x1, x0, x8, le
+; -O0: csel x1, x0, x8, lt
; -O0: bl __aarch64_cas8_rel
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -5094,14 +5154,14 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O0: subs x9, x0, x8
-; -O0: csel x1, x0, x8, le
+; -O0: csel x1, x0, x8, lt
; -O0: bl __aarch64_cas8_acq_rel
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -5110,14 +5170,14 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O0: subs x9, x0, x8
-; -O0: csel x1, x0, x8, le
+; -O0: csel x1, x0, x8, lt
; -O0: bl __aarch64_cas8_acq_rel
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -5125,18 +5185,18 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x10, x8, x1
-; -O0: csel x2, x0, x9, ge
-; -O0: csel x3, x1, x8, ge
+; -O0: subs x10, x1, x8
+; -O0: csel x2, x0, x9, lt
+; -O0: csel x3, x1, x8, lt
; -O0: bl __aarch64_cas16_relax
; -O0: subs x10, x10, x11
; -O0: ccmp x8, x9, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -5144,18 +5204,18 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x10, x8, x1
-; -O0: csel x2, x0, x9, ge
-; -O0: csel x3, x1, x8, ge
+; -O0: subs x10, x1, x8
+; -O0: csel x2, x0, x9, lt
+; -O0: csel x3, x1, x8, lt
; -O0: bl __aarch64_cas16_acq
; -O0: subs x10, x10, x11
; -O0: ccmp x8, x9, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -5163,18 +5223,18 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x10, x8, x1
-; -O0: csel x2, x0, x9, ge
-; -O0: csel x3, x1, x8, ge
+; -O0: subs x10, x1, x8
+; -O0: csel x2, x0, x9, lt
+; -O0: csel x3, x1, x8, lt
; -O0: bl __aarch64_cas16_rel
; -O0: subs x10, x10, x11
; -O0: ccmp x8, x9, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -5182,18 +5242,18 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x10, x8, x1
-; -O0: csel x2, x0, x9, ge
-; -O0: csel x3, x1, x8, ge
+; -O0: subs x10, x1, x8
+; -O0: csel x2, x0, x9, lt
+; -O0: csel x3, x1, x8, lt
; -O0: bl __aarch64_cas16_acq_rel
; -O0: subs x10, x10, x11
; -O0: ccmp x8, x9, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -5201,18 +5261,18 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x10, x8, x1
-; -O0: csel x2, x0, x9, ge
-; -O0: csel x3, x1, x8, ge
+; -O0: subs x10, x1, x8
+; -O0: csel x2, x0, x9, lt
+; -O0: csel x3, x1, x8, lt
; -O0: bl __aarch64_cas16_acq_rel
; -O0: subs x10, x10, x11
; -O0: ccmp x8, x9, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -5220,105 +5280,117 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, le
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas1_relax
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, le
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas1_acq
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, le
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas1_rel
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, le
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O0: sxtb w9, w0
-; -O0: subs w9, w9, w8, sxtb
-; -O0: csel w1, w0, w8, le
+; -O0: sxtb w9, w8
+; -O0: sxtb w8, w0
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lt
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5326,15 +5398,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -5342,15 +5416,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -5358,15 +5434,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -5374,15 +5452,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -5391,12 +5471,12 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -5405,12 +5485,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -5419,12 +5499,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -5433,12 +5513,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -5447,12 +5527,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -5461,12 +5541,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -5475,12 +5555,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -5489,12 +5569,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -5503,12 +5583,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -5517,12 +5597,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -5530,16 +5610,16 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -5547,16 +5627,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -5564,16 +5644,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -5581,16 +5661,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -5598,16 +5678,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -5615,9 +5695,10 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_monotonic:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas1_relax
; -O0: subs w8, w0, w8
;
@@ -5633,9 +5714,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acquire:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas1_acq
; -O0: subs w8, w0, w8
;
@@ -5651,9 +5733,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_release:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas1_rel
; -O0: subs w8, w0, w8
;
@@ -5669,9 +5752,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acq_rel:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8
;
@@ -5687,9 +5771,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_seq_cst:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8
;
@@ -5705,9 +5790,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
-; -O0: and w9, w0, #0xffff
-; -O0: subs w9, w9, w8, uxth
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xffff
+; -O0: and w8, w0, #0xffff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas2_relax
; -O0: subs w8, w0, w8
;
@@ -5723,9 +5809,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
-; -O0: and w9, w0, #0xffff
-; -O0: subs w9, w9, w8, uxth
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xffff
+; -O0: and w8, w0, #0xffff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas2_acq
; -O0: subs w8, w0, w8
;
@@ -5741,9 +5828,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
-; -O0: and w9, w0, #0xffff
-; -O0: subs w9, w9, w8, uxth
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xffff
+; -O0: and w8, w0, #0xffff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas2_rel
; -O0: subs w8, w0, w8
;
@@ -5759,9 +5847,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
-; -O0: and w9, w0, #0xffff
-; -O0: subs w9, w9, w8, uxth
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xffff
+; -O0: and w8, w0, #0xffff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas2_acq_rel
; -O0: subs w8, w0, w8
;
@@ -5777,9 +5866,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
-; -O0: and w9, w0, #0xffff
-; -O0: subs w9, w9, w8, uxth
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xffff
+; -O0: and w8, w0, #0xffff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas2_acq_rel
; -O0: subs w8, w0, w8
;
@@ -6050,9 +6140,10 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value
define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_monotonic:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas1_relax
; -O0: subs w8, w0, w8
;
@@ -6068,9 +6159,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value)
define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acquire:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas1_acq
; -O0: subs w8, w0, w8
;
@@ -6086,9 +6178,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_release:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas1_rel
; -O0: subs w8, w0, w8
;
@@ -6104,9 +6197,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acq_rel:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8
;
@@ -6122,9 +6216,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_seq_cst:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, hi
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, hi
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8
;
@@ -6140,15 +6235,17 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -6156,15 +6253,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6172,15 +6271,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6188,15 +6289,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -6204,15 +6307,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6445,9 +6550,10 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %val
define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_monotonic:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas1_relax
; -O0: subs w8, w0, w8
;
@@ -6455,7 +6561,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -6463,9 +6569,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acquire:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas1_acq
; -O0: subs w8, w0, w8
;
@@ -6473,7 +6580,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -6481,9 +6588,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_release:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas1_rel
; -O0: subs w8, w0, w8
;
@@ -6491,7 +6599,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -6499,9 +6607,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acq_rel:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8
;
@@ -6509,7 +6618,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -6517,9 +6626,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_seq_cst:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8
;
@@ -6527,7 +6637,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -6535,9 +6645,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
-; -O0: and w9, w0, #0xffff
-; -O0: subs w9, w9, w8, uxth
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xffff
+; -O0: and w8, w0, #0xffff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas2_relax
; -O0: subs w8, w0, w8
;
@@ -6545,7 +6656,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
@@ -6553,9 +6664,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
-; -O0: and w9, w0, #0xffff
-; -O0: subs w9, w9, w8, uxth
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xffff
+; -O0: and w8, w0, #0xffff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas2_acq
; -O0: subs w8, w0, w8
;
@@ -6563,7 +6675,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 2
ret i16 %r
@@ -6571,9 +6683,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
-; -O0: and w9, w0, #0xffff
-; -O0: subs w9, w9, w8, uxth
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xffff
+; -O0: and w8, w0, #0xffff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas2_rel
; -O0: subs w8, w0, w8
;
@@ -6581,7 +6694,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value release, align 2
ret i16 %r
@@ -6589,9 +6702,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
-; -O0: and w9, w0, #0xffff
-; -O0: subs w9, w9, w8, uxth
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xffff
+; -O0: and w8, w0, #0xffff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas2_acq_rel
; -O0: subs w8, w0, w8
;
@@ -6599,7 +6713,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
@@ -6607,9 +6721,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
-; -O0: and w9, w0, #0xffff
-; -O0: subs w9, w9, w8, uxth
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xffff
+; -O0: and w8, w0, #0xffff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas2_acq_rel
; -O0: subs w8, w0, w8
;
@@ -6617,7 +6732,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
@@ -6626,14 +6741,14 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O0: subs w9, w0, w8
-; -O0: csel w1, w0, w8, ls
+; -O0: csel w1, w0, w8, lo
; -O0: bl __aarch64_cas4_relax
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -6642,14 +6757,14 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O0: subs w9, w0, w8
-; -O0: csel w1, w0, w8, ls
+; -O0: csel w1, w0, w8, lo
; -O0: bl __aarch64_cas4_acq
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -6658,14 +6773,14 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
; -O0: subs w9, w0, w8
-; -O0: csel w1, w0, w8, ls
+; -O0: csel w1, w0, w8, lo
; -O0: bl __aarch64_cas4_rel
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -6674,14 +6789,14 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O0: subs w9, w0, w8
-; -O0: csel w1, w0, w8, ls
+; -O0: csel w1, w0, w8, lo
; -O0: bl __aarch64_cas4_acq_rel
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -6690,14 +6805,14 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O0: subs w9, w0, w8
-; -O0: csel w1, w0, w8, ls
+; -O0: csel w1, w0, w8, lo
; -O0: bl __aarch64_cas4_acq_rel
; -O0: subs w8, w0, w8
;
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -6706,14 +6821,14 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O0: subs x9, x0, x8
-; -O0: csel x1, x0, x8, ls
+; -O0: csel x1, x0, x8, lo
; -O0: bl __aarch64_cas8_relax
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -6722,14 +6837,14 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O0: subs x9, x0, x8
-; -O0: csel x1, x0, x8, ls
+; -O0: csel x1, x0, x8, lo
; -O0: bl __aarch64_cas8_acq
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -6738,14 +6853,14 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
; -O0: subs x9, x0, x8
-; -O0: csel x1, x0, x8, ls
+; -O0: csel x1, x0, x8, lo
; -O0: bl __aarch64_cas8_rel
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -6754,14 +6869,14 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O0: subs x9, x0, x8
-; -O0: csel x1, x0, x8, ls
+; -O0: csel x1, x0, x8, lo
; -O0: bl __aarch64_cas8_acq_rel
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -6770,14 +6885,14 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O0: subs x9, x0, x8
-; -O0: csel x1, x0, x8, ls
+; -O0: csel x1, x0, x8, lo
; -O0: bl __aarch64_cas8_acq_rel
; -O0: subs x8, x0, x8
;
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -6785,18 +6900,18 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x10, x8, x1
-; -O0: csel x2, x0, x9, hs
-; -O0: csel x3, x1, x8, hs
+; -O0: subs x10, x1, x8
+; -O0: csel x2, x0, x9, lo
+; -O0: csel x3, x1, x8, lo
; -O0: bl __aarch64_cas16_relax
; -O0: subs x10, x10, x11
; -O0: ccmp x8, x9, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -6804,18 +6919,18 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x10, x8, x1
-; -O0: csel x2, x0, x9, hs
-; -O0: csel x3, x1, x8, hs
+; -O0: subs x10, x1, x8
+; -O0: csel x2, x0, x9, lo
+; -O0: csel x3, x1, x8, lo
; -O0: bl __aarch64_cas16_acq
; -O0: subs x10, x10, x11
; -O0: ccmp x8, x9, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -6823,18 +6938,18 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x10, x8, x1
-; -O0: csel x2, x0, x9, hs
-; -O0: csel x3, x1, x8, hs
+; -O0: subs x10, x1, x8
+; -O0: csel x2, x0, x9, lo
+; -O0: csel x3, x1, x8, lo
; -O0: bl __aarch64_cas16_rel
; -O0: subs x10, x10, x11
; -O0: ccmp x8, x9, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -6842,18 +6957,18 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x10, x8, x1
-; -O0: csel x2, x0, x9, hs
-; -O0: csel x3, x1, x8, hs
+; -O0: subs x10, x1, x8
+; -O0: csel x2, x0, x9, lo
+; -O0: csel x3, x1, x8, lo
; -O0: bl __aarch64_cas16_acq_rel
; -O0: subs x10, x10, x11
; -O0: ccmp x8, x9, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -6861,18 +6976,18 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x10, x8, x1
-; -O0: csel x2, x0, x9, hs
-; -O0: csel x3, x1, x8, hs
+; -O0: subs x10, x1, x8
+; -O0: csel x2, x0, x9, lo
+; -O0: csel x3, x1, x8, lo
; -O0: bl __aarch64_cas16_acq_rel
; -O0: subs x10, x10, x11
; -O0: ccmp x8, x9, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -6880,9 +6995,10 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_monotonic:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas1_relax
; -O0: subs w8, w0, w8
;
@@ -6890,7 +7006,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -6898,9 +7014,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acquire:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas1_acq
; -O0: subs w8, w0, w8
;
@@ -6908,7 +7025,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -6916,9 +7033,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_release:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas1_rel
; -O0: subs w8, w0, w8
;
@@ -6926,7 +7044,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -6934,9 +7052,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acq_rel:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8
;
@@ -6944,7 +7063,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -6952,9 +7071,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_seq_cst:
-; -O0: and w9, w0, #0xff
-; -O0: subs w9, w9, w8, uxtb
-; -O0: csel w1, w0, w8, ls
+; -O0: and w9, w8, #0xff
+; -O0: and w8, w0, #0xff
+; -O0: subs w10, w8, w9
+; -O0: csel w1, w8, w9, lo
; -O0: bl __aarch64_cas1_acq_rel
; -O0: subs w8, w0, w8
;
@@ -6962,7 +7082,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -6970,15 +7090,17 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -6986,15 +7108,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -7002,15 +7126,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -7018,15 +7144,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7034,15 +7162,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -7051,12 +7181,12 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -7065,12 +7195,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -7079,12 +7209,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -7093,12 +7223,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -7107,12 +7237,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -7121,12 +7251,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -7135,12 +7265,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -7149,12 +7279,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -7163,12 +7293,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -7177,12 +7307,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -7190,16 +7320,16 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -7207,16 +7337,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -7224,16 +7354,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -7241,16 +7371,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -7258,16 +7388,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll
index 8200e2c2c2b32..2dc6b2393f333 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc.ll
@@ -5220,200 +5220,220 @@ define dso_local i128 @atomicrmw_xor_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value release, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -5715,115 +5735,127 @@ define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value)
define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5831,15 +5863,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -5847,15 +5881,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -5863,15 +5899,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -5879,15 +5917,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6120,200 +6160,220 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value release, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -6321,7 +6381,7 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6330,7 +6390,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -6339,7 +6399,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6348,7 +6408,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -6357,7 +6417,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6366,7 +6426,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -6375,7 +6435,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6384,7 +6444,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -6393,7 +6453,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6402,7 +6462,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -6411,7 +6471,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6420,7 +6480,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -6429,7 +6489,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6438,7 +6498,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -6447,7 +6507,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6456,7 +6516,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -6465,7 +6525,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6474,7 +6534,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -6483,7 +6543,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6492,7 +6552,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -6500,9 +6560,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6513,9 +6573,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -6523,9 +6583,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6536,9 +6596,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -6546,9 +6606,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6559,9 +6619,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -6569,9 +6629,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6582,9 +6642,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -6592,9 +6652,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6605,9 +6665,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -6615,115 +6675,127 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -6731,15 +6803,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6747,15 +6821,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6763,15 +6839,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -6779,15 +6857,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6796,12 +6876,12 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -6810,12 +6890,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -6824,12 +6904,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -6838,12 +6918,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -6852,12 +6932,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -6866,12 +6946,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -6880,12 +6960,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -6894,12 +6974,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -6908,12 +6988,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -6922,12 +7002,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -6935,16 +7015,16 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -6952,16 +7032,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -6969,16 +7049,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -6986,16 +7066,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -7003,16 +7083,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -7020,9 +7100,10 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7040,9 +7121,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7060,9 +7142,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7080,9 +7163,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7100,9 +7184,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7120,9 +7205,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7140,9 +7226,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7160,9 +7247,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7180,9 +7268,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7200,9 +7289,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7515,9 +7605,10 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value
define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7535,9 +7626,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value)
define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7555,9 +7647,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7575,9 +7668,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7595,9 +7689,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7615,15 +7710,17 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -7631,15 +7728,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -7647,15 +7746,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -7663,15 +7764,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7679,15 +7782,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -7920,9 +8025,10 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %val
define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7932,7 +8038,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -7940,9 +8046,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7952,7 +8059,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -7960,9 +8067,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7972,7 +8080,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -7980,9 +8088,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7992,7 +8101,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8000,9 +8109,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8012,7 +8122,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8020,9 +8130,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8032,7 +8143,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
@@ -8040,9 +8151,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8052,7 +8164,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 2
ret i16 %r
@@ -8060,9 +8172,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8072,7 +8185,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value release, align 2
ret i16 %r
@@ -8080,9 +8193,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8092,7 +8206,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
@@ -8100,9 +8214,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8112,7 +8227,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
@@ -8121,7 +8236,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8130,7 +8245,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -8139,7 +8254,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8148,7 +8263,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -8157,7 +8272,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8166,7 +8281,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -8175,7 +8290,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8184,7 +8299,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -8193,7 +8308,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8202,7 +8317,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -8211,7 +8326,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8220,7 +8335,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -8229,7 +8344,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8238,7 +8353,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -8247,7 +8362,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8256,7 +8371,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -8265,7 +8380,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8274,7 +8389,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -8283,7 +8398,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8292,7 +8407,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -8300,9 +8415,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8313,9 +8428,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -8323,9 +8438,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8336,9 +8451,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -8346,9 +8461,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8359,9 +8474,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -8369,9 +8484,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8382,9 +8497,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -8392,9 +8507,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8405,9 +8520,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -8415,9 +8530,10 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8427,7 +8543,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -8435,9 +8551,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8447,7 +8564,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -8455,9 +8572,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8467,7 +8585,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -8475,9 +8593,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8487,7 +8606,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8495,9 +8614,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8507,7 +8627,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8515,15 +8635,17 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -8531,15 +8653,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -8547,15 +8671,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -8563,15 +8689,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -8579,15 +8707,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -8596,12 +8726,12 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -8610,12 +8740,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -8624,12 +8754,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -8638,12 +8768,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -8652,12 +8782,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -8666,12 +8796,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -8680,12 +8810,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -8694,12 +8824,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -8708,12 +8838,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -8722,12 +8852,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -8735,16 +8865,16 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -8752,16 +8882,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -8769,16 +8899,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -8786,16 +8916,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -8803,16 +8933,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll
index 6df602200ebb6..9f0df2fd6c471 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-rcpc3.ll
@@ -5220,200 +5220,220 @@ define dso_local i128 @atomicrmw_xor_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value release, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -5715,115 +5735,127 @@ define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value)
define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5831,15 +5863,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -5847,15 +5881,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -5863,15 +5899,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -5879,15 +5917,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6120,200 +6160,220 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value release, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -6321,7 +6381,7 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6330,7 +6390,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -6339,7 +6399,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6348,7 +6408,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -6357,7 +6417,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6366,7 +6426,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -6375,7 +6435,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6384,7 +6444,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -6393,7 +6453,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6402,7 +6462,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -6411,7 +6471,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6420,7 +6480,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -6429,7 +6489,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6438,7 +6498,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -6447,7 +6507,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6456,7 +6516,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -6465,7 +6525,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6474,7 +6534,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -6483,7 +6543,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6492,7 +6552,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -6500,9 +6560,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6513,9 +6573,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -6523,9 +6583,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6536,9 +6596,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -6546,9 +6606,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6559,9 +6619,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -6569,9 +6629,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6582,9 +6642,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -6592,9 +6652,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6605,9 +6665,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -6615,115 +6675,127 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -6731,15 +6803,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6747,15 +6821,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6763,15 +6839,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -6779,15 +6857,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6796,12 +6876,12 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -6810,12 +6890,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -6824,12 +6904,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -6838,12 +6918,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -6852,12 +6932,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -6866,12 +6946,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -6880,12 +6960,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -6894,12 +6974,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -6908,12 +6988,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -6922,12 +7002,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -6935,16 +7015,16 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -6952,16 +7032,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -6969,16 +7049,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -6986,16 +7066,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -7003,16 +7083,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -7020,9 +7100,10 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7040,9 +7121,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7060,9 +7142,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7080,9 +7163,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7100,9 +7184,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7120,9 +7205,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7140,9 +7226,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7160,9 +7247,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7180,9 +7268,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7200,9 +7289,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7515,9 +7605,10 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value
define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7535,9 +7626,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value)
define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7555,9 +7647,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7575,9 +7668,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7595,9 +7689,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7615,15 +7710,17 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -7631,15 +7728,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -7647,15 +7746,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -7663,15 +7764,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7679,15 +7782,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -7920,9 +8025,10 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %val
define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7932,7 +8038,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -7940,9 +8046,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7952,7 +8059,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -7960,9 +8067,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7972,7 +8080,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -7980,9 +8088,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7992,7 +8101,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8000,9 +8109,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8012,7 +8122,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8020,9 +8130,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8032,7 +8143,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
@@ -8040,9 +8151,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8052,7 +8164,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 2
ret i16 %r
@@ -8060,9 +8172,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8072,7 +8185,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value release, align 2
ret i16 %r
@@ -8080,9 +8193,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8092,7 +8206,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
@@ -8100,9 +8214,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8112,7 +8227,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
@@ -8121,7 +8236,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8130,7 +8245,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -8139,7 +8254,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8148,7 +8263,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -8157,7 +8272,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8166,7 +8281,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -8175,7 +8290,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8184,7 +8299,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -8193,7 +8308,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8202,7 +8317,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -8211,7 +8326,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8220,7 +8335,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -8229,7 +8344,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8238,7 +8353,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -8247,7 +8362,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8256,7 +8371,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -8265,7 +8380,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8274,7 +8389,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -8283,7 +8398,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8292,7 +8407,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -8300,9 +8415,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8313,9 +8428,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -8323,9 +8438,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8336,9 +8451,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -8346,9 +8461,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8359,9 +8474,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -8369,9 +8484,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8382,9 +8497,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -8392,9 +8507,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8405,9 +8520,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -8415,9 +8530,10 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8427,7 +8543,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -8435,9 +8551,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8447,7 +8564,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -8455,9 +8572,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8467,7 +8585,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -8475,9 +8593,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8487,7 +8606,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8495,9 +8614,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8507,7 +8627,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8515,15 +8635,17 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -8531,15 +8653,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -8547,15 +8671,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -8563,15 +8689,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -8579,15 +8707,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -8596,12 +8726,12 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -8610,12 +8740,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -8624,12 +8754,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -8638,12 +8768,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -8652,12 +8782,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -8666,12 +8796,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -8680,12 +8810,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -8694,12 +8824,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -8708,12 +8838,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -8722,12 +8852,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -8735,16 +8865,16 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -8752,16 +8882,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -8769,16 +8899,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -8786,16 +8916,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -8803,16 +8933,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll
index 34cd68c94c6a0..753e79f7c5628 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8_1a.ll
@@ -4205,15 +4205,17 @@ define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -4221,15 +4223,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -4237,15 +4241,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -4253,15 +4259,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -4269,15 +4277,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -4650,18 +4660,18 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, ge
-; -O0: csel x2, x11, x12, ge
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lt
+; -O0: csel x2, x11, x12, lt
; -O0: casp x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -4671,18 +4681,18 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, ge
-; -O0: csel x2, x11, x12, ge
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lt
+; -O0: csel x2, x11, x12, lt
; -O0: caspa x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -4692,18 +4702,18 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, ge
-; -O0: csel x2, x11, x12, ge
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lt
+; -O0: csel x2, x11, x12, lt
; -O0: caspl x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -4713,18 +4723,18 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, ge
-; -O0: csel x2, x11, x12, ge
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lt
+; -O0: csel x2, x11, x12, lt
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -4734,18 +4744,18 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, ge
-; -O0: csel x2, x11, x12, ge
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lt
+; -O0: csel x2, x11, x12, lt
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, ge
-; -O1: csel x8, x4, x2, ge
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lt
+; -O1: csel x8, x4, x2, lt
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -4790,15 +4800,17 @@ define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -4806,15 +4818,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -4822,15 +4836,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -4838,15 +4854,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -4854,15 +4872,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -4871,12 +4891,12 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -4885,12 +4905,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -4899,12 +4919,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -4913,12 +4933,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -4927,12 +4947,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -4941,12 +4961,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -4955,12 +4975,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -4969,12 +4989,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -4983,12 +5003,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -4997,12 +5017,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -5010,16 +5030,16 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -5027,16 +5047,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -5044,16 +5064,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -5061,16 +5081,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -5078,16 +5098,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -5375,15 +5395,17 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5391,15 +5413,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -5407,15 +5431,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -5423,15 +5449,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -5439,15 +5467,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -5820,18 +5850,18 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, hs
-; -O0: csel x2, x11, x12, hs
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lo
+; -O0: csel x2, x11, x12, lo
; -O0: casp x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: casp x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -5841,18 +5871,18 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, hs
-; -O0: csel x2, x11, x12, hs
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lo
+; -O0: csel x2, x11, x12, lo
; -O0: caspa x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspa x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -5862,18 +5892,18 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, hs
-; -O0: csel x2, x11, x12, hs
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lo
+; -O0: csel x2, x11, x12, lo
; -O0: caspl x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspl x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -5883,18 +5913,18 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, hs
-; -O0: csel x2, x11, x12, hs
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lo
+; -O0: csel x2, x11, x12, lo
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -5904,18 +5934,18 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x13, x9, x10
-; -O0: csel x9, x10, x9, hs
-; -O0: csel x2, x11, x12, hs
+; -O0: subs x13, x10, x9
+; -O0: csel x9, x10, x9, lo
+; -O0: csel x2, x11, x12, lo
; -O0: caspal x0, x1, x2, x3, [x8]
; -O0: subs x11, x9, x11
; -O0: ccmp x8, x10, #0, eq
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldp x4, x5, [x0]
-; -O1: cmp x3, x7
-; -O1: csel x9, x7, x3, hs
-; -O1: csel x8, x4, x2, hs
+; -O1: cmp x7, x3
+; -O1: csel x9, x7, x3, lo
+; -O1: csel x8, x4, x2, lo
; -O1: caspal x4, x5, x8, x9, [x0]
; -O1: cmp x4, x6
; -O1: ccmp x5, x7, #0, eq
@@ -5960,15 +5990,17 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5976,15 +6008,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -5992,15 +6026,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6008,15 +6044,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -6024,15 +6062,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6041,12 +6081,12 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -6055,12 +6095,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -6069,12 +6109,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -6083,12 +6123,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -6097,12 +6137,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -6111,12 +6151,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -6125,12 +6165,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -6139,12 +6179,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -6153,12 +6193,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -6167,12 +6207,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -6180,16 +6220,16 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -6197,16 +6237,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -6214,16 +6254,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -6231,16 +6271,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -6248,16 +6288,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll
index 60fd7dab58220..19badf4412e45 100644
--- a/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll
+++ b/llvm/test/CodeGen/AArch64/Atomics/aarch64_be-atomicrmw-v8a.ll
@@ -5220,200 +5220,220 @@ define dso_local i128 @atomicrmw_xor_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_max_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value release, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_max_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_max_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -5715,115 +5735,127 @@ define dso_local i128 @atomicrmw_max_i128_aligned_seq_cst(ptr %ptr, i128 %value)
define dso_local i8 @atomicrmw_max_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_max_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, gt
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, gt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_max_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, gt
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, gt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw max ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -5831,15 +5863,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -5847,15 +5881,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -5863,15 +5899,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -5879,15 +5917,17 @@ define dso_local i16 @atomicrmw_max_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_max_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, gt
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, gt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_max_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, gt
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, gt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw max ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6120,200 +6160,220 @@ define dso_local i128 @atomicrmw_max_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_min_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_aligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_monotonic:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acquire:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_release:
-; -O1: ldxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value release, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_acq_rel:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
}
define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w12, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w9, uxth
; -O0: stlxrh w10, w12, [x11]
; -O0: subs w9, w8, w9, uxth
;
; -O1-LABEL: atomicrmw_min_i16_aligned_seq_cst:
-; -O1: ldaxrh w9, [x0]
-; -O1: sxth w8, w9
-; -O1: cmp w8, w1, sxth
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrh w10, w9, [x0]
+; -O1: sxth w9, w1
+; -O1: ldaxrh w8, [x0]
+; -O1: sxth w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
}
@@ -6321,7 +6381,7 @@ define dso_local i16 @atomicrmw_min_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6330,7 +6390,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_min_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -6339,7 +6399,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6348,7 +6408,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -6357,7 +6417,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6366,7 +6426,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -6375,7 +6435,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6384,7 +6444,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -6393,7 +6453,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, le
+; -O0: csel w12, w9, w8, lt
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -6402,7 +6462,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_min_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, le
+; -O1: csel w9, w8, w1, lt
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -6411,7 +6471,7 @@ define dso_local i32 @atomicrmw_min_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6420,7 +6480,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_min_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -6429,7 +6489,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6438,7 +6498,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -6447,7 +6507,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6456,7 +6516,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -6465,7 +6525,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6474,7 +6534,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -6483,7 +6543,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, le
+; -O0: csel x12, x9, x8, lt
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -6492,7 +6552,7 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_min_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, le
+; -O1: csel x9, x0, x1, lt
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -6500,9 +6560,9 @@ define dso_local i64 @atomicrmw_min_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_monotonic:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6513,9 +6573,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
;
; -O1-LABEL: atomicrmw_min_i128_aligned_monotonic:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -6523,9 +6583,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_monotonic(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acquire:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6536,9 +6596,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acquire:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -6546,9 +6606,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acquire(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_release:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6559,9 +6619,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_release:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -6569,9 +6629,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_release(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_acq_rel:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6582,9 +6642,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_acq_rel:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -6592,9 +6652,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_acq_rel(ptr %ptr, i128 %value)
define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_aligned_seq_cst:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, ge
-; -O0: csel x14, x11, x8, ge
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lt
+; -O0: csel x14, x11, x8, lt
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -6605,9 +6665,9 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
;
; -O1-LABEL: atomicrmw_min_i128_aligned_seq_cst:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, ge
-; -O1: csel x10, x1, x3, ge
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lt
+; -O1: csel x10, x1, x3, lt
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -6615,115 +6675,127 @@ define dso_local i128 @atomicrmw_min_i128_aligned_seq_cst(ptr %ptr, i128 %value)
define dso_local i8 @atomicrmw_min_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_monotonic:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acquire:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acquire, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_release:
-; -O1: ldxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value release, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_acq_rel:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
}
define dso_local i8 @atomicrmw_min_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O0: sxtb w10, w9
-; -O0: subs w10, w10, w8, sxtb
-; -O0: csel w12, w9, w8, le
+; -O0: sxtb w10, w8
+; -O0: sxtb w8, w9
+; -O0: subs w12, w8, w10
+; -O0: csel w12, w8, w10, lt
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w9, uxtb
; -O0: stlxrb w10, w12, [x11]
; -O0: subs w9, w8, w9, uxtb
;
; -O1-LABEL: atomicrmw_min_i8_unaligned_seq_cst:
-; -O1: ldaxrb w9, [x0]
-; -O1: sxtb w8, w9
-; -O1: cmp w8, w1, sxtb
-; -O1: csel w9, w9, w1, le
-; -O1: stlxrb w10, w9, [x0]
+; -O1: sxtb w9, w1
+; -O1: ldaxrb w8, [x0]
+; -O1: sxtb w8, w8
+; -O1: cmp w8, w9
+; -O1: csel w10, w8, w9, lt
+; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw min ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
}
define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_monotonic:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_monotonic:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -6731,15 +6803,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_monotonic(ptr %ptr, i16 %value
define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acquire:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acquire:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -6747,15 +6821,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_release:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_release:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -6763,15 +6839,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_acq_rel:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -6779,15 +6857,17 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
-; -O0: sxth w10, w9
-; -O0: subs w10, w10, w8, sxth
-; -O0: csel w8, w9, w8, le
+; -O0: sxth w10, w8
+; -O0: sxth w8, w9
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i16_unaligned_seq_cst:
+; -O1: sxth w20, w1
; -O1: sxth w8, w0
-; -O1: cmp w8, w20, sxth
-; -O1: csel w8, w0, w20, le
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -6796,12 +6876,12 @@ define dso_local i16 @atomicrmw_min_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -6810,12 +6890,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_monotonic(ptr %ptr, i32 %value
define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -6824,12 +6904,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -6838,12 +6918,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -6852,12 +6932,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, le
+; -O0: csel w8, w9, w8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, le
+; -O1: csel w8, w0, w20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -6866,12 +6946,12 @@ define dso_local i32 @atomicrmw_min_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -6880,12 +6960,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_monotonic(ptr %ptr, i64 %value
define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -6894,12 +6974,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -6908,12 +6988,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -6922,12 +7002,12 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, le
+; -O0: csel x8, x9, x8, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, le
+; -O1: csel x8, x0, x20, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -6935,16 +7015,16 @@ define dso_local i64 @atomicrmw_min_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -6952,16 +7032,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_monotonic(ptr %ptr, i128 %va
define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -6969,16 +7049,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acquire(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -6986,16 +7066,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_release(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -7003,16 +7083,16 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_acq_rel(ptr %ptr, i128 %valu
define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, ge
-; -O0: csel x9, x10, x9, ge
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lt
+; -O0: csel x9, x10, x9, lt
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_min_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, ge
-; -O1: csel x9, x0, x21, ge
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lt
+; -O1: csel x9, x0, x21, lt
; -O1: bl __atomic_compare_exchange
%r = atomicrmw min ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
@@ -7020,9 +7100,10 @@ define dso_local i128 @atomicrmw_min_i128_unaligned_seq_cst(ptr %ptr, i128 %valu
define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7040,9 +7121,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_monotonic(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7060,9 +7142,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7080,9 +7163,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7100,9 +7184,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_aligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7120,9 +7205,10 @@ define dso_local i8 @atomicrmw_umax_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_monotonic:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7140,9 +7226,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acquire:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7160,9 +7247,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_release:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7180,9 +7268,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_acq_rel:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7200,9 +7289,10 @@ define dso_local i16 @atomicrmw_umax_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umax_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_aligned_seq_cst:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -7515,9 +7605,10 @@ define dso_local i128 @atomicrmw_umax_i128_aligned_seq_cst(ptr %ptr, i128 %value
define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7535,9 +7626,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_monotonic(ptr %ptr, i8 %value)
define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7555,9 +7647,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7575,9 +7668,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7595,9 +7689,10 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umax_i8_unaligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, hi
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, hi
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7615,15 +7710,17 @@ define dso_local i8 @atomicrmw_umax_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -7631,15 +7728,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -7647,15 +7746,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -7663,15 +7764,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -7679,15 +7782,17 @@ define dso_local i16 @atomicrmw_umax_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umax_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, hi
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, hi
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umax_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, hi
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, hi
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umax ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -7920,9 +8025,10 @@ define dso_local i128 @atomicrmw_umax_i128_unaligned_seq_cst(ptr %ptr, i128 %val
define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7932,7 +8038,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -7940,9 +8046,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_monotonic(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7952,7 +8059,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -7960,9 +8067,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7972,7 +8080,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -7980,9 +8088,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -7992,7 +8101,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8000,9 +8109,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_aligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8012,7 +8122,7 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8020,9 +8130,10 @@ define dso_local i8 @atomicrmw_umin_i8_aligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_monotonic:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8032,7 +8143,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 2
ret i16 %r
@@ -8040,9 +8151,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_monotonic(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acquire:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8052,7 +8164,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 2
ret i16 %r
@@ -8060,9 +8172,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acquire(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_release:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8072,7 +8185,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value release, align 2
ret i16 %r
@@ -8080,9 +8193,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_release(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_acq_rel:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8092,7 +8206,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 2
ret i16 %r
@@ -8100,9 +8214,10 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_acq_rel(ptr %ptr, i16 %value) {
define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_aligned_seq_cst:
+; -O0: and w8, w8, #0xffff
; -O0: and w9, w12, #0xffff
-; -O0: subs w10, w9, w8, uxth
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrh w8, [x11]
; -O0: cmp w8, w12, uxth
; -O0: stlxrh w10, w13, [x11]
@@ -8112,7 +8227,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
; -O1: and w9, w1, #0xffff
; -O1: ldaxrh w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrh w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 2
ret i16 %r
@@ -8121,7 +8236,7 @@ define dso_local i16 @atomicrmw_umin_i16_aligned_seq_cst(ptr %ptr, i16 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8130,7 +8245,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
; -O1-LABEL: atomicrmw_umin_i32_aligned_monotonic:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 4
ret i32 %r
@@ -8139,7 +8254,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_monotonic(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8148,7 +8263,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acquire:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 4
ret i32 %r
@@ -8157,7 +8272,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acquire(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8166,7 +8281,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_release:
; -O1: ldxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value release, align 4
ret i32 %r
@@ -8175,7 +8290,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_release(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8184,7 +8299,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_acq_rel:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 4
ret i32 %r
@@ -8193,7 +8308,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_acq_rel(ptr %ptr, i32 %value) {
define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w12, w9, w8, ls
+; -O0: csel w12, w9, w8, lo
; -O0: ldaxr w8, [x11]
; -O0: cmp w8, w9
; -O0: stlxr w10, w12, [x11]
@@ -8202,7 +8317,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
; -O1-LABEL: atomicrmw_umin_i32_aligned_seq_cst:
; -O1: ldaxr w8, [x0]
; -O1: cmp w8, w1
-; -O1: csel w9, w8, w1, ls
+; -O1: csel w9, w8, w1, lo
; -O1: stlxr w10, w9, [x0]
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 4
ret i32 %r
@@ -8211,7 +8326,7 @@ define dso_local i32 @atomicrmw_umin_i32_aligned_seq_cst(ptr %ptr, i32 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8220,7 +8335,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
; -O1-LABEL: atomicrmw_umin_i64_aligned_monotonic:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 8
ret i64 %r
@@ -8229,7 +8344,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_monotonic(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8238,7 +8353,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acquire:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 8
ret i64 %r
@@ -8247,7 +8362,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acquire(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8256,7 +8371,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_release:
; -O1: ldxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value release, align 8
ret i64 %r
@@ -8265,7 +8380,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_release(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8274,7 +8389,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_acq_rel:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 8
ret i64 %r
@@ -8283,7 +8398,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_acq_rel(ptr %ptr, i64 %value) {
define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x12, x9, x8, ls
+; -O0: csel x12, x9, x8, lo
; -O0: ldaxr x8, [x11]
; -O0: cmp x8, x9
; -O0: stlxr w10, x12, [x11]
@@ -8292,7 +8407,7 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
; -O1-LABEL: atomicrmw_umin_i64_aligned_seq_cst:
; -O1: ldaxr x0, [x8]
; -O1: cmp x0, x1
-; -O1: csel x9, x0, x1, ls
+; -O1: csel x9, x0, x1, lo
; -O1: stlxr w10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 8
ret i64 %r
@@ -8300,9 +8415,9 @@ define dso_local i64 @atomicrmw_umin_i64_aligned_seq_cst(ptr %ptr, i64 %value) {
define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_monotonic:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8313,9 +8428,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_monotonic:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 16
ret i128 %r
@@ -8323,9 +8438,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_monotonic(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acquire:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8336,9 +8451,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acquire:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 16
ret i128 %r
@@ -8346,9 +8461,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acquire(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_release:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8359,9 +8474,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_release:
; -O1: ldxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value release, align 16
ret i128 %r
@@ -8369,9 +8484,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_release(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8382,9 +8497,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_acq_rel:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 16
ret i128 %r
@@ -8392,9 +8507,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_acq_rel(ptr %ptr, i128 %value
define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
-; -O0: subs x12, x8, x11
-; -O0: csel x15, x13, x10, hs
-; -O0: csel x14, x11, x8, hs
+; -O0: subs x12, x11, x8
+; -O0: csel x15, x13, x10, lo
+; -O0: csel x14, x11, x8, lo
; -O0: ldaxp x10, x12, [x9]
; -O0: cmp x10, x11
; -O0: cmp x12, x13
@@ -8405,9 +8520,9 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
;
; -O1-LABEL: atomicrmw_umin_i128_aligned_seq_cst:
; -O1: ldaxp x1, x0, [x8]
-; -O1: cmp x3, x1
-; -O1: csel x9, x0, x2, hs
-; -O1: csel x10, x1, x3, hs
+; -O1: cmp x1, x3
+; -O1: csel x9, x0, x2, lo
+; -O1: csel x10, x1, x3, lo
; -O1: stlxp w11, x10, x9, [x8]
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 16
ret i128 %r
@@ -8415,9 +8530,10 @@ define dso_local i128 @atomicrmw_umin_i128_aligned_seq_cst(ptr %ptr, i128 %value
define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_monotonic:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8427,7 +8543,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value monotonic, align 1
ret i8 %r
@@ -8435,9 +8551,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_monotonic(ptr %ptr, i8 %value)
define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acquire:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8447,7 +8564,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acquire, align 1
ret i8 %r
@@ -8455,9 +8572,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acquire(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_release:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8467,7 +8585,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value release, align 1
ret i8 %r
@@ -8475,9 +8593,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_release(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_acq_rel:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8487,7 +8606,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value acq_rel, align 1
ret i8 %r
@@ -8495,9 +8614,10 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_acq_rel(ptr %ptr, i8 %value) {
define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O0-LABEL: atomicrmw_umin_i8_unaligned_seq_cst:
+; -O0: and w8, w8, #0xff
; -O0: and w9, w12, #0xff
-; -O0: subs w10, w9, w8, uxtb
-; -O0: csel w13, w12, w8, ls
+; -O0: subs w10, w9, w8
+; -O0: csel w13, w9, w8, lo
; -O0: ldaxrb w8, [x11]
; -O0: cmp w8, w12, uxtb
; -O0: stlxrb w10, w13, [x11]
@@ -8507,7 +8627,7 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
; -O1: and w9, w1, #0xff
; -O1: ldaxrb w8, [x0]
; -O1: cmp w8, w9
-; -O1: csel w10, w8, w9, ls
+; -O1: csel w10, w8, w9, lo
; -O1: stlxrb w11, w10, [x0]
%r = atomicrmw umin ptr %ptr, i8 %value seq_cst, align 1
ret i8 %r
@@ -8515,15 +8635,17 @@ define dso_local i8 @atomicrmw_umin_i8_unaligned_seq_cst(ptr %ptr, i8 %value) {
define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_monotonic:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value monotonic, align 1
ret i16 %r
@@ -8531,15 +8653,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_monotonic(ptr %ptr, i16 %valu
define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acquire:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acquire:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acquire, align 1
ret i16 %r
@@ -8547,15 +8671,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acquire(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_release:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_release:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value release, align 1
ret i16 %r
@@ -8563,15 +8689,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_release(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_acq_rel:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value acq_rel, align 1
ret i16 %r
@@ -8579,15 +8707,17 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_acq_rel(ptr %ptr, i16 %value)
define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value) {
; -O0-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
-; -O0: and w10, w9, #0xffff
-; -O0: subs w10, w10, w8, uxth
-; -O0: csel w8, w9, w8, ls
+; -O0: and w10, w8, #0xffff
+; -O0: and w8, w9, #0xffff
+; -O0: subs w11, w8, w10
+; -O0: csel w8, w8, w10, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i16_unaligned_seq_cst:
+; -O1: and w20, w1, #0xffff
; -O1: and w8, w0, #0xffff
-; -O1: cmp w8, w20, uxth
-; -O1: csel w8, w0, w20, ls
+; -O1: cmp w8, w20
+; -O1: csel w8, w8, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i16 %value seq_cst, align 1
ret i16 %r
@@ -8596,12 +8726,12 @@ define dso_local i16 @atomicrmw_umin_i16_unaligned_seq_cst(ptr %ptr, i16 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_monotonic:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value monotonic, align 1
ret i32 %r
@@ -8610,12 +8740,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_monotonic(ptr %ptr, i32 %valu
define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acquire:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acquire, align 1
ret i32 %r
@@ -8624,12 +8754,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acquire(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_release:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value release, align 1
ret i32 %r
@@ -8638,12 +8768,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_release(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_acq_rel:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value acq_rel, align 1
ret i32 %r
@@ -8652,12 +8782,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_acq_rel(ptr %ptr, i32 %value)
define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value) {
; -O0-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O0: subs w10, w9, w8
-; -O0: csel w8, w9, w8, ls
+; -O0: csel w8, w9, w8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i32_unaligned_seq_cst:
; -O1: cmp w0, w20
-; -O1: csel w8, w0, w20, ls
+; -O1: csel w8, w0, w20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i32 %value seq_cst, align 1
ret i32 %r
@@ -8666,12 +8796,12 @@ define dso_local i32 @atomicrmw_umin_i32_unaligned_seq_cst(ptr %ptr, i32 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_monotonic:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value monotonic, align 1
ret i64 %r
@@ -8680,12 +8810,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_monotonic(ptr %ptr, i64 %valu
define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acquire:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acquire, align 1
ret i64 %r
@@ -8694,12 +8824,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acquire(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_release:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value release, align 1
ret i64 %r
@@ -8708,12 +8838,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_release(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_acq_rel:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value acq_rel, align 1
ret i64 %r
@@ -8722,12 +8852,12 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_acq_rel(ptr %ptr, i64 %value)
define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value) {
; -O0-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O0: subs x10, x9, x8
-; -O0: csel x8, x9, x8, ls
+; -O0: csel x8, x9, x8, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i64_unaligned_seq_cst:
; -O1: cmp x0, x20
-; -O1: csel x8, x0, x20, ls
+; -O1: csel x8, x0, x20, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i64 %value seq_cst, align 1
ret i64 %r
@@ -8735,16 +8865,16 @@ define dso_local i64 @atomicrmw_umin_i64_unaligned_seq_cst(ptr %ptr, i64 %value)
define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_monotonic:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value monotonic, align 1
ret i128 %r
@@ -8752,16 +8882,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_monotonic(ptr %ptr, i128 %v
define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acquire:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acquire:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acquire, align 1
ret i128 %r
@@ -8769,16 +8899,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acquire(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_release:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_release:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value release, align 1
ret i128 %r
@@ -8786,16 +8916,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_release(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_acq_rel:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value acq_rel, align 1
ret i128 %r
@@ -8803,16 +8933,16 @@ define dso_local i128 @atomicrmw_umin_i128_unaligned_acq_rel(ptr %ptr, i128 %val
define dso_local i128 @atomicrmw_umin_i128_unaligned_seq_cst(ptr %ptr, i128 %value) {
; -O0-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
-; -O0: subs x12, x9, x10
-; -O0: csel x8, x11, x8, hs
-; -O0: csel x9, x10, x9, hs
+; -O0: subs x12, x10, x9
+; -O0: csel x8, x11, x8, lo
+; -O0: csel x9, x10, x9, lo
; -O0: bl __atomic_compare_exchange
;
; -O1-LABEL: atomicrmw_umin_i128_unaligned_seq_cst:
; -O1: ldp x0, x1, [x0]
-; -O1: cmp x19, x1
-; -O1: csel x8, x1, x19, hs
-; -O1: csel x9, x0, x21, hs
+; -O1: cmp x1, x19
+; -O1: csel x8, x1, x19, lo
+; -O1: csel x9, x0, x21, lo
; -O1: bl __atomic_compare_exchange
%r = atomicrmw umin ptr %ptr, i128 %value seq_cst, align 1
ret i128 %r
diff --git a/llvm/test/CodeGen/AArch64/arm64-atomic-128.ll b/llvm/test/CodeGen/AArch64/arm64-atomic-128.ll
index 37c61d0a4a0fb..a5c747e421480 100644
--- a/llvm/test/CodeGen/AArch64/arm64-atomic-128.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-atomic-128.ll
@@ -447,10 +447,10 @@ define void @fetch_and_min(ptr %p, i128 %bits) {
; NOOUTLINE-NEXT: .LBB8_1: // %atomicrmw.start
; NOOUTLINE-NEXT: // =>This Inner Loop Header: Depth=1
; NOOUTLINE-NEXT: ldaxp x9, x8, [x0]
-; NOOUTLINE-NEXT: cmp x2, x9
-; NOOUTLINE-NEXT: sbcs xzr, x3, x8
-; NOOUTLINE-NEXT: csel x10, x8, x3, ge
-; NOOUTLINE-NEXT: csel x11, x9, x2, ge
+; NOOUTLINE-NEXT: cmp x9, x2
+; NOOUTLINE-NEXT: sbcs xzr, x8, x3
+; NOOUTLINE-NEXT: csel x10, x8, x3, lt
+; NOOUTLINE-NEXT: csel x11, x9, x2, lt
; NOOUTLINE-NEXT: stlxp w12, x11, x10, [x0]
; NOOUTLINE-NEXT: cbnz w12, .LBB8_1
; NOOUTLINE-NEXT: // %bb.2: // %atomicrmw.end
@@ -464,10 +464,10 @@ define void @fetch_and_min(ptr %p, i128 %bits) {
; OUTLINE-NEXT: .LBB8_1: // %atomicrmw.start
; OUTLINE-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-NEXT: ldaxp x9, x8, [x0]
-; OUTLINE-NEXT: cmp x2, x9
-; OUTLINE-NEXT: sbcs xzr, x3, x8
-; OUTLINE-NEXT: csel x10, x8, x3, ge
-; OUTLINE-NEXT: csel x11, x9, x2, ge
+; OUTLINE-NEXT: cmp x9, x2
+; OUTLINE-NEXT: sbcs xzr, x8, x3
+; OUTLINE-NEXT: csel x10, x8, x3, lt
+; OUTLINE-NEXT: csel x11, x9, x2, lt
; OUTLINE-NEXT: stlxp w12, x11, x10, [x0]
; OUTLINE-NEXT: cbnz w12, .LBB8_1
; OUTLINE-NEXT: // %bb.2: // %atomicrmw.end
@@ -483,10 +483,10 @@ define void @fetch_and_min(ptr %p, i128 %bits) {
; LSE-NEXT: // =>This Inner Loop Header: Depth=1
; LSE-NEXT: mov x7, x5
; LSE-NEXT: mov x6, x4
-; LSE-NEXT: cmp x2, x4
-; LSE-NEXT: sbcs xzr, x3, x7
-; LSE-NEXT: csel x9, x7, x3, ge
-; LSE-NEXT: csel x8, x4, x2, ge
+; LSE-NEXT: cmp x4, x2
+; LSE-NEXT: sbcs xzr, x7, x3
+; LSE-NEXT: csel x9, x7, x3, lt
+; LSE-NEXT: csel x8, x4, x2, lt
; LSE-NEXT: mov x4, x6
; LSE-NEXT: mov x5, x7
; LSE-NEXT: caspal x4, x5, x8, x9, [x0]
@@ -571,10 +571,10 @@ define void @fetch_and_umin(ptr %p, i128 %bits) {
; NOOUTLINE-NEXT: .LBB10_1: // %atomicrmw.start
; NOOUTLINE-NEXT: // =>This Inner Loop Header: Depth=1
; NOOUTLINE-NEXT: ldaxp x9, x8, [x0]
-; NOOUTLINE-NEXT: cmp x2, x9
-; NOOUTLINE-NEXT: sbcs xzr, x3, x8
-; NOOUTLINE-NEXT: csel x10, x8, x3, hs
-; NOOUTLINE-NEXT: csel x11, x9, x2, hs
+; NOOUTLINE-NEXT: cmp x9, x2
+; NOOUTLINE-NEXT: sbcs xzr, x8, x3
+; NOOUTLINE-NEXT: csel x10, x8, x3, lo
+; NOOUTLINE-NEXT: csel x11, x9, x2, lo
; NOOUTLINE-NEXT: stlxp w12, x11, x10, [x0]
; NOOUTLINE-NEXT: cbnz w12, .LBB10_1
; NOOUTLINE-NEXT: // %bb.2: // %atomicrmw.end
@@ -588,10 +588,10 @@ define void @fetch_and_umin(ptr %p, i128 %bits) {
; OUTLINE-NEXT: .LBB10_1: // %atomicrmw.start
; OUTLINE-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-NEXT: ldaxp x9, x8, [x0]
-; OUTLINE-NEXT: cmp x2, x9
-; OUTLINE-NEXT: sbcs xzr, x3, x8
-; OUTLINE-NEXT: csel x10, x8, x3, hs
-; OUTLINE-NEXT: csel x11, x9, x2, hs
+; OUTLINE-NEXT: cmp x9, x2
+; OUTLINE-NEXT: sbcs xzr, x8, x3
+; OUTLINE-NEXT: csel x10, x8, x3, lo
+; OUTLINE-NEXT: csel x11, x9, x2, lo
; OUTLINE-NEXT: stlxp w12, x11, x10, [x0]
; OUTLINE-NEXT: cbnz w12, .LBB10_1
; OUTLINE-NEXT: // %bb.2: // %atomicrmw.end
@@ -607,10 +607,10 @@ define void @fetch_and_umin(ptr %p, i128 %bits) {
; LSE-NEXT: // =>This Inner Loop Header: Depth=1
; LSE-NEXT: mov x7, x5
; LSE-NEXT: mov x6, x4
-; LSE-NEXT: cmp x2, x4
-; LSE-NEXT: sbcs xzr, x3, x7
-; LSE-NEXT: csel x9, x7, x3, hs
-; LSE-NEXT: csel x8, x4, x2, hs
+; LSE-NEXT: cmp x4, x2
+; LSE-NEXT: sbcs xzr, x7, x3
+; LSE-NEXT: csel x9, x7, x3, lo
+; LSE-NEXT: csel x8, x4, x2, lo
; LSE-NEXT: mov x4, x6
; LSE-NEXT: mov x5, x7
; LSE-NEXT: caspal x4, x5, x8, x9, [x0]
@@ -714,8 +714,8 @@ define i128 @atomic_load_seq_cst(ptr %p) {
;
; LSE-LABEL: atomic_load_seq_cst:
; LSE: // %bb.0:
-; LSE-NEXT: mov x2, #0
-; LSE-NEXT: mov x3, #0
+; LSE-NEXT: mov x2, #0 // =0x0
+; LSE-NEXT: mov x3, #0 // =0x0
; LSE-NEXT: caspal x2, x3, x2, x3, [x0]
; LSE-NEXT: mov x0, x2
; LSE-NEXT: mov x1, x3
@@ -747,8 +747,8 @@ define i128 @atomic_load_relaxed(i64, i64, ptr %p) {
;
; LSE-LABEL: atomic_load_relaxed:
; LSE: // %bb.0:
-; LSE-NEXT: mov x0, #0
-; LSE-NEXT: mov x1, #0
+; LSE-NEXT: mov x0, #0 // =0x0
+; LSE-NEXT: mov x1, #0 // =0x0
; LSE-NEXT: casp x0, x1, x0, x1, [x2]
; LSE-NEXT: ret
%r = load atomic i128, ptr %p monotonic, align 16
diff --git a/llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll b/llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll
index 4e3fac3650e98..f96ea0d2ed879 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fmax-safe.ll
@@ -64,8 +64,7 @@ define float @test_cross_fail(float %lhs, float %rhs) {
define i64 @test_integer(i64 %in) {
; CHECK-LABEL: test_integer:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp x0, #0
-; CHECK-NEXT: csel x0, xzr, x0, mi
+; CHECK-NEXT: bic x0, x0, x0, asr #63
; CHECK-NEXT: ret
%cmp = icmp slt i64 %in, 0
%val = select i1 %cmp, i64 0, i64 %in
diff --git a/llvm/test/CodeGen/AArch64/arm64-fmax.ll b/llvm/test/CodeGen/AArch64/arm64-fmax.ll
index f311139e193a5..ab1b978c363f7 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fmax.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fmax.ll
@@ -59,8 +59,7 @@ define float @test_cross_fail(float %lhs, float %rhs) {
define i64 @test_integer(i64 %in) {
; CHECK-LABEL: test_integer:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp x0, #0
-; CHECK-NEXT: csel x0, xzr, x0, mi
+; CHECK-NEXT: bic x0, x0, x0, asr #63
; CHECK-NEXT: ret
%cmp = icmp slt i64 %in, 0
%val = select i1 %cmp, i64 0, i64 %in
diff --git a/llvm/test/CodeGen/AArch64/atomic-ops-lse.ll b/llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
index ac64495138175..fd7a7bf649590 100644
--- a/llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
+++ b/llvm/test/CodeGen/AArch64/atomic-ops-lse.ll
@@ -603,34 +603,34 @@ define dso_local i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE-ATOMICS-NEXT: .LBB18_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB18_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var8
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB18_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB18_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: dmb ish
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw min ptr @var8, i8 %offset seq_cst
@@ -649,34 +649,34 @@ define dso_local i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxth w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE-ATOMICS-NEXT: .LBB19_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB19_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var16
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB19_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB19_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: dmb ish
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw min ptr @var16, i16 %offset seq_cst
@@ -701,7 +701,7 @@ define dso_local i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, le
+; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB20_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -716,7 +716,7 @@ define dso_local i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB20_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -745,7 +745,7 @@ define dso_local i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, le
+; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB21_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -761,7 +761,7 @@ define dso_local i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x0, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x0, x8
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x0, x8, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x0, x8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB21_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -789,7 +789,7 @@ define dso_local void @test_atomic_load_min_i32_noret(i32 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, le
+; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB22_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -803,7 +803,7 @@ define dso_local void @test_atomic_load_min_i32_noret(i32 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB22_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -830,7 +830,7 @@ define dso_local void @test_atomic_load_min_i64_noret(i64 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, le
+; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB23_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -844,7 +844,7 @@ define dso_local void @test_atomic_load_min_i64_noret(i64 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB23_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -872,7 +872,7 @@ define dso_local i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB24_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -888,7 +888,7 @@ define dso_local i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB24_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -918,7 +918,7 @@ define dso_local i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB25_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -934,7 +934,7 @@ define dso_local i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB25_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -963,7 +963,7 @@ define dso_local i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB26_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -978,7 +978,7 @@ define dso_local i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB26_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1007,7 +1007,7 @@ define dso_local i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, ls
+; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB27_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1023,7 +1023,7 @@ define dso_local i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x0, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x0, x8
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x0, x8, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x0, x8, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB27_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1051,7 +1051,7 @@ define dso_local void @test_atomic_load_umin_i32_noret(i32 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, ls
+; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB28_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1065,7 +1065,7 @@ define dso_local void @test_atomic_load_umin_i32_noret(i32 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB28_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1092,7 +1092,7 @@ define dso_local void @test_atomic_load_umin_i64_noret(i64 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, ls
+; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB29_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1106,7 +1106,7 @@ define dso_local void @test_atomic_load_umin_i64_noret(i64 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB29_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1127,34 +1127,34 @@ define dso_local i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE-ATOMICS-NEXT: .LBB30_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB30_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var8
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB30_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB30_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: dmb ish
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw max ptr @var8, i8 %offset seq_cst
@@ -1173,34 +1173,34 @@ define dso_local i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxth w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE-ATOMICS-NEXT: .LBB31_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB31_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var16
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB31_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB31_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: dmb ish
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw max ptr @var16, i16 %offset seq_cst
@@ -5642,34 +5642,34 @@ define dso_local i8 @test_atomic_load_max_i8_acq_rel(i8 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_acq_rel:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE-ATOMICS-NEXT: .LBB163_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB163_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_acq_rel:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var8
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB163_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB163_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw max ptr @var8, i8 %offset acq_rel
@@ -5687,34 +5687,34 @@ define dso_local i16 @test_atomic_load_max_i16_acq_rel(i16 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_acq_rel:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxth w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE-ATOMICS-NEXT: .LBB164_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB164_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_acq_rel:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var16
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB164_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB164_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw max ptr @var16, i16 %offset acq_rel
@@ -5898,34 +5898,34 @@ define dso_local i8 @test_atomic_load_max_i8_acquire(i8 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_acquire:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE-ATOMICS-NEXT: .LBB169_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB169_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_acquire:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var8
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB169_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC-OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB169_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw max ptr @var8, i8 %offset acquire
@@ -5943,34 +5943,34 @@ define dso_local i16 @test_atomic_load_max_i16_acquire(i16 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_acquire:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxth w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE-ATOMICS-NEXT: .LBB170_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB170_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_acquire:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var16
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB170_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC-OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB170_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw max ptr @var16, i16 %offset acquire
@@ -6154,34 +6154,34 @@ define dso_local i8 @test_atomic_load_max_i8_monotonic(i8 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_monotonic:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE-ATOMICS-NEXT: .LBB175_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrb w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB175_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_monotonic:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var8
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB175_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxrb w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC-OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB175_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw max ptr @var8, i8 %offset monotonic
@@ -6199,34 +6199,34 @@ define dso_local i16 @test_atomic_load_max_i16_monotonic(i16 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_monotonic:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxth w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE-ATOMICS-NEXT: .LBB176_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrh w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB176_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_monotonic:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var16
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB176_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxrh w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC-OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB176_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw max ptr @var16, i16 %offset monotonic
@@ -6410,34 +6410,34 @@ define dso_local i8 @test_atomic_load_max_i8_release(i8 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_release:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE-ATOMICS-NEXT: .LBB181_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrb w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB181_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_release:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var8
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB181_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxrb w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB181_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw max ptr @var8, i8 %offset release
@@ -6455,34 +6455,34 @@ define dso_local i16 @test_atomic_load_max_i16_release(i16 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_release:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxth w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE-ATOMICS-NEXT: .LBB182_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrh w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB182_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_release:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var16
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB182_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxrh w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB182_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw max ptr @var16, i16 %offset release
@@ -6666,34 +6666,34 @@ define dso_local i8 @test_atomic_load_max_i8_seq_cst(i8 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_seq_cst:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE-ATOMICS-NEXT: .LBB187_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB187_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_seq_cst:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var8
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB187_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB187_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: dmb ish
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw max ptr @var8, i8 %offset seq_cst
@@ -6712,34 +6712,34 @@ define dso_local i16 @test_atomic_load_max_i16_seq_cst(i16 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_seq_cst:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxth w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE-ATOMICS-NEXT: .LBB188_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB188_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_seq_cst:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var16
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB188_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB188_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: dmb ish
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw max ptr @var16, i16 %offset seq_cst
@@ -6928,34 +6928,34 @@ define dso_local i8 @test_atomic_load_min_i8_acq_rel(i8 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_acq_rel:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE-ATOMICS-NEXT: .LBB193_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB193_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_acq_rel:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var8
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB193_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB193_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw min ptr @var8, i8 %offset acq_rel
@@ -6973,34 +6973,34 @@ define dso_local i16 @test_atomic_load_min_i16_acq_rel(i16 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_acq_rel:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxth w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE-ATOMICS-NEXT: .LBB194_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB194_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_acq_rel:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var16
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB194_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB194_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw min ptr @var16, i16 %offset acq_rel
@@ -7024,7 +7024,7 @@ define dso_local i32 @test_atomic_load_min_i32_acq_rel(i32 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, le
+; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB195_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7039,7 +7039,7 @@ define dso_local i32 @test_atomic_load_min_i32_acq_rel(i32 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB195_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7067,7 +7067,7 @@ define dso_local i64 @test_atomic_load_min_i64_acq_rel(i64 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, le
+; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB196_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7082,7 +7082,7 @@ define dso_local i64 @test_atomic_load_min_i64_acq_rel(i64 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB196_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7110,7 +7110,7 @@ define dso_local void @test_atomic_load_min_i32_noret_acq_rel(i32 %offset) nounw
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, le
+; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB197_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7124,7 +7124,7 @@ define dso_local void @test_atomic_load_min_i32_noret_acq_rel(i32 %offset) nounw
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB197_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7150,7 +7150,7 @@ define dso_local void @test_atomic_load_min_i64_noret_acq_rel(i64 %offset) nounw
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, le
+; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB198_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7164,7 +7164,7 @@ define dso_local void @test_atomic_load_min_i64_noret_acq_rel(i64 %offset) nounw
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB198_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7184,34 +7184,34 @@ define dso_local i8 @test_atomic_load_min_i8_acquire(i8 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_acquire:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE-ATOMICS-NEXT: .LBB199_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB199_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_acquire:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var8
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB199_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB199_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw min ptr @var8, i8 %offset acquire
@@ -7229,34 +7229,34 @@ define dso_local i16 @test_atomic_load_min_i16_acquire(i16 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_acquire:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxth w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE-ATOMICS-NEXT: .LBB200_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB200_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_acquire:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var16
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB200_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB200_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw min ptr @var16, i16 %offset acquire
@@ -7280,7 +7280,7 @@ define dso_local i32 @test_atomic_load_min_i32_acquire(i32 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, le
+; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lt
; OUTLINE-ATOMICS-NEXT: stxr w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB201_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7295,7 +7295,7 @@ define dso_local i32 @test_atomic_load_min_i32_acquire(i32 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB201_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7323,7 +7323,7 @@ define dso_local i64 @test_atomic_load_min_i64_acquire(i64 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, le
+; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lt
; OUTLINE-ATOMICS-NEXT: stxr w11, x10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB202_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7338,7 +7338,7 @@ define dso_local i64 @test_atomic_load_min_i64_acquire(i64 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w11, x10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB202_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7366,7 +7366,7 @@ define dso_local void @test_atomic_load_min_i32_noret_acquire(i32 %offset) nounw
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, le
+; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lt
; OUTLINE-ATOMICS-NEXT: stxr w10, w9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB203_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7380,7 +7380,7 @@ define dso_local void @test_atomic_load_min_i32_noret_acquire(i32 %offset) nounw
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w10, w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB203_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7406,7 +7406,7 @@ define dso_local void @test_atomic_load_min_i64_noret_acquire(i64 %offset) nounw
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, le
+; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lt
; OUTLINE-ATOMICS-NEXT: stxr w10, x9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB204_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7420,7 +7420,7 @@ define dso_local void @test_atomic_load_min_i64_noret_acquire(i64 %offset) nounw
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w10, x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB204_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7440,34 +7440,34 @@ define dso_local i8 @test_atomic_load_min_i8_monotonic(i8 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_monotonic:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE-ATOMICS-NEXT: .LBB205_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrb w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB205_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_monotonic:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var8
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB205_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxrb w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB205_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw min ptr @var8, i8 %offset monotonic
@@ -7485,34 +7485,34 @@ define dso_local i16 @test_atomic_load_min_i16_monotonic(i16 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_monotonic:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxth w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE-ATOMICS-NEXT: .LBB206_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrh w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB206_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_monotonic:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var16
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB206_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxrh w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB206_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw min ptr @var16, i16 %offset monotonic
@@ -7536,7 +7536,7 @@ define dso_local i32 @test_atomic_load_min_i32_monotonic(i32 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr w8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, le
+; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lt
; OUTLINE-ATOMICS-NEXT: stxr w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB207_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7551,7 +7551,7 @@ define dso_local i32 @test_atomic_load_min_i32_monotonic(i32 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr w8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB207_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7579,7 +7579,7 @@ define dso_local i64 @test_atomic_load_min_i64_monotonic(i64 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr x8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, le
+; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lt
; OUTLINE-ATOMICS-NEXT: stxr w11, x10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB208_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7594,7 +7594,7 @@ define dso_local i64 @test_atomic_load_min_i64_monotonic(i64 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr x8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w11, x10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB208_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7622,7 +7622,7 @@ define dso_local void @test_atomic_load_min_i32_noret_monotonic(i32 %offset) nou
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr w9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, le
+; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lt
; OUTLINE-ATOMICS-NEXT: stxr w10, w9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB209_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7636,7 +7636,7 @@ define dso_local void @test_atomic_load_min_i32_noret_monotonic(i32 %offset) nou
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w10, w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB209_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7662,7 +7662,7 @@ define dso_local void @test_atomic_load_min_i64_noret_monotonic(i64 %offset) nou
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr x9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, le
+; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lt
; OUTLINE-ATOMICS-NEXT: stxr w10, x9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB210_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7676,7 +7676,7 @@ define dso_local void @test_atomic_load_min_i64_noret_monotonic(i64 %offset) nou
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w10, x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB210_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7696,34 +7696,34 @@ define dso_local i8 @test_atomic_load_min_i8_release(i8 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_release:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE-ATOMICS-NEXT: .LBB211_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrb w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB211_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_release:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var8
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB211_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxrb w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB211_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw min ptr @var8, i8 %offset release
@@ -7741,34 +7741,34 @@ define dso_local i16 @test_atomic_load_min_i16_release(i16 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_release:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxth w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE-ATOMICS-NEXT: .LBB212_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrh w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB212_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_release:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var16
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB212_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxrh w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB212_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw min ptr @var16, i16 %offset release
@@ -7792,7 +7792,7 @@ define dso_local i32 @test_atomic_load_min_i32_release(i32 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr w8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, le
+; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB213_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7807,7 +7807,7 @@ define dso_local i32 @test_atomic_load_min_i32_release(i32 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr w8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB213_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7835,7 +7835,7 @@ define dso_local i64 @test_atomic_load_min_i64_release(i64 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr x8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, le
+; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB214_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7850,7 +7850,7 @@ define dso_local i64 @test_atomic_load_min_i64_release(i64 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr x8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB214_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7878,7 +7878,7 @@ define dso_local void @test_atomic_load_min_i32_noret_release(i32 %offset) nounw
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr w9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, le
+; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB215_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7892,7 +7892,7 @@ define dso_local void @test_atomic_load_min_i32_noret_release(i32 %offset) nounw
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB215_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7918,7 +7918,7 @@ define dso_local void @test_atomic_load_min_i64_noret_release(i64 %offset) nounw
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr x9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, le
+; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB216_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7932,7 +7932,7 @@ define dso_local void @test_atomic_load_min_i64_noret_release(i64 %offset) nounw
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB216_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -7952,34 +7952,34 @@ define dso_local i8 @test_atomic_load_min_i8_seq_cst(i8 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_seq_cst:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var8
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE-ATOMICS-NEXT: .LBB217_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB217_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_seq_cst:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var8
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB217_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrb w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: sxtb w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB217_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: dmb ish
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw min ptr @var8, i8 %offset seq_cst
@@ -7998,34 +7998,34 @@ define dso_local i16 @test_atomic_load_min_i16_seq_cst(i16 %offset) nounwind {
;
; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_seq_cst:
; OUTLINE-ATOMICS: // %bb.0:
+; OUTLINE-ATOMICS-NEXT: sxth w8, w0
; OUTLINE-ATOMICS-NEXT: adrp x9, var16
; OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE-ATOMICS-NEXT: .LBB218_1: // %atomicrmw.start
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB218_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE-ATOMICS-NEXT: mov w0, w8
; OUTLINE-ATOMICS-NEXT: ret
;
; MSVC-OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_seq_cst:
; MSVC-OUTLINE-ATOMICS: // %bb.0:
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w0
; MSVC-OUTLINE-ATOMICS-NEXT: adrp x9, var16
; MSVC-OUTLINE-ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC-OUTLINE-ATOMICS-NEXT: .LBB218_1: // %atomicrmw.start
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrh w10, [x9]
-; MSVC-OUTLINE-ATOMICS-NEXT: sxth w8, w10
-; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: sxth w0, w10
+; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w8
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB218_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC-OUTLINE-ATOMICS-NEXT: mov w0, w8
; MSVC-OUTLINE-ATOMICS-NEXT: dmb ish
; MSVC-OUTLINE-ATOMICS-NEXT: ret
%old = atomicrmw min ptr @var16, i16 %offset seq_cst
@@ -8050,7 +8050,7 @@ define dso_local i32 @test_atomic_load_min_i32_seq_cst(i32 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, le
+; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB219_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -8065,7 +8065,7 @@ define dso_local i32 @test_atomic_load_min_i32_seq_cst(i32 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB219_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -8094,7 +8094,7 @@ define dso_local i64 @test_atomic_load_min_i64_seq_cst(i64 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, le
+; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB220_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -8110,7 +8110,7 @@ define dso_local i64 @test_atomic_load_min_i64_seq_cst(i64 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x0, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x0, x8
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x0, x8, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x0, x8, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB220_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -8138,7 +8138,7 @@ define dso_local void @test_atomic_load_min_i32_noret_seq_cst(i32 %offset) nounw
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, le
+; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB221_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -8152,7 +8152,7 @@ define dso_local void @test_atomic_load_min_i32_noret_seq_cst(i32 %offset) nounw
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB221_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -8179,7 +8179,7 @@ define dso_local void @test_atomic_load_min_i64_noret_seq_cst(i64 %offset) nounw
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, le
+; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lt
; OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB222_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -8193,7 +8193,7 @@ define dso_local void @test_atomic_load_min_i64_noret_seq_cst(i64 %offset) nounw
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, le
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lt
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB222_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12395,7 +12395,7 @@ define dso_local i8 @test_atomic_load_umin_i8_acq_rel(i8 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB343_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12411,7 +12411,7 @@ define dso_local i8 @test_atomic_load_umin_i8_acq_rel(i8 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB343_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12440,7 +12440,7 @@ define dso_local i16 @test_atomic_load_umin_i16_acq_rel(i16 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB344_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12456,7 +12456,7 @@ define dso_local i16 @test_atomic_load_umin_i16_acq_rel(i16 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB344_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12484,7 +12484,7 @@ define dso_local i32 @test_atomic_load_umin_i32_acq_rel(i32 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB345_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12499,7 +12499,7 @@ define dso_local i32 @test_atomic_load_umin_i32_acq_rel(i32 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB345_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12527,7 +12527,7 @@ define dso_local i64 @test_atomic_load_umin_i64_acq_rel(i64 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, ls
+; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB346_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12542,7 +12542,7 @@ define dso_local i64 @test_atomic_load_umin_i64_acq_rel(i64 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB346_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12570,7 +12570,7 @@ define dso_local void @test_atomic_load_umin_i32_noret_acq_rel(i32 %offset) noun
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, ls
+; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB347_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12584,7 +12584,7 @@ define dso_local void @test_atomic_load_umin_i32_noret_acq_rel(i32 %offset) noun
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB347_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12610,7 +12610,7 @@ define dso_local void @test_atomic_load_umin_i64_noret_acq_rel(i64 %offset) noun
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, ls
+; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB348_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12624,7 +12624,7 @@ define dso_local void @test_atomic_load_umin_i64_noret_acq_rel(i64 %offset) noun
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB348_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12651,7 +12651,7 @@ define dso_local i8 @test_atomic_load_umin_i8_acquire(i8 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB349_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12667,7 +12667,7 @@ define dso_local i8 @test_atomic_load_umin_i8_acquire(i8 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB349_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12696,7 +12696,7 @@ define dso_local i16 @test_atomic_load_umin_i16_acquire(i16 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB350_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12712,7 +12712,7 @@ define dso_local i16 @test_atomic_load_umin_i16_acquire(i16 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB350_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12740,7 +12740,7 @@ define dso_local i32 @test_atomic_load_umin_i32_acquire(i32 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lo
; OUTLINE-ATOMICS-NEXT: stxr w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB351_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12755,7 +12755,7 @@ define dso_local i32 @test_atomic_load_umin_i32_acquire(i32 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB351_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12783,7 +12783,7 @@ define dso_local i64 @test_atomic_load_umin_i64_acquire(i64 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, ls
+; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lo
; OUTLINE-ATOMICS-NEXT: stxr w11, x10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB352_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12798,7 +12798,7 @@ define dso_local i64 @test_atomic_load_umin_i64_acquire(i64 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w11, x10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB352_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12826,7 +12826,7 @@ define dso_local void @test_atomic_load_umin_i32_noret_acquire(i32 %offset) noun
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, ls
+; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lo
; OUTLINE-ATOMICS-NEXT: stxr w10, w9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB353_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12840,7 +12840,7 @@ define dso_local void @test_atomic_load_umin_i32_noret_acquire(i32 %offset) noun
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w10, w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB353_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12866,7 +12866,7 @@ define dso_local void @test_atomic_load_umin_i64_noret_acquire(i64 %offset) noun
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, ls
+; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lo
; OUTLINE-ATOMICS-NEXT: stxr w10, x9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB354_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12880,7 +12880,7 @@ define dso_local void @test_atomic_load_umin_i64_noret_acquire(i64 %offset) noun
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w10, x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB354_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12907,7 +12907,7 @@ define dso_local i8 @test_atomic_load_umin_i8_monotonic(i8 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB355_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12923,7 +12923,7 @@ define dso_local i8 @test_atomic_load_umin_i8_monotonic(i8 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxrb w0, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stxrb w11, w10, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB355_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12952,7 +12952,7 @@ define dso_local i16 @test_atomic_load_umin_i16_monotonic(i16 %offset) nounwind
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB356_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12968,7 +12968,7 @@ define dso_local i16 @test_atomic_load_umin_i16_monotonic(i16 %offset) nounwind
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxrh w0, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stxrh w11, w10, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB356_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -12996,7 +12996,7 @@ define dso_local i32 @test_atomic_load_umin_i32_monotonic(i32 %offset) nounwind
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr w8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lo
; OUTLINE-ATOMICS-NEXT: stxr w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB357_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13011,7 +13011,7 @@ define dso_local i32 @test_atomic_load_umin_i32_monotonic(i32 %offset) nounwind
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr w8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB357_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13039,7 +13039,7 @@ define dso_local i64 @test_atomic_load_umin_i64_monotonic(i64 %offset) nounwind
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr x8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, ls
+; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lo
; OUTLINE-ATOMICS-NEXT: stxr w11, x10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB358_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13054,7 +13054,7 @@ define dso_local i64 @test_atomic_load_umin_i64_monotonic(i64 %offset) nounwind
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr x8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w11, x10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB358_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13082,7 +13082,7 @@ define dso_local void @test_atomic_load_umin_i32_noret_monotonic(i32 %offset) no
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr w9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, ls
+; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lo
; OUTLINE-ATOMICS-NEXT: stxr w10, w9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB359_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13096,7 +13096,7 @@ define dso_local void @test_atomic_load_umin_i32_noret_monotonic(i32 %offset) no
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w10, w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB359_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13122,7 +13122,7 @@ define dso_local void @test_atomic_load_umin_i64_noret_monotonic(i64 %offset) no
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr x9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, ls
+; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lo
; OUTLINE-ATOMICS-NEXT: stxr w10, x9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB360_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13136,7 +13136,7 @@ define dso_local void @test_atomic_load_umin_i64_noret_monotonic(i64 %offset) no
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stxr w10, x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB360_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13163,7 +13163,7 @@ define dso_local i8 @test_atomic_load_umin_i8_release(i8 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB361_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13179,7 +13179,7 @@ define dso_local i8 @test_atomic_load_umin_i8_release(i8 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxrb w0, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB361_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13208,7 +13208,7 @@ define dso_local i16 @test_atomic_load_umin_i16_release(i16 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB362_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13224,7 +13224,7 @@ define dso_local i16 @test_atomic_load_umin_i16_release(i16 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxrh w0, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB362_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13252,7 +13252,7 @@ define dso_local i32 @test_atomic_load_umin_i32_release(i32 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr w8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB363_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13267,7 +13267,7 @@ define dso_local i32 @test_atomic_load_umin_i32_release(i32 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr w8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB363_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13295,7 +13295,7 @@ define dso_local i64 @test_atomic_load_umin_i64_release(i64 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr x8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, ls
+; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB364_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13310,7 +13310,7 @@ define dso_local i64 @test_atomic_load_umin_i64_release(i64 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr x8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB364_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13338,7 +13338,7 @@ define dso_local void @test_atomic_load_umin_i32_noret_release(i32 %offset) noun
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr w9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, ls
+; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB365_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13352,7 +13352,7 @@ define dso_local void @test_atomic_load_umin_i32_noret_release(i32 %offset) noun
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB365_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13378,7 +13378,7 @@ define dso_local void @test_atomic_load_umin_i64_noret_release(i64 %offset) noun
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldxr x9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, ls
+; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB366_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13392,7 +13392,7 @@ define dso_local void @test_atomic_load_umin_i64_noret_release(i64 %offset) noun
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldxr x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB366_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13419,7 +13419,7 @@ define dso_local i8 @test_atomic_load_umin_i8_seq_cst(i8 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB367_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13435,7 +13435,7 @@ define dso_local i8 @test_atomic_load_umin_i8_seq_cst(i8 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrb w0, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrb w11, w10, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB367_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13465,7 +13465,7 @@ define dso_local i16 @test_atomic_load_umin_i16_seq_cst(i16 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB368_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13481,7 +13481,7 @@ define dso_local i16 @test_atomic_load_umin_i16_seq_cst(i16 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxrh w0, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w0, w9
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxrh w11, w10, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB368_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13510,7 +13510,7 @@ define dso_local i32 @test_atomic_load_umin_i32_seq_cst(i32 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB369_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13525,7 +13525,7 @@ define dso_local i32 @test_atomic_load_umin_i32_seq_cst(i32 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w8, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w8, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w10, w8, w0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, w10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB369_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13554,7 +13554,7 @@ define dso_local i64 @test_atomic_load_umin_i64_seq_cst(i64 %offset) nounwind {
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x8, [x9]
; OUTLINE-ATOMICS-NEXT: cmp x8, x0
-; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, ls
+; OUTLINE-ATOMICS-NEXT: csel x10, x8, x0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB370_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13570,7 +13570,7 @@ define dso_local i64 @test_atomic_load_umin_i64_seq_cst(i64 %offset) nounwind {
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x0, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x0, x8
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x0, x8, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x10, x0, x8, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w11, x10, [x9]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w11, .LBB370_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13598,7 +13598,7 @@ define dso_local void @test_atomic_load_umin_i32_noret_seq_cst(i32 %offset) noun
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, ls
+; OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB371_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13612,7 +13612,7 @@ define dso_local void @test_atomic_load_umin_i32_noret_seq_cst(i32 %offset) noun
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp w9, w0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel w9, w9, w0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, w9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB371_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13639,7 +13639,7 @@ define dso_local void @test_atomic_load_umin_i64_noret_seq_cst(i64 %offset) noun
; OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, ls
+; OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lo
; OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB372_1
; OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -13653,7 +13653,7 @@ define dso_local void @test_atomic_load_umin_i64_noret_seq_cst(i64 %offset) noun
; MSVC-OUTLINE-ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC-OUTLINE-ATOMICS-NEXT: ldaxr x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cmp x9, x0
-; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, ls
+; MSVC-OUTLINE-ATOMICS-NEXT: csel x9, x9, x0, lo
; MSVC-OUTLINE-ATOMICS-NEXT: stlxr w10, x9, [x8]
; MSVC-OUTLINE-ATOMICS-NEXT: cbnz w10, .LBB372_1
; MSVC-OUTLINE-ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
diff --git a/llvm/test/CodeGen/AArch64/atomic-ops.ll b/llvm/test/CodeGen/AArch64/atomic-ops.ll
index 5adda9aaaaf90..d190b18d2db1c 100644
--- a/llvm/test/CodeGen/AArch64/atomic-ops.ll
+++ b/llvm/test/CodeGen/AArch64/atomic-ops.ll
@@ -1413,66 +1413,66 @@ define dso_local i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
define dso_local i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
; INLINE_ATOMICS-LABEL: test_atomic_load_min_i8:
; INLINE_ATOMICS: // %bb.0:
+; INLINE_ATOMICS-NEXT: sxtb w8, w0
; INLINE_ATOMICS-NEXT: adrp x9, var8
; INLINE_ATOMICS-NEXT: add x9, x9, :lo12:var8
; INLINE_ATOMICS-NEXT: .LBB24_1: // %atomicrmw.start
; INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; INLINE_ATOMICS-NEXT: ldaxrb w10, [x9]
-; INLINE_ATOMICS-NEXT: sxtb w8, w10
-; INLINE_ATOMICS-NEXT: cmp w8, w0, sxtb
-; INLINE_ATOMICS-NEXT: csel w10, w10, w0, le
+; INLINE_ATOMICS-NEXT: sxtb w0, w10
+; INLINE_ATOMICS-NEXT: cmp w0, w8
+; INLINE_ATOMICS-NEXT: csel w10, w0, w8, lt
; INLINE_ATOMICS-NEXT: stxrb w11, w10, [x9]
; INLINE_ATOMICS-NEXT: cbnz w11, .LBB24_1
; INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; INLINE_ATOMICS-NEXT: mov w0, w8
; INLINE_ATOMICS-NEXT: ret
;
; MSVC_INLINE_ATOMICS-LABEL: test_atomic_load_min_i8:
; MSVC_INLINE_ATOMICS: // %bb.0:
+; MSVC_INLINE_ATOMICS-NEXT: sxtb w8, w0
; MSVC_INLINE_ATOMICS-NEXT: adrp x9, var8
; MSVC_INLINE_ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC_INLINE_ATOMICS-NEXT: .LBB24_1: // %atomicrmw.start
; MSVC_INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_INLINE_ATOMICS-NEXT: ldaxrb w10, [x9]
-; MSVC_INLINE_ATOMICS-NEXT: sxtb w8, w10
-; MSVC_INLINE_ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC_INLINE_ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC_INLINE_ATOMICS-NEXT: sxtb w0, w10
+; MSVC_INLINE_ATOMICS-NEXT: cmp w0, w8
+; MSVC_INLINE_ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC_INLINE_ATOMICS-NEXT: stxrb w11, w10, [x9]
; MSVC_INLINE_ATOMICS-NEXT: cbnz w11, .LBB24_1
; MSVC_INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC_INLINE_ATOMICS-NEXT: mov w0, w8
; MSVC_INLINE_ATOMICS-NEXT: ret
;
; OUTLINE_ATOMICS-LABEL: test_atomic_load_min_i8:
; OUTLINE_ATOMICS: // %bb.0:
+; OUTLINE_ATOMICS-NEXT: sxtb w8, w0
; OUTLINE_ATOMICS-NEXT: adrp x9, var8
; OUTLINE_ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE_ATOMICS-NEXT: .LBB24_1: // %atomicrmw.start
; OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE_ATOMICS-NEXT: ldaxrb w10, [x9]
-; OUTLINE_ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE_ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE_ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE_ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE_ATOMICS-NEXT: cmp w0, w8
+; OUTLINE_ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE_ATOMICS-NEXT: stxrb w11, w10, [x9]
; OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB24_1
; OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE_ATOMICS-NEXT: mov w0, w8
; OUTLINE_ATOMICS-NEXT: ret
;
; MSVC_OUTLINE_ATOMICS-LABEL: test_atomic_load_min_i8:
; MSVC_OUTLINE_ATOMICS: // %bb.0:
+; MSVC_OUTLINE_ATOMICS-NEXT: sxtb w8, w0
; MSVC_OUTLINE_ATOMICS-NEXT: adrp x9, var8
; MSVC_OUTLINE_ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC_OUTLINE_ATOMICS-NEXT: .LBB24_1: // %atomicrmw.start
; MSVC_OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_OUTLINE_ATOMICS-NEXT: ldaxrb w10, [x9]
-; MSVC_OUTLINE_ATOMICS-NEXT: sxtb w8, w10
-; MSVC_OUTLINE_ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC_OUTLINE_ATOMICS-NEXT: sxtb w0, w10
+; MSVC_OUTLINE_ATOMICS-NEXT: cmp w0, w8
+; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC_OUTLINE_ATOMICS-NEXT: stxrb w11, w10, [x9]
; MSVC_OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB24_1
; MSVC_OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC_OUTLINE_ATOMICS-NEXT: mov w0, w8
; MSVC_OUTLINE_ATOMICS-NEXT: ret
;
; LSE-LABEL: test_atomic_load_min_i8:
@@ -1488,66 +1488,66 @@ define dso_local i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
define dso_local i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
; INLINE_ATOMICS-LABEL: test_atomic_load_min_i16:
; INLINE_ATOMICS: // %bb.0:
+; INLINE_ATOMICS-NEXT: sxth w8, w0
; INLINE_ATOMICS-NEXT: adrp x9, var16
; INLINE_ATOMICS-NEXT: add x9, x9, :lo12:var16
; INLINE_ATOMICS-NEXT: .LBB25_1: // %atomicrmw.start
; INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; INLINE_ATOMICS-NEXT: ldxrh w10, [x9]
-; INLINE_ATOMICS-NEXT: sxth w8, w10
-; INLINE_ATOMICS-NEXT: cmp w8, w0, sxth
-; INLINE_ATOMICS-NEXT: csel w10, w10, w0, le
+; INLINE_ATOMICS-NEXT: sxth w0, w10
+; INLINE_ATOMICS-NEXT: cmp w0, w8
+; INLINE_ATOMICS-NEXT: csel w10, w0, w8, lt
; INLINE_ATOMICS-NEXT: stlxrh w11, w10, [x9]
; INLINE_ATOMICS-NEXT: cbnz w11, .LBB25_1
; INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; INLINE_ATOMICS-NEXT: mov w0, w8
; INLINE_ATOMICS-NEXT: ret
;
; MSVC_INLINE_ATOMICS-LABEL: test_atomic_load_min_i16:
; MSVC_INLINE_ATOMICS: // %bb.0:
+; MSVC_INLINE_ATOMICS-NEXT: sxth w8, w0
; MSVC_INLINE_ATOMICS-NEXT: adrp x9, var16
; MSVC_INLINE_ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC_INLINE_ATOMICS-NEXT: .LBB25_1: // %atomicrmw.start
; MSVC_INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_INLINE_ATOMICS-NEXT: ldxrh w10, [x9]
-; MSVC_INLINE_ATOMICS-NEXT: sxth w8, w10
-; MSVC_INLINE_ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC_INLINE_ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC_INLINE_ATOMICS-NEXT: sxth w0, w10
+; MSVC_INLINE_ATOMICS-NEXT: cmp w0, w8
+; MSVC_INLINE_ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC_INLINE_ATOMICS-NEXT: stlxrh w11, w10, [x9]
; MSVC_INLINE_ATOMICS-NEXT: cbnz w11, .LBB25_1
; MSVC_INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC_INLINE_ATOMICS-NEXT: mov w0, w8
; MSVC_INLINE_ATOMICS-NEXT: ret
;
; OUTLINE_ATOMICS-LABEL: test_atomic_load_min_i16:
; OUTLINE_ATOMICS: // %bb.0:
+; OUTLINE_ATOMICS-NEXT: sxth w8, w0
; OUTLINE_ATOMICS-NEXT: adrp x9, var16
; OUTLINE_ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE_ATOMICS-NEXT: .LBB25_1: // %atomicrmw.start
; OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE_ATOMICS-NEXT: ldxrh w10, [x9]
-; OUTLINE_ATOMICS-NEXT: sxth w8, w10
-; OUTLINE_ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE_ATOMICS-NEXT: csel w10, w10, w0, le
+; OUTLINE_ATOMICS-NEXT: sxth w0, w10
+; OUTLINE_ATOMICS-NEXT: cmp w0, w8
+; OUTLINE_ATOMICS-NEXT: csel w10, w0, w8, lt
; OUTLINE_ATOMICS-NEXT: stlxrh w11, w10, [x9]
; OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB25_1
; OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE_ATOMICS-NEXT: mov w0, w8
; OUTLINE_ATOMICS-NEXT: ret
;
; MSVC_OUTLINE_ATOMICS-LABEL: test_atomic_load_min_i16:
; MSVC_OUTLINE_ATOMICS: // %bb.0:
+; MSVC_OUTLINE_ATOMICS-NEXT: sxth w8, w0
; MSVC_OUTLINE_ATOMICS-NEXT: adrp x9, var16
; MSVC_OUTLINE_ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC_OUTLINE_ATOMICS-NEXT: .LBB25_1: // %atomicrmw.start
; MSVC_OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_OUTLINE_ATOMICS-NEXT: ldxrh w10, [x9]
-; MSVC_OUTLINE_ATOMICS-NEXT: sxth w8, w10
-; MSVC_OUTLINE_ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w10, w0, le
+; MSVC_OUTLINE_ATOMICS-NEXT: sxth w0, w10
+; MSVC_OUTLINE_ATOMICS-NEXT: cmp w0, w8
+; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w0, w8, lt
; MSVC_OUTLINE_ATOMICS-NEXT: stlxrh w11, w10, [x9]
; MSVC_OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB25_1
; MSVC_OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC_OUTLINE_ATOMICS-NEXT: mov w0, w8
; MSVC_OUTLINE_ATOMICS-NEXT: ret
;
; LSE-LABEL: test_atomic_load_min_i16:
@@ -1569,7 +1569,7 @@ define dso_local i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
; INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; INLINE_ATOMICS-NEXT: ldxr w8, [x9]
; INLINE_ATOMICS-NEXT: cmp w8, w0
-; INLINE_ATOMICS-NEXT: csel w10, w8, w0, le
+; INLINE_ATOMICS-NEXT: csel w10, w8, w0, lt
; INLINE_ATOMICS-NEXT: stxr w11, w10, [x9]
; INLINE_ATOMICS-NEXT: cbnz w11, .LBB26_1
; INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1584,7 +1584,7 @@ define dso_local i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
; MSVC_INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_INLINE_ATOMICS-NEXT: ldxr w8, [x9]
; MSVC_INLINE_ATOMICS-NEXT: cmp w8, w0
-; MSVC_INLINE_ATOMICS-NEXT: csel w10, w8, w0, le
+; MSVC_INLINE_ATOMICS-NEXT: csel w10, w8, w0, lt
; MSVC_INLINE_ATOMICS-NEXT: stxr w11, w10, [x9]
; MSVC_INLINE_ATOMICS-NEXT: cbnz w11, .LBB26_1
; MSVC_INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1599,7 +1599,7 @@ define dso_local i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
; OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE_ATOMICS-NEXT: ldxr w8, [x9]
; OUTLINE_ATOMICS-NEXT: cmp w8, w0
-; OUTLINE_ATOMICS-NEXT: csel w10, w8, w0, le
+; OUTLINE_ATOMICS-NEXT: csel w10, w8, w0, lt
; OUTLINE_ATOMICS-NEXT: stxr w11, w10, [x9]
; OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB26_1
; OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1614,7 +1614,7 @@ define dso_local i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
; MSVC_OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_OUTLINE_ATOMICS-NEXT: ldxr w8, [x9]
; MSVC_OUTLINE_ATOMICS-NEXT: cmp w8, w0
-; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w8, w0, le
+; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w8, w0, lt
; MSVC_OUTLINE_ATOMICS-NEXT: stxr w11, w10, [x9]
; MSVC_OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB26_1
; MSVC_OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1640,7 +1640,7 @@ define dso_local i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
; INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; INLINE_ATOMICS-NEXT: ldaxr x8, [x9]
; INLINE_ATOMICS-NEXT: cmp x8, x0
-; INLINE_ATOMICS-NEXT: csel x10, x8, x0, le
+; INLINE_ATOMICS-NEXT: csel x10, x8, x0, lt
; INLINE_ATOMICS-NEXT: stlxr w11, x10, [x9]
; INLINE_ATOMICS-NEXT: cbnz w11, .LBB27_1
; INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1656,7 +1656,7 @@ define dso_local i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
; MSVC_INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_INLINE_ATOMICS-NEXT: ldaxr x0, [x9]
; MSVC_INLINE_ATOMICS-NEXT: cmp x0, x8
-; MSVC_INLINE_ATOMICS-NEXT: csel x10, x0, x8, le
+; MSVC_INLINE_ATOMICS-NEXT: csel x10, x0, x8, lt
; MSVC_INLINE_ATOMICS-NEXT: stlxr w11, x10, [x9]
; MSVC_INLINE_ATOMICS-NEXT: cbnz w11, .LBB27_1
; MSVC_INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1671,7 +1671,7 @@ define dso_local i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
; OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE_ATOMICS-NEXT: ldaxr x8, [x9]
; OUTLINE_ATOMICS-NEXT: cmp x8, x0
-; OUTLINE_ATOMICS-NEXT: csel x10, x8, x0, le
+; OUTLINE_ATOMICS-NEXT: csel x10, x8, x0, lt
; OUTLINE_ATOMICS-NEXT: stlxr w11, x10, [x9]
; OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB27_1
; OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1687,7 +1687,7 @@ define dso_local i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
; MSVC_OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_OUTLINE_ATOMICS-NEXT: ldaxr x0, [x9]
; MSVC_OUTLINE_ATOMICS-NEXT: cmp x0, x8
-; MSVC_OUTLINE_ATOMICS-NEXT: csel x10, x0, x8, le
+; MSVC_OUTLINE_ATOMICS-NEXT: csel x10, x0, x8, lt
; MSVC_OUTLINE_ATOMICS-NEXT: stlxr w11, x10, [x9]
; MSVC_OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB27_1
; MSVC_OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -1707,67 +1707,67 @@ define dso_local i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
define dso_local i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
; INLINE_ATOMICS-LABEL: test_atomic_load_max_i8:
; INLINE_ATOMICS: // %bb.0:
+; INLINE_ATOMICS-NEXT: sxtb w8, w0
; INLINE_ATOMICS-NEXT: adrp x9, var8
; INLINE_ATOMICS-NEXT: add x9, x9, :lo12:var8
; INLINE_ATOMICS-NEXT: .LBB28_1: // %atomicrmw.start
; INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; INLINE_ATOMICS-NEXT: ldaxrb w10, [x9]
-; INLINE_ATOMICS-NEXT: sxtb w8, w10
-; INLINE_ATOMICS-NEXT: cmp w8, w0, sxtb
-; INLINE_ATOMICS-NEXT: csel w10, w10, w0, gt
+; INLINE_ATOMICS-NEXT: sxtb w0, w10
+; INLINE_ATOMICS-NEXT: cmp w0, w8
+; INLINE_ATOMICS-NEXT: csel w10, w0, w8, gt
; INLINE_ATOMICS-NEXT: stlxrb w11, w10, [x9]
; INLINE_ATOMICS-NEXT: cbnz w11, .LBB28_1
; INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; INLINE_ATOMICS-NEXT: mov w0, w8
; INLINE_ATOMICS-NEXT: ret
;
; MSVC_INLINE_ATOMICS-LABEL: test_atomic_load_max_i8:
; MSVC_INLINE_ATOMICS: // %bb.0:
+; MSVC_INLINE_ATOMICS-NEXT: sxtb w8, w0
; MSVC_INLINE_ATOMICS-NEXT: adrp x9, var8
; MSVC_INLINE_ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC_INLINE_ATOMICS-NEXT: .LBB28_1: // %atomicrmw.start
; MSVC_INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_INLINE_ATOMICS-NEXT: ldaxrb w10, [x9]
-; MSVC_INLINE_ATOMICS-NEXT: sxtb w8, w10
-; MSVC_INLINE_ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC_INLINE_ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC_INLINE_ATOMICS-NEXT: sxtb w0, w10
+; MSVC_INLINE_ATOMICS-NEXT: cmp w0, w8
+; MSVC_INLINE_ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC_INLINE_ATOMICS-NEXT: stlxrb w11, w10, [x9]
; MSVC_INLINE_ATOMICS-NEXT: cbnz w11, .LBB28_1
; MSVC_INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC_INLINE_ATOMICS-NEXT: mov w0, w8
; MSVC_INLINE_ATOMICS-NEXT: dmb ish
; MSVC_INLINE_ATOMICS-NEXT: ret
;
; OUTLINE_ATOMICS-LABEL: test_atomic_load_max_i8:
; OUTLINE_ATOMICS: // %bb.0:
+; OUTLINE_ATOMICS-NEXT: sxtb w8, w0
; OUTLINE_ATOMICS-NEXT: adrp x9, var8
; OUTLINE_ATOMICS-NEXT: add x9, x9, :lo12:var8
; OUTLINE_ATOMICS-NEXT: .LBB28_1: // %atomicrmw.start
; OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE_ATOMICS-NEXT: ldaxrb w10, [x9]
-; OUTLINE_ATOMICS-NEXT: sxtb w8, w10
-; OUTLINE_ATOMICS-NEXT: cmp w8, w0, sxtb
-; OUTLINE_ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE_ATOMICS-NEXT: sxtb w0, w10
+; OUTLINE_ATOMICS-NEXT: cmp w0, w8
+; OUTLINE_ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE_ATOMICS-NEXT: stlxrb w11, w10, [x9]
; OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB28_1
; OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE_ATOMICS-NEXT: mov w0, w8
; OUTLINE_ATOMICS-NEXT: ret
;
; MSVC_OUTLINE_ATOMICS-LABEL: test_atomic_load_max_i8:
; MSVC_OUTLINE_ATOMICS: // %bb.0:
+; MSVC_OUTLINE_ATOMICS-NEXT: sxtb w8, w0
; MSVC_OUTLINE_ATOMICS-NEXT: adrp x9, var8
; MSVC_OUTLINE_ATOMICS-NEXT: add x9, x9, :lo12:var8
; MSVC_OUTLINE_ATOMICS-NEXT: .LBB28_1: // %atomicrmw.start
; MSVC_OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_OUTLINE_ATOMICS-NEXT: ldaxrb w10, [x9]
-; MSVC_OUTLINE_ATOMICS-NEXT: sxtb w8, w10
-; MSVC_OUTLINE_ATOMICS-NEXT: cmp w8, w0, sxtb
-; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC_OUTLINE_ATOMICS-NEXT: sxtb w0, w10
+; MSVC_OUTLINE_ATOMICS-NEXT: cmp w0, w8
+; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC_OUTLINE_ATOMICS-NEXT: stlxrb w11, w10, [x9]
; MSVC_OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB28_1
; MSVC_OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC_OUTLINE_ATOMICS-NEXT: mov w0, w8
; MSVC_OUTLINE_ATOMICS-NEXT: dmb ish
; MSVC_OUTLINE_ATOMICS-NEXT: ret
;
@@ -1784,66 +1784,66 @@ define dso_local i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
define dso_local i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
; INLINE_ATOMICS-LABEL: test_atomic_load_max_i16:
; INLINE_ATOMICS: // %bb.0:
+; INLINE_ATOMICS-NEXT: sxth w8, w0
; INLINE_ATOMICS-NEXT: adrp x9, var16
; INLINE_ATOMICS-NEXT: add x9, x9, :lo12:var16
; INLINE_ATOMICS-NEXT: .LBB29_1: // %atomicrmw.start
; INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; INLINE_ATOMICS-NEXT: ldaxrh w10, [x9]
-; INLINE_ATOMICS-NEXT: sxth w8, w10
-; INLINE_ATOMICS-NEXT: cmp w8, w0, sxth
-; INLINE_ATOMICS-NEXT: csel w10, w10, w0, gt
+; INLINE_ATOMICS-NEXT: sxth w0, w10
+; INLINE_ATOMICS-NEXT: cmp w0, w8
+; INLINE_ATOMICS-NEXT: csel w10, w0, w8, gt
; INLINE_ATOMICS-NEXT: stxrh w11, w10, [x9]
; INLINE_ATOMICS-NEXT: cbnz w11, .LBB29_1
; INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; INLINE_ATOMICS-NEXT: mov w0, w8
; INLINE_ATOMICS-NEXT: ret
;
; MSVC_INLINE_ATOMICS-LABEL: test_atomic_load_max_i16:
; MSVC_INLINE_ATOMICS: // %bb.0:
+; MSVC_INLINE_ATOMICS-NEXT: sxth w8, w0
; MSVC_INLINE_ATOMICS-NEXT: adrp x9, var16
; MSVC_INLINE_ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC_INLINE_ATOMICS-NEXT: .LBB29_1: // %atomicrmw.start
; MSVC_INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_INLINE_ATOMICS-NEXT: ldaxrh w10, [x9]
-; MSVC_INLINE_ATOMICS-NEXT: sxth w8, w10
-; MSVC_INLINE_ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC_INLINE_ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC_INLINE_ATOMICS-NEXT: sxth w0, w10
+; MSVC_INLINE_ATOMICS-NEXT: cmp w0, w8
+; MSVC_INLINE_ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC_INLINE_ATOMICS-NEXT: stxrh w11, w10, [x9]
; MSVC_INLINE_ATOMICS-NEXT: cbnz w11, .LBB29_1
; MSVC_INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC_INLINE_ATOMICS-NEXT: mov w0, w8
; MSVC_INLINE_ATOMICS-NEXT: ret
;
; OUTLINE_ATOMICS-LABEL: test_atomic_load_max_i16:
; OUTLINE_ATOMICS: // %bb.0:
+; OUTLINE_ATOMICS-NEXT: sxth w8, w0
; OUTLINE_ATOMICS-NEXT: adrp x9, var16
; OUTLINE_ATOMICS-NEXT: add x9, x9, :lo12:var16
; OUTLINE_ATOMICS-NEXT: .LBB29_1: // %atomicrmw.start
; OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE_ATOMICS-NEXT: ldaxrh w10, [x9]
-; OUTLINE_ATOMICS-NEXT: sxth w8, w10
-; OUTLINE_ATOMICS-NEXT: cmp w8, w0, sxth
-; OUTLINE_ATOMICS-NEXT: csel w10, w10, w0, gt
+; OUTLINE_ATOMICS-NEXT: sxth w0, w10
+; OUTLINE_ATOMICS-NEXT: cmp w0, w8
+; OUTLINE_ATOMICS-NEXT: csel w10, w0, w8, gt
; OUTLINE_ATOMICS-NEXT: stxrh w11, w10, [x9]
; OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB29_1
; OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; OUTLINE_ATOMICS-NEXT: mov w0, w8
; OUTLINE_ATOMICS-NEXT: ret
;
; MSVC_OUTLINE_ATOMICS-LABEL: test_atomic_load_max_i16:
; MSVC_OUTLINE_ATOMICS: // %bb.0:
+; MSVC_OUTLINE_ATOMICS-NEXT: sxth w8, w0
; MSVC_OUTLINE_ATOMICS-NEXT: adrp x9, var16
; MSVC_OUTLINE_ATOMICS-NEXT: add x9, x9, :lo12:var16
; MSVC_OUTLINE_ATOMICS-NEXT: .LBB29_1: // %atomicrmw.start
; MSVC_OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_OUTLINE_ATOMICS-NEXT: ldaxrh w10, [x9]
-; MSVC_OUTLINE_ATOMICS-NEXT: sxth w8, w10
-; MSVC_OUTLINE_ATOMICS-NEXT: cmp w8, w0, sxth
-; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w10, w0, gt
+; MSVC_OUTLINE_ATOMICS-NEXT: sxth w0, w10
+; MSVC_OUTLINE_ATOMICS-NEXT: cmp w0, w8
+; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w0, w8, gt
; MSVC_OUTLINE_ATOMICS-NEXT: stxrh w11, w10, [x9]
; MSVC_OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB29_1
; MSVC_OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
-; MSVC_OUTLINE_ATOMICS-NEXT: mov w0, w8
; MSVC_OUTLINE_ATOMICS-NEXT: ret
;
; LSE-LABEL: test_atomic_load_max_i16:
@@ -2008,7 +2008,7 @@ define dso_local i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
; INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; INLINE_ATOMICS-NEXT: ldxrb w0, [x8]
; INLINE_ATOMICS-NEXT: cmp w0, w9
-; INLINE_ATOMICS-NEXT: csel w10, w0, w9, ls
+; INLINE_ATOMICS-NEXT: csel w10, w0, w9, lo
; INLINE_ATOMICS-NEXT: stxrb w11, w10, [x8]
; INLINE_ATOMICS-NEXT: cbnz w11, .LBB32_1
; INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2024,7 +2024,7 @@ define dso_local i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
; MSVC_INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_INLINE_ATOMICS-NEXT: ldxrb w0, [x8]
; MSVC_INLINE_ATOMICS-NEXT: cmp w0, w9
-; MSVC_INLINE_ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC_INLINE_ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC_INLINE_ATOMICS-NEXT: stxrb w11, w10, [x8]
; MSVC_INLINE_ATOMICS-NEXT: cbnz w11, .LBB32_1
; MSVC_INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2040,7 +2040,7 @@ define dso_local i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
; OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE_ATOMICS-NEXT: ldxrb w0, [x8]
; OUTLINE_ATOMICS-NEXT: cmp w0, w9
-; OUTLINE_ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE_ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE_ATOMICS-NEXT: stxrb w11, w10, [x8]
; OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB32_1
; OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2056,7 +2056,7 @@ define dso_local i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
; MSVC_OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_OUTLINE_ATOMICS-NEXT: ldxrb w0, [x8]
; MSVC_OUTLINE_ATOMICS-NEXT: cmp w0, w9
-; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC_OUTLINE_ATOMICS-NEXT: stxrb w11, w10, [x8]
; MSVC_OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB32_1
; MSVC_OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2083,7 +2083,7 @@ define dso_local i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
; INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; INLINE_ATOMICS-NEXT: ldaxrh w0, [x8]
; INLINE_ATOMICS-NEXT: cmp w0, w9
-; INLINE_ATOMICS-NEXT: csel w10, w0, w9, ls
+; INLINE_ATOMICS-NEXT: csel w10, w0, w9, lo
; INLINE_ATOMICS-NEXT: stxrh w11, w10, [x8]
; INLINE_ATOMICS-NEXT: cbnz w11, .LBB33_1
; INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2099,7 +2099,7 @@ define dso_local i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
; MSVC_INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_INLINE_ATOMICS-NEXT: ldaxrh w0, [x8]
; MSVC_INLINE_ATOMICS-NEXT: cmp w0, w9
-; MSVC_INLINE_ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC_INLINE_ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC_INLINE_ATOMICS-NEXT: stxrh w11, w10, [x8]
; MSVC_INLINE_ATOMICS-NEXT: cbnz w11, .LBB33_1
; MSVC_INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2115,7 +2115,7 @@ define dso_local i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
; OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE_ATOMICS-NEXT: ldaxrh w0, [x8]
; OUTLINE_ATOMICS-NEXT: cmp w0, w9
-; OUTLINE_ATOMICS-NEXT: csel w10, w0, w9, ls
+; OUTLINE_ATOMICS-NEXT: csel w10, w0, w9, lo
; OUTLINE_ATOMICS-NEXT: stxrh w11, w10, [x8]
; OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB33_1
; OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2131,7 +2131,7 @@ define dso_local i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
; MSVC_OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_OUTLINE_ATOMICS-NEXT: ldaxrh w0, [x8]
; MSVC_OUTLINE_ATOMICS-NEXT: cmp w0, w9
-; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w0, w9, ls
+; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w0, w9, lo
; MSVC_OUTLINE_ATOMICS-NEXT: stxrh w11, w10, [x8]
; MSVC_OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB33_1
; MSVC_OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2157,7 +2157,7 @@ define dso_local i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
; INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; INLINE_ATOMICS-NEXT: ldaxr w8, [x9]
; INLINE_ATOMICS-NEXT: cmp w8, w0
-; INLINE_ATOMICS-NEXT: csel w10, w8, w0, ls
+; INLINE_ATOMICS-NEXT: csel w10, w8, w0, lo
; INLINE_ATOMICS-NEXT: stlxr w11, w10, [x9]
; INLINE_ATOMICS-NEXT: cbnz w11, .LBB34_1
; INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2172,7 +2172,7 @@ define dso_local i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
; MSVC_INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_INLINE_ATOMICS-NEXT: ldaxr w8, [x9]
; MSVC_INLINE_ATOMICS-NEXT: cmp w8, w0
-; MSVC_INLINE_ATOMICS-NEXT: csel w10, w8, w0, ls
+; MSVC_INLINE_ATOMICS-NEXT: csel w10, w8, w0, lo
; MSVC_INLINE_ATOMICS-NEXT: stlxr w11, w10, [x9]
; MSVC_INLINE_ATOMICS-NEXT: cbnz w11, .LBB34_1
; MSVC_INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2188,7 +2188,7 @@ define dso_local i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
; OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE_ATOMICS-NEXT: ldaxr w8, [x9]
; OUTLINE_ATOMICS-NEXT: cmp w8, w0
-; OUTLINE_ATOMICS-NEXT: csel w10, w8, w0, ls
+; OUTLINE_ATOMICS-NEXT: csel w10, w8, w0, lo
; OUTLINE_ATOMICS-NEXT: stlxr w11, w10, [x9]
; OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB34_1
; OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2203,7 +2203,7 @@ define dso_local i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
; MSVC_OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_OUTLINE_ATOMICS-NEXT: ldaxr w8, [x9]
; MSVC_OUTLINE_ATOMICS-NEXT: cmp w8, w0
-; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w8, w0, ls
+; MSVC_OUTLINE_ATOMICS-NEXT: csel w10, w8, w0, lo
; MSVC_OUTLINE_ATOMICS-NEXT: stlxr w11, w10, [x9]
; MSVC_OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB34_1
; MSVC_OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2230,7 +2230,7 @@ define dso_local i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
; INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; INLINE_ATOMICS-NEXT: ldaxr x8, [x9]
; INLINE_ATOMICS-NEXT: cmp x8, x0
-; INLINE_ATOMICS-NEXT: csel x10, x8, x0, ls
+; INLINE_ATOMICS-NEXT: csel x10, x8, x0, lo
; INLINE_ATOMICS-NEXT: stlxr w11, x10, [x9]
; INLINE_ATOMICS-NEXT: cbnz w11, .LBB35_1
; INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2245,7 +2245,7 @@ define dso_local i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
; MSVC_INLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_INLINE_ATOMICS-NEXT: ldaxr x8, [x9]
; MSVC_INLINE_ATOMICS-NEXT: cmp x8, x0
-; MSVC_INLINE_ATOMICS-NEXT: csel x10, x8, x0, ls
+; MSVC_INLINE_ATOMICS-NEXT: csel x10, x8, x0, lo
; MSVC_INLINE_ATOMICS-NEXT: stlxr w11, x10, [x9]
; MSVC_INLINE_ATOMICS-NEXT: cbnz w11, .LBB35_1
; MSVC_INLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2260,7 +2260,7 @@ define dso_local i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
; OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; OUTLINE_ATOMICS-NEXT: ldaxr x8, [x9]
; OUTLINE_ATOMICS-NEXT: cmp x8, x0
-; OUTLINE_ATOMICS-NEXT: csel x10, x8, x0, ls
+; OUTLINE_ATOMICS-NEXT: csel x10, x8, x0, lo
; OUTLINE_ATOMICS-NEXT: stlxr w11, x10, [x9]
; OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB35_1
; OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
@@ -2275,7 +2275,7 @@ define dso_local i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
; MSVC_OUTLINE_ATOMICS-NEXT: // =>This Inner Loop Header: Depth=1
; MSVC_OUTLINE_ATOMICS-NEXT: ldaxr x8, [x9]
; MSVC_OUTLINE_ATOMICS-NEXT: cmp x8, x0
-; MSVC_OUTLINE_ATOMICS-NEXT: csel x10, x8, x0, ls
+; MSVC_OUTLINE_ATOMICS-NEXT: csel x10, x8, x0, lo
; MSVC_OUTLINE_ATOMICS-NEXT: stlxr w11, x10, [x9]
; MSVC_OUTLINE_ATOMICS-NEXT: cbnz w11, .LBB35_1
; MSVC_OUTLINE_ATOMICS-NEXT: // %bb.2: // %atomicrmw.end
diff --git a/llvm/test/CodeGen/AArch64/cond-sel.ll b/llvm/test/CodeGen/AArch64/cond-sel.ll
index 34578f43c6649..6ba8e2966a9c8 100644
--- a/llvm/test/CodeGen/AArch64/cond-sel.ll
+++ b/llvm/test/CodeGen/AArch64/cond-sel.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -enable-machine-outliner=never -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mcpu=cyclone | FileCheck %s
; RUN: llc -enable-machine-outliner=never -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
@@ -6,73 +7,197 @@
define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
; CHECK-LABEL: test_csel:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: mov w8, #52 // =0x34
+; CHECK-NEXT: mov w9, #42 // =0x2a
+; CHECK-NEXT: csel w8, w9, w8, hi
+; CHECK-NEXT: adrp x9, :got:var32
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var32]
+; CHECK-NEXT: str w8, [x9]
+; CHECK-NEXT: sxtw x8, w1
+; CHECK-NEXT: cmp x2, w1, sxtw
+; CHECK-NEXT: csel x8, x2, x8, lt
+; CHECK-NEXT: adrp x9, :got:var64
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var64]
+; CHECK-NEXT: str x8, [x9]
+; CHECK-NEXT: ret
+;
+; CHECK-NOFP-LABEL: test_csel:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NOFP-NEXT: mov w8, #52 // =0x34
+; CHECK-NOFP-NEXT: mov w9, #42 // =0x2a
+; CHECK-NOFP-NEXT: cmp w0, w1
+; CHECK-NOFP-NEXT: adrp x10, :got:var32
+; CHECK-NOFP-NEXT: csel w8, w9, w8, hi
+; CHECK-NOFP-NEXT: sxtw x9, w1
+; CHECK-NOFP-NEXT: ldr x10, [x10, :got_lo12:var32]
+; CHECK-NOFP-NEXT: adrp x11, :got:var64
+; CHECK-NOFP-NEXT: cmp x2, w1, sxtw
+; CHECK-NOFP-NEXT: ldr x11, [x11, :got_lo12:var64]
+; CHECK-NOFP-NEXT: str w8, [x10]
+; CHECK-NOFP-NEXT: csel x8, x2, x9, lt
+; CHECK-NOFP-NEXT: str x8, [x11]
+; CHECK-NOFP-NEXT: ret
%tst1 = icmp ugt i32 %lhs32, %rhs32
%val1 = select i1 %tst1, i32 42, i32 52
store i32 %val1, ptr @var32
-; CHECK-DAG: mov [[W52:w[0-9]+]], #{{52|0x34}}
-; CHECK-DAG: mov [[W42:w[0-9]+]], #{{42|0x2a}}
-; CHECK: csel {{w[0-9]+}}, [[W42]], [[W52]], hi
%rhs64 = sext i32 %rhs32 to i64
%tst2 = icmp sle i64 %lhs64, %rhs64
%val2 = select i1 %tst2, i64 %lhs64, i64 %rhs64
store i64 %val2, ptr @var64
-; CHECK: sxtw [[EXT_RHS:x[0-9]+]], {{[wx]}}[[RHS:[0-9]+]]
-; CHECK: cmp [[LHS:x[0-9]+]], w[[RHS]], sxtw
-; CHECK: csel {{x[0-9]+}}, [[LHS]], [[EXT_RHS]], le
ret void
-; CHECK: ret
}
define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %rhs64) {
; CHECK-LABEL: test_floatcsel:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcmp s0, s1
+; CHECK-NEXT: mov w8, #52 // =0x34
+; CHECK-NEXT: mov w9, #42 // =0x2a
+; CHECK-NEXT: csel w8, w9, w8, mi
+; CHECK-NEXT: csel w8, w9, w8, gt
+; CHECK-NEXT: adrp x9, :got:var32
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var32]
+; CHECK-NEXT: str w8, [x9]
+; CHECK-NEXT: fcmp d2, d3
+; CHECK-NEXT: mov w8, #15 // =0xf
+; CHECK-NEXT: mov w9, #9 // =0x9
+; CHECK-NEXT: csel x8, x9, x8, eq
+; CHECK-NEXT: csel x8, x9, x8, vs
+; CHECK-NEXT: adrp x9, :got:var64
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var64]
+; CHECK-NEXT: str x8, [x9]
+; CHECK-NEXT: ret
+;
+; CHECK-NOFP-LABEL: test_floatcsel:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: stp x30, x23, [sp, #-48]! // 16-byte Folded Spill
+; CHECK-NOFP-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-NOFP-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-NOFP-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NOFP-NEXT: .cfi_offset w19, -8
+; CHECK-NOFP-NEXT: .cfi_offset w20, -16
+; CHECK-NOFP-NEXT: .cfi_offset w21, -24
+; CHECK-NOFP-NEXT: .cfi_offset w22, -32
+; CHECK-NOFP-NEXT: .cfi_offset w23, -40
+; CHECK-NOFP-NEXT: .cfi_offset w30, -48
+; CHECK-NOFP-NEXT: mov x19, x3
+; CHECK-NOFP-NEXT: mov x20, x2
+; CHECK-NOFP-NEXT: mov w21, w1
+; CHECK-NOFP-NEXT: mov w22, w0
+; CHECK-NOFP-NEXT: bl __unordsf2
+; CHECK-NOFP-NEXT: mov w23, w0
+; CHECK-NOFP-NEXT: mov w0, w22
+; CHECK-NOFP-NEXT: mov w1, w21
+; CHECK-NOFP-NEXT: bl __eqsf2
+; CHECK-NOFP-NEXT: cmp w0, #0
+; CHECK-NOFP-NEXT: adrp x10, :got:var32
+; CHECK-NOFP-NEXT: mov w8, #52 // =0x34
+; CHECK-NOFP-NEXT: ccmp w23, #0, #0, ne
+; CHECK-NOFP-NEXT: mov w9, #42 // =0x2a
+; CHECK-NOFP-NEXT: ldr x10, [x10, :got_lo12:var32]
+; CHECK-NOFP-NEXT: csel w8, w9, w8, eq
+; CHECK-NOFP-NEXT: mov x0, x20
+; CHECK-NOFP-NEXT: mov x1, x19
+; CHECK-NOFP-NEXT: str w8, [x10]
+; CHECK-NOFP-NEXT: bl __unorddf2
+; CHECK-NOFP-NEXT: mov w21, w0
+; CHECK-NOFP-NEXT: mov x0, x20
+; CHECK-NOFP-NEXT: mov x1, x19
+; CHECK-NOFP-NEXT: bl __eqdf2
+; CHECK-NOFP-NEXT: cmp w0, #0
+; CHECK-NOFP-NEXT: adrp x10, :got:var64
+; CHECK-NOFP-NEXT: mov w8, #15 // =0xf
+; CHECK-NOFP-NEXT: csinc w9, w21, wzr, ne
+; CHECK-NOFP-NEXT: ldr x10, [x10, :got_lo12:var64]
+; CHECK-NOFP-NEXT: cmp w9, #0
+; CHECK-NOFP-NEXT: mov w9, #9 // =0x9
+; CHECK-NOFP-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-NOFP-NEXT: csel x8, x9, x8, ne
+; CHECK-NOFP-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-NOFP-NEXT: str x8, [x10]
+; CHECK-NOFP-NEXT: ldp x30, x23, [sp], #48 // 16-byte Folded Reload
+; CHECK-NOFP-NEXT: ret
%tst1 = fcmp one float %lhs32, %rhs32
-; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}}
-; CHECK-NOFP-NOT: fcmp
%val1 = select i1 %tst1, i32 42, i32 52
store i32 %val1, ptr @var32
-; CHECK: mov [[W52:w[0-9]+]], #{{52|0x34}}
-; CHECK: mov [[W42:w[0-9]+]], #{{42|0x2a}}
-; CHECK: csel [[MAYBETRUE:w[0-9]+]], [[W42]], [[W52]], mi
-; CHECK: csel {{w[0-9]+}}, [[W42]], [[MAYBETRUE]], gt
%tst2 = fcmp ueq double %lhs64, %rhs64
-; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}}
-; CHECK-NOFP-NOT: fcmp
%val2 = select i1 %tst2, i64 9, i64 15
store i64 %val2, ptr @var64
-; CHECK: mov w[[CONST15:[0-9]+]], #15
-; CHECK: mov {{[wx]}}[[CONST9:[0-9]+]], #{{9|0x9}}
-; CHECK: csel [[MAYBETRUE:x[0-9]+]], x[[CONST9]], x[[CONST15]], eq
-; CHECK: csel {{x[0-9]+}}, x[[CONST9]], [[MAYBETRUE]], vs
ret void
-; CHECK: ret
}
define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
; CHECK-LABEL: test_csinc:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: csinc w8, w0, w1, ls
+; CHECK-NEXT: adrp x9, :got:var32
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var32]
+; CHECK-NEXT: str w8, [x9]
+; CHECK-NEXT: add w8, w1, #42
+; CHECK-NEXT: cmp w0, w8
+; CHECK-NEXT: csinc w8, w0, w1, le
+; CHECK-NEXT: str w8, [x9]
+; CHECK-NEXT: sxtw x8, w1
+; CHECK-NEXT: cmp x2, w1, sxtw
+; CHECK-NEXT: adrp x9, :got:var64
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var64]
+; CHECK-NEXT: csinc x8, x2, x8, ls
+; CHECK-NEXT: str x8, [x9]
+; CHECK-NEXT: mov w8, w1
+; CHECK-NEXT: cmp x2, w1, uxtw
+; CHECK-NEXT: csinc x8, x2, x8, le
+; CHECK-NEXT: str x8, [x9]
+; CHECK-NEXT: ret
+;
+; CHECK-NOFP-LABEL: test_csinc:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: adrp x8, :got:var32
+; CHECK-NOFP-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NOFP-NEXT: cmp w0, w1
+; CHECK-NOFP-NEXT: add w9, w1, #42
+; CHECK-NOFP-NEXT: ldr x8, [x8, :got_lo12:var32]
+; CHECK-NOFP-NEXT: csinc w10, w0, w1, ls
+; CHECK-NOFP-NEXT: cmp w0, w9
+; CHECK-NOFP-NEXT: sxtw x9, w1
+; CHECK-NOFP-NEXT: str w10, [x8]
+; CHECK-NOFP-NEXT: csinc w10, w0, w1, le
+; CHECK-NOFP-NEXT: cmp x2, w1, sxtw
+; CHECK-NOFP-NEXT: str w10, [x8]
+; CHECK-NOFP-NEXT: adrp x8, :got:var64
+; CHECK-NOFP-NEXT: csinc x9, x2, x9, ls
+; CHECK-NOFP-NEXT: ldr x8, [x8, :got_lo12:var64]
+; CHECK-NOFP-NEXT: mov w10, w1
+; CHECK-NOFP-NEXT: cmp x2, w1, uxtw
+; CHECK-NOFP-NEXT: str x9, [x8]
+; CHECK-NOFP-NEXT: csinc x9, x2, x10, le
+; CHECK-NOFP-NEXT: str x9, [x8]
+; CHECK-NOFP-NEXT: ret
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
%tst1 = icmp ugt i32 %lhs32, %rhs32
%inc1 = add i32 %rhs32, 1
%val1 = select i1 %tst1, i32 %inc1, i32 %lhs32
store volatile i32 %val1, ptr @var32
-; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
-; CHECK: csinc {{w[0-9]+}}, [[LHS]], [[RHS]], ls
%rhs2 = add i32 %rhs32, 42
%tst2 = icmp sle i32 %lhs32, %rhs2
%inc2 = add i32 %rhs32, 1
%val2 = select i1 %tst2, i32 %lhs32, i32 %inc2
store volatile i32 %val2, ptr @var32
-; CHECK: cmp [[LHS:w[0-9]+]], {{w[0-9]+}}
-; CHECK: csinc {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
%rhs3 = sext i32 %rhs32 to i64
@@ -80,39 +205,76 @@ define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
%inc3 = add i64 %rhs3, 1
%val3 = select i1 %tst3, i64 %inc3, i64 %lhs64
store volatile i64 %val3, ptr @var64
-; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
-; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
%rhs4 = zext i32 %rhs32 to i64
%tst4 = icmp sle i64 %lhs64, %rhs4
%inc4 = add i64 %rhs4, 1
%val4 = select i1 %tst4, i64 %lhs64, i64 %inc4
store volatile i64 %val4, ptr @var64
-; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
-; CHECK: csinc {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
ret void
-; CHECK: ret
}
define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
; CHECK-LABEL: test_csinv:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: csinv w8, w0, w1, ls
+; CHECK-NEXT: adrp x9, :got:var32
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var32]
+; CHECK-NEXT: str w8, [x9]
+; CHECK-NEXT: add w8, w1, #42
+; CHECK-NEXT: cmp w0, w8
+; CHECK-NEXT: csinv w8, w0, w1, le
+; CHECK-NEXT: str w8, [x9]
+; CHECK-NEXT: sxtw x8, w1
+; CHECK-NEXT: cmp x2, w1, sxtw
+; CHECK-NEXT: adrp x9, :got:var64
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var64]
+; CHECK-NEXT: csinv x8, x2, x8, ls
+; CHECK-NEXT: str x8, [x9]
+; CHECK-NEXT: mov w8, w1
+; CHECK-NEXT: cmp x2, w1, uxtw
+; CHECK-NEXT: csinv x8, x2, x8, le
+; CHECK-NEXT: str x8, [x9]
+; CHECK-NEXT: ret
+;
+; CHECK-NOFP-LABEL: test_csinv:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: adrp x8, :got:var32
+; CHECK-NOFP-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NOFP-NEXT: cmp w0, w1
+; CHECK-NOFP-NEXT: add w9, w1, #42
+; CHECK-NOFP-NEXT: ldr x8, [x8, :got_lo12:var32]
+; CHECK-NOFP-NEXT: csinv w10, w0, w1, ls
+; CHECK-NOFP-NEXT: cmp w0, w9
+; CHECK-NOFP-NEXT: sxtw x9, w1
+; CHECK-NOFP-NEXT: str w10, [x8]
+; CHECK-NOFP-NEXT: csinv w10, w0, w1, le
+; CHECK-NOFP-NEXT: cmp x2, w1, sxtw
+; CHECK-NOFP-NEXT: str w10, [x8]
+; CHECK-NOFP-NEXT: adrp x8, :got:var64
+; CHECK-NOFP-NEXT: csinv x9, x2, x9, ls
+; CHECK-NOFP-NEXT: ldr x8, [x8, :got_lo12:var64]
+; CHECK-NOFP-NEXT: mov w10, w1
+; CHECK-NOFP-NEXT: cmp x2, w1, uxtw
+; CHECK-NOFP-NEXT: str x9, [x8]
+; CHECK-NOFP-NEXT: csinv x9, x2, x10, le
+; CHECK-NOFP-NEXT: str x9, [x8]
+; CHECK-NOFP-NEXT: ret
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
%tst1 = icmp ugt i32 %lhs32, %rhs32
%inc1 = xor i32 -1, %rhs32
%val1 = select i1 %tst1, i32 %inc1, i32 %lhs32
store volatile i32 %val1, ptr @var32
-; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
-; CHECK: csinv {{w[0-9]+}}, [[LHS]], [[RHS]], ls
%rhs2 = add i32 %rhs32, 42
%tst2 = icmp sle i32 %lhs32, %rhs2
%inc2 = xor i32 -1, %rhs32
%val2 = select i1 %tst2, i32 %lhs32, i32 %inc2
store volatile i32 %val2, ptr @var32
-; CHECK: cmp [[LHS:w[0-9]+]], {{w[0-9]+}}
-; CHECK: csinv {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
%rhs3 = sext i32 %rhs32 to i64
@@ -120,67 +282,135 @@ define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
%inc3 = xor i64 -1, %rhs3
%val3 = select i1 %tst3, i64 %inc3, i64 %lhs64
store volatile i64 %val3, ptr @var64
-; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
-; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
%rhs4 = zext i32 %rhs32 to i64
%tst4 = icmp sle i64 %lhs64, %rhs4
%inc4 = xor i64 -1, %rhs4
%val4 = select i1 %tst4, i64 %lhs64, i64 %inc4
store volatile i64 %val4, ptr @var64
-; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
-; CHECK: csinv {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
ret void
-; CHECK: ret
}
define void @test_csinv0(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) minsize {
; CHECK-LABEL: test_csinv0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: csetm w8, ls
+; CHECK-NEXT: adrp x9, :got:var32
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var32]
+; CHECK-NEXT: str w8, [x9]
+; CHECK-NEXT: add w8, w1, #42
+; CHECK-NEXT: cmp w0, w8
+; CHECK-NEXT: csinv w8, w8, wzr, gt
+; CHECK-NEXT: str w8, [x9]
+; CHECK-NEXT: mov w8, #19 // =0x13
+; CHECK-NEXT: mul x8, x3, x8
+; CHECK-NEXT: cmp x2, x8
+; CHECK-NEXT: csinv x8, x8, xzr, hi
+; CHECK-NEXT: adrp x9, :got:var64
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var64]
+; CHECK-NEXT: str x8, [x9]
+; CHECK-NEXT: ret
+;
+; CHECK-NOFP-LABEL: test_csinv0:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov w8, #19 // =0x13
+; CHECK-NOFP-NEXT: adrp x9, :got:var32
+; CHECK-NOFP-NEXT: cmp w0, w1
+; CHECK-NOFP-NEXT: mul x8, x3, x8
+; CHECK-NOFP-NEXT: ldr x9, [x9, :got_lo12:var32]
+; CHECK-NOFP-NEXT: add w10, w1, #42
+; CHECK-NOFP-NEXT: csetm w11, ls
+; CHECK-NOFP-NEXT: cmp w0, w10
+; CHECK-NOFP-NEXT: str w11, [x9]
+; CHECK-NOFP-NEXT: adrp x11, :got:var64
+; CHECK-NOFP-NEXT: csinv w10, w10, wzr, gt
+; CHECK-NOFP-NEXT: ldr x11, [x11, :got_lo12:var64]
+; CHECK-NOFP-NEXT: str w10, [x9]
+; CHECK-NOFP-NEXT: cmp x2, x8
+; CHECK-NOFP-NEXT: csinv x8, x8, xzr, hi
+; CHECK-NOFP-NEXT: str x8, [x11]
+; CHECK-NOFP-NEXT: ret
%tst1 = icmp ugt i32 %lhs32, %rhs32
%val1 = select i1 %tst1, i32 0, i32 -1
store volatile i32 %val1, ptr @var32
-; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
-; CHECK: csetm {{w[0-9]+}}, ls
%rhs2 = add i32 %rhs32, 42
%tst2 = icmp sle i32 %lhs32, %rhs2
%val2 = select i1 %tst2, i32 -1, i32 %rhs2
store volatile i32 %val2, ptr @var32
-; CHECK: cmp [[LHS2:w[0-9]+]], [[RHS2:w[0-9]+]]
-; CHECK: csinv {{w[0-9]+}}, [[RHS2]], wzr, gt
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
%rhs3 = mul i64 %rhs64, 19
%tst3 = icmp ugt i64 %lhs64, %rhs3
%val3 = select i1 %tst3, i64 %rhs3, i64 -1
store volatile i64 %val3, ptr @var64
-; CHECK: cmp [[LHS3:x[0-9]+]], [[RHS3:x[0-9]+]]
-; CHECK: csinv {{x[0-9]+}}, [[RHS3]], xzr, hi
ret void
-; CHECK: ret
}
define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
; CHECK-LABEL: test_csneg:
+; CHECK: // %bb.0:
+; CHECK-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: csneg w8, w0, w1, ls
+; CHECK-NEXT: adrp x9, :got:var32
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var32]
+; CHECK-NEXT: str w8, [x9]
+; CHECK-NEXT: add w8, w1, #42
+; CHECK-NEXT: cmp w0, w8
+; CHECK-NEXT: csneg w8, w0, w1, le
+; CHECK-NEXT: str w8, [x9]
+; CHECK-NEXT: sxtw x8, w1
+; CHECK-NEXT: cmp x2, w1, sxtw
+; CHECK-NEXT: adrp x9, :got:var64
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var64]
+; CHECK-NEXT: csneg x8, x2, x8, ls
+; CHECK-NEXT: str x8, [x9]
+; CHECK-NEXT: mov w8, w1
+; CHECK-NEXT: cmp x2, w1, uxtw
+; CHECK-NEXT: csneg x8, x2, x8, le
+; CHECK-NEXT: str x8, [x9]
+; CHECK-NEXT: ret
+;
+; CHECK-NOFP-LABEL: test_csneg:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: adrp x8, :got:var32
+; CHECK-NOFP-NEXT: // kill: def $w1 killed $w1 def $x1
+; CHECK-NOFP-NEXT: cmp w0, w1
+; CHECK-NOFP-NEXT: add w9, w1, #42
+; CHECK-NOFP-NEXT: ldr x8, [x8, :got_lo12:var32]
+; CHECK-NOFP-NEXT: csneg w10, w0, w1, ls
+; CHECK-NOFP-NEXT: cmp w0, w9
+; CHECK-NOFP-NEXT: sxtw x9, w1
+; CHECK-NOFP-NEXT: str w10, [x8]
+; CHECK-NOFP-NEXT: csneg w10, w0, w1, le
+; CHECK-NOFP-NEXT: cmp x2, w1, sxtw
+; CHECK-NOFP-NEXT: str w10, [x8]
+; CHECK-NOFP-NEXT: adrp x8, :got:var64
+; CHECK-NOFP-NEXT: csneg x9, x2, x9, ls
+; CHECK-NOFP-NEXT: ldr x8, [x8, :got_lo12:var64]
+; CHECK-NOFP-NEXT: mov w10, w1
+; CHECK-NOFP-NEXT: cmp x2, w1, uxtw
+; CHECK-NOFP-NEXT: str x9, [x8]
+; CHECK-NOFP-NEXT: csneg x9, x2, x10, le
+; CHECK-NOFP-NEXT: str x9, [x8]
+; CHECK-NOFP-NEXT: ret
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
%tst1 = icmp ugt i32 %lhs32, %rhs32
%inc1 = sub i32 0, %rhs32
%val1 = select i1 %tst1, i32 %inc1, i32 %lhs32
store volatile i32 %val1, ptr @var32
-; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
-; CHECK: csneg {{w[0-9]+}}, [[LHS]], [[RHS]], ls
%rhs2 = add i32 %rhs32, 42
%tst2 = icmp sle i32 %lhs32, %rhs2
%inc2 = sub i32 0, %rhs32
%val2 = select i1 %tst2, i32 %lhs32, i32 %inc2
store volatile i32 %val2, ptr @var32
-; CHECK: cmp [[LHS:w[0-9]+]], {{w[0-9]+}}
-; CHECK: csneg {{w[0-9]+}}, [[LHS]], {{w[0-9]+}}, le
; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
%rhs3 = sext i32 %rhs32 to i64
@@ -188,65 +418,112 @@ define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) minsize {
%inc3 = sub i64 0, %rhs3
%val3 = select i1 %tst3, i64 %inc3, i64 %lhs64
store volatile i64 %val3, ptr @var64
-; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
-; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, ls
%rhs4 = zext i32 %rhs32 to i64
%tst4 = icmp sle i64 %lhs64, %rhs4
%inc4 = sub i64 0, %rhs4
%val4 = select i1 %tst4, i64 %lhs64, i64 %inc4
store volatile i64 %val4, ptr @var64
-; CHECK: cmp [[LHS:x[0-9]+]], {{w[0-9]+}}
-; CHECK: csneg {{x[0-9]+}}, [[LHS]], {{x[0-9]+}}, le
ret void
-; CHECK: ret
}
define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) {
; CHECK-LABEL: test_cset:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: cset w8, eq
+; CHECK-NEXT: adrp x9, :got:var32
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var32]
+; CHECK-NEXT: str w8, [x9]
+; CHECK-NEXT: cmp x2, w1, sxtw
+; CHECK-NEXT: cset w8, ls
+; CHECK-NEXT: adrp x9, :got:var64
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var64]
+; CHECK-NEXT: str x8, [x9]
+; CHECK-NEXT: ret
+;
+; CHECK-NOFP-LABEL: test_cset:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: adrp x8, :got:var32
+; CHECK-NOFP-NEXT: cmp w0, w1
+; CHECK-NOFP-NEXT: adrp x10, :got:var64
+; CHECK-NOFP-NEXT: ldr x8, [x8, :got_lo12:var32]
+; CHECK-NOFP-NEXT: cset w9, eq
+; CHECK-NOFP-NEXT: cmp x2, w1, sxtw
+; CHECK-NOFP-NEXT: ldr x10, [x10, :got_lo12:var64]
+; CHECK-NOFP-NEXT: str w9, [x8]
+; CHECK-NOFP-NEXT: cset w8, ls
+; CHECK-NOFP-NEXT: str x8, [x10]
+; CHECK-NOFP-NEXT: ret
; N.b. code is not optimal here (32-bit csinc would be better) but
; incoming DAG is too complex
%tst1 = icmp eq i32 %lhs, %rhs
%val1 = zext i1 %tst1 to i32
store i32 %val1, ptr @var32
-; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
-; CHECK: cset {{w[0-9]+}}, eq
%rhs64 = sext i32 %rhs to i64
%tst2 = icmp ule i64 %lhs64, %rhs64
%val2 = zext i1 %tst2 to i64
store i64 %val2, ptr @var64
-; CHECK: cset {{w[0-9]+}}, ls
ret void
-; CHECK: ret
}
define void @test_csetm(i32 %lhs, i32 %rhs, i64 %lhs64) {
; CHECK-LABEL: test_csetm:
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: csetm w8, eq
+; CHECK-NEXT: adrp x9, :got:var32
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var32]
+; CHECK-NEXT: str w8, [x9]
+; CHECK-NEXT: cmp x2, w1, sxtw
+; CHECK-NEXT: csetm x8, ls
+; CHECK-NEXT: adrp x9, :got:var64
+; CHECK-NEXT: ldr x9, [x9, :got_lo12:var64]
+; CHECK-NEXT: str x8, [x9]
+; CHECK-NEXT: ret
+;
+; CHECK-NOFP-LABEL: test_csetm:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: adrp x8, :got:var32
+; CHECK-NOFP-NEXT: cmp w0, w1
+; CHECK-NOFP-NEXT: adrp x10, :got:var64
+; CHECK-NOFP-NEXT: ldr x8, [x8, :got_lo12:var32]
+; CHECK-NOFP-NEXT: csetm w9, eq
+; CHECK-NOFP-NEXT: cmp x2, w1, sxtw
+; CHECK-NOFP-NEXT: ldr x10, [x10, :got_lo12:var64]
+; CHECK-NOFP-NEXT: str w9, [x8]
+; CHECK-NOFP-NEXT: csetm x8, ls
+; CHECK-NOFP-NEXT: str x8, [x10]
+; CHECK-NOFP-NEXT: ret
%tst1 = icmp eq i32 %lhs, %rhs
%val1 = sext i1 %tst1 to i32
store i32 %val1, ptr @var32
-; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
-; CHECK: csetm {{w[0-9]+}}, eq
%rhs64 = sext i32 %rhs to i64
%tst2 = icmp ule i64 %lhs64, %rhs64
%val2 = sext i1 %tst2 to i64
store i64 %val2, ptr @var64
-; CHECK: csetm {{x[0-9]+}}, ls
ret void
-; CHECK: ret
}
define <1 x i1> @test_wide_comparison(i32 %in) {
; CHECK-LABEL: test_wide_comparison:
-; CHECK: cmp w0, #1234
-; CHECK: cset
+; CHECK: // %bb.0:
+; CHECK-NEXT: cmp w0, #1234
+; CHECK-NEXT: cset w0, gt
+; CHECK-NEXT: ret
+;
+; CHECK-NOFP-LABEL: test_wide_comparison:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: cmp w0, #1234
+; CHECK-NOFP-NEXT: cset w0, gt
+; CHECK-NOFP-NEXT: ret
%tmp = icmp sgt i32 %in, 1234
%res = select i1 %tmp, <1 x i1> <i1 1>, <1 x i1> zeroinitializer
@@ -255,7 +532,14 @@ define <1 x i1> @test_wide_comparison(i32 %in) {
define i32 @test_select_undef() {
; CHECK-LABEL: test_select_undef:
-; CHECK: ret
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w0, #0 // =0x0
+; CHECK-NEXT: ret
+;
+; CHECK-NOFP-LABEL: test_select_undef:
+; CHECK-NOFP: // %bb.0:
+; CHECK-NOFP-NEXT: mov w0, wzr
+; CHECK-NOFP-NEXT: ret
%res = select i1 undef, i32 0, i32 42
ret i32 %res
}
diff --git a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
index dcb0051bd4c3c..b791a2b26527c 100644
--- a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
@@ -285,21 +285,21 @@ define <2 x i16> @stest_f64i16(<2 x double> %x) {
; CHECK-CVT-SD-LABEL: stest_f64i16:
; CHECK-CVT-SD: // %bb.0: // %entry
; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-CVT-SD-NEXT: movi v1.2s, #127, msl #8
-; CHECK-CVT-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-CVT-SD-NEXT: smin v0.2s, v0.2s, v1.2s
; CHECK-CVT-SD-NEXT: mvni v1.2s, #127, msl #8
+; CHECK-CVT-SD-NEXT: movi v2.2s, #127, msl #8
+; CHECK-CVT-SD-NEXT: xtn v0.2s, v0.2d
; CHECK-CVT-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-CVT-SD-NEXT: smin v0.2s, v0.2s, v2.2s
; CHECK-CVT-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: stest_f64i16:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-SD-NEXT: movi v1.2s, #127, msl #8
-; CHECK-FP16-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-FP16-SD-NEXT: smin v0.2s, v0.2s, v1.2s
; CHECK-FP16-SD-NEXT: mvni v1.2s, #127, msl #8
+; CHECK-FP16-SD-NEXT: movi v2.2s, #127, msl #8
+; CHECK-FP16-SD-NEXT: xtn v0.2s, v0.2d
; CHECK-FP16-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-FP16-SD-NEXT: smin v0.2s, v0.2s, v2.2s
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-CVT-GI-LABEL: stest_f64i16:
@@ -348,15 +348,45 @@ entry:
}
define <2 x i16> @ustest_f64i16(<2 x double> %x) {
-; CHECK-LABEL: ustest_f64i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: movi d1, #0x00ffff0000ffff
-; CHECK-NEXT: movi v2.2d, #0000000000000000
-; CHECK-NEXT: xtn v0.2s, v0.2d
-; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: smax v0.2s, v0.2s, v2.2s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f64i16:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT: movi v1.2d, #0000000000000000
+; CHECK-CVT-SD-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-CVT-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-CVT-SD-NEXT: smin v0.2s, v0.2s, v2.2s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f64i16:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT: movi v1.2d, #0000000000000000
+; CHECK-FP16-SD-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-FP16-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-FP16-SD-NEXT: smin v0.2s, v0.2s, v2.2s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f64i16:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: movi d1, #0x00ffff0000ffff
+; CHECK-CVT-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-CVT-GI-NEXT: smax v0.2s, v0.2s, v2.2s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f64i16:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: movi d1, #0x00ffff0000ffff
+; CHECK-FP16-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-FP16-GI-NEXT: smax v0.2s, v0.2s, v2.2s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i32>
%0 = icmp slt <2 x i32> %conv, <i32 65535, i32 65535>
@@ -2090,21 +2120,21 @@ define <2 x i16> @stest_f64i16_mm(<2 x double> %x) {
; CHECK-CVT-SD-LABEL: stest_f64i16_mm:
; CHECK-CVT-SD: // %bb.0: // %entry
; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-CVT-SD-NEXT: movi v1.2s, #127, msl #8
-; CHECK-CVT-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-CVT-SD-NEXT: smin v0.2s, v0.2s, v1.2s
; CHECK-CVT-SD-NEXT: mvni v1.2s, #127, msl #8
+; CHECK-CVT-SD-NEXT: movi v2.2s, #127, msl #8
+; CHECK-CVT-SD-NEXT: xtn v0.2s, v0.2d
; CHECK-CVT-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-CVT-SD-NEXT: smin v0.2s, v0.2s, v2.2s
; CHECK-CVT-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: stest_f64i16_mm:
; CHECK-FP16-SD: // %bb.0: // %entry
; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-FP16-SD-NEXT: movi v1.2s, #127, msl #8
-; CHECK-FP16-SD-NEXT: xtn v0.2s, v0.2d
-; CHECK-FP16-SD-NEXT: smin v0.2s, v0.2s, v1.2s
; CHECK-FP16-SD-NEXT: mvni v1.2s, #127, msl #8
+; CHECK-FP16-SD-NEXT: movi v2.2s, #127, msl #8
+; CHECK-FP16-SD-NEXT: xtn v0.2s, v0.2d
; CHECK-FP16-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-FP16-SD-NEXT: smin v0.2s, v0.2s, v2.2s
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-CVT-GI-LABEL: stest_f64i16_mm:
@@ -2150,15 +2180,45 @@ entry:
}
define <2 x i16> @ustest_f64i16_mm(<2 x double> %x) {
-; CHECK-LABEL: ustest_f64i16_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: movi d1, #0x00ffff0000ffff
-; CHECK-NEXT: movi v2.2d, #0000000000000000
-; CHECK-NEXT: xtn v0.2s, v0.2d
-; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: smax v0.2s, v0.2s, v2.2s
-; CHECK-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f64i16_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-SD-NEXT: movi v1.2d, #0000000000000000
+; CHECK-CVT-SD-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-CVT-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-CVT-SD-NEXT: smin v0.2s, v0.2s, v2.2s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: ustest_f64i16_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-SD-NEXT: movi v1.2d, #0000000000000000
+; CHECK-FP16-SD-NEXT: movi d2, #0x00ffff0000ffff
+; CHECK-FP16-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-FP16-SD-NEXT: smin v0.2s, v0.2s, v2.2s
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f64i16_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: movi d1, #0x00ffff0000ffff
+; CHECK-CVT-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-CVT-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-CVT-GI-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-CVT-GI-NEXT: smax v0.2s, v0.2s, v2.2s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f64i16_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: movi d1, #0x00ffff0000ffff
+; CHECK-FP16-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-FP16-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-FP16-GI-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-FP16-GI-NEXT: smax v0.2s, v0.2s, v2.2s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i32>
%spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 65535, i32 65535>)
@@ -2590,26 +2650,26 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) {
; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-CVT-SD-NEXT: mov d0, v0.d[1]
; CHECK-CVT-SD-NEXT: bl __fixdfti
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-CVT-SD-NEXT: mov x19, x0
; CHECK-CVT-SD-NEXT: mov x20, x1
-; CHECK-CVT-SD-NEXT: mov d0, v0.d[1]
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-CVT-SD-NEXT: bl __fixdfti
-; CHECK-CVT-SD-NEXT: cmp x1, #1
+; CHECK-CVT-SD-NEXT: bic x9, x1, x1, asr #63
+; CHECK-CVT-SD-NEXT: cmp x1, #0
+; CHECK-CVT-SD-NEXT: bic x8, x20, x20, asr #63
+; CHECK-CVT-SD-NEXT: csel x10, xzr, x0, mi
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
-; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
-; CHECK-CVT-SD-NEXT: cmp x20, #1
-; CHECK-CVT-SD-NEXT: csinc x10, x20, xzr, lt
-; CHECK-CVT-SD-NEXT: csel x11, x19, xzr, lt
-; CHECK-CVT-SD-NEXT: cmp x10, #0
+; CHECK-CVT-SD-NEXT: cmp x9, #1
+; CHECK-CVT-SD-NEXT: csel x9, x10, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: fmov d0, x9
+; CHECK-CVT-SD-NEXT: csel x9, xzr, x19, mi
+; CHECK-CVT-SD-NEXT: cmp x8, #1
+; CHECK-CVT-SD-NEXT: csel x8, x9, xzr, lt
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-CVT-SD-NEXT: csel x10, xzr, x11, mi
-; CHECK-CVT-SD-NEXT: cmp x9, #0
-; CHECK-CVT-SD-NEXT: csel x8, xzr, x8, mi
-; CHECK-CVT-SD-NEXT: fmov d0, x10
; CHECK-CVT-SD-NEXT: fmov d1, x8
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-CVT-SD-NEXT: add sp, sp, #48
@@ -2625,26 +2685,26 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) {
; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-FP16-SD-NEXT: mov d0, v0.d[1]
; CHECK-FP16-SD-NEXT: bl __fixdfti
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-FP16-SD-NEXT: mov x19, x0
; CHECK-FP16-SD-NEXT: mov x20, x1
-; CHECK-FP16-SD-NEXT: mov d0, v0.d[1]
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-FP16-SD-NEXT: bl __fixdfti
-; CHECK-FP16-SD-NEXT: cmp x1, #1
+; CHECK-FP16-SD-NEXT: bic x9, x1, x1, asr #63
+; CHECK-FP16-SD-NEXT: cmp x1, #0
+; CHECK-FP16-SD-NEXT: bic x8, x20, x20, asr #63
+; CHECK-FP16-SD-NEXT: csel x10, xzr, x0, mi
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
-; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
-; CHECK-FP16-SD-NEXT: cmp x20, #1
-; CHECK-FP16-SD-NEXT: csinc x10, x20, xzr, lt
-; CHECK-FP16-SD-NEXT: csel x11, x19, xzr, lt
-; CHECK-FP16-SD-NEXT: cmp x10, #0
+; CHECK-FP16-SD-NEXT: cmp x9, #1
+; CHECK-FP16-SD-NEXT: csel x9, x10, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: fmov d0, x9
+; CHECK-FP16-SD-NEXT: csel x9, xzr, x19, mi
+; CHECK-FP16-SD-NEXT: cmp x8, #1
+; CHECK-FP16-SD-NEXT: csel x8, x9, xzr, lt
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-FP16-SD-NEXT: csel x10, xzr, x11, mi
-; CHECK-FP16-SD-NEXT: cmp x9, #0
-; CHECK-FP16-SD-NEXT: csel x8, xzr, x8, mi
-; CHECK-FP16-SD-NEXT: fmov d0, x10
; CHECK-FP16-SD-NEXT: fmov d1, x8
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-FP16-SD-NEXT: add sp, sp, #48
@@ -3048,26 +3108,26 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) {
; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-CVT-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-CVT-SD-NEXT: mov s0, v0.s[1]
; CHECK-CVT-SD-NEXT: bl __fixsfti
; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-CVT-SD-NEXT: mov x19, x0
; CHECK-CVT-SD-NEXT: mov x20, x1
-; CHECK-CVT-SD-NEXT: mov s0, v0.s[1]
+; CHECK-CVT-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-CVT-SD-NEXT: bl __fixsfti
-; CHECK-CVT-SD-NEXT: cmp x1, #1
+; CHECK-CVT-SD-NEXT: bic x9, x1, x1, asr #63
+; CHECK-CVT-SD-NEXT: cmp x1, #0
+; CHECK-CVT-SD-NEXT: bic x8, x20, x20, asr #63
+; CHECK-CVT-SD-NEXT: csel x10, xzr, x0, mi
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
-; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
-; CHECK-CVT-SD-NEXT: cmp x20, #1
-; CHECK-CVT-SD-NEXT: csinc x10, x20, xzr, lt
-; CHECK-CVT-SD-NEXT: csel x11, x19, xzr, lt
-; CHECK-CVT-SD-NEXT: cmp x10, #0
+; CHECK-CVT-SD-NEXT: cmp x9, #1
+; CHECK-CVT-SD-NEXT: csel x9, x10, xzr, lt
+; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: fmov d0, x9
+; CHECK-CVT-SD-NEXT: csel x9, xzr, x19, mi
+; CHECK-CVT-SD-NEXT: cmp x8, #1
+; CHECK-CVT-SD-NEXT: csel x8, x9, xzr, lt
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-CVT-SD-NEXT: csel x10, xzr, x11, mi
-; CHECK-CVT-SD-NEXT: cmp x9, #0
-; CHECK-CVT-SD-NEXT: csel x8, xzr, x8, mi
-; CHECK-CVT-SD-NEXT: fmov d0, x10
; CHECK-CVT-SD-NEXT: fmov d1, x8
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-CVT-SD-NEXT: add sp, sp, #48
@@ -3084,26 +3144,26 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) {
; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-FP16-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-FP16-SD-NEXT: mov s0, v0.s[1]
; CHECK-FP16-SD-NEXT: bl __fixsfti
; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
; CHECK-FP16-SD-NEXT: mov x19, x0
; CHECK-FP16-SD-NEXT: mov x20, x1
-; CHECK-FP16-SD-NEXT: mov s0, v0.s[1]
+; CHECK-FP16-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
; CHECK-FP16-SD-NEXT: bl __fixsfti
-; CHECK-FP16-SD-NEXT: cmp x1, #1
+; CHECK-FP16-SD-NEXT: bic x9, x1, x1, asr #63
+; CHECK-FP16-SD-NEXT: cmp x1, #0
+; CHECK-FP16-SD-NEXT: bic x8, x20, x20, asr #63
+; CHECK-FP16-SD-NEXT: csel x10, xzr, x0, mi
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
-; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
-; CHECK-FP16-SD-NEXT: cmp x20, #1
-; CHECK-FP16-SD-NEXT: csinc x10, x20, xzr, lt
-; CHECK-FP16-SD-NEXT: csel x11, x19, xzr, lt
-; CHECK-FP16-SD-NEXT: cmp x10, #0
+; CHECK-FP16-SD-NEXT: cmp x9, #1
+; CHECK-FP16-SD-NEXT: csel x9, x10, xzr, lt
+; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: fmov d0, x9
+; CHECK-FP16-SD-NEXT: csel x9, xzr, x19, mi
+; CHECK-FP16-SD-NEXT: cmp x8, #1
+; CHECK-FP16-SD-NEXT: csel x8, x9, xzr, lt
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-FP16-SD-NEXT: csel x10, xzr, x11, mi
-; CHECK-FP16-SD-NEXT: cmp x9, #0
-; CHECK-FP16-SD-NEXT: csel x8, xzr, x8, mi
-; CHECK-FP16-SD-NEXT: fmov d0, x10
; CHECK-FP16-SD-NEXT: fmov d1, x8
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-FP16-SD-NEXT: add sp, sp, #48
@@ -3430,74 +3490,16 @@ entry:
define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) {
; CHECK-CVT-SD-LABEL: ustest_f16i64_mm:
; CHECK-CVT-SD: // %bb.0: // %entry
-; CHECK-CVT-SD-NEXT: sub sp, sp, #48
-; CHECK-CVT-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-CVT-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-CVT-SD-NEXT: .cfi_def_cfa_offset 48
-; CHECK-CVT-SD-NEXT: .cfi_offset w19, -8
-; CHECK-CVT-SD-NEXT: .cfi_offset w20, -16
-; CHECK-CVT-SD-NEXT: .cfi_offset w30, -32
-; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-CVT-SD-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-CVT-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
-; CHECK-CVT-SD-NEXT: bl __fixhfti
-; CHECK-CVT-SD-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-CVT-SD-NEXT: mov x19, x0
-; CHECK-CVT-SD-NEXT: mov x20, x1
-; CHECK-CVT-SD-NEXT: mov h0, v0.h[1]
-; CHECK-CVT-SD-NEXT: bl __fixhfti
-; CHECK-CVT-SD-NEXT: cmp x1, #1
-; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, lt
-; CHECK-CVT-SD-NEXT: csinc x9, x1, xzr, lt
-; CHECK-CVT-SD-NEXT: cmp x20, #1
-; CHECK-CVT-SD-NEXT: csinc x10, x20, xzr, lt
-; CHECK-CVT-SD-NEXT: csel x11, x19, xzr, lt
-; CHECK-CVT-SD-NEXT: cmp x10, #0
-; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-CVT-SD-NEXT: csel x10, xzr, x11, mi
-; CHECK-CVT-SD-NEXT: cmp x9, #0
-; CHECK-CVT-SD-NEXT: csel x8, xzr, x8, mi
-; CHECK-CVT-SD-NEXT: fmov d0, x10
-; CHECK-CVT-SD-NEXT: fmov d1, x8
-; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-CVT-SD-NEXT: add sp, sp, #48
+; CHECK-CVT-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-CVT-SD-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-CVT-SD-NEXT: ret
;
; CHECK-FP16-SD-LABEL: ustest_f16i64_mm:
; CHECK-FP16-SD: // %bb.0: // %entry
-; CHECK-FP16-SD-NEXT: sub sp, sp, #48
-; CHECK-FP16-SD-NEXT: str x30, [sp, #16] // 8-byte Spill
-; CHECK-FP16-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-FP16-SD-NEXT: .cfi_def_cfa_offset 48
-; CHECK-FP16-SD-NEXT: .cfi_offset w19, -8
-; CHECK-FP16-SD-NEXT: .cfi_offset w20, -16
-; CHECK-FP16-SD-NEXT: .cfi_offset w30, -32
-; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-SD-NEXT: str q0, [sp] // 16-byte Spill
-; CHECK-FP16-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
-; CHECK-FP16-SD-NEXT: bl __fixhfti
-; CHECK-FP16-SD-NEXT: ldr q0, [sp] // 16-byte Reload
-; CHECK-FP16-SD-NEXT: mov x19, x0
-; CHECK-FP16-SD-NEXT: mov x20, x1
-; CHECK-FP16-SD-NEXT: mov h0, v0.h[1]
-; CHECK-FP16-SD-NEXT: bl __fixhfti
-; CHECK-FP16-SD-NEXT: cmp x1, #1
-; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
-; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, lt
-; CHECK-FP16-SD-NEXT: csinc x9, x1, xzr, lt
-; CHECK-FP16-SD-NEXT: cmp x20, #1
-; CHECK-FP16-SD-NEXT: csinc x10, x20, xzr, lt
-; CHECK-FP16-SD-NEXT: csel x11, x19, xzr, lt
-; CHECK-FP16-SD-NEXT: cmp x10, #0
-; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-FP16-SD-NEXT: csel x10, xzr, x11, mi
-; CHECK-FP16-SD-NEXT: cmp x9, #0
-; CHECK-FP16-SD-NEXT: csel x8, xzr, x8, mi
-; CHECK-FP16-SD-NEXT: fmov d0, x10
-; CHECK-FP16-SD-NEXT: fmov d1, x8
-; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-FP16-SD-NEXT: add sp, sp, #48
+; CHECK-FP16-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-FP16-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-FP16-SD-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-FP16-SD-NEXT: ret
;
; CHECK-CVT-GI-LABEL: ustest_f16i64_mm:
diff --git a/llvm/test/CodeGen/AArch64/sat-add.ll b/llvm/test/CodeGen/AArch64/sat-add.ll
index 39f0ca57863b9..55af82dea7196 100644
--- a/llvm/test/CodeGen/AArch64/sat-add.ll
+++ b/llvm/test/CodeGen/AArch64/sat-add.ll
@@ -10,9 +10,9 @@ define i8 @unsigned_sat_constant_i8_using_min(i8 %x) {
; CHECK-LABEL: unsigned_sat_constant_i8_using_min:
; CHECK: // %bb.0:
; CHECK-NEXT: and w9, w0, #0xff
-; CHECK-NEXT: mov w8, #-43 // =0xffffffd5
+; CHECK-NEXT: mov w8, #213 // =0xd5
; CHECK-NEXT: cmp w9, #213
-; CHECK-NEXT: csel w8, w0, w8, lo
+; CHECK-NEXT: csel w8, w9, w8, lo
; CHECK-NEXT: add w0, w8, #42
; CHECK-NEXT: ret
%c = icmp ult i8 %x, -43
@@ -53,9 +53,9 @@ define i16 @unsigned_sat_constant_i16_using_min(i16 %x) {
; CHECK-LABEL: unsigned_sat_constant_i16_using_min:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #65493 // =0xffd5
-; CHECK-NEXT: cmp w8, w0, uxth
-; CHECK-NEXT: mov w8, #-43 // =0xffffffd5
-; CHECK-NEXT: csel w8, w0, w8, hi
+; CHECK-NEXT: and w9, w0, #0xffff
+; CHECK-NEXT: cmp w9, w8
+; CHECK-NEXT: csel w8, w9, w8, lo
; CHECK-NEXT: add w0, w8, #42
; CHECK-NEXT: ret
%c = icmp ult i16 %x, -43
@@ -171,10 +171,11 @@ define i64 @unsigned_sat_constant_i64_using_cmp_notval(i64 %x) {
define i8 @unsigned_sat_variable_i8_using_min(i8 %x, i8 %y) {
; CHECK-LABEL: unsigned_sat_variable_i8_using_min:
; CHECK: // %bb.0:
-; CHECK-NEXT: and w8, w0, #0xff
-; CHECK-NEXT: mvn w9, w1
-; CHECK-NEXT: cmp w8, w9, uxtb
-; CHECK-NEXT: csinv w8, w0, w1, lo
+; CHECK-NEXT: mov w8, #255 // =0xff
+; CHECK-NEXT: and w9, w0, #0xff
+; CHECK-NEXT: bic w8, w8, w1
+; CHECK-NEXT: cmp w9, w8
+; CHECK-NEXT: csel w8, w9, w8, lo
; CHECK-NEXT: add w0, w8, w1
; CHECK-NEXT: ret
%noty = xor i8 %y, -1
@@ -217,10 +218,11 @@ define i8 @unsigned_sat_variable_i8_using_cmp_notval(i8 %x, i8 %y) {
define i16 @unsigned_sat_variable_i16_using_min(i16 %x, i16 %y) {
; CHECK-LABEL: unsigned_sat_variable_i16_using_min:
; CHECK: // %bb.0:
-; CHECK-NEXT: and w8, w0, #0xffff
-; CHECK-NEXT: mvn w9, w1
-; CHECK-NEXT: cmp w8, w9, uxth
-; CHECK-NEXT: csinv w8, w0, w1, lo
+; CHECK-NEXT: mov w8, #65535 // =0xffff
+; CHECK-NEXT: and w9, w0, #0xffff
+; CHECK-NEXT: bic w8, w8, w1
+; CHECK-NEXT: cmp w9, w8
+; CHECK-NEXT: csel w8, w9, w8, lo
; CHECK-NEXT: add w0, w8, w1
; CHECK-NEXT: ret
%noty = xor i16 %y, -1
diff --git a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
index 1b7ef739c9479..d3109cdb3a5c8 100644
--- a/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
+++ b/llvm/test/CodeGen/AMDGPU/a-v-flat-atomicrmw.ll
@@ -7633,7 +7633,7 @@ define void @flat_atomic_min_i64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: s_waitcnt vmcnt(1)
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_cmp_le_i64_e32 vcc, v[2:3], v[0:1]
+; GFX90A-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[0:1]
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
@@ -7679,7 +7679,7 @@ define void @flat_atomic_min_i64_ret_a_a(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v2, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[2:3], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_cmp_le_i64_e32 vcc, v[2:3], v[0:1]
+; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[0:1]
; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_accvgpr_write_b32 a1, v3
; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
@@ -7728,7 +7728,7 @@ define void @flat_atomic_min_i64_ret_av_av(ptr %ptr) #0 {
; GFX90A-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GFX90A-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GFX90A-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX90A-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -7769,7 +7769,7 @@ define void @flat_atomic_min_i64_ret_av_av(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
@@ -8013,7 +8013,7 @@ define void @flat_atomic_umin_i64_ret_a_a(ptr %ptr) #0 {
; GFX90A-NEXT: s_waitcnt vmcnt(1)
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_cmp_le_u64_e32 vcc, v[2:3], v[0:1]
+; GFX90A-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
@@ -8059,7 +8059,7 @@ define void @flat_atomic_umin_i64_ret_a_a(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v2, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[2:3], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_cmp_le_u64_e32 vcc, v[2:3], v[0:1]
+; GFX950-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_accvgpr_write_b32 a1, v3
; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
@@ -8108,7 +8108,7 @@ define void @flat_atomic_umin_i64_ret_av_av(ptr %ptr) #0 {
; GFX90A-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GFX90A-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GFX90A-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GFX90A-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX90A-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -8149,7 +8149,7 @@ define void @flat_atomic_umin_i64_ret_av_av(ptr %ptr) #0 {
; GFX950-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GFX950-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
@@ -16007,7 +16007,7 @@ define void @flat_atomic_min_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_waitcnt vmcnt(1)
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_cmp_le_i64_e32 vcc, v[2:3], v[0:1]
+; GFX90A-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[0:1]
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
@@ -16051,7 +16051,7 @@ define void @flat_atomic_min_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_cselect_b32 s0, s0, -1
; GFX950-NEXT: scratch_load_dwordx2 v[2:3], off, s0
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_cmp_le_i64_e32 vcc, v[2:3], v[0:1]
+; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[0:1]
; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_accvgpr_write_b32 a1, v3
; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
@@ -16099,7 +16099,7 @@ define void @flat_atomic_min_i64_saddr_ret_av_av(ptr inreg %ptr) #0 {
; GFX90A-NEXT: buffer_load_dword v2, v4, s[0:3], 0 offen
; GFX90A-NEXT: buffer_load_dword v3, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_cmp_le_i64_e32 vcc, v[2:3], v[0:1]
+; GFX90A-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[0:1]
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX90A-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -16137,7 +16137,7 @@ define void @flat_atomic_min_i64_saddr_ret_av_av(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_cselect_b32 s0, s0, -1
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], off, s0
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GFX950-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
@@ -16375,7 +16375,7 @@ define void @flat_atomic_umin_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX90A-NEXT: s_waitcnt vmcnt(1)
; GFX90A-NEXT: v_accvgpr_write_b32 a0, v2
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_cmp_le_u64_e32 vcc, v[2:3], v[0:1]
+; GFX90A-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX90A-NEXT: v_accvgpr_write_b32 a1, v3
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
@@ -16419,7 +16419,7 @@ define void @flat_atomic_umin_i64_saddr_ret_a_a(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_cselect_b32 s0, s0, -1
; GFX950-NEXT: scratch_load_dwordx2 v[2:3], off, s0
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_cmp_le_u64_e32 vcc, v[2:3], v[0:1]
+; GFX950-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
; GFX950-NEXT: v_accvgpr_write_b32 a0, v2
; GFX950-NEXT: v_accvgpr_write_b32 a1, v3
; GFX950-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
@@ -16467,7 +16467,7 @@ define void @flat_atomic_umin_i64_saddr_ret_av_av(ptr inreg %ptr) #0 {
; GFX90A-NEXT: buffer_load_dword v2, v4, s[0:3], 0 offen
; GFX90A-NEXT: buffer_load_dword v3, v4, s[0:3], 0 offen offset:4
; GFX90A-NEXT: s_waitcnt vmcnt(0)
-; GFX90A-NEXT: v_cmp_le_u64_e32 vcc, v[2:3], v[0:1]
+; GFX90A-NEXT: v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX90A-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX90A-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -16505,7 +16505,7 @@ define void @flat_atomic_umin_i64_saddr_ret_av_av(ptr inreg %ptr) #0 {
; GFX950-NEXT: s_cselect_b32 s0, s0, -1
; GFX950-NEXT: scratch_load_dwordx2 v[0:1], off, s0
; GFX950-NEXT: s_waitcnt vmcnt(0)
-; GFX950-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GFX950-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GFX950-NEXT: s_nop 1
; GFX950-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX950-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
index 199a65b52a858..9e642c7e35a36 100644
--- a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll
@@ -6927,7 +6927,7 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn(ptr inreg %sbase, i32 %voff
; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-SDAG-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GFX950-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX950-SDAG-NEXT: s_nop 1
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
@@ -7117,7 +7117,7 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn_neg128(ptr inreg %sbase, i3
; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-SDAG-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GFX950-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX950-SDAG-NEXT: s_nop 1
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
@@ -7283,7 +7283,7 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-SDAG-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GFX950-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX950-SDAG-NEXT: s_nop 1
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -7441,7 +7441,7 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-SDAG-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GFX950-SDAG-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GFX950-SDAG-NEXT: s_nop 1
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -8587,7 +8587,7 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn(ptr inreg %sbase, i32 %vof
; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-SDAG-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GFX950-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GFX950-SDAG-NEXT: s_nop 1
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
@@ -8777,7 +8777,7 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn_neg128(ptr inreg %sbase, i
; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX950-SDAG-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GFX950-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GFX950-SDAG-NEXT: s_nop 1
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
@@ -8943,7 +8943,7 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset,
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-SDAG-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GFX950-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GFX950-SDAG-NEXT: s_nop 1
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
@@ -9101,7 +9101,7 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v4, -1, v0, vcc
; GFX950-SDAG-NEXT: scratch_load_dwordx2 v[0:1], v4, off
; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0)
-; GFX950-SDAG-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GFX950-SDAG-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GFX950-SDAG-NEXT: s_nop 1
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX950-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
index 25fbdbc83b2b9..ee0f70f6f3bc9 100644
--- a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
@@ -5859,7 +5859,7 @@ define amdgpu_kernel void @atomic_min_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s3
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[12:15], 0 offen
@@ -5908,7 +5908,7 @@ define amdgpu_kernel void @atomic_min_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: v_mov_b32_e32 v5, s2
; GCN2-NEXT: v_mov_b32_e32 v4, s3
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[88:91], 0 offen
@@ -5944,7 +5944,7 @@ define amdgpu_kernel void @atomic_min_i64_offset(ptr %out, i64 %in) {
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_i64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX12-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v1, s3, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v0, s2, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s0
@@ -5997,7 +5997,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s5
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[12:15], 0 offen
@@ -6049,7 +6049,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: v_mov_b32_e32 v5, s4
; GCN2-NEXT: v_mov_b32_e32 v4, s5
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[88:91], 0 offen
@@ -6089,7 +6089,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_i64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX12-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v3, s5, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s0
@@ -6152,7 +6152,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s3
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[12:15], 0 offen
@@ -6205,7 +6205,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN2-NEXT: v_mov_b32_e32 v5, s2
; GCN2-NEXT: v_mov_b32_e32 v4, s3
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[88:91], 0 offen
@@ -6246,7 +6246,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_i64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX12-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v1, s3, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v0, s2, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s0
@@ -6302,7 +6302,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN1-NEXT: buffer_load_dword v1, v3, s[16:19], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s13
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[16:19], 0 offen
@@ -6356,7 +6356,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN2-NEXT: v_mov_b32_e32 v5, s12
; GCN2-NEXT: v_mov_b32_e32 v4, s13
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[88:91], 0 offen
@@ -6397,7 +6397,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_i64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX12-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v3, s5, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s0
@@ -6455,7 +6455,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s3
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[12:15], 0 offen
@@ -6502,7 +6502,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GCN2-NEXT: v_mov_b32_e32 v5, s2
; GCN2-NEXT: v_mov_b32_e32 v4, s3
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[88:91], 0 offen
@@ -6537,7 +6537,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_i64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX12-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v1, s3, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v0, s2, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s0
@@ -6587,7 +6587,7 @@ define amdgpu_kernel void @atomic_min_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s5
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[12:15], 0 offen
@@ -6637,7 +6637,7 @@ define amdgpu_kernel void @atomic_min_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: v_mov_b32_e32 v5, s4
; GCN2-NEXT: v_mov_b32_e32 v4, s5
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[88:91], 0 offen
@@ -6676,7 +6676,7 @@ define amdgpu_kernel void @atomic_min_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_i64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX12-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v3, s5, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s0
@@ -6736,7 +6736,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s3
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[12:15], 0 offen
@@ -6787,7 +6787,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN2-NEXT: v_mov_b32_e32 v5, s2
; GCN2-NEXT: v_mov_b32_e32 v4, s3
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[88:91], 0 offen
@@ -6827,7 +6827,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64(ptr %out, i64 %in, i64 %index)
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_i64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX12-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v1, s3, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v0, s2, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s0
@@ -6880,7 +6880,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: buffer_load_dword v1, v3, s[16:19], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s13
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[16:19], 0 offen
@@ -6932,7 +6932,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: v_mov_b32_e32 v5, s12
; GCN2-NEXT: v_mov_b32_e32 v4, s13
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[88:91], 0 offen
@@ -6972,7 +6972,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_i64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX12-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v3, s5, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s0
@@ -7031,7 +7031,7 @@ define amdgpu_kernel void @atomic_umin_i64_offset(ptr %out, i64 %in) {
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s3
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[0:1]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[12:15], 0 offen
@@ -7080,7 +7080,7 @@ define amdgpu_kernel void @atomic_umin_i64_offset(ptr %out, i64 %in) {
; GCN2-NEXT: v_mov_b32_e32 v5, s2
; GCN2-NEXT: v_mov_b32_e32 v4, s3
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[0:1]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[88:91], 0 offen
@@ -7116,7 +7116,7 @@ define amdgpu_kernel void @atomic_umin_i64_offset(ptr %out, i64 %in) {
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v1, s3, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v0, s2, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s0
@@ -7169,7 +7169,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_offset(ptr %out, ptr %out2, i64 %
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s5
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[0:1]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[12:15], 0 offen
@@ -7221,7 +7221,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_offset(ptr %out, ptr %out2, i64 %
; GCN2-NEXT: v_mov_b32_e32 v5, s4
; GCN2-NEXT: v_mov_b32_e32 v4, s5
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[0:1]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[88:91], 0 offen
@@ -7261,7 +7261,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_offset(ptr %out, ptr %out2, i64 %
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v3, s5, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s0
@@ -7324,7 +7324,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64_offset(ptr %out, i64 %in, i64
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s3
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[0:1]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[12:15], 0 offen
@@ -7377,7 +7377,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64_offset(ptr %out, i64 %in, i64
; GCN2-NEXT: v_mov_b32_e32 v5, s2
; GCN2-NEXT: v_mov_b32_e32 v4, s3
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[0:1]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[88:91], 0 offen
@@ -7418,7 +7418,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64_offset(ptr %out, i64 %in, i64
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v1, s3, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v0, s2, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s0
@@ -7474,7 +7474,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(ptr %out, ptr %out2
; GCN1-NEXT: buffer_load_dword v1, v3, s[16:19], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s13
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[12:13], v[0:1]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[12:13], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[16:19], 0 offen
@@ -7528,7 +7528,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(ptr %out, ptr %out2
; GCN2-NEXT: v_mov_b32_e32 v5, s12
; GCN2-NEXT: v_mov_b32_e32 v4, s13
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[12:13], v[0:1]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[12:13], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[88:91], 0 offen
@@ -7569,7 +7569,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(ptr %out, ptr %out2
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v3, s5, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s0
@@ -7627,7 +7627,7 @@ define amdgpu_kernel void @atomic_umin_i64(ptr %out, i64 %in) {
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s3
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[0:1]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[12:15], 0 offen
@@ -7674,7 +7674,7 @@ define amdgpu_kernel void @atomic_umin_i64(ptr %out, i64 %in) {
; GCN2-NEXT: v_mov_b32_e32 v5, s2
; GCN2-NEXT: v_mov_b32_e32 v4, s3
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[0:1]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[88:91], 0 offen
@@ -7709,7 +7709,7 @@ define amdgpu_kernel void @atomic_umin_i64(ptr %out, i64 %in) {
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v1, s3, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v0, s2, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s0
@@ -7759,7 +7759,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s5
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[0:1]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[12:15], 0 offen
@@ -7809,7 +7809,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GCN2-NEXT: v_mov_b32_e32 v5, s4
; GCN2-NEXT: v_mov_b32_e32 v4, s5
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[0:1]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[88:91], 0 offen
@@ -7848,7 +7848,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v3, s5, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s0
@@ -7908,7 +7908,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s3
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[0:1]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[12:15], 0 offen
@@ -7959,7 +7959,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64(ptr %out, i64 %in, i64 %index)
; GCN2-NEXT: v_mov_b32_e32 v5, s2
; GCN2-NEXT: v_mov_b32_e32 v4, s3
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[0:1]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[88:91], 0 offen
@@ -7999,7 +7999,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64(ptr %out, i64 %in, i64 %index)
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[2:3], v[0:1]
+; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v1, s3, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v0, s2, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[0:1], s0
@@ -8052,7 +8052,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64(ptr %out, ptr %out2, i64 %
; GCN1-NEXT: buffer_load_dword v1, v3, s[16:19], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s13
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[12:13], v[0:1]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[12:13], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[16:19], 0 offen
@@ -8104,7 +8104,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64(ptr %out, ptr %out2, i64 %
; GCN2-NEXT: v_mov_b32_e32 v5, s12
; GCN2-NEXT: v_mov_b32_e32 v4, s13
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[12:13], v[0:1]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[12:13], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[88:91], 0 offen
@@ -8144,7 +8144,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64(ptr %out, ptr %out2, i64 %
; GFX12-NEXT: s_cselect_b32 s0, s0, -1
; GFX12-NEXT: scratch_load_b64 v[0:1], off, s0
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[0:1]
+; GFX12-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1]
; GFX12-NEXT: v_cndmask_b32_e32 v3, s5, v1, vcc_lo
; GFX12-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo
; GFX12-NEXT: scratch_store_b64 off, v[2:3], s0
diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
index 35ee77bce12f6..6c820e9cf9bb4 100644
--- a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_noprivate.ll
@@ -3236,7 +3236,7 @@ define amdgpu_kernel void @atomic_min_i64_offset(ptr %out, i64 %in) {
; GFX7-NEXT: .LBB40_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -3266,7 +3266,7 @@ define amdgpu_kernel void @atomic_min_i64_offset(ptr %out, i64 %in) {
; GFX8-NEXT: .LBB40_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -3316,7 +3316,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v3
; GFX7-NEXT: v_mov_b32_e32 v8, v2
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -3351,7 +3351,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_offset(ptr %out, ptr %out2, i64 %i
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v3
; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -3409,7 +3409,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GFX7-NEXT: .LBB42_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -3443,7 +3443,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GFX8-NEXT: .LBB42_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -3501,7 +3501,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v3
; GFX7-NEXT: v_mov_b32_e32 v8, v2
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -3538,7 +3538,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v3
; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -3594,7 +3594,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GFX7-NEXT: .LBB44_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -3624,7 +3624,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GFX8-NEXT: .LBB44_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -3673,7 +3673,7 @@ define amdgpu_kernel void @atomic_min_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v1
; GFX7-NEXT: v_mov_b32_e32 v8, v0
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -3708,7 +3708,7 @@ define amdgpu_kernel void @atomic_min_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v1
; GFX8-NEXT: v_mov_b32_e32 v8, v0
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -3763,7 +3763,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64(ptr %out, i64 %in, i64 %index)
; GFX7-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -3795,7 +3795,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64(ptr %out, i64 %in, i64 %index)
; GFX8-NEXT: .LBB46_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -3850,7 +3850,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v3
; GFX7-NEXT: v_mov_b32_e32 v8, v2
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -3885,7 +3885,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v3
; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -3940,7 +3940,7 @@ define amdgpu_kernel void @atomic_umin_i64_offset(ptr %out, i64 %in) {
; GFX7-NEXT: .LBB48_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[2:3]
+; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -3970,7 +3970,7 @@ define amdgpu_kernel void @atomic_umin_i64_offset(ptr %out, i64 %in) {
; GFX8-NEXT: .LBB48_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -4020,7 +4020,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_offset(ptr %out, ptr %out2, i64 %
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v3
; GFX7-NEXT: v_mov_b32_e32 v8, v2
-; GFX7-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[8:9]
+; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -4055,7 +4055,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_offset(ptr %out, ptr %out2, i64 %
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v3
; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[8:9]
+; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -4113,7 +4113,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64_offset(ptr %out, i64 %in, i64
; GFX7-NEXT: .LBB50_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[2:3]
+; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -4147,7 +4147,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64_offset(ptr %out, i64 %in, i64
; GFX8-NEXT: .LBB50_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -4205,7 +4205,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(ptr %out, ptr %out2
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v3
; GFX7-NEXT: v_mov_b32_e32 v8, v2
-; GFX7-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[8:9]
+; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -4242,7 +4242,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(ptr %out, ptr %out2
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v3
; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[8:9]
+; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -4298,7 +4298,7 @@ define amdgpu_kernel void @atomic_umin_i64(ptr %out, i64 %in) {
; GFX7-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[2:3]
+; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -4328,7 +4328,7 @@ define amdgpu_kernel void @atomic_umin_i64(ptr %out, i64 %in) {
; GFX8-NEXT: .LBB52_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -4377,7 +4377,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v1
; GFX7-NEXT: v_mov_b32_e32 v8, v0
-; GFX7-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[8:9]
+; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -4412,7 +4412,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret(ptr %out, ptr %out2, i64 %in) {
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v1
; GFX8-NEXT: v_mov_b32_e32 v8, v0
-; GFX8-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[8:9]
+; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -4467,7 +4467,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64(ptr %out, i64 %in, i64 %index)
; GFX7-NEXT: .LBB54_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[2:3]
+; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -4499,7 +4499,7 @@ define amdgpu_kernel void @atomic_umin_i64_addr64(ptr %out, i64 %in, i64 %index)
; GFX8-NEXT: .LBB54_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -4554,7 +4554,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64(ptr %out, ptr %out2, i64 %
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v3
; GFX7-NEXT: v_mov_b32_e32 v8, v2
-; GFX7-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[8:9]
+; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -4589,7 +4589,7 @@ define amdgpu_kernel void @atomic_umin_i64_ret_addr64(ptr %out, ptr %out2, i64 %
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v3
; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_cmp_ge_u64_e32 vcc, s[4:5], v[8:9]
+; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
index 9e27f6badfdac..e92b9166c6837 100644
--- a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system.ll
@@ -17324,7 +17324,7 @@ define void @flat_atomic_umin_i64_noret(ptr %ptr, i64 %in) {
; GCN1-NEXT: .LBB107_4: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GCN1-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -17349,7 +17349,7 @@ define void @flat_atomic_umin_i64_noret(ptr %ptr, i64 %in) {
; GCN1-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN1-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN1-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -17383,7 +17383,7 @@ define void @flat_atomic_umin_i64_noret(ptr %ptr, i64 %in) {
; GCN2-NEXT: .LBB107_4: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GCN2-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -17408,7 +17408,7 @@ define void @flat_atomic_umin_i64_noret(ptr %ptr, i64 %in) {
; GCN2-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN2-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN2-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -17437,7 +17437,7 @@ define void @flat_atomic_umin_i64_noret(ptr %ptr, i64 %in) {
; GCN3-NEXT: .LBB107_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GCN3-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -17461,7 +17461,7 @@ define void @flat_atomic_umin_i64_noret(ptr %ptr, i64 %in) {
; GCN3-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN3-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN3-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -17501,7 +17501,7 @@ define void @flat_atomic_umin_i64_noret_offset(ptr %out, i64 %in) {
; GCN1-NEXT: .LBB108_4: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GCN1-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -17526,7 +17526,7 @@ define void @flat_atomic_umin_i64_noret_offset(ptr %out, i64 %in) {
; GCN1-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN1-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN1-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -17562,7 +17562,7 @@ define void @flat_atomic_umin_i64_noret_offset(ptr %out, i64 %in) {
; GCN2-NEXT: .LBB108_4: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GCN2-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -17587,7 +17587,7 @@ define void @flat_atomic_umin_i64_noret_offset(ptr %out, i64 %in) {
; GCN2-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN2-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN2-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -17618,7 +17618,7 @@ define void @flat_atomic_umin_i64_noret_offset(ptr %out, i64 %in) {
; GCN3-NEXT: .LBB108_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GCN3-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -17642,7 +17642,7 @@ define void @flat_atomic_umin_i64_noret_offset(ptr %out, i64 %in) {
; GCN3-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN3-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN3-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -17678,7 +17678,7 @@ define i64 @flat_atomic_umin_i64_ret(ptr %ptr, i64 %in) {
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v7, v5
; GCN1-NEXT: v_mov_b32_e32 v6, v4
-; GCN1-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GCN1-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -17702,7 +17702,7 @@ define i64 @flat_atomic_umin_i64_ret(ptr %ptr, i64 %in) {
; GCN1-NEXT: buffer_load_dword v4, v0, s[0:3], 0 offen
; GCN1-NEXT: buffer_load_dword v5, v1, s[0:3], 0 offen
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_le_u64_e32 vcc, v[4:5], v[2:3]
+; GCN1-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GCN1-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
@@ -17736,7 +17736,7 @@ define i64 @flat_atomic_umin_i64_ret(ptr %ptr, i64 %in) {
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v7, v5
; GCN2-NEXT: v_mov_b32_e32 v6, v4
-; GCN2-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GCN2-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -17760,7 +17760,7 @@ define i64 @flat_atomic_umin_i64_ret(ptr %ptr, i64 %in) {
; GCN2-NEXT: buffer_load_dword v4, v0, s[0:3], 0 offen
; GCN2-NEXT: buffer_load_dword v5, v1, s[0:3], 0 offen
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_le_u64_e32 vcc, v[4:5], v[2:3]
+; GCN2-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GCN2-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
@@ -17797,7 +17797,7 @@ define i64 @flat_atomic_umin_i64_ret(ptr %ptr, i64 %in) {
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
-; GCN3-NEXT: v_cmp_le_u64_e32 vcc, v[8:9], v[2:3]
+; GCN3-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -17819,7 +17819,7 @@ define i64 @flat_atomic_umin_i64_ret(ptr %ptr, i64 %in) {
; GCN3-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN3-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN3-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -17862,7 +17862,7 @@ define i64 @flat_atomic_umin_i64_ret_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v9, v1
; GCN1-NEXT: v_mov_b32_e32 v8, v0
-; GCN1-NEXT: v_cmp_le_u64_e32 vcc, v[8:9], v[2:3]
+; GCN1-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -17885,7 +17885,7 @@ define i64 @flat_atomic_umin_i64_ret_offset(ptr %out, i64 %in) {
; GCN1-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN1-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN1-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN1-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -17924,7 +17924,7 @@ define i64 @flat_atomic_umin_i64_ret_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v9, v1
; GCN2-NEXT: v_mov_b32_e32 v8, v0
-; GCN2-NEXT: v_cmp_le_u64_e32 vcc, v[8:9], v[2:3]
+; GCN2-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -17947,7 +17947,7 @@ define i64 @flat_atomic_umin_i64_ret_offset(ptr %out, i64 %in) {
; GCN2-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN2-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN2-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN2-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -17981,7 +17981,7 @@ define i64 @flat_atomic_umin_i64_ret_offset(ptr %out, i64 %in) {
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
-; GCN3-NEXT: v_cmp_le_u64_e32 vcc, v[8:9], v[2:3]
+; GCN3-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -18003,7 +18003,7 @@ define i64 @flat_atomic_umin_i64_ret_offset(ptr %out, i64 %in) {
; GCN3-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN3-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN3-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -18048,7 +18048,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_scalar(ptr inreg %ptr, i64 in
; GCN1-NEXT: .LBB111_4: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -18075,7 +18075,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_scalar(ptr inreg %ptr, i64 in
; GCN1-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s7
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[0:1]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
@@ -18114,7 +18114,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_scalar(ptr inreg %ptr, i64 in
; GCN2-NEXT: .LBB111_4: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -18140,7 +18140,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_scalar(ptr inreg %ptr, i64 in
; GCN2-NEXT: v_mov_b32_e32 v5, s6
; GCN2-NEXT: v_mov_b32_e32 v4, s7
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[0:1]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
@@ -18172,7 +18172,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_scalar(ptr inreg %ptr, i64 in
; GCN3-NEXT: .LBB111_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GCN3-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -18196,7 +18196,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_scalar(ptr inreg %ptr, i64 in
; GCN3-NEXT: v_mov_b32_e32 v4, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[0:1]
+; GCN3-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[0:1]
; GCN3-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
@@ -18241,7 +18241,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_offset_scalar(ptr inreg %out,
; GCN1-NEXT: .LBB112_4: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -18268,7 +18268,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_offset_scalar(ptr inreg %out,
; GCN1-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s7
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[0:1]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
@@ -18309,7 +18309,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_offset_scalar(ptr inreg %out,
; GCN2-NEXT: .LBB112_4: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -18335,7 +18335,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_offset_scalar(ptr inreg %out,
; GCN2-NEXT: v_mov_b32_e32 v5, s6
; GCN2-NEXT: v_mov_b32_e32 v4, s7
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[0:1]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
@@ -18369,7 +18369,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_offset_scalar(ptr inreg %out,
; GCN3-NEXT: .LBB112_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GCN3-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -18393,7 +18393,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_offset_scalar(ptr inreg %out,
; GCN3-NEXT: v_mov_b32_e32 v4, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[0:1]
+; GCN3-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[0:1]
; GCN3-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
@@ -18433,7 +18433,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v9, v1
; GCN1-NEXT: v_mov_b32_e32 v8, v0
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; GCN1-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -18461,7 +18461,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN1-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s7
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[0:1]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[0:3], 0 offen
@@ -18497,7 +18497,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v9, v1
; GCN2-NEXT: v_mov_b32_e32 v8, v0
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; GCN2-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -18524,7 +18524,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN2-NEXT: v_mov_b32_e32 v5, s6
; GCN2-NEXT: v_mov_b32_e32 v4, s7
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[0:1]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[0:3], 0 offen
@@ -18553,7 +18553,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
-; GCN3-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; GCN3-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; GCN3-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -18578,7 +18578,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN3-NEXT: v_mov_b32_e32 v4, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[0:1]
+; GCN3-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[0:1]
; GCN3-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
@@ -18620,7 +18620,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_offset_scalar(ptr inreg %out, i6
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v9, v1
; GCN1-NEXT: v_mov_b32_e32 v8, v0
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; GCN1-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -18648,7 +18648,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_offset_scalar(ptr inreg %out, i6
; GCN1-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s7
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[0:1]
+; GCN1-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[0:3], 0 offen
@@ -18686,7 +18686,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_offset_scalar(ptr inreg %out, i6
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v9, v1
; GCN2-NEXT: v_mov_b32_e32 v8, v0
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; GCN2-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -18713,7 +18713,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_offset_scalar(ptr inreg %out, i6
; GCN2-NEXT: v_mov_b32_e32 v5, s6
; GCN2-NEXT: v_mov_b32_e32 v4, s7
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[0:1]
+; GCN2-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[0:3], 0 offen
@@ -18744,7 +18744,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_offset_scalar(ptr inreg %out, i6
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
-; GCN3-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; GCN3-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; GCN3-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -18769,7 +18769,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_offset_scalar(ptr inreg %out, i6
; GCN3-NEXT: v_mov_b32_e32 v4, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[0:1]
+; GCN3-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[0:1]
; GCN3-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
@@ -18816,7 +18816,7 @@ define void @flat_atomic_umin_i64_noret_offset__amdgpu_no_remote_memory(ptr %out
; GCN1-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN1-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN1-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -18858,7 +18858,7 @@ define void @flat_atomic_umin_i64_noret_offset__amdgpu_no_remote_memory(ptr %out
; GCN2-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN2-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN2-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -18897,7 +18897,7 @@ define void @flat_atomic_umin_i64_noret_offset__amdgpu_no_remote_memory(ptr %out
; GCN3-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN3-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN3-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -18945,7 +18945,7 @@ define i64 @flat_atomic_umin_i64_ret_offset__amdgpu_no_remote_memory(ptr %out, i
; GCN1-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN1-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN1-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN1-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -18988,7 +18988,7 @@ define i64 @flat_atomic_umin_i64_ret_offset__amdgpu_no_remote_memory(ptr %out, i
; GCN2-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN2-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN2-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN2-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -19028,7 +19028,7 @@ define i64 @flat_atomic_umin_i64_ret_offset__amdgpu_no_remote_memory(ptr %out, i
; GCN3-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN3-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_le_u64_e32 vcc, v[0:1], v[2:3]
+; GCN3-NEXT: v_cmp_lt_u64_e32 vcc, v[0:1], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -19071,7 +19071,7 @@ define void @flat_atomic_min_i64_noret(ptr %ptr, i64 %in) {
; GCN1-NEXT: .LBB117_4: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GCN1-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -19096,7 +19096,7 @@ define void @flat_atomic_min_i64_noret(ptr %ptr, i64 %in) {
; GCN1-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN1-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN1-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -19130,7 +19130,7 @@ define void @flat_atomic_min_i64_noret(ptr %ptr, i64 %in) {
; GCN2-NEXT: .LBB117_4: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GCN2-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -19155,7 +19155,7 @@ define void @flat_atomic_min_i64_noret(ptr %ptr, i64 %in) {
; GCN2-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN2-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN2-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -19184,7 +19184,7 @@ define void @flat_atomic_min_i64_noret(ptr %ptr, i64 %in) {
; GCN3-NEXT: .LBB117_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GCN3-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -19208,7 +19208,7 @@ define void @flat_atomic_min_i64_noret(ptr %ptr, i64 %in) {
; GCN3-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN3-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN3-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -19248,7 +19248,7 @@ define void @flat_atomic_min_i64_noret_offset(ptr %out, i64 %in) {
; GCN1-NEXT: .LBB118_4: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GCN1-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -19273,7 +19273,7 @@ define void @flat_atomic_min_i64_noret_offset(ptr %out, i64 %in) {
; GCN1-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN1-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN1-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -19309,7 +19309,7 @@ define void @flat_atomic_min_i64_noret_offset(ptr %out, i64 %in) {
; GCN2-NEXT: .LBB118_4: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GCN2-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -19334,7 +19334,7 @@ define void @flat_atomic_min_i64_noret_offset(ptr %out, i64 %in) {
; GCN2-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN2-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN2-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -19365,7 +19365,7 @@ define void @flat_atomic_min_i64_noret_offset(ptr %out, i64 %in) {
; GCN3-NEXT: .LBB118_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GCN3-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -19389,7 +19389,7 @@ define void @flat_atomic_min_i64_noret_offset(ptr %out, i64 %in) {
; GCN3-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN3-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN3-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -19425,7 +19425,7 @@ define i64 @flat_atomic_min_i64_ret(ptr %ptr, i64 %in) {
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v7, v5
; GCN1-NEXT: v_mov_b32_e32 v6, v4
-; GCN1-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GCN1-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -19449,7 +19449,7 @@ define i64 @flat_atomic_min_i64_ret(ptr %ptr, i64 %in) {
; GCN1-NEXT: buffer_load_dword v4, v0, s[0:3], 0 offen
; GCN1-NEXT: buffer_load_dword v5, v1, s[0:3], 0 offen
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_le_i64_e32 vcc, v[4:5], v[2:3]
+; GCN1-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GCN1-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
@@ -19483,7 +19483,7 @@ define i64 @flat_atomic_min_i64_ret(ptr %ptr, i64 %in) {
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v7, v5
; GCN2-NEXT: v_mov_b32_e32 v6, v4
-; GCN2-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GCN2-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -19507,7 +19507,7 @@ define i64 @flat_atomic_min_i64_ret(ptr %ptr, i64 %in) {
; GCN2-NEXT: buffer_load_dword v4, v0, s[0:3], 0 offen
; GCN2-NEXT: buffer_load_dword v5, v1, s[0:3], 0 offen
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_le_i64_e32 vcc, v[4:5], v[2:3]
+; GCN2-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc
; GCN2-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
@@ -19544,7 +19544,7 @@ define i64 @flat_atomic_min_i64_ret(ptr %ptr, i64 %in) {
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
-; GCN3-NEXT: v_cmp_le_i64_e32 vcc, v[8:9], v[2:3]
+; GCN3-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -19566,7 +19566,7 @@ define i64 @flat_atomic_min_i64_ret(ptr %ptr, i64 %in) {
; GCN3-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN3-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN3-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -19609,7 +19609,7 @@ define i64 @flat_atomic_min_i64_ret_offset(ptr %out, i64 %in) {
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v9, v1
; GCN1-NEXT: v_mov_b32_e32 v8, v0
-; GCN1-NEXT: v_cmp_le_i64_e32 vcc, v[8:9], v[2:3]
+; GCN1-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -19632,7 +19632,7 @@ define i64 @flat_atomic_min_i64_ret_offset(ptr %out, i64 %in) {
; GCN1-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN1-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN1-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN1-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -19671,7 +19671,7 @@ define i64 @flat_atomic_min_i64_ret_offset(ptr %out, i64 %in) {
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v9, v1
; GCN2-NEXT: v_mov_b32_e32 v8, v0
-; GCN2-NEXT: v_cmp_le_i64_e32 vcc, v[8:9], v[2:3]
+; GCN2-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -19694,7 +19694,7 @@ define i64 @flat_atomic_min_i64_ret_offset(ptr %out, i64 %in) {
; GCN2-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN2-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN2-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN2-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -19728,7 +19728,7 @@ define i64 @flat_atomic_min_i64_ret_offset(ptr %out, i64 %in) {
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
-; GCN3-NEXT: v_cmp_le_i64_e32 vcc, v[8:9], v[2:3]
+; GCN3-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -19750,7 +19750,7 @@ define i64 @flat_atomic_min_i64_ret_offset(ptr %out, i64 %in) {
; GCN3-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN3-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN3-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -19795,7 +19795,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GCN1-NEXT: .LBB121_4: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -19822,7 +19822,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GCN1-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s7
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
@@ -19861,7 +19861,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GCN2-NEXT: .LBB121_4: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -19887,7 +19887,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GCN2-NEXT: v_mov_b32_e32 v5, s6
; GCN2-NEXT: v_mov_b32_e32 v4, s7
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
@@ -19919,7 +19919,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GCN3-NEXT: .LBB121_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -19943,7 +19943,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GCN3-NEXT: v_mov_b32_e32 v4, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[0:1]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[0:1]
; GCN3-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
@@ -19988,7 +19988,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_offset_scalar(ptr inreg %out,
; GCN1-NEXT: .LBB122_4: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -20015,7 +20015,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_offset_scalar(ptr inreg %out,
; GCN1-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s7
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
@@ -20056,7 +20056,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_offset_scalar(ptr inreg %out,
; GCN2-NEXT: .LBB122_4: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -20082,7 +20082,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_offset_scalar(ptr inreg %out,
; GCN2-NEXT: v_mov_b32_e32 v5, s6
; GCN2-NEXT: v_mov_b32_e32 v4, s7
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
@@ -20116,7 +20116,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_offset_scalar(ptr inreg %out,
; GCN3-NEXT: .LBB122_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -20140,7 +20140,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_offset_scalar(ptr inreg %out,
; GCN3-NEXT: v_mov_b32_e32 v4, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[0:1]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[0:1]
; GCN3-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v0, v2, s[0:3], 0 offen
@@ -20180,7 +20180,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v9, v1
; GCN1-NEXT: v_mov_b32_e32 v8, v0
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; GCN1-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -20208,7 +20208,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN1-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s7
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[0:3], 0 offen
@@ -20244,7 +20244,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v9, v1
; GCN2-NEXT: v_mov_b32_e32 v8, v0
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; GCN2-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -20271,7 +20271,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN2-NEXT: v_mov_b32_e32 v5, s6
; GCN2-NEXT: v_mov_b32_e32 v4, s7
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[0:3], 0 offen
@@ -20300,7 +20300,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; GCN3-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -20325,7 +20325,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GCN3-NEXT: v_mov_b32_e32 v4, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[0:1]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[0:1]
; GCN3-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
@@ -20367,7 +20367,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_offset_scalar(ptr inreg %out, i64
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v9, v1
; GCN1-NEXT: v_mov_b32_e32 v8, v0
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; GCN1-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -20395,7 +20395,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_offset_scalar(ptr inreg %out, i64
; GCN1-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s7
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[0:3], 0 offen
@@ -20433,7 +20433,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_offset_scalar(ptr inreg %out, i64
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v9, v1
; GCN2-NEXT: v_mov_b32_e32 v8, v0
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; GCN2-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -20460,7 +20460,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_offset_scalar(ptr inreg %out, i64
; GCN2-NEXT: v_mov_b32_e32 v5, s6
; GCN2-NEXT: v_mov_b32_e32 v4, s7
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[0:3], 0 offen
@@ -20491,7 +20491,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_offset_scalar(ptr inreg %out, i64
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; GCN3-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -20516,7 +20516,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_offset_scalar(ptr inreg %out, i64
; GCN3-NEXT: v_mov_b32_e32 v4, s6
; GCN3-NEXT: v_mov_b32_e32 v3, s7
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[0:1]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[0:1]
; GCN3-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v4, v2, s[0:3], 0 offen
@@ -20567,7 +20567,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN1-NEXT: .LBB125_4: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -20594,7 +20594,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s3
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[12:15], 0 offen
@@ -20638,7 +20638,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN2-NEXT: .LBB125_4: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -20664,7 +20664,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN2-NEXT: v_mov_b32_e32 v5, s2
; GCN2-NEXT: v_mov_b32_e32 v4, s3
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[88:91], 0 offen
@@ -20708,7 +20708,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN3-NEXT: .LBB125_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -20732,7 +20732,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GCN3-NEXT: v_mov_b32_e32 v4, s2
; GCN3-NEXT: v_mov_b32_e32 v3, s3
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN3-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v0, v2, s[12:15], 0 offen
@@ -20778,7 +20778,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v9, v1
; GCN1-NEXT: v_mov_b32_e32 v8, v0
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[8:9]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[8:9]
; GCN1-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -20806,7 +20806,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN1-NEXT: buffer_load_dword v1, v3, s[16:19], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s13
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[16:19], 0 offen
@@ -20849,7 +20849,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v9, v1
; GCN2-NEXT: v_mov_b32_e32 v8, v0
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[8:9]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[8:9]
; GCN2-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -20876,7 +20876,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN2-NEXT: v_mov_b32_e32 v5, s12
; GCN2-NEXT: v_mov_b32_e32 v4, s13
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[88:91], 0 offen
@@ -20919,7 +20919,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[8:9]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[8:9]
; GCN3-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -20944,7 +20944,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GCN3-NEXT: v_mov_b32_e32 v4, s12
; GCN3-NEXT: v_mov_b32_e32 v3, s13
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[0:1]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[0:1]
; GCN3-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v4, v2, s[16:19], 0 offen
@@ -20994,7 +20994,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GCN1-NEXT: .LBB127_4: ; %atomicrmw.start
; GCN1-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -21021,7 +21021,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GCN1-NEXT: buffer_load_dword v1, v3, s[12:15], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s3
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v2, s[12:15], 0 offen
@@ -21059,7 +21059,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GCN2-NEXT: .LBB127_4: ; %atomicrmw.start
; GCN2-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -21085,7 +21085,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GCN2-NEXT: v_mov_b32_e32 v5, s2
; GCN2-NEXT: v_mov_b32_e32 v4, s3
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v2, s[88:91], 0 offen
@@ -21123,7 +21123,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GCN3-NEXT: .LBB127_4: ; %atomicrmw.start
; GCN3-NEXT: ; =>This Inner Loop Header: Depth=1
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -21147,7 +21147,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GCN3-NEXT: v_mov_b32_e32 v4, s2
; GCN3-NEXT: v_mov_b32_e32 v3, s3
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; GCN3-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v0, v2, s[12:15], 0 offen
@@ -21189,7 +21189,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN1-NEXT: v_mov_b32_e32 v9, v1
; GCN1-NEXT: v_mov_b32_e32 v8, v0
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[8:9]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[8:9]
; GCN1-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN1-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -21217,7 +21217,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN1-NEXT: buffer_load_dword v1, v3, s[16:19], 0 offen
; GCN1-NEXT: v_mov_b32_e32 v4, s13
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[0:1]
+; GCN1-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[0:1]
; GCN1-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN1-NEXT: buffer_store_dword v5, v2, s[16:19], 0 offen
@@ -21258,7 +21258,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN2-NEXT: v_mov_b32_e32 v9, v1
; GCN2-NEXT: v_mov_b32_e32 v8, v0
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[8:9]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[8:9]
; GCN2-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN2-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -21285,7 +21285,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN2-NEXT: v_mov_b32_e32 v5, s12
; GCN2-NEXT: v_mov_b32_e32 v4, s13
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[0:1]
+; GCN2-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[0:1]
; GCN2-NEXT: v_cndmask_b32_e32 v5, v5, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc
; GCN2-NEXT: buffer_store_dword v5, v2, s[88:91], 0 offen
@@ -21326,7 +21326,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN3-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN3-NEXT: v_mov_b32_e32 v9, v1
; GCN3-NEXT: v_mov_b32_e32 v8, v0
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[8:9]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[8:9]
; GCN3-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GCN3-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -21351,7 +21351,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GCN3-NEXT: v_mov_b32_e32 v4, s12
; GCN3-NEXT: v_mov_b32_e32 v3, s13
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[0:1]
+; GCN3-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[0:1]
; GCN3-NEXT: v_cndmask_b32_e32 v4, v4, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v4, v2, s[16:19], 0 offen
@@ -21402,7 +21402,7 @@ define void @flat_atomic_min_i64_noret_offset__amdgpu_no_remote_memory(ptr %out,
; GCN1-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN1-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN1-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN1-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -21444,7 +21444,7 @@ define void @flat_atomic_min_i64_noret_offset__amdgpu_no_remote_memory(ptr %out,
; GCN2-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN2-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN2-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN2-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -21483,7 +21483,7 @@ define void @flat_atomic_min_i64_noret_offset__amdgpu_no_remote_memory(ptr %out,
; GCN3-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN3-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN3-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v0, v4, s[0:3], 0 offen
@@ -21531,7 +21531,7 @@ define i64 @flat_atomic_min_i64_ret_offset__amdgpu_no_remote_memory(ptr %out, i6
; GCN1-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN1-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN1-NEXT: s_waitcnt vmcnt(0)
-; GCN1-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN1-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN1-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN1-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN1-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -21574,7 +21574,7 @@ define i64 @flat_atomic_min_i64_ret_offset__amdgpu_no_remote_memory(ptr %out, i6
; GCN2-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN2-NEXT: buffer_load_dword v1, v5, s[0:3], 0 offen
; GCN2-NEXT: s_waitcnt vmcnt(0)
-; GCN2-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN2-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN2-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN2-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN2-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
@@ -21614,7 +21614,7 @@ define i64 @flat_atomic_min_i64_ret_offset__amdgpu_no_remote_memory(ptr %out, i6
; GCN3-NEXT: buffer_load_dword v0, v4, s[0:3], 0 offen
; GCN3-NEXT: buffer_load_dword v1, v4, s[0:3], 0 offen offset:4
; GCN3-NEXT: s_waitcnt vmcnt(0)
-; GCN3-NEXT: v_cmp_le_i64_e32 vcc, v[0:1], v[2:3]
+; GCN3-NEXT: v_cmp_lt_i64_e32 vcc, v[0:1], v[2:3]
; GCN3-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
; GCN3-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
; GCN3-NEXT: buffer_store_dword v2, v4, s[0:3], 0 offen
diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
index f655d4761fa31..a31c5b48bc91b 100644
--- a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64_system_noprivate.ll
@@ -7653,7 +7653,7 @@ define void @flat_atomic_umin_i64_noret(ptr %ptr, i64 %in) {
; GFX7-NEXT: .LBB107_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX7-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -7680,7 +7680,7 @@ define void @flat_atomic_umin_i64_noret(ptr %ptr, i64 %in) {
; GFX8-NEXT: .LBB107_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -7704,7 +7704,7 @@ define void @flat_atomic_umin_i64_noret(ptr %ptr, i64 %in) {
; GFX9-NEXT: .LBB107_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -7737,7 +7737,7 @@ define void @flat_atomic_umin_i64_noret_offset(ptr %out, i64 %in) {
; GFX7-NEXT: .LBB108_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX7-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[8:9], v[4:7] glc
@@ -7766,7 +7766,7 @@ define void @flat_atomic_umin_i64_noret_offset(ptr %out, i64 %in) {
; GFX8-NEXT: .LBB108_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[8:9], v[4:7] glc
@@ -7790,7 +7790,7 @@ define void @flat_atomic_umin_i64_noret_offset(ptr %out, i64 %in) {
; GFX9-NEXT: .LBB108_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] offset:32 glc
@@ -7824,7 +7824,7 @@ define i64 @flat_atomic_umin_i64_ret(ptr %ptr, i64 %in) {
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: v_mov_b32_e32 v6, v4
-; GFX7-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX7-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -7853,7 +7853,7 @@ define i64 @flat_atomic_umin_i64_ret(ptr %ptr, i64 %in) {
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v7, v5
; GFX8-NEXT: v_mov_b32_e32 v6, v4
-; GFX8-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -7879,7 +7879,7 @@ define i64 @flat_atomic_umin_i64_ret(ptr %ptr, i64 %in) {
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
-; GFX9-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -7914,7 +7914,7 @@ define i64 @flat_atomic_umin_i64_ret_offset(ptr %out, i64 %in) {
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v1
; GFX7-NEXT: v_mov_b32_e32 v8, v0
-; GFX7-NEXT: v_cmp_le_u64_e32 vcc, v[8:9], v[2:3]
+; GFX7-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -7943,7 +7943,7 @@ define i64 @flat_atomic_umin_i64_ret_offset(ptr %out, i64 %in) {
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v1
; GFX8-NEXT: v_mov_b32_e32 v8, v0
-; GFX8-NEXT: v_cmp_le_u64_e32 vcc, v[8:9], v[2:3]
+; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -7967,7 +7967,7 @@ define i64 @flat_atomic_umin_i64_ret_offset(ptr %out, i64 %in) {
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
-; GFX9-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] offset:32 glc
@@ -8007,7 +8007,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_scalar(ptr inreg %ptr, i64 in
; GFX7-NEXT: .LBB111_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -8042,7 +8042,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_scalar(ptr inreg %ptr, i64 in
; GFX8-NEXT: .LBB111_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -8072,7 +8072,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_scalar(ptr inreg %ptr, i64 in
; GFX9-NEXT: .LBB111_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -8111,7 +8111,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_offset_scalar(ptr inreg %out,
; GFX7-NEXT: .LBB112_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -8146,7 +8146,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_offset_scalar(ptr inreg %out,
; GFX8-NEXT: .LBB112_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -8176,7 +8176,7 @@ define amdgpu_gfx void @flat_atomic_umin_i64_noret_offset_scalar(ptr inreg %out,
; GFX9-NEXT: .LBB112_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] offset:32 glc
@@ -8218,7 +8218,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v1
; GFX7-NEXT: v_mov_b32_e32 v8, v0
-; GFX7-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -8253,7 +8253,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v1
; GFX8-NEXT: v_mov_b32_e32 v8, v0
-; GFX8-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -8283,7 +8283,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v9, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v0
-; GFX9-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; GFX9-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -8322,7 +8322,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_offset_scalar(ptr inreg %out, i6
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v1
; GFX7-NEXT: v_mov_b32_e32 v8, v0
-; GFX7-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; GFX7-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -8357,7 +8357,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_offset_scalar(ptr inreg %out, i6
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v1
; GFX8-NEXT: v_mov_b32_e32 v8, v0
-; GFX8-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -8387,7 +8387,7 @@ define amdgpu_gfx i64 @flat_atomic_umin_i64_ret_offset_scalar(ptr inreg %out, i6
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v9, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v0
-; GFX9-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; GFX9-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] offset:32 glc
@@ -8487,7 +8487,7 @@ define void @flat_atomic_min_i64_noret(ptr %ptr, i64 %in) {
; GFX7-NEXT: .LBB117_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX7-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -8514,7 +8514,7 @@ define void @flat_atomic_min_i64_noret(ptr %ptr, i64 %in) {
; GFX8-NEXT: .LBB117_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -8538,7 +8538,7 @@ define void @flat_atomic_min_i64_noret(ptr %ptr, i64 %in) {
; GFX9-NEXT: .LBB117_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -8571,7 +8571,7 @@ define void @flat_atomic_min_i64_noret_offset(ptr %out, i64 %in) {
; GFX7-NEXT: .LBB118_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX7-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[8:9], v[4:7] glc
@@ -8600,7 +8600,7 @@ define void @flat_atomic_min_i64_noret_offset(ptr %out, i64 %in) {
; GFX8-NEXT: .LBB118_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[8:9], v[4:7] glc
@@ -8624,7 +8624,7 @@ define void @flat_atomic_min_i64_noret_offset(ptr %out, i64 %in) {
; GFX9-NEXT: .LBB118_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] offset:32 glc
@@ -8658,7 +8658,7 @@ define i64 @flat_atomic_min_i64_ret(ptr %ptr, i64 %in) {
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v7, v5
; GFX7-NEXT: v_mov_b32_e32 v6, v4
-; GFX7-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX7-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -8687,7 +8687,7 @@ define i64 @flat_atomic_min_i64_ret(ptr %ptr, i64 %in) {
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v7, v5
; GFX8-NEXT: v_mov_b32_e32 v6, v4
-; GFX8-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -8713,7 +8713,7 @@ define i64 @flat_atomic_min_i64_ret(ptr %ptr, i64 %in) {
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
-; GFX9-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -8748,7 +8748,7 @@ define i64 @flat_atomic_min_i64_ret_offset(ptr %out, i64 %in) {
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v1
; GFX7-NEXT: v_mov_b32_e32 v8, v0
-; GFX7-NEXT: v_cmp_le_i64_e32 vcc, v[8:9], v[2:3]
+; GFX7-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -8777,7 +8777,7 @@ define i64 @flat_atomic_min_i64_ret_offset(ptr %out, i64 %in) {
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v1
; GFX8-NEXT: v_mov_b32_e32 v8, v0
-; GFX8-NEXT: v_cmp_le_i64_e32 vcc, v[8:9], v[2:3]
+; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -8801,7 +8801,7 @@ define i64 @flat_atomic_min_i64_ret_offset(ptr %out, i64 %in) {
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
-; GFX9-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] offset:32 glc
@@ -8841,7 +8841,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX7-NEXT: .LBB121_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -8876,7 +8876,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX8-NEXT: .LBB121_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -8906,7 +8906,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_scalar(ptr inreg %ptr, i64 inr
; GFX9-NEXT: .LBB121_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -8945,7 +8945,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_offset_scalar(ptr inreg %out,
; GFX7-NEXT: .LBB122_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -8980,7 +8980,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_offset_scalar(ptr inreg %out,
; GFX8-NEXT: .LBB122_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -9010,7 +9010,7 @@ define amdgpu_gfx void @flat_atomic_min_i64_noret_offset_scalar(ptr inreg %out,
; GFX9-NEXT: .LBB122_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] offset:32 glc
@@ -9052,7 +9052,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v1
; GFX7-NEXT: v_mov_b32_e32 v8, v0
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -9087,7 +9087,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v1
; GFX8-NEXT: v_mov_b32_e32 v8, v0
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -9117,7 +9117,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_scalar(ptr inreg %ptr, i64 inreg
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v9, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v0
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; GFX9-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -9156,7 +9156,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_offset_scalar(ptr inreg %out, i64
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v1
; GFX7-NEXT: v_mov_b32_e32 v8, v0
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -9191,7 +9191,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_offset_scalar(ptr inreg %out, i64
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v1
; GFX8-NEXT: v_mov_b32_e32 v8, v0
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -9221,7 +9221,7 @@ define amdgpu_gfx i64 @flat_atomic_min_i64_ret_offset_scalar(ptr inreg %out, i64
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v9, v1
; GFX9-NEXT: v_mov_b32_e32 v8, v0
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; GFX9-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] offset:32 glc
@@ -9259,7 +9259,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GFX7-NEXT: .LBB125_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -9293,7 +9293,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GFX8-NEXT: .LBB125_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -9325,7 +9325,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr %out, i64 %in, i64 %
; GFX9-NEXT: .LBB125_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] offset:32 glc
@@ -9367,7 +9367,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v3
; GFX7-NEXT: v_mov_b32_e32 v8, v2
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -9404,7 +9404,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v3
; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -9439,7 +9439,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr %out, ptr %out2,
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v9, v3
; GFX9-NEXT: v_mov_b32_e32 v8, v2
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[8:9]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[8:9]
; GFX9-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] offset:32 glc
@@ -9479,7 +9479,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GFX7-NEXT: .LBB127_1: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX7-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -9509,7 +9509,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GFX8-NEXT: .LBB127_1: ; %atomicrmw.start
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -9539,7 +9539,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr %out, i64 %in) {
; GFX9-NEXT: .LBB127_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -9577,7 +9577,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v9, v3
; GFX7-NEXT: v_mov_b32_e32 v8, v2
-; GFX7-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; GFX7-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; GFX7-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX7-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -9612,7 +9612,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v9, v3
; GFX8-NEXT: v_mov_b32_e32 v8, v2
-; GFX8-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; GFX8-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX8-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -9647,7 +9647,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr %out, ptr %out2, i64 %i
; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v9, v3
; GFX9-NEXT: v_mov_b32_e32 v8, v2
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[8:9]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[8:9]
; GFX9-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; GFX9-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
index 63d63da56080b..96dc0e225c44c 100644
--- a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll
@@ -1375,7 +1375,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn(ptr addrspace(1) inreg %s
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v10, v4
; GFX9-NEXT: v_mov_b32_e32 v9, v3
-; GFX9-NEXT: v_cmp_le_i64_e32 vcc, v[9:10], v[1:2]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[9:10], v[1:2]
; GFX9-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[3:4], v[5:6], v[7:10], off glc
@@ -1402,7 +1402,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn(ptr addrspace(1) inreg %s
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v10, v4
; GFX10-NEXT: v_mov_b32_e32 v9, v3
-; GFX10-NEXT: v_cmp_le_i64_e32 vcc, v[9:10], v[1:2]
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc, v[9:10], v[1:2]
; GFX10-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX10-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX10-NEXT: global_atomic_cmpswap_x2 v[3:4], v[5:6], v[7:10], off glc
@@ -1433,7 +1433,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn(ptr addrspace(1) inreg %s
; GFX11-NEXT: v_mov_b32_e32 v10, v4
; GFX11-NEXT: v_mov_b32_e32 v9, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_le_i64_e32 vcc, v[9:10], v[1:2]
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc, v[9:10], v[1:2]
; GFX11-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX11-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX11-NEXT: global_atomic_cmpswap_b64 v[3:4], v[5:6], v[7:10], off glc
@@ -1465,7 +1465,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn(ptr addrspace(1) inreg %s
; GFX12-NEXT: v_mov_b32_e32 v10, v4
; GFX12-NEXT: v_mov_b32_e32 v9, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_cmp_le_i64_e32 vcc, v[9:10], v[1:2]
+; GFX12-NEXT: v_cmp_lt_i64_e32 vcc, v[9:10], v[1:2]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
@@ -1505,7 +1505,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn_neg128(ptr addrspace(1) i
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v10, v4
; GFX9-NEXT: v_mov_b32_e32 v9, v3
-; GFX9-NEXT: v_cmp_le_i64_e32 vcc, v[9:10], v[1:2]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[9:10], v[1:2]
; GFX9-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[3:4], v[5:6], v[7:10], off offset:-128 glc
@@ -1532,7 +1532,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn_neg128(ptr addrspace(1) i
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v10, v4
; GFX10-NEXT: v_mov_b32_e32 v9, v3
-; GFX10-NEXT: v_cmp_le_i64_e32 vcc, v[9:10], v[1:2]
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc, v[9:10], v[1:2]
; GFX10-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX10-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX10-NEXT: global_atomic_cmpswap_x2 v[3:4], v[5:6], v[7:10], off offset:-128 glc
@@ -1563,7 +1563,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn_neg128(ptr addrspace(1) i
; GFX11-NEXT: v_mov_b32_e32 v10, v4
; GFX11-NEXT: v_mov_b32_e32 v9, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_le_i64_e32 vcc, v[9:10], v[1:2]
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc, v[9:10], v[1:2]
; GFX11-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX11-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX11-NEXT: global_atomic_cmpswap_b64 v[3:4], v[5:6], v[7:10], off offset:-128 glc
@@ -1595,7 +1595,7 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn_neg128(ptr addrspace(1) i
; GFX12-NEXT: v_mov_b32_e32 v10, v4
; GFX12-NEXT: v_mov_b32_e32 v9, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_cmp_le_i64_e32 vcc, v[9:10], v[1:2]
+; GFX12-NEXT: v_cmp_lt_i64_e32 vcc, v[9:10], v[1:2]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
@@ -1634,7 +1634,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn(ptr addrspace(1) inreg %sbase,
; GFX9-NEXT: .LBB14_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_le_i64_e32 vcc, v[5:6], v[1:2]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[5:6], v[1:2]
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[3:4], v[7:8], v[3:6], off glc
@@ -1658,7 +1658,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn(ptr addrspace(1) inreg %sbase,
; GFX10-NEXT: .LBB14_1: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_le_i64_e32 vcc, v[5:6], v[1:2]
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc, v[5:6], v[1:2]
; GFX10-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX10-NEXT: global_atomic_cmpswap_x2 v[3:4], v[7:8], v[3:6], off glc
@@ -1685,7 +1685,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn(ptr addrspace(1) inreg %sbase,
; GFX11-NEXT: .LBB14_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_le_i64_e32 vcc, v[5:6], v[1:2]
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc, v[5:6], v[1:2]
; GFX11-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX11-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX11-NEXT: global_atomic_cmpswap_b64 v[3:4], v[7:8], v[3:6], off glc
@@ -1713,7 +1713,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn(ptr addrspace(1) inreg %sbase,
; GFX12-NEXT: .LBB14_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_le_i64_e32 vcc, v[5:6], v[1:2]
+; GFX12-NEXT: v_cmp_lt_i64_e32 vcc, v[5:6], v[1:2]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
@@ -1749,7 +1749,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX9-NEXT: .LBB15_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_le_i64_e32 vcc, v[5:6], v[1:2]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[5:6], v[1:2]
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[3:4], v[7:8], v[3:6], off offset:-128 glc
@@ -1773,7 +1773,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX10-NEXT: .LBB15_1: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_le_i64_e32 vcc, v[5:6], v[1:2]
+; GFX10-NEXT: v_cmp_lt_i64_e32 vcc, v[5:6], v[1:2]
; GFX10-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX10-NEXT: global_atomic_cmpswap_x2 v[3:4], v[7:8], v[3:6], off offset:-128 glc
@@ -1800,7 +1800,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: .LBB15_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_le_i64_e32 vcc, v[5:6], v[1:2]
+; GFX11-NEXT: v_cmp_lt_i64_e32 vcc, v[5:6], v[1:2]
; GFX11-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX11-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX11-NEXT: global_atomic_cmpswap_b64 v[3:4], v[7:8], v[3:6], off offset:-128 glc
@@ -1828,7 +1828,7 @@ define amdgpu_ps void @global_min_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: .LBB15_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_le_i64_e32 vcc, v[5:6], v[1:2]
+; GFX12-NEXT: v_cmp_lt_i64_e32 vcc, v[5:6], v[1:2]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
@@ -3223,7 +3223,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn(ptr addrspace(1) inreg %
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v10, v4
; GFX9-NEXT: v_mov_b32_e32 v9, v3
-; GFX9-NEXT: v_cmp_le_u64_e32 vcc, v[9:10], v[1:2]
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[1:2]
; GFX9-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[3:4], v[5:6], v[7:10], off glc
@@ -3250,7 +3250,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn(ptr addrspace(1) inreg %
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v10, v4
; GFX10-NEXT: v_mov_b32_e32 v9, v3
-; GFX10-NEXT: v_cmp_le_u64_e32 vcc, v[9:10], v[1:2]
+; GFX10-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[1:2]
; GFX10-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX10-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX10-NEXT: global_atomic_cmpswap_x2 v[3:4], v[5:6], v[7:10], off glc
@@ -3281,7 +3281,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn(ptr addrspace(1) inreg %
; GFX11-NEXT: v_mov_b32_e32 v10, v4
; GFX11-NEXT: v_mov_b32_e32 v9, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_le_u64_e32 vcc, v[9:10], v[1:2]
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[1:2]
; GFX11-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX11-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX11-NEXT: global_atomic_cmpswap_b64 v[3:4], v[5:6], v[7:10], off glc
@@ -3313,7 +3313,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn(ptr addrspace(1) inreg %
; GFX12-NEXT: v_mov_b32_e32 v10, v4
; GFX12-NEXT: v_mov_b32_e32 v9, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_cmp_le_u64_e32 vcc, v[9:10], v[1:2]
+; GFX12-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[1:2]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
@@ -3353,7 +3353,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn_neg128(ptr addrspace(1)
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v10, v4
; GFX9-NEXT: v_mov_b32_e32 v9, v3
-; GFX9-NEXT: v_cmp_le_u64_e32 vcc, v[9:10], v[1:2]
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[1:2]
; GFX9-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[3:4], v[5:6], v[7:10], off offset:-128 glc
@@ -3380,7 +3380,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn_neg128(ptr addrspace(1)
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v10, v4
; GFX10-NEXT: v_mov_b32_e32 v9, v3
-; GFX10-NEXT: v_cmp_le_u64_e32 vcc, v[9:10], v[1:2]
+; GFX10-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[1:2]
; GFX10-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX10-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX10-NEXT: global_atomic_cmpswap_x2 v[3:4], v[5:6], v[7:10], off offset:-128 glc
@@ -3411,7 +3411,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn_neg128(ptr addrspace(1)
; GFX11-NEXT: v_mov_b32_e32 v10, v4
; GFX11-NEXT: v_mov_b32_e32 v9, v3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_cmp_le_u64_e32 vcc, v[9:10], v[1:2]
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[1:2]
; GFX11-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX11-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
; GFX11-NEXT: global_atomic_cmpswap_b64 v[3:4], v[5:6], v[7:10], off offset:-128 glc
@@ -3443,7 +3443,7 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn_neg128(ptr addrspace(1)
; GFX12-NEXT: v_mov_b32_e32 v10, v4
; GFX12-NEXT: v_mov_b32_e32 v9, v3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_cmp_le_u64_e32 vcc, v[9:10], v[1:2]
+; GFX12-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[1:2]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v8, v2, v10, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v7, v1, v9, vcc
@@ -3482,7 +3482,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn(ptr addrspace(1) inreg %sbase
; GFX9-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_le_u64_e32 vcc, v[5:6], v[1:2]
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[5:6], v[1:2]
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[3:4], v[7:8], v[3:6], off glc
@@ -3506,7 +3506,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn(ptr addrspace(1) inreg %sbase
; GFX10-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_le_u64_e32 vcc, v[5:6], v[1:2]
+; GFX10-NEXT: v_cmp_lt_u64_e32 vcc, v[5:6], v[1:2]
; GFX10-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX10-NEXT: global_atomic_cmpswap_x2 v[3:4], v[7:8], v[3:6], off glc
@@ -3533,7 +3533,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn(ptr addrspace(1) inreg %sbase
; GFX11-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_le_u64_e32 vcc, v[5:6], v[1:2]
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc, v[5:6], v[1:2]
; GFX11-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX11-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX11-NEXT: global_atomic_cmpswap_b64 v[3:4], v[7:8], v[3:6], off glc
@@ -3561,7 +3561,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn(ptr addrspace(1) inreg %sbase
; GFX12-NEXT: .LBB30_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_le_u64_e32 vcc, v[5:6], v[1:2]
+; GFX12-NEXT: v_cmp_lt_u64_e32 vcc, v[5:6], v[1:2]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
@@ -3597,7 +3597,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX9-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_le_u64_e32 vcc, v[5:6], v[1:2]
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[5:6], v[1:2]
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[3:4], v[7:8], v[3:6], off offset:-128 glc
@@ -3621,7 +3621,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX10-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_le_u64_e32 vcc, v[5:6], v[1:2]
+; GFX10-NEXT: v_cmp_lt_u64_e32 vcc, v[5:6], v[1:2]
; GFX10-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX10-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX10-NEXT: global_atomic_cmpswap_x2 v[3:4], v[7:8], v[3:6], off offset:-128 glc
@@ -3648,7 +3648,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX11-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-NEXT: s_waitcnt vmcnt(0)
-; GFX11-NEXT: v_cmp_le_u64_e32 vcc, v[5:6], v[1:2]
+; GFX11-NEXT: v_cmp_lt_u64_e32 vcc, v[5:6], v[1:2]
; GFX11-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX11-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
; GFX11-NEXT: global_atomic_cmpswap_b64 v[3:4], v[7:8], v[3:6], off offset:-128 glc
@@ -3676,7 +3676,7 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn_neg128(ptr addrspace(1) inreg
; GFX12-NEXT: .LBB31_1: ; %atomicrmw.start
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX12-NEXT: s_wait_loadcnt 0x0
-; GFX12-NEXT: v_cmp_le_u64_e32 vcc, v[5:6], v[1:2]
+; GFX12-NEXT: v_cmp_lt_u64_e32 vcc, v[5:6], v[1:2]
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX12-NEXT: v_cndmask_b32_e32 v3, v1, v5, vcc
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
index 6a4c2849ba4a3..b4fa9ec150675 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
@@ -8229,7 +8229,7 @@ define void @global_atomic_umin_i64_noret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: .LBB107_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; SI-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -8259,7 +8259,7 @@ define void @global_atomic_umin_i64_noret(ptr addrspace(1) %ptr, i64 %in) {
; VI-NEXT: .LBB107_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; VI-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; VI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -8283,7 +8283,7 @@ define void @global_atomic_umin_i64_noret(ptr addrspace(1) %ptr, i64 %in) {
; GFX9-NEXT: .LBB107_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off glc
@@ -8315,7 +8315,7 @@ define void @global_atomic_umin_i64_noret_offset(ptr addrspace(1) %out, i64 %in)
; SI-NEXT: .LBB108_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; SI-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -8347,7 +8347,7 @@ define void @global_atomic_umin_i64_noret_offset(ptr addrspace(1) %out, i64 %in)
; VI-NEXT: .LBB108_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; VI-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; VI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -8371,7 +8371,7 @@ define void @global_atomic_umin_i64_noret_offset(ptr addrspace(1) %out, i64 %in)
; GFX9-NEXT: .LBB108_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off offset:32 glc
@@ -8408,7 +8408,7 @@ define i64 @global_atomic_umin_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: .LBB109_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_le_u64_e32 vcc, v[10:11], v[4:5]
+; SI-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5]
; SI-NEXT: v_cndmask_b32_e32 v9, v5, v11, vcc
; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -8440,7 +8440,7 @@ define i64 @global_atomic_umin_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v7, v5
; VI-NEXT: v_mov_b32_e32 v6, v4
-; VI-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; VI-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; VI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -8466,7 +8466,7 @@ define i64 @global_atomic_umin_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
-; GFX9-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off glc
@@ -8502,7 +8502,7 @@ define i64 @global_atomic_umin_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; SI-NEXT: .LBB110_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_le_u64_e32 vcc, v[10:11], v[4:5]
+; SI-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[4:5]
; SI-NEXT: v_cndmask_b32_e32 v9, v5, v11, vcc
; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -8536,7 +8536,7 @@ define i64 @global_atomic_umin_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v9, v1
; VI-NEXT: v_mov_b32_e32 v8, v0
-; VI-NEXT: v_cmp_le_u64_e32 vcc, v[8:9], v[2:3]
+; VI-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; VI-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -8560,7 +8560,7 @@ define i64 @global_atomic_umin_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
-; GFX9-NEXT: v_cmp_le_u64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off offset:32 glc
@@ -8601,7 +8601,7 @@ define amdgpu_gfx void @global_atomic_umin_i64_noret_scalar(ptr addrspace(1) inr
; SI-NEXT: .LBB111_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_ge_u64_e32 vcc, s[34:35], v[2:3]
+; SI-NEXT: v_cmp_gt_u64_e32 vcc, s[34:35], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -8642,7 +8642,7 @@ define amdgpu_gfx void @global_atomic_umin_i64_noret_scalar(ptr addrspace(1) inr
; VI-NEXT: .LBB111_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; VI-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; VI-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -8669,7 +8669,7 @@ define amdgpu_gfx void @global_atomic_umin_i64_noret_scalar(ptr addrspace(1) inr
; GFX9-NEXT: .LBB111_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v4, v[0:3], s[4:5] glc
@@ -8709,7 +8709,7 @@ define amdgpu_gfx void @global_atomic_umin_i64_noret_offset_scalar(ptr addrspace
; SI-NEXT: .LBB112_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_ge_u64_e32 vcc, s[34:35], v[2:3]
+; SI-NEXT: v_cmp_gt_u64_e32 vcc, s[34:35], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -8750,7 +8750,7 @@ define amdgpu_gfx void @global_atomic_umin_i64_noret_offset_scalar(ptr addrspace
; VI-NEXT: .LBB112_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; VI-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; VI-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -8777,7 +8777,7 @@ define amdgpu_gfx void @global_atomic_umin_i64_noret_offset_scalar(ptr addrspace
; GFX9-NEXT: .LBB112_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v4, v[0:3], s[4:5] offset:32 glc
@@ -8818,7 +8818,7 @@ define amdgpu_gfx i64 @global_atomic_umin_i64_ret_scalar(ptr addrspace(1) inreg
; SI-NEXT: .LBB113_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_ge_u64_e32 vcc, s[34:35], v[4:5]
+; SI-NEXT: v_cmp_gt_u64_e32 vcc, s[34:35], v[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v7, v4, vcc
@@ -8861,7 +8861,7 @@ define amdgpu_gfx i64 @global_atomic_umin_i64_ret_scalar(ptr addrspace(1) inreg
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v9, v1
; VI-NEXT: v_mov_b32_e32 v8, v0
-; VI-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; VI-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; VI-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; VI-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -8888,7 +8888,7 @@ define amdgpu_gfx i64 @global_atomic_umin_i64_ret_scalar(ptr addrspace(1) inreg
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v8, v1
; GFX9-NEXT: v_mov_b32_e32 v7, v0
-; GFX9-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[7:8]
+; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[7:8]
; GFX9-NEXT: v_cndmask_b32_e32 v6, v3, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v4, v7, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v2, v[5:8], s[4:5] glc
@@ -8926,7 +8926,7 @@ define amdgpu_gfx i64 @global_atomic_umin_i64_ret_offset_scalar(ptr addrspace(1)
; SI-NEXT: .LBB114_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_ge_u64_e32 vcc, s[34:35], v[4:5]
+; SI-NEXT: v_cmp_gt_u64_e32 vcc, s[34:35], v[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v7, v4, vcc
@@ -8969,7 +8969,7 @@ define amdgpu_gfx i64 @global_atomic_umin_i64_ret_offset_scalar(ptr addrspace(1)
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v9, v1
; VI-NEXT: v_mov_b32_e32 v8, v0
-; VI-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[8:9]
+; VI-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[8:9]
; VI-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; VI-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -8996,7 +8996,7 @@ define amdgpu_gfx i64 @global_atomic_umin_i64_ret_offset_scalar(ptr addrspace(1)
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v8, v1
; GFX9-NEXT: v_mov_b32_e32 v7, v0
-; GFX9-NEXT: v_cmp_ge_u64_e32 vcc, s[6:7], v[7:8]
+; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[6:7], v[7:8]
; GFX9-NEXT: v_cndmask_b32_e32 v6, v3, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v4, v7, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v2, v[5:8], s[4:5] offset:32 glc
@@ -9105,7 +9105,7 @@ define void @global_atomic_min_i64_noret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: .LBB117_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; SI-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -9135,7 +9135,7 @@ define void @global_atomic_min_i64_noret(ptr addrspace(1) %ptr, i64 %in) {
; VI-NEXT: .LBB117_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; VI-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; VI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -9159,7 +9159,7 @@ define void @global_atomic_min_i64_noret(ptr addrspace(1) %ptr, i64 %in) {
; GFX9-NEXT: .LBB117_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off glc
@@ -9191,7 +9191,7 @@ define void @global_atomic_min_i64_noret_offset(ptr addrspace(1) %out, i64 %in)
; SI-NEXT: .LBB118_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; SI-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -9223,7 +9223,7 @@ define void @global_atomic_min_i64_noret_offset(ptr addrspace(1) %out, i64 %in)
; VI-NEXT: .LBB118_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; VI-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; VI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -9247,7 +9247,7 @@ define void @global_atomic_min_i64_noret_offset(ptr addrspace(1) %out, i64 %in)
; GFX9-NEXT: .LBB118_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off offset:32 glc
@@ -9284,7 +9284,7 @@ define i64 @global_atomic_min_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; SI-NEXT: .LBB119_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_le_i64_e32 vcc, v[10:11], v[4:5]
+; SI-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[4:5]
; SI-NEXT: v_cndmask_b32_e32 v9, v5, v11, vcc
; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -9316,7 +9316,7 @@ define i64 @global_atomic_min_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v7, v5
; VI-NEXT: v_mov_b32_e32 v6, v4
-; VI-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; VI-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; VI-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7] glc
@@ -9342,7 +9342,7 @@ define i64 @global_atomic_min_i64_ret(ptr addrspace(1) %ptr, i64 %in) {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
-; GFX9-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off glc
@@ -9378,7 +9378,7 @@ define i64 @global_atomic_min_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; SI-NEXT: .LBB120_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_le_i64_e32 vcc, v[10:11], v[4:5]
+; SI-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[4:5]
; SI-NEXT: v_cndmask_b32_e32 v9, v5, v11, vcc
; SI-NEXT: v_cndmask_b32_e32 v8, v4, v10, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -9412,7 +9412,7 @@ define i64 @global_atomic_min_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v9, v1
; VI-NEXT: v_mov_b32_e32 v8, v0
-; VI-NEXT: v_cmp_le_i64_e32 vcc, v[8:9], v[2:3]
+; VI-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v7, v3, v9, vcc
; VI-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[6:9] glc
@@ -9436,7 +9436,7 @@ define i64 @global_atomic_min_i64_ret_offset(ptr addrspace(1) %out, i64 %in) {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v7, v5
; GFX9-NEXT: v_mov_b32_e32 v6, v4
-; GFX9-NEXT: v_cmp_le_i64_e32 vcc, v[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v6, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[4:5], v[0:1], v[4:7], off offset:32 glc
@@ -9477,7 +9477,7 @@ define amdgpu_gfx void @global_atomic_min_i64_noret_scalar(ptr addrspace(1) inre
; SI-NEXT: .LBB121_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_ge_i64_e32 vcc, s[34:35], v[2:3]
+; SI-NEXT: v_cmp_gt_i64_e32 vcc, s[34:35], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -9518,7 +9518,7 @@ define amdgpu_gfx void @global_atomic_min_i64_noret_scalar(ptr addrspace(1) inre
; VI-NEXT: .LBB121_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; VI-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; VI-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -9545,7 +9545,7 @@ define amdgpu_gfx void @global_atomic_min_i64_noret_scalar(ptr addrspace(1) inre
; GFX9-NEXT: .LBB121_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v4, v[0:3], s[4:5] glc
@@ -9585,7 +9585,7 @@ define amdgpu_gfx void @global_atomic_min_i64_noret_offset_scalar(ptr addrspace(
; SI-NEXT: .LBB122_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_ge_i64_e32 vcc, s[34:35], v[2:3]
+; SI-NEXT: v_cmp_gt_i64_e32 vcc, s[34:35], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -9626,7 +9626,7 @@ define amdgpu_gfx void @global_atomic_min_i64_noret_offset_scalar(ptr addrspace(
; VI-NEXT: .LBB122_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; VI-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; VI-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -9653,7 +9653,7 @@ define amdgpu_gfx void @global_atomic_min_i64_noret_offset_scalar(ptr addrspace(
; GFX9-NEXT: .LBB122_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[2:3]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v6, v2, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v4, v[0:3], s[4:5] offset:32 glc
@@ -9694,7 +9694,7 @@ define amdgpu_gfx i64 @global_atomic_min_i64_ret_scalar(ptr addrspace(1) inreg %
; SI-NEXT: .LBB123_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_ge_i64_e32 vcc, s[34:35], v[4:5]
+; SI-NEXT: v_cmp_gt_i64_e32 vcc, s[34:35], v[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v7, v4, vcc
@@ -9737,7 +9737,7 @@ define amdgpu_gfx i64 @global_atomic_min_i64_ret_scalar(ptr addrspace(1) inreg %
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v9, v1
; VI-NEXT: v_mov_b32_e32 v8, v0
-; VI-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; VI-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; VI-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; VI-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -9764,7 +9764,7 @@ define amdgpu_gfx i64 @global_atomic_min_i64_ret_scalar(ptr addrspace(1) inreg %
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v8, v1
; GFX9-NEXT: v_mov_b32_e32 v7, v0
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[7:8]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[7:8]
; GFX9-NEXT: v_cndmask_b32_e32 v6, v3, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v4, v7, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v2, v[5:8], s[4:5] glc
@@ -9802,7 +9802,7 @@ define amdgpu_gfx i64 @global_atomic_min_i64_ret_offset_scalar(ptr addrspace(1)
; SI-NEXT: .LBB124_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt vmcnt(0)
-; SI-NEXT: v_cmp_ge_i64_e32 vcc, s[34:35], v[4:5]
+; SI-NEXT: v_cmp_gt_i64_e32 vcc, s[34:35], v[4:5]
; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_cndmask_b32_e32 v3, v6, v5, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v7, v4, vcc
@@ -9845,7 +9845,7 @@ define amdgpu_gfx i64 @global_atomic_min_i64_ret_offset_scalar(ptr addrspace(1)
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v9, v1
; VI-NEXT: v_mov_b32_e32 v8, v0
-; VI-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[8:9]
+; VI-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[8:9]
; VI-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; VI-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[2:3], v[6:9] glc
@@ -9872,7 +9872,7 @@ define amdgpu_gfx i64 @global_atomic_min_i64_ret_offset_scalar(ptr addrspace(1)
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v8, v1
; GFX9-NEXT: v_mov_b32_e32 v7, v0
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[6:7], v[7:8]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[6:7], v[7:8]
; GFX9-NEXT: v_cndmask_b32_e32 v6, v3, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v4, v7, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v2, v[5:8], s[4:5] offset:32 glc
@@ -9910,7 +9910,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr addrspace(1) %out, i
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: .LBB125_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; SI-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -9951,7 +9951,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr addrspace(1) %out, i
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: .LBB125_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; VI-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; VI-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -9984,7 +9984,7 @@ define amdgpu_kernel void @atomic_min_i64_addr64_offset(ptr addrspace(1) %out, i
; GFX9-NEXT: v_mov_b32_e32 v3, s7
; GFX9-NEXT: .LBB125_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v6, v[0:3], s[0:1] offset:32 glc
@@ -10024,7 +10024,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr addrspace(1) %ou
; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: .LBB126_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[2:3]
+; SI-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -10072,7 +10072,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr addrspace(1) %ou
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v9, v3
; VI-NEXT: v_mov_b32_e32 v8, v2
-; VI-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; VI-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; VI-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; VI-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -10108,7 +10108,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(ptr addrspace(1) %ou
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v8, v1
; GFX9-NEXT: v_mov_b32_e32 v7, v0
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[7:8]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[7:8]
; GFX9-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v4, v[5:8], s[0:1] offset:32 glc
@@ -10149,7 +10149,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr addrspace(1) %out, i64 %in) {
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: .LBB127_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; SI-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -10184,7 +10184,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr addrspace(1) %out, i64 %in) {
; VI-NEXT: v_mov_b32_e32 v3, s7
; VI-NEXT: .LBB127_1: ; %atomicrmw.start
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
-; VI-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; VI-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; VI-NEXT: v_cndmask_b32_e32 v1, v6, v3, vcc
; VI-NEXT: v_cndmask_b32_e32 v0, v7, v2, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[0:1], v[4:5], v[0:3] glc
@@ -10213,7 +10213,7 @@ define amdgpu_kernel void @atomic_min_i64(ptr addrspace(1) %out, i64 %in) {
; GFX9-NEXT: v_mov_b32_e32 v3, s7
; GFX9-NEXT: .LBB127_1: ; %atomicrmw.start
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[2:3]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v5, v2, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v6, v[0:3], s[0:1] glc
@@ -10251,7 +10251,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr addrspace(1) %out, ptr
; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: .LBB128_1: ; %atomicrmw.start
; SI-NEXT: ; =>This Inner Loop Header: Depth=1
-; SI-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[2:3]
+; SI-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v1, v8, v3, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v9, v2, vcc
; SI-NEXT: s_waitcnt expcnt(0)
@@ -10297,7 +10297,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr addrspace(1) %out, ptr
; VI-NEXT: ; =>This Inner Loop Header: Depth=1
; VI-NEXT: v_mov_b32_e32 v9, v3
; VI-NEXT: v_mov_b32_e32 v8, v2
-; VI-NEXT: v_cmp_ge_i64_e32 vcc, s[4:5], v[8:9]
+; VI-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[8:9]
; VI-NEXT: v_cndmask_b32_e32 v7, v4, v9, vcc
; VI-NEXT: v_cndmask_b32_e32 v6, v5, v8, vcc
; VI-NEXT: flat_atomic_cmpswap_x2 v[2:3], v[0:1], v[6:9] glc
@@ -10333,7 +10333,7 @@ define amdgpu_kernel void @atomic_min_i64_ret_addr64(ptr addrspace(1) %out, ptr
; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX9-NEXT: v_mov_b32_e32 v8, v1
; GFX9-NEXT: v_mov_b32_e32 v7, v0
-; GFX9-NEXT: v_cmp_ge_i64_e32 vcc, s[12:13], v[7:8]
+; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[12:13], v[7:8]
; GFX9-NEXT: v_cndmask_b32_e32 v6, v2, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v7, vcc
; GFX9-NEXT: global_atomic_cmpswap_x2 v[0:1], v4, v[5:8], s[0:1] glc
diff --git a/llvm/test/CodeGen/AMDGPU/max.ll b/llvm/test/CodeGen/AMDGPU/max.ll
index 84ef83d47a8db..daf64869d8fe8 100644
--- a/llvm/test/CodeGen/AMDGPU/max.ll
+++ b/llvm/test/CodeGen/AMDGPU/max.ll
@@ -1173,7 +1173,7 @@ define amdgpu_kernel void @test_umax_uge_i64(ptr addrspace(1) %out, i64 %a, i64
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
-; SI-NEXT: v_cmp_ge_u64_e32 vcc, s[2:3], v[0:1]
+; SI-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1]
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: s_cselect_b32 s0, s3, s9
@@ -1281,7 +1281,7 @@ define amdgpu_kernel void @test_imax_sge_i64(ptr addrspace(1) %out, i64 %a, i64
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s9
-; SI-NEXT: v_cmp_ge_i64_e32 vcc, s[2:3], v[0:1]
+; SI-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1]
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: s_and_b64 s[0:1], vcc, exec
; SI-NEXT: s_cselect_b32 s0, s3, s9
diff --git a/llvm/test/CodeGen/AMDGPU/min.ll b/llvm/test/CodeGen/AMDGPU/min.ll
index 6ebb6aaa4520f..58f619e2c1bf1 100644
--- a/llvm/test/CodeGen/AMDGPU/min.ll
+++ b/llvm/test/CodeGen/AMDGPU/min.ll
@@ -2937,7 +2937,7 @@ define amdgpu_kernel void @v_test_umin_ult_i32_multi_use(ptr addrspace(1) %out0,
; EG: ; %bb.0:
; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6
-; EG-NEXT: ALU 16, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 15, @12, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 0
; EG-NEXT: MEM_RAT MSKOR T2.XW, T3.X
; EG-NEXT: CF_END
@@ -2960,9 +2960,8 @@ define amdgpu_kernel void @v_test_umin_ult_i32_multi_use(ptr addrspace(1) %out0,
; EG-NEXT: MOV T2.Y, 0.0,
; EG-NEXT: MOV * T2.Z, 0.0,
; EG-NEXT: LSHR T3.X, KC0[2].Z, literal.x,
-; EG-NEXT: SETGE_UINT * T0.W, T0.X, T1.X,
+; EG-NEXT: MIN_UINT * T0.X, T0.X, T1.X,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
-; EG-NEXT: CNDE_INT T0.X, PV.W, T0.X, T1.X,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
@@ -2982,10 +2981,9 @@ define amdgpu_kernel void @v_test_umin_ult_i32_multi_use(ptr addrspace(1) %out0,
; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_cmp_lt_u32 s4, s5
; CI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; CI-NEXT: s_min_u32 s2, s4, s5
+; CI-NEXT: v_mov_b32_e32 v5, s2
; CI-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1]
-; CI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; CI-NEXT: s_cselect_b32 s0, s4, s5
-; CI-NEXT: v_mov_b32_e32 v5, s0
; CI-NEXT: flat_store_dword v[0:1], v5
; CI-NEXT: flat_store_byte v[2:3], v4
; CI-NEXT: s_endpgm
@@ -3006,10 +3004,9 @@ define amdgpu_kernel void @v_test_umin_ult_i32_multi_use(ptr addrspace(1) %out0,
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_cmp_lt_u32 s4, s5
; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: s_min_u32 s2, s4, s5
+; VI-NEXT: v_mov_b32_e32 v5, s2
; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1]
-; VI-NEXT: s_and_b64 s[0:1], s[0:1], exec
-; VI-NEXT: s_cselect_b32 s0, s4, s5
-; VI-NEXT: v_mov_b32_e32 v5, s0
; VI-NEXT: flat_store_dword v[0:1], v5
; VI-NEXT: flat_store_byte v[2:3], v4
; VI-NEXT: s_endpgm
@@ -3024,10 +3021,9 @@ define amdgpu_kernel void @v_test_umin_ult_i32_multi_use(ptr addrspace(1) %out0,
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_cmp_lt_u32 s8, s9
; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0
+; GFX9-NEXT: s_min_u32 s6, s8, s9
+; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
-; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec
-; GFX9-NEXT: s_cselect_b32 s4, s8, s9
-; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: global_store_dword v0, v2, s[0:1]
; GFX9-NEXT: global_store_byte v0, v1, s[2:3]
; GFX9-NEXT: s_endpgm
@@ -3035,60 +3031,55 @@ define amdgpu_kernel void @v_test_umin_ult_i32_multi_use(ptr addrspace(1) %out0,
; GFX10-LABEL: v_test_umin_ult_i32_multi_use:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0
-; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_load_dword s8, s[4:5], 0x0
; GFX10-NEXT: s_load_dword s9, s[6:7], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_cmp_lt_u32 s8, s9
; GFX10-NEXT: s_cselect_b32 s4, -1, 0
-; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
-; GFX10-NEXT: s_and_b32 s4, s4, exec_lo
-; GFX10-NEXT: s_cselect_b32 s4, s8, s9
-; GFX10-NEXT: v_mov_b32_e32 v2, s4
-; GFX10-NEXT: global_store_dword v1, v2, s[0:1]
-; GFX10-NEXT: global_store_byte v1, v0, s[2:3]
+; GFX10-NEXT: s_min_u32 s5, s8, s9
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s4
+; GFX10-NEXT: v_mov_b32_e32 v1, s5
+; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX10-NEXT: global_store_byte v0, v2, s[2:3]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: v_test_umin_ult_i32_multi_use:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b256 s[0:7], s[4:5], 0x0
-; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_load_b32 s4, s[4:5], 0x0
; GFX11-NEXT: s_load_b32 s5, s[6:7], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_cmp_lt_u32 s4, s5
; GFX11-NEXT: s_cselect_b32 s6, -1, 0
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s6
-; GFX11-NEXT: s_and_b32 s6, s6, exec_lo
-; GFX11-NEXT: s_cselect_b32 s4, s4, s5
-; GFX11-NEXT: v_mov_b32_e32 v2, s4
+; GFX11-NEXT: s_min_u32 s4, s4, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s6
+; GFX11-NEXT: v_mov_b32_e32 v1, s4
; GFX11-NEXT: s_clause 0x1
-; GFX11-NEXT: global_store_b32 v1, v2, s[0:1]
-; GFX11-NEXT: global_store_b8 v1, v0, s[2:3]
+; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
+; GFX11-NEXT: global_store_b8 v0, v2, s[2:3]
; GFX11-NEXT: s_endpgm
;
; GFX1250-LABEL: v_test_umin_ult_i32_multi_use:
; GFX1250: ; %bb.0:
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: s_load_b256 s[8:15], s[4:5], 0x0 nv
-; GFX1250-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-NEXT: v_mov_b32_e32 v0, 0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_load_b32 s0, s[12:13], 0x0
; GFX1250-NEXT: s_load_b32 s1, s[14:15], 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_cmp_lt_u32 s0, s1
; GFX1250-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, s2
-; GFX1250-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1250-NEXT: s_cselect_b32 s0, s0, s1
-; GFX1250-NEXT: v_mov_b32_e32 v2, s0
+; GFX1250-NEXT: s_min_u32 s0, s0, s1
+; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, s2
+; GFX1250-NEXT: v_mov_b32_e32 v1, s0
; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b32 v1, v2, s[8:9]
-; GFX1250-NEXT: global_store_b8 v1, v0, s[10:11]
+; GFX1250-NEXT: global_store_b32 v0, v1, s[8:9]
+; GFX1250-NEXT: global_store_b8 v0, v2, s[10:11]
; GFX1250-NEXT: s_endpgm
%a = load i32, ptr addrspace(1) %aptr, align 4
%b = load i32, ptr addrspace(1) %bptr, align 4
@@ -3104,7 +3095,7 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; EG: ; %bb.0:
; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6
-; EG-NEXT: ALU 24, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 23, @12, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT MSKOR T2.XW, T3.X
; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
; EG-NEXT: CF_END
@@ -3116,13 +3107,12 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; EG-NEXT: MOV * T1.X, KC0[3].X,
; EG-NEXT: ALU clause starting at 12:
; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
-; EG-NEXT: SETGE_UINT * T1.W, T0.X, T1.X,
+; EG-NEXT: MIN_UINT * T1.W, T0.X, T1.X,
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
-; EG-NEXT: CNDE_INT T1.W, PS, T0.X, T1.X,
; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
-; EG-NEXT: LSHL T2.X, PV.W, PS,
-; EG-NEXT: LSHL * T2.W, literal.x, PS,
+; EG-NEXT: LSHL T2.X, T1.W, PV.W,
+; EG-NEXT: LSHL * T2.W, literal.x, PV.W,
; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
; EG-NEXT: MOV T2.Y, 0.0,
; EG-NEXT: AND_INT T0.W, KC0[2].Z, literal.x,
@@ -3159,11 +3149,11 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; CI-NEXT: v_mov_b32_e32 v2, s2
; CI-NEXT: v_mov_b32_e32 v3, s3
; CI-NEXT: s_waitcnt vmcnt(0)
+; CI-NEXT: v_min_u32_e32 v6, v4, v5
; CI-NEXT: v_cmp_lt_u32_e32 vcc, v4, v5
-; CI-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
-; CI-NEXT: flat_store_short v[0:1], v4
-; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; CI-NEXT: flat_store_byte v[2:3], v0
+; CI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; CI-NEXT: flat_store_short v[0:1], v6
+; CI-NEXT: flat_store_byte v[2:3], v4
; CI-NEXT: s_endpgm
;
; VI-LABEL: v_test_umin_ult_i16_multi_use:
@@ -3184,14 +3174,14 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
; VI-NEXT: s_waitcnt vmcnt(1)
-; VI-NEXT: v_and_b32_e32 v6, 0xffff, v4
+; VI-NEXT: v_and_b32_e32 v4, 0xffff, v4
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_and_b32_e32 v7, 0xffff, v5
-; VI-NEXT: v_cmp_lt_u32_e32 vcc, v7, v6
-; VI-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
-; VI-NEXT: flat_store_short v[0:1], v4
-; VI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; VI-NEXT: flat_store_byte v[2:3], v0
+; VI-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; VI-NEXT: v_min_u32_e32 v6, v5, v4
+; VI-NEXT: v_cmp_lt_u32_e32 vcc, v5, v4
+; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
+; VI-NEXT: flat_store_short v[0:1], v6
+; VI-NEXT: flat_store_byte v[2:3], v4
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: v_test_umin_ult_i16_multi_use:
@@ -3202,10 +3192,10 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; GFX9-NEXT: global_load_ushort v1, v0, s[4:5]
; GFX9-NEXT: global_load_ushort v2, v0, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_cmp_lt_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:WORD_0
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
-; GFX9-NEXT: global_store_short v0, v1, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
+; GFX9-NEXT: v_min_u32_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
+; GFX9-NEXT: v_cmp_lt_u32_sdwa s[4:5], v1, v2 src0_sel:WORD_0 src1_sel:WORD_0
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
+; GFX9-NEXT: global_store_short v0, v3, s[0:1]
; GFX9-NEXT: global_store_byte v0, v1, s[2:3]
; GFX9-NEXT: s_endpgm
;
@@ -3218,11 +3208,11 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; GFX10-NEXT: global_load_ushort v1, v0, s[4:5]
; GFX10-NEXT: global_load_ushort v2, v0, s[6:7]
; GFX10-NEXT: s_waitcnt vmcnt(0)
-; GFX10-NEXT: v_cmp_lt_u32_sdwa vcc_lo, v1, v2 src0_sel:WORD_0 src1_sel:WORD_0
-; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
-; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
-; GFX10-NEXT: global_store_short v0, v1, s[0:1]
-; GFX10-NEXT: global_store_byte v0, v2, s[2:3]
+; GFX10-NEXT: v_cmp_lt_u32_sdwa s4, v1, v2 src0_sel:WORD_0 src1_sel:WORD_0
+; GFX10-NEXT: v_min_u32_sdwa v3, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
+; GFX10-NEXT: global_store_short v0, v3, s[0:1]
+; GFX10-NEXT: global_store_byte v0, v1, s[2:3]
; GFX10-NEXT: s_endpgm
;
; GFX11-TRUE16-LABEL: v_test_umin_ult_i16_multi_use:
@@ -3234,16 +3224,16 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; GFX11-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[6:7]
; GFX11-TRUE16-NEXT: global_load_d16_b16 v2, v0, s[4:5]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_lt_u32_e32 vcc_lo, v4, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_u32_e32 vcc_lo, v2, v1
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v3, v2, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-TRUE16-NEXT: global_store_b8 v0, v2, s[2:3]
+; GFX11-TRUE16-NEXT: global_store_b16 v0, v3, s[0:1]
+; GFX11-TRUE16-NEXT: global_store_b8 v0, v1, s[2:3]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_test_umin_ult_i16_multi_use:
@@ -3255,16 +3245,16 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; GFX11-FAKE16-NEXT: global_load_u16 v1, v0, s[6:7]
; GFX11-FAKE16-NEXT: global_load_u16 v2, v0, s[4:5]
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v1
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v2
+; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-FAKE16-NEXT: v_cmp_lt_u32_e32 vcc_lo, v4, v3
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX11-FAKE16-NEXT: v_cmp_lt_u32_e32 vcc_lo, v2, v1
+; GFX11-FAKE16-NEXT: v_min_u32_e32 v3, v2, v1
+; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: global_store_b8 v0, v2, s[2:3]
+; GFX11-FAKE16-NEXT: global_store_b16 v0, v3, s[0:1]
+; GFX11-FAKE16-NEXT: global_store_b8 v0, v1, s[2:3]
; GFX11-FAKE16-NEXT: s_endpgm
;
; GFX1250-LABEL: v_test_umin_ult_i16_multi_use:
@@ -3277,16 +3267,16 @@ define amdgpu_kernel void @v_test_umin_ult_i16_multi_use(ptr addrspace(1) %out0,
; GFX1250-NEXT: global_load_u16 v1, v0, s[14:15]
; GFX1250-NEXT: global_load_u16 v2, v0, s[12:13]
; GFX1250-NEXT: s_wait_loadcnt 0x1
-; GFX1250-NEXT: v_and_b32_e32 v3, 0xffff, v1
+; GFX1250-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX1250-NEXT: s_wait_loadcnt 0x0
-; GFX1250-NEXT: v_and_b32_e32 v4, 0xffff, v2
+; GFX1250-NEXT: v_and_b32_e32 v2, 0xffff, v2
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, v4, v3
-; GFX1250-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc_lo
-; GFX1250-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo
+; GFX1250-NEXT: v_cmp_lt_u32_e32 vcc_lo, v2, v1
+; GFX1250-NEXT: v_min_u32_e32 v3, v2, v1
+; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX1250-NEXT: s_clause 0x1
-; GFX1250-NEXT: global_store_b16 v0, v1, s[8:9]
-; GFX1250-NEXT: global_store_b8 v0, v2, s[10:11]
+; GFX1250-NEXT: global_store_b16 v0, v3, s[8:9]
+; GFX1250-NEXT: global_store_b8 v0, v1, s[10:11]
; GFX1250-NEXT: s_endpgm
%a = load i16, ptr addrspace(1) %aptr, align 2
%b = load i16, ptr addrspace(1) %bptr, align 2
@@ -4435,7 +4425,7 @@ define amdgpu_kernel void @test_umin_ule_i64(ptr addrspace(1) %out, i64 %a, i64
; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s4
; CI-NEXT: v_mov_b32_e32 v2, s5
-; CI-NEXT: v_cmp_le_u64_e32 vcc, s[2:3], v[1:2]
+; CI-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[1:2]
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_and_b64 s[0:1], vcc, exec
; CI-NEXT: s_cselect_b32 s0, s3, s5
@@ -4456,7 +4446,7 @@ define amdgpu_kernel void @test_umin_ule_i64(ptr addrspace(1) %out, i64 %a, i64
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
-; VI-NEXT: v_cmp_le_u64_e32 vcc, s[2:3], v[1:2]
+; VI-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[1:2]
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_and_b64 s[0:1], vcc, exec
; VI-NEXT: s_cselect_b32 s0, s3, s5
@@ -4474,7 +4464,7 @@ define amdgpu_kernel void @test_umin_ule_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
-; GFX9-NEXT: v_cmp_le_u64_e32 vcc, s[2:3], v[0:1]
+; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: s_cselect_b32 s3, s3, s5
; GFX9-NEXT: s_cselect_b32 s2, s2, s4
@@ -4490,7 +4480,7 @@ define amdgpu_kernel void @test_umin_ule_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_cmp_le_u64_e64 s6, s[2:3], s[4:5]
+; GFX10-NEXT: v_cmp_lt_u64_e64 s6, s[2:3], s[4:5]
; GFX10-NEXT: s_and_b32 s6, s6, exec_lo
; GFX10-NEXT: s_cselect_b32 s2, s2, s4
; GFX10-NEXT: s_cselect_b32 s3, s3, s5
@@ -4506,7 +4496,7 @@ define amdgpu_kernel void @test_umin_ule_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x10
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_u64_e64 s6, s[2:3], s[4:5]
+; GFX11-NEXT: v_cmp_lt_u64_e64 s6, s[2:3], s[4:5]
; GFX11-NEXT: s_and_b32 s6, s6, exec_lo
; GFX11-NEXT: s_cselect_b32 s2, s2, s4
; GFX11-NEXT: s_cselect_b32 s3, s3, s5
@@ -4685,7 +4675,7 @@ define amdgpu_kernel void @test_imin_sle_i64(ptr addrspace(1) %out, i64 %a, i64
; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s4
; CI-NEXT: v_mov_b32_e32 v2, s5
-; CI-NEXT: v_cmp_le_i64_e32 vcc, s[2:3], v[1:2]
+; CI-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[1:2]
; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: s_and_b64 s[0:1], vcc, exec
; CI-NEXT: s_cselect_b32 s0, s3, s5
@@ -4706,7 +4696,7 @@ define amdgpu_kernel void @test_imin_sle_i64(ptr addrspace(1) %out, i64 %a, i64
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s4
; VI-NEXT: v_mov_b32_e32 v2, s5
-; VI-NEXT: v_cmp_le_i64_e32 vcc, s[2:3], v[1:2]
+; VI-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[1:2]
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_and_b64 s[0:1], vcc, exec
; VI-NEXT: s_cselect_b32 s0, s3, s5
@@ -4724,7 +4714,7 @@ define amdgpu_kernel void @test_imin_sle_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
-; GFX9-NEXT: v_cmp_le_i64_e32 vcc, s[2:3], v[0:1]
+; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
; GFX9-NEXT: s_and_b64 s[6:7], vcc, exec
; GFX9-NEXT: s_cselect_b32 s3, s3, s5
; GFX9-NEXT: s_cselect_b32 s2, s2, s4
@@ -4740,7 +4730,7 @@ define amdgpu_kernel void @test_imin_sle_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[8:9], 0x10
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_cmp_le_i64_e64 s6, s[2:3], s[4:5]
+; GFX10-NEXT: v_cmp_lt_i64_e64 s6, s[2:3], s[4:5]
; GFX10-NEXT: s_and_b32 s6, s6, exec_lo
; GFX10-NEXT: s_cselect_b32 s2, s2, s4
; GFX10-NEXT: s_cselect_b32 s3, s3, s5
@@ -4756,7 +4746,7 @@ define amdgpu_kernel void @test_imin_sle_i64(ptr addrspace(1) %out, i64 %a, i64
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x10
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_cmp_le_i64_e64 s6, s[2:3], s[4:5]
+; GFX11-NEXT: v_cmp_lt_i64_e64 s6, s[2:3], s[4:5]
; GFX11-NEXT: s_and_b32 s6, s6, exec_lo
; GFX11-NEXT: s_cselect_b32 s2, s2, s4
; GFX11-NEXT: s_cselect_b32 s3, s3, s5
diff --git a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
index 76f8f484fc763..016175011c4b1 100644
--- a/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
@@ -859,27 +859,25 @@ define amdgpu_kernel void @v_min_max_v2i16_user(ptr addrspace(1) %out0, ptr addr
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v2, v0, s[14:15] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX9-NEXT: v_cmp_gt_i32_sdwa vcc, sext(v1), sext(v2) src0_sel:WORD_0 src1_sel:WORD_0
; GFX9-NEXT: v_cmp_gt_i32_sdwa s[0:1], sext(v1), sext(v2) src0_sel:WORD_1 src1_sel:WORD_1
-; GFX9-NEXT: v_lshrrev_b32_e32 v4, 16, v2
-; GFX9-NEXT: v_cndmask_b32_e32 v5, v2, v1, vcc
-; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
-; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v6, v4, v3, s[0:1]
-; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
-; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v5
-; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1
-; GFX9-NEXT: v_lshlrev_b32_e32 v2, 1, v2
-; GFX9-NEXT: v_lshl_or_b32 v4, v6, 16, v4
-; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1
-; GFX9-NEXT: v_or_b32_e32 v2, v5, v2
-; GFX9-NEXT: global_store_dword v0, v4, s[8:9]
+; GFX9-NEXT: v_max_i32_sdwa v4, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
+; GFX9-NEXT: v_min_i32_sdwa v6, sext(v2), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:WORD_0
+; GFX9-NEXT: v_cndmask_b32_e64 v7, 0, 1, s[0:1]
+; GFX9-NEXT: v_cmp_gt_i32_sdwa s[0:1], sext(v1), sext(v2) src0_sel:WORD_0 src1_sel:WORD_0
+; GFX9-NEXT: v_max_i32_sdwa v3, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_min_i32_sdwa v5, sext(v2), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
+; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
+; GFX9-NEXT: v_and_b32_e32 v2, 0xffff, v4
+; GFX9-NEXT: v_and_b32_e32 v4, 0xffff, v6
+; GFX9-NEXT: v_lshlrev_b32_e32 v6, 1, v7
+; GFX9-NEXT: v_lshl_or_b32 v2, v3, 16, v2
+; GFX9-NEXT: v_or_b32_e32 v1, v1, v6
+; GFX9-NEXT: v_lshl_or_b32 v3, v5, 16, v4
+; GFX9-NEXT: global_store_dword v0, v2, s[8:9]
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: global_store_dword v0, v1, s[10:11]
+; GFX9-NEXT: global_store_dword v0, v3, s[10:11]
; GFX9-NEXT: s_waitcnt vmcnt(0)
-; GFX9-NEXT: v_and_b32_e32 v0, 3, v2
+; GFX9-NEXT: v_and_b32_e32 v0, 3, v1
; GFX9-NEXT: global_store_byte v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm
@@ -900,81 +898,87 @@ define amdgpu_kernel void @v_min_max_v2i16_user(ptr addrspace(1) %out0, ptr addr
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s3
-; VI-NEXT: v_ashrrev_i32_e32 v10, 16, v4
-; VI-NEXT: v_ashrrev_i32_e32 v11, 16, v5
-; VI-NEXT: v_bfe_i32 v6, v4, 0, 16
-; VI-NEXT: v_bfe_i32 v7, v5, 0, 16
-; VI-NEXT: v_lshrrev_b32_e32 v8, 16, v4
-; VI-NEXT: v_lshrrev_b32_e32 v9, 16, v5
-; VI-NEXT: v_cmp_gt_i32_e32 vcc, v10, v11
-; VI-NEXT: v_cndmask_b32_e32 v10, v9, v8, vcc
-; VI-NEXT: v_cmp_gt_i32_e64 s[0:1], v6, v7
-; VI-NEXT: v_cndmask_b32_e64 v6, v5, v4, s[0:1]
-; VI-NEXT: v_cndmask_b32_e32 v7, v8, v9, vcc
-; VI-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; VI-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1]
-; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; VI-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[0:1]
-; VI-NEXT: v_or_b32_sdwa v6, v6, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; VI-NEXT: v_readfirstlane_b32 s0, v4
+; VI-NEXT: v_readfirstlane_b32 s1, v5
+; VI-NEXT: s_ashr_i32 s2, s0, 16
+; VI-NEXT: s_ashr_i32 s3, s1, 16
+; VI-NEXT: s_sext_i32_i16 s4, s0
+; VI-NEXT: s_sext_i32_i16 s5, s1
+; VI-NEXT: s_cmp_gt_i32 s4, s5
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: s_cmp_gt_i32 s2, s3
+; VI-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[0:1]
+; VI-NEXT: s_cselect_b64 s[0:1], -1, 0
+; VI-NEXT: s_max_i32 s6, s2, s3
+; VI-NEXT: s_max_i32 s7, s4, s5
+; VI-NEXT: s_min_i32 s2, s3, s2
+; VI-NEXT: s_min_i32 s3, s5, s4
+; VI-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[0:1]
+; VI-NEXT: s_lshl_b32 s0, s6, 16
+; VI-NEXT: s_and_b32 s1, s7, 0xffff
+; VI-NEXT: s_lshl_b32 s2, s2, 16
+; VI-NEXT: s_and_b32 s3, s3, 0xffff
; VI-NEXT: v_lshlrev_b32_e32 v5, 1, v5
-; VI-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; VI-NEXT: flat_store_dword v[0:1], v6
+; VI-NEXT: s_or_b32 s0, s1, s0
+; VI-NEXT: s_or_b32 s1, s3, s2
+; VI-NEXT: v_or_b32_e32 v4, v4, v5
+; VI-NEXT: v_mov_b32_e32 v5, s0
+; VI-NEXT: v_mov_b32_e32 v6, s1
+; VI-NEXT: v_and_b32_e32 v4, 3, v4
+; VI-NEXT: flat_store_dword v[0:1], v5
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_or_b32_e32 v0, v9, v5
-; VI-NEXT: v_or_b32_sdwa v4, v4, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; VI-NEXT: v_and_b32_e32 v0, 3, v0
-; VI-NEXT: flat_store_dword v[2:3], v4
+; VI-NEXT: flat_store_dword v[2:3], v6
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: flat_store_byte v[0:1], v0
+; VI-NEXT: flat_store_byte v[0:1], v4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm
;
; CI-LABEL: v_min_max_v2i16_user:
; CI: ; %bb.0:
-; CI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x9
-; CI-NEXT: s_mov_b32 s7, 0xf000
-; CI-NEXT: s_mov_b32 s6, -1
-; CI-NEXT: s_mov_b32 s2, s6
-; CI-NEXT: s_mov_b32 s3, s7
+; CI-NEXT: s_load_dwordx8 s[4:11], s[4:5], 0x9
+; CI-NEXT: s_mov_b32 s3, 0xf000
+; CI-NEXT: s_mov_b32 s2, -1
+; CI-NEXT: s_mov_b32 s14, s2
+; CI-NEXT: s_mov_b32 s15, s3
; CI-NEXT: s_waitcnt lgkmcnt(0)
-; CI-NEXT: s_mov_b32 s0, s12
-; CI-NEXT: s_mov_b32 s1, s13
-; CI-NEXT: s_mov_b32 s12, s14
-; CI-NEXT: s_mov_b32 s13, s15
-; CI-NEXT: s_mov_b32 s14, s6
-; CI-NEXT: s_mov_b32 s15, s7
-; CI-NEXT: buffer_load_sshort v0, off, s[0:3], 0 glc
+; CI-NEXT: s_mov_b32 s12, s8
+; CI-NEXT: s_mov_b32 s13, s9
+; CI-NEXT: s_mov_b32 s8, s10
+; CI-NEXT: s_mov_b32 s9, s11
+; CI-NEXT: s_mov_b32 s10, s2
+; CI-NEXT: s_mov_b32 s11, s3
+; CI-NEXT: buffer_load_sshort v0, off, s[12:15], 0 glc
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: buffer_load_sshort v1, off, s[0:3], 0 offset:2 glc
+; CI-NEXT: buffer_load_sshort v1, off, s[12:15], 0 offset:2 glc
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: buffer_load_sshort v2, off, s[12:15], 0 glc
+; CI-NEXT: buffer_load_sshort v2, off, s[8:11], 0 glc
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: buffer_load_sshort v3, off, s[12:15], 0 offset:2 glc
+; CI-NEXT: buffer_load_sshort v3, off, s[8:11], 0 offset:2 glc
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: s_mov_b32 s4, s8
-; CI-NEXT: s_mov_b32 s5, s9
-; CI-NEXT: s_mov_b32 s12, s10
-; CI-NEXT: s_mov_b32 s13, s11
+; CI-NEXT: s_mov_b32 s0, s4
+; CI-NEXT: s_mov_b32 s1, s5
+; CI-NEXT: s_mov_b32 s8, s6
+; CI-NEXT: s_mov_b32 s9, s7
+; CI-NEXT: v_max_i32_e32 v4, v0, v2
+; CI-NEXT: v_cmp_gt_i32_e32 vcc, v1, v3
+; CI-NEXT: v_max_i32_e32 v5, v1, v3
+; CI-NEXT: v_min_i32_e32 v7, v3, v1
+; CI-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; CI-NEXT: v_cmp_gt_i32_e32 vcc, v0, v2
-; CI-NEXT: v_cmp_gt_i32_e64 s[0:1], v1, v3
-; CI-NEXT: v_cndmask_b32_e32 v4, v2, v0, vcc
-; CI-NEXT: v_cndmask_b32_e64 v5, v3, v1, s[0:1]
-; CI-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CI-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
-; CI-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
-; CI-NEXT: buffer_store_short v5, off, s[4:7], 0 offset:2
+; CI-NEXT: v_min_i32_e32 v6, v2, v0
+; CI-NEXT: v_lshlrev_b32_e32 v1, 1, v1
+; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
+; CI-NEXT: v_or_b32_e32 v0, v0, v1
+; CI-NEXT: v_and_b32_e32 v0, 3, v0
+; CI-NEXT: buffer_store_short v5, off, s[0:3], 0 offset:2
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: buffer_store_short v4, off, s[4:7], 0
+; CI-NEXT: buffer_store_short v4, off, s[0:3], 0
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: buffer_store_short v1, off, s[12:15], 0 offset:2
+; CI-NEXT: buffer_store_short v7, off, s[8:11], 0 offset:2
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: buffer_store_short v0, off, s[12:15], 0
+; CI-NEXT: buffer_store_short v6, off, s[8:11], 0
; CI-NEXT: s_waitcnt vmcnt(0)
-; CI-NEXT: v_lshlrev_b32_e32 v0, 1, v2
-; CI-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CI-NEXT: v_or_b32_e32 v0, v1, v0
-; CI-NEXT: v_and_b32_e32 v0, 3, v0
-; CI-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; CI-NEXT: buffer_store_byte v0, off, s[0:3], 0
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_endpgm
%val0 = load volatile <2 x i16>, ptr addrspace(1) %ptr0
diff --git a/llvm/test/CodeGen/ARM/atomic-64bit.ll b/llvm/test/CodeGen/ARM/atomic-64bit.ll
index ca9939c0f8c55..b99f1136a16c5 100644
--- a/llvm/test/CodeGen/ARM/atomic-64bit.ll
+++ b/llvm/test/CodeGen/ARM/atomic-64bit.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB --check-prefix=CHECK-THUMB-LE
; RUN: llc < %s -mtriple=armebv7 -target-abi apcs | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
@@ -6,214 +7,529 @@
; RUN: llc < %s -mtriple=armv8m--none-eabi | FileCheck %s --check-prefix=CHECK-M
define i64 @test1(ptr %ptr, i64 %val) {
-; CHECK-LABEL: test1:
-; CHECK: dmb {{ish$}}
-; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK-LE: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
-; CHECK-LE: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
-; CHECK-BE: adds [[REG4:(r[0-9]?[13579])]], [[REG2]]
-; CHECK-BE: adc [[REG3:(r[0-9]?[02468])]], [[REG1]]
-; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
-; CHECK: cmp
-; CHECK: bne
-; CHECK: dmb {{ish$}}
-
-; CHECK-THUMB-LABEL: test1:
-; CHECK-THUMB: dmb {{ish$}}
-; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB-LE: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
-; CHECK-THUMB-LE: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
-; CHECK-THUMB-BE: adds.w [[REG4:[a-z0-9]+]], [[REG2]]
-; CHECK-THUMB-BE: adc.w [[REG3:[a-z0-9]+]], [[REG1]]
-; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
-; CHECK-THUMB: cmp
-; CHECK-THUMB: bne
-; CHECK-THUMB: dmb {{ish$}}
-
-; CHECK-M: __atomic_fetch_add_8
+; CHECK-LE-LABEL: test1:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: LBB0_1: @ %atomicrmw.start
+; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-LE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-LE-NEXT: adds r6, r4, r1
+; CHECK-LE-NEXT: adc r7, r5, r2
+; CHECK-LE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: bne LBB0_1
+; CHECK-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-LE-NEXT: mov r0, r4
+; CHECK-LE-NEXT: mov r1, r5
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: pop {r4, r5, r6, r7, pc}
+;
+; CHECK-THUMB-LE-LABEL: test1:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: mov r12, r0
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: .LBB0_1: @ %atomicrmw.start
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-LE-NEXT: adds.w lr, r0, r2
+; CHECK-THUMB-LE-NEXT: adc.w r4, r1, r3
+; CHECK-THUMB-LE-NEXT: strexd r5, lr, r4, [r12]
+; CHECK-THUMB-LE-NEXT: cmp r5, #0
+; CHECK-THUMB-LE-NEXT: bne .LBB0_1
+; CHECK-THUMB-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-BE-LABEL: test1:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: .LBB0_1: @ %atomicrmw.start
+; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-BE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-BE-NEXT: adds r7, r5, r2
+; CHECK-BE-NEXT: adc r6, r4, r1
+; CHECK-BE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: bne .LBB0_1
+; CHECK-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-BE-NEXT: mov r0, r4
+; CHECK-BE-NEXT: mov r1, r5
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: pop {r4, r5, r6, r7, pc}
+;
+; CHECK-THUMB-BE-LABEL: test1:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: mov r12, r0
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: .LBB0_1: @ %atomicrmw.start
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-BE-NEXT: adds.w lr, r1, r3
+; CHECK-THUMB-BE-NEXT: adc.w r4, r0, r2
+; CHECK-THUMB-BE-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-BE-NEXT: cmp r5, #0
+; CHECK-THUMB-BE-NEXT: bne .LBB0_1
+; CHECK-THUMB-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r7, pc}
+
+
%r = atomicrmw add ptr %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test2(ptr %ptr, i64 %val) {
-; CHECK-LABEL: test2:
-; CHECK: dmb {{ish$}}
-; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK-LE: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
-; CHECK-LE: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
-; CHECK-BE: subs [[REG4:(r[0-9]?[13579])]], [[REG2]]
-; CHECK-BE: sbc [[REG3:(r[0-9]?[02468])]], [[REG1]]
-; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
-; CHECK: cmp
-; CHECK: bne
-; CHECK: dmb {{ish$}}
-
-; CHECK-THUMB-LABEL: test2:
-; CHECK-THUMB: dmb {{ish$}}
-; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB-LE: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
-; CHECK-THUMB-LE: sbc.w [[REG4:[a-z0-9]+]], [[REG2]]
-; CHECK-THUMB-BE: subs.w [[REG4:[a-z0-9]+]], [[REG2]]
-; CHECK-THUMB-BE: sbc.w [[REG3:[a-z0-9]+]], [[REG1]]
-; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
-; CHECK-THUMB: cmp
-; CHECK-THUMB: bne
-; CHECK-THUMB: dmb {{ish$}}
-
-; CHECK-M: __atomic_fetch_sub_8
+; CHECK-LE-LABEL: test2:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: LBB1_1: @ %atomicrmw.start
+; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-LE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-LE-NEXT: subs r6, r4, r1
+; CHECK-LE-NEXT: sbc r7, r5, r2
+; CHECK-LE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: bne LBB1_1
+; CHECK-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-LE-NEXT: mov r0, r4
+; CHECK-LE-NEXT: mov r1, r5
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: pop {r4, r5, r6, r7, pc}
+;
+; CHECK-THUMB-LE-LABEL: test2:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: mov r12, r0
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: .LBB1_1: @ %atomicrmw.start
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-LE-NEXT: subs.w lr, r0, r2
+; CHECK-THUMB-LE-NEXT: sbc.w r4, r1, r3
+; CHECK-THUMB-LE-NEXT: strexd r5, lr, r4, [r12]
+; CHECK-THUMB-LE-NEXT: cmp r5, #0
+; CHECK-THUMB-LE-NEXT: bne .LBB1_1
+; CHECK-THUMB-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-BE-LABEL: test2:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: .LBB1_1: @ %atomicrmw.start
+; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-BE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-BE-NEXT: subs r7, r5, r2
+; CHECK-BE-NEXT: sbc r6, r4, r1
+; CHECK-BE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: bne .LBB1_1
+; CHECK-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-BE-NEXT: mov r0, r4
+; CHECK-BE-NEXT: mov r1, r5
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: pop {r4, r5, r6, r7, pc}
+;
+; CHECK-THUMB-BE-LABEL: test2:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: mov r12, r0
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: .LBB1_1: @ %atomicrmw.start
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-BE-NEXT: subs.w lr, r1, r3
+; CHECK-THUMB-BE-NEXT: sbc.w r4, r0, r2
+; CHECK-THUMB-BE-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-BE-NEXT: cmp r5, #0
+; CHECK-THUMB-BE-NEXT: bne .LBB1_1
+; CHECK-THUMB-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r7, pc}
+
+
%r = atomicrmw sub ptr %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test3(ptr %ptr, i64 %val) {
-; CHECK-LABEL: test3:
-; CHECK: dmb {{ish$}}
-; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK-LE-DAG: and [[REG3:(r[0-9]?[02468])]], [[REG1]],
-; CHECK-LE-DAG: and [[REG4:(r[0-9]?[13579])]], [[REG2]],
-; CHECK-BE-DAG: and [[REG4:(r[0-9]?[13579])]], [[REG2]],
-; CHECK-BE-DAG: and [[REG3:(r[0-9]?[02468])]], [[REG1]],
-; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
-; CHECK: cmp
-; CHECK: bne
-; CHECK: dmb {{ish$}}
-
+; CHECK-LE-LABEL: test3:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: LBB2_1: @ %atomicrmw.start
+; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-LE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-LE-NEXT: and r6, r4, r1
+; CHECK-LE-NEXT: and r7, r5, r2
+; CHECK-LE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: bne LBB2_1
+; CHECK-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-LE-NEXT: mov r0, r4
+; CHECK-LE-NEXT: mov r1, r5
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: pop {r4, r5, r6, r7, pc}
+;
; CHECK-THUMB-LABEL: test3:
-; CHECK-THUMB: dmb {{ish$}}
-; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB-LE-DAG: and.w [[REG3:[a-z0-9]+]], [[REG1]],
-; CHECK-THUMB-LE-DAG: and.w [[REG4:[a-z0-9]+]], [[REG2]],
-; CHECK-THUMB-BE-DAG: and.w [[REG4:[a-z0-9]+]], [[REG2]],
-; CHECK-THUMB-BE-DAG: and.w [[REG3:[a-z0-9]+]], [[REG1]],
-; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
-; CHECK-THUMB: cmp
-; CHECK-THUMB: bne
-; CHECK-THUMB: dmb {{ish$}}
-
-; CHECK-M: _atomic_fetch_and_8
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-NEXT: mov r12, r0
+; CHECK-THUMB-NEXT: dmb ish
+; CHECK-THUMB-NEXT: .LBB2_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-NEXT: and.w lr, r0, r2
+; CHECK-THUMB-NEXT: and.w r4, r1, r3
+; CHECK-THUMB-NEXT: strexd r5, lr, r4, [r12]
+; CHECK-THUMB-NEXT: cmp r5, #0
+; CHECK-THUMB-NEXT: bne .LBB2_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: dmb ish
+; CHECK-THUMB-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-BE-LABEL: test3:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: .LBB2_1: @ %atomicrmw.start
+; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-BE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-BE-NEXT: and r6, r4, r1
+; CHECK-BE-NEXT: and r7, r5, r2
+; CHECK-BE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: bne .LBB2_1
+; CHECK-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-BE-NEXT: mov r0, r4
+; CHECK-BE-NEXT: mov r1, r5
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: pop {r4, r5, r6, r7, pc}
+
+
%r = atomicrmw and ptr %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test4(ptr %ptr, i64 %val) {
-; CHECK-LABEL: test4:
-; CHECK: dmb {{ish$}}
-; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK-LE-DAG: orr [[REG3:(r[0-9]?[02468])]], [[REG1]],
-; CHECK-LE-DAG: orr [[REG4:(r[0-9]?[13579])]], [[REG2]],
-; CHECK-BE-DAG: orr [[REG4:(r[0-9]?[13579])]], [[REG2]],
-; CHECK-BE-DAG: orr [[REG3:(r[0-9]?[02468])]], [[REG1]],
-; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
-; CHECK: cmp
-; CHECK: bne
-; CHECK: dmb {{ish$}}
-
+; CHECK-LE-LABEL: test4:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: LBB3_1: @ %atomicrmw.start
+; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-LE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-LE-NEXT: orr r6, r4, r1
+; CHECK-LE-NEXT: orr r7, r5, r2
+; CHECK-LE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: bne LBB3_1
+; CHECK-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-LE-NEXT: mov r0, r4
+; CHECK-LE-NEXT: mov r1, r5
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: pop {r4, r5, r6, r7, pc}
+;
; CHECK-THUMB-LABEL: test4:
-; CHECK-THUMB: dmb {{ish$}}
-; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB-LE-DAG: orr.w [[REG3:[a-z0-9]+]], [[REG1]],
-; CHECK-THUMB-LE-DAG: orr.w [[REG4:[a-z0-9]+]], [[REG2]],
-; CHECK-THUMB-BE-DAG: orr.w [[REG4:[a-z0-9]+]], [[REG2]],
-; CHECK-THUMB-BE-DAG: orr.w [[REG3:[a-z0-9]+]], [[REG1]],
-; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
-; CHECK-THUMB: cmp
-; CHECK-THUMB: bne
-; CHECK-THUMB: dmb {{ish$}}
-
-; CHECK-M: __atomic_fetch_or_8
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-NEXT: mov r12, r0
+; CHECK-THUMB-NEXT: dmb ish
+; CHECK-THUMB-NEXT: .LBB3_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-NEXT: orr.w lr, r0, r2
+; CHECK-THUMB-NEXT: orr.w r4, r1, r3
+; CHECK-THUMB-NEXT: strexd r5, lr, r4, [r12]
+; CHECK-THUMB-NEXT: cmp r5, #0
+; CHECK-THUMB-NEXT: bne .LBB3_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: dmb ish
+; CHECK-THUMB-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-BE-LABEL: test4:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: .LBB3_1: @ %atomicrmw.start
+; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-BE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-BE-NEXT: orr r6, r4, r1
+; CHECK-BE-NEXT: orr r7, r5, r2
+; CHECK-BE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: bne .LBB3_1
+; CHECK-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-BE-NEXT: mov r0, r4
+; CHECK-BE-NEXT: mov r1, r5
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: pop {r4, r5, r6, r7, pc}
+
+
%r = atomicrmw or ptr %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test5(ptr %ptr, i64 %val) {
-; CHECK-LABEL: test5:
-; CHECK: dmb {{ish$}}
-; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK-LE-DAG: eor [[REG3:(r[0-9]?[02468])]], [[REG1]],
-; CHECK-LE-DAG: eor [[REG4:(r[0-9]?[13579])]], [[REG2]],
-; CHECK-BE-DAG: eor [[REG4:(r[0-9]?[13579])]], [[REG2]],
-; CHECK-BE-DAG: eor [[REG3:(r[0-9]?[02468])]], [[REG1]],
-; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
-; CHECK: cmp
-; CHECK: bne
-; CHECK: dmb {{ish$}}
-
+; CHECK-LE-LABEL: test5:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: LBB4_1: @ %atomicrmw.start
+; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-LE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-LE-NEXT: eor r6, r4, r1
+; CHECK-LE-NEXT: eor r7, r5, r2
+; CHECK-LE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: bne LBB4_1
+; CHECK-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-LE-NEXT: mov r0, r4
+; CHECK-LE-NEXT: mov r1, r5
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: pop {r4, r5, r6, r7, pc}
+;
; CHECK-THUMB-LABEL: test5:
-; CHECK-THUMB: dmb {{ish$}}
-; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB-LE-DAG: eor.w [[REG3:[a-z0-9]+]], [[REG1]],
-; CHECK-THUMB-LE-DAG: eor.w [[REG4:[a-z0-9]+]], [[REG2]],
-; CHECK-THUMB-BE-DAG: eor.w [[REG4:[a-z0-9]+]], [[REG2]],
-; CHECK-THUMB-BE-DAG: eor.w [[REG3:[a-z0-9]+]], [[REG1]],
-; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
-; CHECK-THUMB: cmp
-; CHECK-THUMB: bne
-; CHECK-THUMB: dmb {{ish$}}
-
-; CHECK-M: __atomic_fetch_xor_8
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-NEXT: mov r12, r0
+; CHECK-THUMB-NEXT: dmb ish
+; CHECK-THUMB-NEXT: .LBB4_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-NEXT: eor.w lr, r0, r2
+; CHECK-THUMB-NEXT: eor.w r4, r1, r3
+; CHECK-THUMB-NEXT: strexd r5, lr, r4, [r12]
+; CHECK-THUMB-NEXT: cmp r5, #0
+; CHECK-THUMB-NEXT: bne .LBB4_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: dmb ish
+; CHECK-THUMB-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-BE-LABEL: test5:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: .LBB4_1: @ %atomicrmw.start
+; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-BE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-BE-NEXT: eor r6, r4, r1
+; CHECK-BE-NEXT: eor r7, r5, r2
+; CHECK-BE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: bne .LBB4_1
+; CHECK-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-BE-NEXT: mov r0, r4
+; CHECK-BE-NEXT: mov r1, r5
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: pop {r4, r5, r6, r7, pc}
+
+
%r = atomicrmw xor ptr %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test6(ptr %ptr, i64 %val) {
-; CHECK-LABEL: test6:
-; CHECK: dmb {{ish$}}
-; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
-; CHECK: cmp
-; CHECK: bne
-; CHECK: dmb {{ish$}}
-
+; CHECK-LE-LABEL: test6:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: push {r4, r5, lr}
+; CHECK-LE-NEXT: mov r5, r2
+; CHECK-LE-NEXT: mov r2, r0
+; CHECK-LE-NEXT: mov r4, r1
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: LBB5_1: @ %atomicrmw.start
+; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-LE-NEXT: ldrexd r0, r1, [r2]
+; CHECK-LE-NEXT: strexd r3, r4, r5, [r2]
+; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: bne LBB5_1
+; CHECK-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: pop {r4, r5, pc}
+;
; CHECK-THUMB-LABEL: test6:
-; CHECK-THUMB: dmb {{ish$}}
-; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
-; CHECK-THUMB: cmp
-; CHECK-THUMB: bne
-; CHECK-THUMB: dmb {{ish$}}
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: .save {r7, lr}
+; CHECK-THUMB-NEXT: push {r7, lr}
+; CHECK-THUMB-NEXT: dmb ish
+; CHECK-THUMB-NEXT: .LBB5_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexd r12, r1, [r0]
+; CHECK-THUMB-NEXT: strexd lr, r2, r3, [r0]
+; CHECK-THUMB-NEXT: cmp.w lr, #0
+; CHECK-THUMB-NEXT: bne .LBB5_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r12
+; CHECK-THUMB-NEXT: dmb ish
+; CHECK-THUMB-NEXT: pop {r7, pc}
+;
+; CHECK-BE-LABEL: test6:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: push {r4, r5, lr}
+; CHECK-BE-NEXT: mov r5, r2
+; CHECK-BE-NEXT: mov r2, r0
+; CHECK-BE-NEXT: mov r4, r1
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: .LBB5_1: @ %atomicrmw.start
+; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-BE-NEXT: ldrexd r0, r1, [r2]
+; CHECK-BE-NEXT: strexd r3, r4, r5, [r2]
+; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: bne .LBB5_1
+; CHECK-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: pop {r4, r5, pc}
+
-; CHECK-M: __atomic_exchange_8
%r = atomicrmw xchg ptr %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test7(ptr %ptr, i64 %val1, i64 %val2) {
-; CHECK-LABEL: test7:
-; CHECK-DAG: mov [[VAL1LO:r[0-9]+]], r1
-; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK-LE-DAG: eor [[MISMATCH_LO:.*]], [[REG1]], [[VAL1LO]]
-; CHECK-LE-DAG: eor [[MISMATCH_HI:.*]], [[REG2]], r2
-; CHECK-BE-DAG: eor [[MISMATCH_LO:.*]], [[REG2]], r2
-; CHECK-BE-DAG: eor [[MISMATCH_HI:.*]], [[REG1]], r1
-; CHECK: orrs {{r[0-9]+}}, [[MISMATCH_LO]], [[MISMATCH_HI]]
-; CHECK: bne
-; CHECK-DAG: dmb {{ish$}}
-; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
-; CHECK: cmp
-; CHECK: beq
-; CHECK: dmb {{ish$}}
-
-; CHECK-THUMB-LABEL: test7:
-; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB-LE-DAG: eor.w [[MISMATCH_LO:[a-z0-9]+]], [[REG1]], r2
-; CHECK-THUMB-LE-DAG: eor.w [[MISMATCH_HI:[a-z0-9]+]], [[REG2]], r3
-; CHECK-THUMB-BE-DAG: eor.w [[MISMATCH_HI:[a-z0-9]+]], [[REG1]], r2
-; CHECK-THUMB-BE-DAG: eor.w [[MISMATCH_LO:[a-z0-9]+]], [[REG2]], r3
-; CHECK-THUMB-LE: orrs.w {{.*}}, [[MISMATCH_LO]], [[MISMATCH_HI]]
-; CHECK-THUMB: bne
-; CHECK-THUMB: dmb {{ish$}}
-; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
-; CHECK-THUMB: cmp
-; CHECK-THUMB: beq
-; CHECK-THUMB: dmb {{ish$}}
-
-; CHECK-M: __atomic_compare_exchange_8
+; CHECK-LE-LABEL: test7:
+; CHECK-LE: @ %bb.0: @ %cmpxchg.start
+; CHECK-LE-NEXT: push {r4, r6, r7, lr}
+; CHECK-LE-NEXT: mov r9, r1
+; CHECK-LE-NEXT: mov r12, r0
+; CHECK-LE-NEXT: ldrexd r0, r1, [r0]
+; CHECK-LE-NEXT: mov r6, r3
+; CHECK-LE-NEXT: eor r3, r1, r2
+; CHECK-LE-NEXT: eor r4, r0, r9
+; CHECK-LE-NEXT: orrs r3, r4, r3
+; CHECK-LE-NEXT: bne LBB6_4
+; CHECK-LE-NEXT: @ %bb.1: @ %cmpxchg.fencedstore
+; CHECK-LE-NEXT: ldr r7, [sp, #16]
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: LBB6_2: @ %cmpxchg.trystore
+; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-LE-NEXT: strexd r3, r6, r7, [r12]
+; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: beq LBB6_5
+; CHECK-LE-NEXT: @ %bb.3: @ %cmpxchg.releasedload
+; CHECK-LE-NEXT: @ in Loop: Header=BB6_2 Depth=1
+; CHECK-LE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-LE-NEXT: eor r3, r0, r9
+; CHECK-LE-NEXT: eor r4, r1, r2
+; CHECK-LE-NEXT: orrs r3, r3, r4
+; CHECK-LE-NEXT: beq LBB6_2
+; CHECK-LE-NEXT: LBB6_4: @ %cmpxchg.nostore
+; CHECK-LE-NEXT: clrex
+; CHECK-LE-NEXT: LBB6_5: @ %cmpxchg.end
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: pop {r4, r6, r7, pc}
+;
+; CHECK-THUMB-LE-LABEL: test7:
+; CHECK-THUMB-LE: @ %bb.0: @ %cmpxchg.start
+; CHECK-THUMB-LE-NEXT: .save {r4, r5, r6, lr}
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r6, lr}
+; CHECK-THUMB-LE-NEXT: mov r12, r0
+; CHECK-THUMB-LE-NEXT: ldrexd r0, r1, [r0]
+; CHECK-THUMB-LE-NEXT: eor.w lr, r1, r3
+; CHECK-THUMB-LE-NEXT: eor.w r4, r0, r2
+; CHECK-THUMB-LE-NEXT: orrs.w r4, r4, lr
+; CHECK-THUMB-LE-NEXT: bne .LBB6_4
+; CHECK-THUMB-LE-NEXT: @ %bb.1: @ %cmpxchg.fencedstore
+; CHECK-THUMB-LE-NEXT: ldrd r4, lr, [sp, #16]
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: .LBB6_2: @ %cmpxchg.trystore
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-LE-NEXT: cbz r5, .LBB6_5
+; CHECK-THUMB-LE-NEXT: @ %bb.3: @ %cmpxchg.releasedload
+; CHECK-THUMB-LE-NEXT: @ in Loop: Header=BB6_2 Depth=1
+; CHECK-THUMB-LE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-LE-NEXT: eor.w r5, r0, r2
+; CHECK-THUMB-LE-NEXT: eor.w r6, r1, r3
+; CHECK-THUMB-LE-NEXT: orrs r5, r6
+; CHECK-THUMB-LE-NEXT: beq .LBB6_2
+; CHECK-THUMB-LE-NEXT: .LBB6_4: @ %cmpxchg.nostore
+; CHECK-THUMB-LE-NEXT: clrex
+; CHECK-THUMB-LE-NEXT: .LBB6_5: @ %cmpxchg.end
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r6, pc}
+;
+; CHECK-BE-LABEL: test7:
+; CHECK-BE: @ %bb.0: @ %cmpxchg.start
+; CHECK-BE-NEXT: push {r4, r5, r6, lr}
+; CHECK-BE-NEXT: mov r12, r1
+; CHECK-BE-NEXT: mov lr, r0
+; CHECK-BE-NEXT: ldrexd r0, r1, [r0]
+; CHECK-BE-NEXT: mov r4, r3
+; CHECK-BE-NEXT: eor r3, r0, r12
+; CHECK-BE-NEXT: eor r6, r1, r2
+; CHECK-BE-NEXT: orrs r3, r6, r3
+; CHECK-BE-NEXT: bne .LBB6_4
+; CHECK-BE-NEXT: @ %bb.1: @ %cmpxchg.fencedstore
+; CHECK-BE-NEXT: ldr r5, [sp, #16]
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: .LBB6_2: @ %cmpxchg.trystore
+; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-BE-NEXT: strexd r3, r4, r5, [lr]
+; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: beq .LBB6_5
+; CHECK-BE-NEXT: @ %bb.3: @ %cmpxchg.releasedload
+; CHECK-BE-NEXT: @ in Loop: Header=BB6_2 Depth=1
+; CHECK-BE-NEXT: ldrexd r0, r1, [lr]
+; CHECK-BE-NEXT: eor r3, r0, r12
+; CHECK-BE-NEXT: eor r6, r1, r2
+; CHECK-BE-NEXT: orrs r3, r6, r3
+; CHECK-BE-NEXT: beq .LBB6_2
+; CHECK-BE-NEXT: .LBB6_4: @ %cmpxchg.nostore
+; CHECK-BE-NEXT: clrex
+; CHECK-BE-NEXT: .LBB6_5: @ %cmpxchg.end
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: pop {r4, r5, r6, pc}
+;
+; CHECK-THUMB-BE-LABEL: test7:
+; CHECK-THUMB-BE: @ %bb.0: @ %cmpxchg.start
+; CHECK-THUMB-BE-NEXT: .save {r4, r5, r6, lr}
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r6, lr}
+; CHECK-THUMB-BE-NEXT: mov r12, r0
+; CHECK-THUMB-BE-NEXT: ldrexd r0, r1, [r0]
+; CHECK-THUMB-BE-NEXT: eor.w lr, r0, r2
+; CHECK-THUMB-BE-NEXT: eor.w r4, r1, r3
+; CHECK-THUMB-BE-NEXT: orrs.w r4, r4, lr
+; CHECK-THUMB-BE-NEXT: bne .LBB6_4
+; CHECK-THUMB-BE-NEXT: @ %bb.1: @ %cmpxchg.fencedstore
+; CHECK-THUMB-BE-NEXT: ldrd r4, lr, [sp, #16]
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: .LBB6_2: @ %cmpxchg.trystore
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-BE-NEXT: cbz r5, .LBB6_5
+; CHECK-THUMB-BE-NEXT: @ %bb.3: @ %cmpxchg.releasedload
+; CHECK-THUMB-BE-NEXT: @ in Loop: Header=BB6_2 Depth=1
+; CHECK-THUMB-BE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-BE-NEXT: eor.w r5, r0, r2
+; CHECK-THUMB-BE-NEXT: eor.w r6, r1, r3
+; CHECK-THUMB-BE-NEXT: orrs r5, r6
+; CHECK-THUMB-BE-NEXT: beq .LBB6_2
+; CHECK-THUMB-BE-NEXT: .LBB6_4: @ %cmpxchg.nostore
+; CHECK-THUMB-BE-NEXT: clrex
+; CHECK-THUMB-BE-NEXT: .LBB6_5: @ %cmpxchg.end
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r6, pc}
+
+
%pair = cmpxchg ptr %ptr, i64 %val1, i64 %val2 seq_cst seq_cst
%r = extractvalue { i64, i1 } %pair, 0
@@ -224,20 +540,20 @@ define i64 @test7(ptr %ptr, i64 %val1, i64 %val2) {
; isn't supported.
define i64 @test8(ptr %ptr) {
; CHECK-LABEL: test8:
-; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK-NOT: strexd
-; CHECK: clrex
-; CHECK-NOT: strexd
-; CHECK: dmb {{ish$}}
-
+; CHECK: @ %bb.0:
+; CHECK-NEXT: ldrexd r0, r1, [r0]
+; CHECK-NEXT: clrex
+; CHECK-NEXT: dmb ish
+; CHECK-NEXT: bx lr
+;
; CHECK-THUMB-LABEL: test8:
-; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB-NOT: strexd
-; CHECK-THUMB: clrex
-; CHECK-THUMB-NOT: strexd
-; CHECK-THUMB: dmb {{ish$}}
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: ldrexd r0, r1, [r0]
+; CHECK-THUMB-NEXT: clrex
+; CHECK-THUMB-NEXT: dmb ish
+; CHECK-THUMB-NEXT: bx lr
+
-; CHECK-M: __atomic_load_8
%r = load atomic i64, ptr %ptr seq_cst, align 8
ret i64 %r
@@ -247,185 +563,444 @@ define i64 @test8(ptr %ptr) {
; way to write it. Except on M class devices, where ldrexd/strexd aren't
; supported.
define void @test9(ptr %ptr, i64 %val) {
-; CHECK-LABEL: test9:
-; CHECK: dmb {{ish$}}
-; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
-; CHECK: cmp
-; CHECK: bne
-; CHECK: dmb {{ish$}}
-
+; CHECK-LE-LABEL: test9:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: push {r4, r5, lr}
+; CHECK-LE-NEXT: mov r3, r2
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: mov r2, r1
+; CHECK-LE-NEXT: LBB8_1: @ %atomicrmw.start
+; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-LE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-LE-NEXT: strexd r1, r2, r3, [r0]
+; CHECK-LE-NEXT: cmp r1, #0
+; CHECK-LE-NEXT: bne LBB8_1
+; CHECK-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: pop {r4, r5, pc}
+;
; CHECK-THUMB-LABEL: test9:
-; CHECK-THUMB: dmb {{ish$}}
-; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
-; CHECK-THUMB: cmp
-; CHECK-THUMB: bne
-; CHECK-THUMB: dmb {{ish$}}
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: dmb ish
+; CHECK-THUMB-NEXT: .LBB8_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexd r1, r12, [r0]
+; CHECK-THUMB-NEXT: strexd r1, r2, r3, [r0]
+; CHECK-THUMB-NEXT: cmp r1, #0
+; CHECK-THUMB-NEXT: bne .LBB8_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: dmb ish
+; CHECK-THUMB-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test9:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: push {r4, r5, lr}
+; CHECK-BE-NEXT: mov r3, r2
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: mov r2, r1
+; CHECK-BE-NEXT: .LBB8_1: @ %atomicrmw.start
+; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-BE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-BE-NEXT: strexd r1, r2, r3, [r0]
+; CHECK-BE-NEXT: cmp r1, #0
+; CHECK-BE-NEXT: bne .LBB8_1
+; CHECK-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: pop {r4, r5, pc}
+
-; CHECK-M: __atomic_store_8
store atomic i64 %val, ptr %ptr seq_cst, align 8
ret void
}
define i64 @test10(ptr %ptr, i64 %val) {
-; CHECK-LABEL: test10:
-; CHECK: dmb {{ish$}}
-; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
-; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]
-; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
-; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
-; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
-; CHECK: movge [[OUT_HI]], [[REG2]]
-; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
-; CHECK: movge [[OUT_LO]], [[REG1]]
-; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
-; CHECK: cmp
-; CHECK: bne
-; CHECK: dmb {{ish$}}
-
-; CHECK-THUMB-LABEL: test10:
-; CHECK-THUMB: dmb {{ish$}}
-; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
-; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]
-; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
-; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
-; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
-; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
-; CHECK-THUMB: itt ge
-; CHECK-THUMB: movge [[OUT_HI]], [[REG2]]
-; CHECK-THUMB: movge [[OUT_LO]], [[REG1]]
-; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
-; CHECK-THUMB: cmp
-; CHECK-THUMB: bne
-; CHECK-THUMB: dmb {{ish$}}
-
-; CHECK-M: __atomic_compare_exchange_8
+; CHECK-LE-LABEL: test10:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: LBB9_1: @ %atomicrmw.start
+; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-LE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-LE-NEXT: mov r7, r2
+; CHECK-LE-NEXT: subs r3, r4, r1
+; CHECK-LE-NEXT: sbcs r3, r5, r2
+; CHECK-LE-NEXT: movlt r7, r5
+; CHECK-LE-NEXT: mov r6, r1
+; CHECK-LE-NEXT: movlt r6, r4
+; CHECK-LE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: bne LBB9_1
+; CHECK-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-LE-NEXT: mov r0, r4
+; CHECK-LE-NEXT: mov r1, r5
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: pop {r4, r5, r6, r7, pc}
+;
+; CHECK-THUMB-LE-LABEL: test10:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: mov r12, r0
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: .LBB9_1: @ %atomicrmw.start
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-LE-NEXT: mov r4, r2
+; CHECK-THUMB-LE-NEXT: subs.w lr, r0, r2
+; CHECK-THUMB-LE-NEXT: sbcs.w lr, r1, r3
+; CHECK-THUMB-LE-NEXT: mov lr, r3
+; CHECK-THUMB-LE-NEXT: itt lt
+; CHECK-THUMB-LE-NEXT: movlt lr, r1
+; CHECK-THUMB-LE-NEXT: movlt r4, r0
+; CHECK-THUMB-LE-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-LE-NEXT: cmp r5, #0
+; CHECK-THUMB-LE-NEXT: bne .LBB9_1
+; CHECK-THUMB-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-BE-LABEL: test10:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: .LBB9_1: @ %atomicrmw.start
+; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-BE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-BE-NEXT: mov r7, r2
+; CHECK-BE-NEXT: subs r3, r5, r2
+; CHECK-BE-NEXT: sbcs r3, r4, r1
+; CHECK-BE-NEXT: movlt r7, r5
+; CHECK-BE-NEXT: mov r6, r1
+; CHECK-BE-NEXT: movlt r6, r4
+; CHECK-BE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: bne .LBB9_1
+; CHECK-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-BE-NEXT: mov r0, r4
+; CHECK-BE-NEXT: mov r1, r5
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: pop {r4, r5, r6, r7, pc}
+;
+; CHECK-THUMB-BE-LABEL: test10:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: mov r12, r0
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: .LBB9_1: @ %atomicrmw.start
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-BE-NEXT: mov r4, r2
+; CHECK-THUMB-BE-NEXT: subs.w lr, r1, r3
+; CHECK-THUMB-BE-NEXT: sbcs.w lr, r0, r2
+; CHECK-THUMB-BE-NEXT: mov lr, r3
+; CHECK-THUMB-BE-NEXT: itt lt
+; CHECK-THUMB-BE-NEXT: movlt lr, r1
+; CHECK-THUMB-BE-NEXT: movlt r4, r0
+; CHECK-THUMB-BE-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-BE-NEXT: cmp r5, #0
+; CHECK-THUMB-BE-NEXT: bne .LBB9_1
+; CHECK-THUMB-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r7, pc}
+
+
%r = atomicrmw min ptr %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test11(ptr %ptr, i64 %val) {
-; CHECK-LABEL: test11:
-; CHECK: dmb {{ish$}}
-; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
-; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]
-; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
-; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
-; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
-; CHECK: movhs [[OUT_HI]], [[REG2]]
-; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
-; CHECK: movhs [[OUT_LO]], [[REG1]]
-; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
-; CHECK: cmp
-; CHECK: bne
-; CHECK: dmb {{ish$}}
-
-; CHECK-THUMB-LABEL: test11:
-; CHECK-THUMB: dmb {{ish$}}
-; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
-; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]
-; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
-; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
-; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
-; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
-; CHECK-THUMB: itt hs
-; CHECK-THUMB: movhs [[OUT_HI]], [[REG2]]
-; CHECK-THUMB: movhs [[OUT_LO]], [[REG1]]
-; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
-; CHECK-THUMB: cmp
-; CHECK-THUMB: bne
-; CHECK-THUMB: dmb {{ish$}}
-
-; CHECK-M: __atomic_compare_exchange_8
+; CHECK-LE-LABEL: test11:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: LBB10_1: @ %atomicrmw.start
+; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-LE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-LE-NEXT: mov r7, r2
+; CHECK-LE-NEXT: subs r3, r4, r1
+; CHECK-LE-NEXT: sbcs r3, r5, r2
+; CHECK-LE-NEXT: movlo r7, r5
+; CHECK-LE-NEXT: mov r6, r1
+; CHECK-LE-NEXT: movlo r6, r4
+; CHECK-LE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: bne LBB10_1
+; CHECK-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-LE-NEXT: mov r0, r4
+; CHECK-LE-NEXT: mov r1, r5
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: pop {r4, r5, r6, r7, pc}
+;
+; CHECK-THUMB-LE-LABEL: test11:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: mov r12, r0
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: .LBB10_1: @ %atomicrmw.start
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-LE-NEXT: mov r4, r2
+; CHECK-THUMB-LE-NEXT: subs.w lr, r0, r2
+; CHECK-THUMB-LE-NEXT: sbcs.w lr, r1, r3
+; CHECK-THUMB-LE-NEXT: mov lr, r3
+; CHECK-THUMB-LE-NEXT: itt lo
+; CHECK-THUMB-LE-NEXT: movlo lr, r1
+; CHECK-THUMB-LE-NEXT: movlo r4, r0
+; CHECK-THUMB-LE-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-LE-NEXT: cmp r5, #0
+; CHECK-THUMB-LE-NEXT: bne .LBB10_1
+; CHECK-THUMB-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-BE-LABEL: test11:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: .LBB10_1: @ %atomicrmw.start
+; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-BE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-BE-NEXT: mov r7, r2
+; CHECK-BE-NEXT: subs r3, r5, r2
+; CHECK-BE-NEXT: sbcs r3, r4, r1
+; CHECK-BE-NEXT: movlo r7, r5
+; CHECK-BE-NEXT: mov r6, r1
+; CHECK-BE-NEXT: movlo r6, r4
+; CHECK-BE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: bne .LBB10_1
+; CHECK-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-BE-NEXT: mov r0, r4
+; CHECK-BE-NEXT: mov r1, r5
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: pop {r4, r5, r6, r7, pc}
+;
+; CHECK-THUMB-BE-LABEL: test11:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: mov r12, r0
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: .LBB10_1: @ %atomicrmw.start
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-BE-NEXT: mov r4, r2
+; CHECK-THUMB-BE-NEXT: subs.w lr, r1, r3
+; CHECK-THUMB-BE-NEXT: sbcs.w lr, r0, r2
+; CHECK-THUMB-BE-NEXT: mov lr, r3
+; CHECK-THUMB-BE-NEXT: itt lo
+; CHECK-THUMB-BE-NEXT: movlo lr, r1
+; CHECK-THUMB-BE-NEXT: movlo r4, r0
+; CHECK-THUMB-BE-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-BE-NEXT: cmp r5, #0
+; CHECK-THUMB-BE-NEXT: bne .LBB10_1
+; CHECK-THUMB-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r7, pc}
+
+
%r = atomicrmw umin ptr %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test12(ptr %ptr, i64 %val) {
-; CHECK-LABEL: test12:
-; CHECK: dmb {{ish$}}
-; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
-; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]
-; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
-; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
-; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
-; CHECK: movlt [[OUT_HI]], [[REG2]]
-; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
-; CHECK: movlt [[OUT_LO]], [[REG1]]
-; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
-; CHECK: cmp
-; CHECK: bne
-; CHECK: dmb {{ish$}}
-
-; CHECK-THUMB-LABEL: test12:
-; CHECK-THUMB: dmb {{ish$}}
-; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
-; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]
-; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
-; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
-; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
-; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
-; CHECK-THUMB: itt lt
-; CHECK-THUMB: movlt [[OUT_HI]], [[REG2]]
-; CHECK-THUMB: movlt [[OUT_LO]], [[REG1]]
-; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
-; CHECK-THUMB: cmp
-; CHECK-THUMB: bne
-; CHECK-THUMB: dmb {{ish$}}
-
-; CHECK-M: __atomic_compare_exchange_8
+; CHECK-LE-LABEL: test12:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: LBB11_1: @ %atomicrmw.start
+; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-LE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-LE-NEXT: mov r7, r2
+; CHECK-LE-NEXT: subs r3, r1, r4
+; CHECK-LE-NEXT: sbcs r3, r2, r5
+; CHECK-LE-NEXT: movlt r7, r5
+; CHECK-LE-NEXT: mov r6, r1
+; CHECK-LE-NEXT: movlt r6, r4
+; CHECK-LE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: bne LBB11_1
+; CHECK-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-LE-NEXT: mov r0, r4
+; CHECK-LE-NEXT: mov r1, r5
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: pop {r4, r5, r6, r7, pc}
+;
+; CHECK-THUMB-LE-LABEL: test12:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: mov r12, r0
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: .LBB11_1: @ %atomicrmw.start
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-LE-NEXT: mov r4, r2
+; CHECK-THUMB-LE-NEXT: subs.w lr, r2, r0
+; CHECK-THUMB-LE-NEXT: sbcs.w lr, r3, r1
+; CHECK-THUMB-LE-NEXT: mov lr, r3
+; CHECK-THUMB-LE-NEXT: itt lt
+; CHECK-THUMB-LE-NEXT: movlt lr, r1
+; CHECK-THUMB-LE-NEXT: movlt r4, r0
+; CHECK-THUMB-LE-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-LE-NEXT: cmp r5, #0
+; CHECK-THUMB-LE-NEXT: bne .LBB11_1
+; CHECK-THUMB-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-BE-LABEL: test12:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: .LBB11_1: @ %atomicrmw.start
+; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-BE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-BE-NEXT: mov r7, r2
+; CHECK-BE-NEXT: subs r3, r2, r5
+; CHECK-BE-NEXT: sbcs r3, r1, r4
+; CHECK-BE-NEXT: movlt r7, r5
+; CHECK-BE-NEXT: mov r6, r1
+; CHECK-BE-NEXT: movlt r6, r4
+; CHECK-BE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: bne .LBB11_1
+; CHECK-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-BE-NEXT: mov r0, r4
+; CHECK-BE-NEXT: mov r1, r5
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: pop {r4, r5, r6, r7, pc}
+;
+; CHECK-THUMB-BE-LABEL: test12:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: mov r12, r0
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: .LBB11_1: @ %atomicrmw.start
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-BE-NEXT: mov r4, r2
+; CHECK-THUMB-BE-NEXT: subs.w lr, r3, r1
+; CHECK-THUMB-BE-NEXT: sbcs.w lr, r2, r0
+; CHECK-THUMB-BE-NEXT: mov lr, r3
+; CHECK-THUMB-BE-NEXT: itt lt
+; CHECK-THUMB-BE-NEXT: movlt lr, r1
+; CHECK-THUMB-BE-NEXT: movlt r4, r0
+; CHECK-THUMB-BE-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-BE-NEXT: cmp r5, #0
+; CHECK-THUMB-BE-NEXT: bne .LBB11_1
+; CHECK-THUMB-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r7, pc}
+
+
%r = atomicrmw max ptr %ptr, i64 %val seq_cst
ret i64 %r
}
define i64 @test13(ptr %ptr, i64 %val) {
-; CHECK-LABEL: test13:
-; CHECK: dmb {{ish$}}
-; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
-; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
-; CHECK-LE: subs {{[^,]+}}, r1, [[REG1]]
-; CHECK-BE: subs {{[^,]+}}, r2, [[REG2]]
-; CHECK-LE: sbcs {{[^,]+}}, r2, [[REG2]]
-; CHECK-BE: sbcs {{[^,]+}}, r1, [[REG1]]
-; CHECK: movlo [[OUT_HI]], [[REG2]]
-; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
-; CHECK: movlo [[OUT_LO]], [[REG1]]
-; CHECK: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
-; CHECK: cmp
-; CHECK: bne
-; CHECK: dmb {{ish$}}
-
-; CHECK-THUMB-LABEL: test13:
-; CHECK-THUMB: dmb {{ish$}}
-; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
-; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
-; CHECK-THUMB-LE: subs.w {{[^,]+}}, r2, [[REG1]]
-; CHECK-THUMB-BE: subs.w {{[^,]+}}, r3, [[REG2]]
-; CHECK-THUMB-LE: sbcs.w {{[^,]+}}, r3, [[REG2]]
-; CHECK-THUMB-BE: sbcs.w {{[^,]+}}, r2, [[REG1]]
-; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
-; CHECK-THUMB: itt lo
-; CHECK-THUMB: movlo [[OUT_HI]], [[REG2]]
-; CHECK-THUMB: movlo [[OUT_LO]], [[REG1]]
-; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[OUT_LO]], [[OUT_HI]]
-; CHECK-THUMB: cmp
-; CHECK-THUMB: bne
-; CHECK-THUMB: dmb {{ish$}}
-
-; CHECK-M: __atomic_compare_exchange_8
+; CHECK-LE-LABEL: test13:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: LBB12_1: @ %atomicrmw.start
+; CHECK-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-LE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-LE-NEXT: mov r7, r2
+; CHECK-LE-NEXT: subs r3, r1, r4
+; CHECK-LE-NEXT: sbcs r3, r2, r5
+; CHECK-LE-NEXT: movlo r7, r5
+; CHECK-LE-NEXT: mov r6, r1
+; CHECK-LE-NEXT: movlo r6, r4
+; CHECK-LE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-LE-NEXT: cmp r3, #0
+; CHECK-LE-NEXT: bne LBB12_1
+; CHECK-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-LE-NEXT: mov r0, r4
+; CHECK-LE-NEXT: mov r1, r5
+; CHECK-LE-NEXT: dmb ish
+; CHECK-LE-NEXT: pop {r4, r5, r6, r7, pc}
+;
+; CHECK-THUMB-LE-LABEL: test13:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: mov r12, r0
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: .LBB12_1: @ %atomicrmw.start
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-LE-NEXT: mov r4, r2
+; CHECK-THUMB-LE-NEXT: subs.w lr, r2, r0
+; CHECK-THUMB-LE-NEXT: sbcs.w lr, r3, r1
+; CHECK-THUMB-LE-NEXT: mov lr, r3
+; CHECK-THUMB-LE-NEXT: itt lo
+; CHECK-THUMB-LE-NEXT: movlo lr, r1
+; CHECK-THUMB-LE-NEXT: movlo r4, r0
+; CHECK-THUMB-LE-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-LE-NEXT: cmp r5, #0
+; CHECK-THUMB-LE-NEXT: bne .LBB12_1
+; CHECK-THUMB-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-LE-NEXT: dmb ish
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-BE-LABEL: test13:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: .LBB12_1: @ %atomicrmw.start
+; CHECK-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-BE-NEXT: ldrexd r4, r5, [r0]
+; CHECK-BE-NEXT: mov r7, r2
+; CHECK-BE-NEXT: subs r3, r2, r5
+; CHECK-BE-NEXT: sbcs r3, r1, r4
+; CHECK-BE-NEXT: movlo r7, r5
+; CHECK-BE-NEXT: mov r6, r1
+; CHECK-BE-NEXT: movlo r6, r4
+; CHECK-BE-NEXT: strexd r3, r6, r7, [r0]
+; CHECK-BE-NEXT: cmp r3, #0
+; CHECK-BE-NEXT: bne .LBB12_1
+; CHECK-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-BE-NEXT: mov r0, r4
+; CHECK-BE-NEXT: mov r1, r5
+; CHECK-BE-NEXT: dmb ish
+; CHECK-BE-NEXT: pop {r4, r5, r6, r7, pc}
+;
+; CHECK-THUMB-BE-LABEL: test13:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: .save {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: mov r12, r0
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: .LBB12_1: @ %atomicrmw.start
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: ldrexd r0, r1, [r12]
+; CHECK-THUMB-BE-NEXT: mov r4, r2
+; CHECK-THUMB-BE-NEXT: subs.w lr, r3, r1
+; CHECK-THUMB-BE-NEXT: sbcs.w lr, r2, r0
+; CHECK-THUMB-BE-NEXT: mov lr, r3
+; CHECK-THUMB-BE-NEXT: itt lo
+; CHECK-THUMB-BE-NEXT: movlo lr, r1
+; CHECK-THUMB-BE-NEXT: movlo r4, r0
+; CHECK-THUMB-BE-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-BE-NEXT: cmp r5, #0
+; CHECK-THUMB-BE-NEXT: bne .LBB12_1
+; CHECK-THUMB-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-BE-NEXT: dmb ish
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r7, pc}
+
+
%r = atomicrmw umax ptr %ptr, i64 %val seq_cst
ret i64 %r
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-M: {{.*}}
diff --git a/llvm/test/CodeGen/ARM/atomic-ops-v8.ll b/llvm/test/CodeGen/ARM/atomic-ops-v8.ll
index d48b070aa862e..0ffca7782030f 100644
--- a/llvm/test/CodeGen/ARM/atomic-ops-v8.ll
+++ b/llvm/test/CodeGen/ARM/atomic-ops-v8.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=armv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE --check-prefix=CHECK-ARM --check-prefix=CHECK-ARM-LE
; RUN: llc -mtriple=armebv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE --check-prefix=CHECK-ARM --check-prefix=CHECK-ARM-BE
; RUN: llc -mtriple=thumbv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE --check-prefix=CHECK-THUMB --check-prefix=CHECK-THUMB-LE
@@ -9,1387 +10,2379 @@
@var64 = global i64 0
define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_add_i8:
+; CHECK-ARM-LABEL: test_atomic_load_add_i8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var8
+; CHECK-ARM-NEXT: movt r12, :upper16:var8
+; CHECK-ARM-NEXT: .LBB0_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaexb r1, [r12]
+; CHECK-ARM-NEXT: add r3, r1, r0
+; CHECK-ARM-NEXT: stlexb r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB0_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_add_i8:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var8
+; CHECK-THUMB-NEXT: movt r12, :upper16:var8
+; CHECK-THUMB-NEXT: .LBB0_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaexb r1, [r12]
+; CHECK-THUMB-NEXT: adds r3, r1, r0
+; CHECK-THUMB-NEXT: stlexb r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB0_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw add ptr @var8, i8 %offset seq_cst
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
-; CHECK: movt r[[ADDR]], :upper16:var8
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i8 %old
}
define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_add_i16:
+; CHECK-ARM-LABEL: test_atomic_load_add_i16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var16
+; CHECK-ARM-NEXT: movt r12, :upper16:var16
+; CHECK-ARM-NEXT: .LBB1_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaexh r1, [r12]
+; CHECK-ARM-NEXT: add r3, r1, r0
+; CHECK-ARM-NEXT: strexh r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB1_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_add_i16:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var16
+; CHECK-THUMB-NEXT: movt r12, :upper16:var16
+; CHECK-THUMB-NEXT: .LBB1_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaexh r1, [r12]
+; CHECK-THUMB-NEXT: adds r3, r1, r0
+; CHECK-THUMB-NEXT: strexh r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB1_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw add ptr @var16, i16 %offset acquire
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
-; CHECK: movt r[[ADDR]], :upper16:var16
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i16 %old
}
define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_add_i32:
+; CHECK-ARM-LABEL: test_atomic_load_add_i32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var32
+; CHECK-ARM-NEXT: movt r12, :upper16:var32
+; CHECK-ARM-NEXT: .LBB2_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrex r1, [r12]
+; CHECK-ARM-NEXT: add r3, r1, r0
+; CHECK-ARM-NEXT: stlex r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB2_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_add_i32:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var32
+; CHECK-THUMB-NEXT: movt r12, :upper16:var32
+; CHECK-THUMB-NEXT: .LBB2_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrex r1, [r12]
+; CHECK-THUMB-NEXT: adds r3, r1, r0
+; CHECK-THUMB-NEXT: stlex r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB2_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw add ptr @var32, i32 %offset release
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
-; CHECK: movt r[[ADDR]], :upper16:var32
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i32 %old
}
define void @test_atomic_load_add_i64(i64 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_add_i64:
+; CHECK-ARM-LE-LABEL: test_atomic_load_add_i64:
+; CHECK-ARM-LE: @ %bb.0:
+; CHECK-ARM-LE-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-LE-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-LE-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-LE-NEXT: .LBB3_1: @ %atomicrmw.start
+; CHECK-ARM-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-LE-NEXT: ldrexd r4, r5, [r2]
+; CHECK-ARM-LE-NEXT: adds r6, r4, r0
+; CHECK-ARM-LE-NEXT: adc r7, r5, r1
+; CHECK-ARM-LE-NEXT: strexd r3, r6, r7, [r2]
+; CHECK-ARM-LE-NEXT: cmp r3, #0
+; CHECK-ARM-LE-NEXT: bne .LBB3_1
+; CHECK-ARM-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-LE-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-LE-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-ARM-BE-LABEL: test_atomic_load_add_i64:
+; CHECK-ARM-BE: @ %bb.0:
+; CHECK-ARM-BE-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-BE-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-BE-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-BE-NEXT: .LBB3_1: @ %atomicrmw.start
+; CHECK-ARM-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-BE-NEXT: ldrexd r4, r5, [r2]
+; CHECK-ARM-BE-NEXT: adds r7, r5, r1
+; CHECK-ARM-BE-NEXT: adc r6, r4, r0
+; CHECK-ARM-BE-NEXT: strexd r3, r6, r7, [r2]
+; CHECK-ARM-BE-NEXT: cmp r3, #0
+; CHECK-ARM-BE-NEXT: bne .LBB3_1
+; CHECK-ARM-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-BE-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-BE-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-THUMB-LE-LABEL: test_atomic_load_add_i64:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-LE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-LE-NEXT: .LBB3_1: @ %atomicrmw.start
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: ldrexd r3, r2, [r12]
+; CHECK-THUMB-LE-NEXT: adds.w lr, r3, r0
+; CHECK-THUMB-LE-NEXT: adc.w r4, r2, r1
+; CHECK-THUMB-LE-NEXT: strexd r5, lr, r4, [r12]
+; CHECK-THUMB-LE-NEXT: cmp r5, #0
+; CHECK-THUMB-LE-NEXT: bne .LBB3_1
+; CHECK-THUMB-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-LE-NEXT: strd r3, r2, [r12]
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-THUMB-BE-LABEL: test_atomic_load_add_i64:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-BE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-BE-NEXT: .LBB3_1: @ %atomicrmw.start
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: ldrexd r3, r2, [r12]
+; CHECK-THUMB-BE-NEXT: adds.w lr, r2, r1
+; CHECK-THUMB-BE-NEXT: adc.w r4, r3, r0
+; CHECK-THUMB-BE-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-BE-NEXT: cmp r5, #0
+; CHECK-THUMB-BE-NEXT: bne .LBB3_1
+; CHECK-THUMB-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-BE-NEXT: strd r3, r2, [r12]
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r7, pc}
%old = atomicrmw add ptr @var64, i64 %offset monotonic
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
-; CHECK: movt r[[ADDR]], :upper16:var64
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-LE-NEXT: adds{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
-; CHECK-LE-NEXT: adc{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1
-; CHECK-BE-NEXT: adds{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
-; CHECK-BE-NEXT: adc{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0
-; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]]
+
store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_sub_i8:
+; CHECK-ARM-LABEL: test_atomic_load_sub_i8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var8
+; CHECK-ARM-NEXT: movt r12, :upper16:var8
+; CHECK-ARM-NEXT: .LBB4_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrexb r1, [r12]
+; CHECK-ARM-NEXT: sub r3, r1, r0
+; CHECK-ARM-NEXT: strexb r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB4_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_sub_i8:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var8
+; CHECK-THUMB-NEXT: movt r12, :upper16:var8
+; CHECK-THUMB-NEXT: .LBB4_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexb r1, [r12]
+; CHECK-THUMB-NEXT: subs r3, r1, r0
+; CHECK-THUMB-NEXT: strexb r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB4_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw sub ptr @var8, i8 %offset monotonic
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
-; CHECK: movt r[[ADDR]], :upper16:var8
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: sub{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i8 %old
}
define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_sub_i16:
+; CHECK-ARM-LABEL: test_atomic_load_sub_i16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var16
+; CHECK-ARM-NEXT: movt r12, :upper16:var16
+; CHECK-ARM-NEXT: .LBB5_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrexh r1, [r12]
+; CHECK-ARM-NEXT: sub r3, r1, r0
+; CHECK-ARM-NEXT: stlexh r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB5_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_sub_i16:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var16
+; CHECK-THUMB-NEXT: movt r12, :upper16:var16
+; CHECK-THUMB-NEXT: .LBB5_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexh r1, [r12]
+; CHECK-THUMB-NEXT: subs r3, r1, r0
+; CHECK-THUMB-NEXT: stlexh r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB5_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw sub ptr @var16, i16 %offset release
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
-; CHECK: movt r[[ADDR]], :upper16:var16
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: sub{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i16 %old
}
define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_sub_i32:
+; CHECK-ARM-LABEL: test_atomic_load_sub_i32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var32
+; CHECK-ARM-NEXT: movt r12, :upper16:var32
+; CHECK-ARM-NEXT: .LBB6_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaex r1, [r12]
+; CHECK-ARM-NEXT: sub r3, r1, r0
+; CHECK-ARM-NEXT: strex r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB6_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_sub_i32:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var32
+; CHECK-THUMB-NEXT: movt r12, :upper16:var32
+; CHECK-THUMB-NEXT: .LBB6_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaex r1, [r12]
+; CHECK-THUMB-NEXT: subs r3, r1, r0
+; CHECK-THUMB-NEXT: strex r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB6_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw sub ptr @var32, i32 %offset acquire
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
-; CHECK: movt r[[ADDR]], :upper16:var32
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: sub{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: strex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i32 %old
}
define void @test_atomic_load_sub_i64(i64 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_sub_i64:
+; CHECK-ARM-LE-LABEL: test_atomic_load_sub_i64:
+; CHECK-ARM-LE: @ %bb.0:
+; CHECK-ARM-LE-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-LE-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-LE-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-LE-NEXT: .LBB7_1: @ %atomicrmw.start
+; CHECK-ARM-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-LE-NEXT: ldaexd r4, r5, [r2]
+; CHECK-ARM-LE-NEXT: subs r6, r4, r0
+; CHECK-ARM-LE-NEXT: sbc r7, r5, r1
+; CHECK-ARM-LE-NEXT: stlexd r3, r6, r7, [r2]
+; CHECK-ARM-LE-NEXT: cmp r3, #0
+; CHECK-ARM-LE-NEXT: bne .LBB7_1
+; CHECK-ARM-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-LE-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-LE-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-ARM-BE-LABEL: test_atomic_load_sub_i64:
+; CHECK-ARM-BE: @ %bb.0:
+; CHECK-ARM-BE-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-BE-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-BE-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-BE-NEXT: .LBB7_1: @ %atomicrmw.start
+; CHECK-ARM-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-BE-NEXT: ldaexd r4, r5, [r2]
+; CHECK-ARM-BE-NEXT: subs r7, r5, r1
+; CHECK-ARM-BE-NEXT: sbc r6, r4, r0
+; CHECK-ARM-BE-NEXT: stlexd r3, r6, r7, [r2]
+; CHECK-ARM-BE-NEXT: cmp r3, #0
+; CHECK-ARM-BE-NEXT: bne .LBB7_1
+; CHECK-ARM-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-BE-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-BE-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-THUMB-LE-LABEL: test_atomic_load_sub_i64:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-LE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-LE-NEXT: .LBB7_1: @ %atomicrmw.start
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: ldaexd r3, r2, [r12]
+; CHECK-THUMB-LE-NEXT: subs.w lr, r3, r0
+; CHECK-THUMB-LE-NEXT: sbc.w r4, r2, r1
+; CHECK-THUMB-LE-NEXT: stlexd r5, lr, r4, [r12]
+; CHECK-THUMB-LE-NEXT: cmp r5, #0
+; CHECK-THUMB-LE-NEXT: bne .LBB7_1
+; CHECK-THUMB-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-LE-NEXT: strd r3, r2, [r12]
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-THUMB-BE-LABEL: test_atomic_load_sub_i64:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-BE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-BE-NEXT: .LBB7_1: @ %atomicrmw.start
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: ldaexd r3, r2, [r12]
+; CHECK-THUMB-BE-NEXT: subs.w lr, r2, r1
+; CHECK-THUMB-BE-NEXT: sbc.w r4, r3, r0
+; CHECK-THUMB-BE-NEXT: stlexd r5, r4, lr, [r12]
+; CHECK-THUMB-BE-NEXT: cmp r5, #0
+; CHECK-THUMB-BE-NEXT: bne .LBB7_1
+; CHECK-THUMB-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-BE-NEXT: strd r3, r2, [r12]
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r7, pc}
%old = atomicrmw sub ptr @var64, i64 %offset seq_cst
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
-; CHECK: movt r[[ADDR]], :upper16:var64
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-LE-NEXT: subs{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
-; CHECK-LE-NEXT: sbc{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1
-; CHECK-BE-NEXT: subs{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
-; CHECK-BE-NEXT: sbc{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0
-; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]]
+
store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_and_i8:
+; CHECK-ARM-LABEL: test_atomic_load_and_i8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var8
+; CHECK-ARM-NEXT: movt r12, :upper16:var8
+; CHECK-ARM-NEXT: .LBB8_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrexb r1, [r12]
+; CHECK-ARM-NEXT: and r3, r1, r0
+; CHECK-ARM-NEXT: stlexb r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB8_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_and_i8:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var8
+; CHECK-THUMB-NEXT: movt r12, :upper16:var8
+; CHECK-THUMB-NEXT: .LBB8_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexb r1, [r12]
+; CHECK-THUMB-NEXT: and.w r3, r1, r0
+; CHECK-THUMB-NEXT: stlexb r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB8_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw and ptr @var8, i8 %offset release
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
-; CHECK: movt r[[ADDR]], :upper16:var8
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: and{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i8 %old
}
define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_and_i16:
+; CHECK-ARM-LABEL: test_atomic_load_and_i16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var16
+; CHECK-ARM-NEXT: movt r12, :upper16:var16
+; CHECK-ARM-NEXT: .LBB9_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrexh r1, [r12]
+; CHECK-ARM-NEXT: and r3, r1, r0
+; CHECK-ARM-NEXT: strexh r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB9_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_and_i16:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var16
+; CHECK-THUMB-NEXT: movt r12, :upper16:var16
+; CHECK-THUMB-NEXT: .LBB9_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexh r1, [r12]
+; CHECK-THUMB-NEXT: and.w r3, r1, r0
+; CHECK-THUMB-NEXT: strexh r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB9_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw and ptr @var16, i16 %offset monotonic
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
-; CHECK: movt r[[ADDR]], :upper16:var16
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: and{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i16 %old
}
define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_and_i32:
+; CHECK-ARM-LABEL: test_atomic_load_and_i32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var32
+; CHECK-ARM-NEXT: movt r12, :upper16:var32
+; CHECK-ARM-NEXT: .LBB10_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaex r1, [r12]
+; CHECK-ARM-NEXT: and r3, r1, r0
+; CHECK-ARM-NEXT: stlex r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB10_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_and_i32:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var32
+; CHECK-THUMB-NEXT: movt r12, :upper16:var32
+; CHECK-THUMB-NEXT: .LBB10_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaex r1, [r12]
+; CHECK-THUMB-NEXT: and.w r3, r1, r0
+; CHECK-THUMB-NEXT: stlex r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB10_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw and ptr @var32, i32 %offset seq_cst
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
-; CHECK: movt r[[ADDR]], :upper16:var32
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: and{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i32 %old
}
define void @test_atomic_load_and_i64(i64 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_and_i64:
+; CHECK-ARM-LABEL: test_atomic_load_and_i64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-NEXT: .LBB11_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaexd r4, r5, [r2]
+; CHECK-ARM-NEXT: and r7, r5, r1
+; CHECK-ARM-NEXT: and r6, r4, r0
+; CHECK-ARM-NEXT: strexd r3, r6, r7, [r2]
+; CHECK-ARM-NEXT: cmp r3, #0
+; CHECK-ARM-NEXT: bne .LBB11_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-THUMB-LABEL: test_atomic_load_and_i64:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-NEXT: .LBB11_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaexd r3, r2, [r12]
+; CHECK-THUMB-NEXT: and.w lr, r2, r1
+; CHECK-THUMB-NEXT: and.w r4, r3, r0
+; CHECK-THUMB-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-NEXT: cmp r5, #0
+; CHECK-THUMB-NEXT: bne .LBB11_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: strd r3, r2, [r12]
+; CHECK-THUMB-NEXT: pop {r4, r5, r7, pc}
%old = atomicrmw and ptr @var64, i64 %offset acquire
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
-; CHECK: movt r[[ADDR]], :upper16:var64
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-LE-DAG: and{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
-; CHECK-LE-DAG: and{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
-; CHECK-BE-DAG: and{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
-; CHECK-BE-DAG: and{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
-; CHECK: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]]
+
store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_or_i8:
+; CHECK-ARM-LABEL: test_atomic_load_or_i8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var8
+; CHECK-ARM-NEXT: movt r12, :upper16:var8
+; CHECK-ARM-NEXT: .LBB12_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaexb r1, [r12]
+; CHECK-ARM-NEXT: orr r3, r1, r0
+; CHECK-ARM-NEXT: stlexb r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB12_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_or_i8:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var8
+; CHECK-THUMB-NEXT: movt r12, :upper16:var8
+; CHECK-THUMB-NEXT: .LBB12_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaexb r1, [r12]
+; CHECK-THUMB-NEXT: orr.w r3, r1, r0
+; CHECK-THUMB-NEXT: stlexb r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB12_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw or ptr @var8, i8 %offset seq_cst
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
-; CHECK: movt r[[ADDR]], :upper16:var8
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: orr{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i8 %old
}
define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_or_i16:
+; CHECK-ARM-LABEL: test_atomic_load_or_i16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var16
+; CHECK-ARM-NEXT: movt r12, :upper16:var16
+; CHECK-ARM-NEXT: .LBB13_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrexh r1, [r12]
+; CHECK-ARM-NEXT: orr r3, r1, r0
+; CHECK-ARM-NEXT: strexh r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB13_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_or_i16:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var16
+; CHECK-THUMB-NEXT: movt r12, :upper16:var16
+; CHECK-THUMB-NEXT: .LBB13_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexh r1, [r12]
+; CHECK-THUMB-NEXT: orr.w r3, r1, r0
+; CHECK-THUMB-NEXT: strexh r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB13_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw or ptr @var16, i16 %offset monotonic
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
-; CHECK: movt r[[ADDR]], :upper16:var16
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: orr{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i16 %old
}
define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_or_i32:
+; CHECK-ARM-LABEL: test_atomic_load_or_i32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var32
+; CHECK-ARM-NEXT: movt r12, :upper16:var32
+; CHECK-ARM-NEXT: .LBB14_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaex r1, [r12]
+; CHECK-ARM-NEXT: orr r3, r1, r0
+; CHECK-ARM-NEXT: strex r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB14_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_or_i32:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var32
+; CHECK-THUMB-NEXT: movt r12, :upper16:var32
+; CHECK-THUMB-NEXT: .LBB14_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaex r1, [r12]
+; CHECK-THUMB-NEXT: orr.w r3, r1, r0
+; CHECK-THUMB-NEXT: strex r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB14_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw or ptr @var32, i32 %offset acquire
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
-; CHECK: movt r[[ADDR]], :upper16:var32
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: orr{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: strex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i32 %old
}
define void @test_atomic_load_or_i64(i64 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_or_i64:
+; CHECK-ARM-LABEL: test_atomic_load_or_i64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-NEXT: .LBB15_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrexd r4, r5, [r2]
+; CHECK-ARM-NEXT: orr r7, r5, r1
+; CHECK-ARM-NEXT: orr r6, r4, r0
+; CHECK-ARM-NEXT: stlexd r3, r6, r7, [r2]
+; CHECK-ARM-NEXT: cmp r3, #0
+; CHECK-ARM-NEXT: bne .LBB15_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-THUMB-LABEL: test_atomic_load_or_i64:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-NEXT: .LBB15_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexd r3, r2, [r12]
+; CHECK-THUMB-NEXT: orr.w lr, r2, r1
+; CHECK-THUMB-NEXT: orr.w r4, r3, r0
+; CHECK-THUMB-NEXT: stlexd r5, r4, lr, [r12]
+; CHECK-THUMB-NEXT: cmp r5, #0
+; CHECK-THUMB-NEXT: bne .LBB15_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: strd r3, r2, [r12]
+; CHECK-THUMB-NEXT: pop {r4, r5, r7, pc}
%old = atomicrmw or ptr @var64, i64 %offset release
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
-; CHECK: movt r[[ADDR]], :upper16:var64
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-LE-DAG: orr{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
-; CHECK-LE-DAG: orr{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
-; CHECK-BE-DAG: orr{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
-; CHECK-BE-DAG: orr{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
-; CHECK: stlexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]]
+
store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_xor_i8:
+; CHECK-ARM-LABEL: test_atomic_load_xor_i8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var8
+; CHECK-ARM-NEXT: movt r12, :upper16:var8
+; CHECK-ARM-NEXT: .LBB16_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaexb r1, [r12]
+; CHECK-ARM-NEXT: eor r3, r1, r0
+; CHECK-ARM-NEXT: strexb r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB16_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_xor_i8:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var8
+; CHECK-THUMB-NEXT: movt r12, :upper16:var8
+; CHECK-THUMB-NEXT: .LBB16_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaexb r1, [r12]
+; CHECK-THUMB-NEXT: eor.w r3, r1, r0
+; CHECK-THUMB-NEXT: strexb r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB16_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw xor ptr @var8, i8 %offset acquire
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
-; CHECK: movt r[[ADDR]], :upper16:var8
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: eor{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i8 %old
}
define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_xor_i16:
+; CHECK-ARM-LABEL: test_atomic_load_xor_i16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var16
+; CHECK-ARM-NEXT: movt r12, :upper16:var16
+; CHECK-ARM-NEXT: .LBB17_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrexh r1, [r12]
+; CHECK-ARM-NEXT: eor r3, r1, r0
+; CHECK-ARM-NEXT: stlexh r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB17_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_xor_i16:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var16
+; CHECK-THUMB-NEXT: movt r12, :upper16:var16
+; CHECK-THUMB-NEXT: .LBB17_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexh r1, [r12]
+; CHECK-THUMB-NEXT: eor.w r3, r1, r0
+; CHECK-THUMB-NEXT: stlexh r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB17_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw xor ptr @var16, i16 %offset release
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
-; CHECK: movt r[[ADDR]], :upper16:var16
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: eor{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i16 %old
}
define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_xor_i32:
+; CHECK-ARM-LABEL: test_atomic_load_xor_i32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var32
+; CHECK-ARM-NEXT: movt r12, :upper16:var32
+; CHECK-ARM-NEXT: .LBB18_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaex r1, [r12]
+; CHECK-ARM-NEXT: eor r3, r1, r0
+; CHECK-ARM-NEXT: stlex r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB18_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_xor_i32:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var32
+; CHECK-THUMB-NEXT: movt r12, :upper16:var32
+; CHECK-THUMB-NEXT: .LBB18_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaex r1, [r12]
+; CHECK-THUMB-NEXT: eor.w r3, r1, r0
+; CHECK-THUMB-NEXT: stlex r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB18_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw xor ptr @var32, i32 %offset seq_cst
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
-; CHECK: movt r[[ADDR]], :upper16:var32
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: eor{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0
-; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i32 %old
}
define void @test_atomic_load_xor_i64(i64 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_xor_i64:
+; CHECK-ARM-LABEL: test_atomic_load_xor_i64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-NEXT: .LBB19_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrexd r4, r5, [r2]
+; CHECK-ARM-NEXT: eor r7, r5, r1
+; CHECK-ARM-NEXT: eor r6, r4, r0
+; CHECK-ARM-NEXT: strexd r3, r6, r7, [r2]
+; CHECK-ARM-NEXT: cmp r3, #0
+; CHECK-ARM-NEXT: bne .LBB19_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-THUMB-LABEL: test_atomic_load_xor_i64:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-NEXT: .LBB19_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexd r3, r2, [r12]
+; CHECK-THUMB-NEXT: eor.w lr, r2, r1
+; CHECK-THUMB-NEXT: eor.w r4, r3, r0
+; CHECK-THUMB-NEXT: strexd r5, r4, lr, [r12]
+; CHECK-THUMB-NEXT: cmp r5, #0
+; CHECK-THUMB-NEXT: bne .LBB19_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: strd r3, r2, [r12]
+; CHECK-THUMB-NEXT: pop {r4, r5, r7, pc}
%old = atomicrmw xor ptr @var64, i64 %offset monotonic
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
-; CHECK: movt r[[ADDR]], :upper16:var64
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]]
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-LE-DAG: eor{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
-; CHECK-LE-DAG: eor{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
-; CHECK-BE-DAG: eor{{(\.w)?}} [[NEW2:r[0-9]+|lr]], r[[OLD2]], r1
-; CHECK-BE-DAG: eor{{(\.w)?}} [[NEW1:r[0-9]+|lr]], r[[OLD1]], r0
-; CHECK: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: strd r[[OLD1]], r[[OLD2]], [r[[ADDR]]]
+
store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xchg_i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r2, :lower16:var8
+; CHECK-NEXT: movt r2, :upper16:var8
+; CHECK-NEXT: .LBB20_1: @ %atomicrmw.start
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ldrexb r1, [r2]
+; CHECK-NEXT: strexb r3, r0, [r2]
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: bne .LBB20_1
+; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-NEXT: mov r0, r1
+; CHECK-NEXT: bx lr
%old = atomicrmw xchg ptr @var8, i8 %offset monotonic
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
-; CHECK: movt r[[ADDR]], :upper16:var8
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], r0, [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: mov r0, r[[OLD]]
ret i8 %old
}
define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xchg_i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r2, :lower16:var16
+; CHECK-NEXT: movt r2, :upper16:var16
+; CHECK-NEXT: .LBB21_1: @ %atomicrmw.start
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ldaexh r1, [r2]
+; CHECK-NEXT: stlexh r3, r0, [r2]
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: bne .LBB21_1
+; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-NEXT: mov r0, r1
+; CHECK-NEXT: bx lr
%old = atomicrmw xchg ptr @var16, i16 %offset seq_cst
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
-; CHECK: movt r[[ADDR]], :upper16:var16
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r0, [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: mov r0, r[[OLD]]
ret i16 %old
}
define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
; CHECK-LABEL: test_atomic_load_xchg_i32:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r2, :lower16:var32
+; CHECK-NEXT: movt r2, :upper16:var32
+; CHECK-NEXT: .LBB22_1: @ %atomicrmw.start
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ldrex r1, [r2]
+; CHECK-NEXT: stlex r3, r0, [r2]
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: bne .LBB22_1
+; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-NEXT: mov r0, r1
+; CHECK-NEXT: bx lr
%old = atomicrmw xchg ptr @var32, i32 %offset release
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
-; CHECK: movt r[[ADDR]], :upper16:var32
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r0, [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: mov r0, r[[OLD]]
ret i32 %old
}
define void @test_atomic_load_xchg_i64(i64 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_xchg_i64:
+; CHECK-ARM-LABEL: test_atomic_load_xchg_i64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: push {r4, r5, r11, lr}
+; CHECK-ARM-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-NEXT: @ kill: def $r1 killed $r1 killed $r0_r1 def $r0_r1
+; CHECK-ARM-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-NEXT: @ kill: def $r0 killed $r0 killed $r0_r1 def $r0_r1
+; CHECK-ARM-NEXT: .LBB23_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaexd r4, r5, [r2]
+; CHECK-ARM-NEXT: strexd r3, r0, r1, [r2]
+; CHECK-ARM-NEXT: cmp r3, #0
+; CHECK-ARM-NEXT: bne .LBB23_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-NEXT: pop {r4, r5, r11, pc}
+;
+; CHECK-THUMB-LABEL: test_atomic_load_xchg_i64:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: push {r7, lr}
+; CHECK-THUMB-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-NEXT: .LBB23_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaexd r3, lr, [r12]
+; CHECK-THUMB-NEXT: strexd r2, r0, r1, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB23_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: strd r3, lr, [r12]
+; CHECK-THUMB-NEXT: pop {r7, pc}
%old = atomicrmw xchg ptr @var64, i64 %offset acquire
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
-; CHECK: movt r[[ADDR]], :upper16:var64
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexd [[OLD1:r[0-9]+]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: strd [[OLD1]], [[OLD2]], [r[[ADDR]]]
store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_min_i8(i8 signext %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_min_i8:
+; CHECK-ARM-LABEL: test_atomic_load_min_i8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var8
+; CHECK-ARM-NEXT: movt r12, :upper16:var8
+; CHECK-ARM-NEXT: .LBB24_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaexb r1, [r12]
+; CHECK-ARM-NEXT: sxtb r3, r1
+; CHECK-ARM-NEXT: cmp r3, r0
+; CHECK-ARM-NEXT: movge r3, r0
+; CHECK-ARM-NEXT: strexb r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB24_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_min_i8:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var8
+; CHECK-THUMB-NEXT: movt r12, :upper16:var8
+; CHECK-THUMB-NEXT: .LBB24_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaexb r1, [r12]
+; CHECK-THUMB-NEXT: sxtb r3, r1
+; CHECK-THUMB-NEXT: cmp r3, r0
+; CHECK-THUMB-NEXT: it ge
+; CHECK-THUMB-NEXT: movge r3, r0
+; CHECK-THUMB-NEXT: strexb r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB24_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw min ptr @var8, i8 %offset acquire
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK-DAG: movw [[ADDR:r[0-9]+|lr]], :lower16:var8
-; CHECK-DAG: movt [[ADDR]], :upper16:var8
-
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
-; CHECK-NEXT: sxtb r[[OLDX:[0-9]+]], r[[OLD]]
+
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: cmp r[[OLDX]], r0
; Thumb mode: it le
-; CHECK: movle r[[OLDX]], r[[OLD]]
-; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], r[[OLDX]], {{.*}}[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i8 %old
}
define i16 @test_atomic_load_min_i16(i16 signext %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_min_i16:
+; CHECK-ARM-LABEL: test_atomic_load_min_i16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var16
+; CHECK-ARM-NEXT: movt r12, :upper16:var16
+; CHECK-ARM-NEXT: .LBB25_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrexh r1, [r12]
+; CHECK-ARM-NEXT: sxth r3, r1
+; CHECK-ARM-NEXT: cmp r3, r0
+; CHECK-ARM-NEXT: movge r3, r0
+; CHECK-ARM-NEXT: stlexh r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB25_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_min_i16:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var16
+; CHECK-THUMB-NEXT: movt r12, :upper16:var16
+; CHECK-THUMB-NEXT: .LBB25_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexh r1, [r12]
+; CHECK-THUMB-NEXT: sxth r3, r1
+; CHECK-THUMB-NEXT: cmp r3, r0
+; CHECK-THUMB-NEXT: it ge
+; CHECK-THUMB-NEXT: movge r3, r0
+; CHECK-THUMB-NEXT: stlexh r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB25_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw min ptr @var16, i16 %offset release
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var16
-; CHECK: movt [[ADDR]], :upper16:var16
-
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
-; CHECK-NEXT: sxth r[[OLDX:[0-9]+]], r[[OLD]]
+
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: cmp r[[OLDX]], r0
; Thumb mode: it le
-; CHECK: movle r[[OLDX]], r[[OLD]]
-; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r[[OLDX]], {{.*}}[[ADDR]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i16 %old
}
define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_min_i32:
+; CHECK-ARM-LABEL: test_atomic_load_min_i32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var32
+; CHECK-ARM-NEXT: movt r12, :upper16:var32
+; CHECK-ARM-NEXT: .LBB26_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrex r1, [r12]
+; CHECK-ARM-NEXT: mov r3, r0
+; CHECK-ARM-NEXT: cmp r1, r0
+; CHECK-ARM-NEXT: movlt r3, r1
+; CHECK-ARM-NEXT: strex r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB26_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_min_i32:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var32
+; CHECK-THUMB-NEXT: movt r12, :upper16:var32
+; CHECK-THUMB-NEXT: .LBB26_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrex r1, [r12]
+; CHECK-THUMB-NEXT: mov r3, r0
+; CHECK-THUMB-NEXT: cmp r1, r0
+; CHECK-THUMB-NEXT: it lt
+; CHECK-THUMB-NEXT: movlt r3, r1
+; CHECK-THUMB-NEXT: strex r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB26_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw min ptr @var32, i32 %offset monotonic
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
-; CHECK: movt r[[ADDR]], :upper16:var32
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0
-; CHECK-NEXT: cmp r[[OLD]], r0
; Thumb mode: it le
-; CHECK: movle r[[NEW]], r[[OLD]]
-; CHECK-NEXT: strex [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i32 %old
}
define void @test_atomic_load_min_i64(i64 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_min_i64:
+; CHECK-ARM-LE-LABEL: test_atomic_load_min_i64:
+; CHECK-ARM-LE: @ %bb.0:
+; CHECK-ARM-LE-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-LE-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-LE-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-LE-NEXT: .LBB27_1: @ %atomicrmw.start
+; CHECK-ARM-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-LE-NEXT: ldaexd r4, r5, [r2]
+; CHECK-ARM-LE-NEXT: mov r7, r1
+; CHECK-ARM-LE-NEXT: subs r3, r4, r0
+; CHECK-ARM-LE-NEXT: sbcs r3, r5, r1
+; CHECK-ARM-LE-NEXT: movlt r7, r5
+; CHECK-ARM-LE-NEXT: mov r6, r0
+; CHECK-ARM-LE-NEXT: movlt r6, r4
+; CHECK-ARM-LE-NEXT: stlexd r3, r6, r7, [r2]
+; CHECK-ARM-LE-NEXT: cmp r3, #0
+; CHECK-ARM-LE-NEXT: bne .LBB27_1
+; CHECK-ARM-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-LE-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-LE-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-ARM-BE-LABEL: test_atomic_load_min_i64:
+; CHECK-ARM-BE: @ %bb.0:
+; CHECK-ARM-BE-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-BE-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-BE-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-BE-NEXT: .LBB27_1: @ %atomicrmw.start
+; CHECK-ARM-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-BE-NEXT: ldaexd r4, r5, [r2]
+; CHECK-ARM-BE-NEXT: mov r7, r1
+; CHECK-ARM-BE-NEXT: subs r3, r5, r1
+; CHECK-ARM-BE-NEXT: sbcs r3, r4, r0
+; CHECK-ARM-BE-NEXT: movlt r7, r5
+; CHECK-ARM-BE-NEXT: mov r6, r0
+; CHECK-ARM-BE-NEXT: movlt r6, r4
+; CHECK-ARM-BE-NEXT: stlexd r3, r6, r7, [r2]
+; CHECK-ARM-BE-NEXT: cmp r3, #0
+; CHECK-ARM-BE-NEXT: bne .LBB27_1
+; CHECK-ARM-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-BE-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-BE-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-THUMB-LE-LABEL: test_atomic_load_min_i64:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-LE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-LE-NEXT: .LBB27_1: @ %atomicrmw.start
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: ldaexd r3, lr, [r12]
+; CHECK-THUMB-LE-NEXT: mov r4, r0
+; CHECK-THUMB-LE-NEXT: subs r2, r3, r0
+; CHECK-THUMB-LE-NEXT: sbcs.w r2, lr, r1
+; CHECK-THUMB-LE-NEXT: mov r2, r1
+; CHECK-THUMB-LE-NEXT: itt lt
+; CHECK-THUMB-LE-NEXT: movlt r2, lr
+; CHECK-THUMB-LE-NEXT: movlt r4, r3
+; CHECK-THUMB-LE-NEXT: stlexd r5, r4, r2, [r12]
+; CHECK-THUMB-LE-NEXT: cmp r5, #0
+; CHECK-THUMB-LE-NEXT: bne .LBB27_1
+; CHECK-THUMB-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-LE-NEXT: strd r3, lr, [r12]
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-THUMB-BE-LABEL: test_atomic_load_min_i64:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-BE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-BE-NEXT: .LBB27_1: @ %atomicrmw.start
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: ldaexd r3, lr, [r12]
+; CHECK-THUMB-BE-NEXT: mov r4, r0
+; CHECK-THUMB-BE-NEXT: subs.w r2, lr, r1
+; CHECK-THUMB-BE-NEXT: sbcs.w r2, r3, r0
+; CHECK-THUMB-BE-NEXT: mov r2, r1
+; CHECK-THUMB-BE-NEXT: itt lt
+; CHECK-THUMB-BE-NEXT: movlt r2, lr
+; CHECK-THUMB-BE-NEXT: movlt r4, r3
+; CHECK-THUMB-BE-NEXT: stlexd r5, r4, r2, [r12]
+; CHECK-THUMB-BE-NEXT: cmp r5, #0
+; CHECK-THUMB-BE-NEXT: bne .LBB27_1
+; CHECK-THUMB-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-BE-NEXT: strd r3, lr, [r12]
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r7, pc}
%old = atomicrmw min ptr @var64, i64 %offset seq_cst
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
-; CHECK: movt r[[ADDR]], :upper16:var64
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1
-; CHECK-ARM-LE: subs {{[^,]+}}, r0, [[OLD1]]
-; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]]
-; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]]
-; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]]
-; CHECK-ARM: movge [[MINHI]], [[OLD2]]
-; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0
-; CHECK-ARM: movge [[MINLO]], [[OLD1]]
-; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
-; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]]
+
store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_max_i8(i8 signext %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_max_i8:
+; CHECK-ARM-LABEL: test_atomic_load_max_i8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var8
+; CHECK-ARM-NEXT: movt r12, :upper16:var8
+; CHECK-ARM-NEXT: .LBB28_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaexb r1, [r12]
+; CHECK-ARM-NEXT: sxtb r3, r1
+; CHECK-ARM-NEXT: cmp r3, r0
+; CHECK-ARM-NEXT: movle r3, r0
+; CHECK-ARM-NEXT: stlexb r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB28_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_max_i8:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var8
+; CHECK-THUMB-NEXT: movt r12, :upper16:var8
+; CHECK-THUMB-NEXT: .LBB28_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaexb r1, [r12]
+; CHECK-THUMB-NEXT: sxtb r3, r1
+; CHECK-THUMB-NEXT: cmp r3, r0
+; CHECK-THUMB-NEXT: it le
+; CHECK-THUMB-NEXT: movle r3, r0
+; CHECK-THUMB-NEXT: stlexb r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB28_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw max ptr @var8, i8 %offset seq_cst
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var8
-; CHECK: movt [[ADDR]], :upper16:var8
-
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
-; CHECK-NEXT: sxtb r[[OLDX:[0-9]+]], r[[OLD]]
+
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: cmp r[[OLDX]], r0
; Thumb mode: it gt
-; CHECK: movgt r[[OLDX]], r[[OLD]]
-; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], r[[OLDX]], {{.*}}[[ADDR]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i8 %old
}
define i16 @test_atomic_load_max_i16(i16 signext %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_max_i16:
+; CHECK-ARM-LABEL: test_atomic_load_max_i16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var16
+; CHECK-ARM-NEXT: movt r12, :upper16:var16
+; CHECK-ARM-NEXT: .LBB29_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaexh r1, [r12]
+; CHECK-ARM-NEXT: sxth r3, r1
+; CHECK-ARM-NEXT: cmp r3, r0
+; CHECK-ARM-NEXT: movle r3, r0
+; CHECK-ARM-NEXT: strexh r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB29_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_max_i16:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var16
+; CHECK-THUMB-NEXT: movt r12, :upper16:var16
+; CHECK-THUMB-NEXT: .LBB29_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaexh r1, [r12]
+; CHECK-THUMB-NEXT: sxth r3, r1
+; CHECK-THUMB-NEXT: cmp r3, r0
+; CHECK-THUMB-NEXT: it le
+; CHECK-THUMB-NEXT: movle r3, r0
+; CHECK-THUMB-NEXT: strexh r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB29_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw max ptr @var16, i16 %offset acquire
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
-; CHECK: movt r[[ADDR]], :upper16:var16
-
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
-; CHECK-NEXT: sxth r[[OLDX:[0-9]+]], r[[OLD]]
+
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: cmp r[[OLDX]], r0
; Thumb mode: it gt
-; CHECK: movgt r[[OLDX]], r[[OLD]]
-; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[OLDX]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i16 %old
}
define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_max_i32:
+; CHECK-ARM-LABEL: test_atomic_load_max_i32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var32
+; CHECK-ARM-NEXT: movt r12, :upper16:var32
+; CHECK-ARM-NEXT: .LBB30_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrex r1, [r12]
+; CHECK-ARM-NEXT: mov r3, r0
+; CHECK-ARM-NEXT: cmp r1, r0
+; CHECK-ARM-NEXT: movgt r3, r1
+; CHECK-ARM-NEXT: stlex r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB30_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_max_i32:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var32
+; CHECK-THUMB-NEXT: movt r12, :upper16:var32
+; CHECK-THUMB-NEXT: .LBB30_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrex r1, [r12]
+; CHECK-THUMB-NEXT: mov r3, r0
+; CHECK-THUMB-NEXT: cmp r1, r0
+; CHECK-THUMB-NEXT: it gt
+; CHECK-THUMB-NEXT: movgt r3, r1
+; CHECK-THUMB-NEXT: stlex r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB30_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw max ptr @var32, i32 %offset release
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
-; CHECK: movt r[[ADDR]], :upper16:var32
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0
-; CHECK-NEXT: cmp r[[OLD]], r0
; Thumb mode: it gt
-; CHECK: movgt r[[NEW]], r[[OLD]]
-; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i32 %old
}
define void @test_atomic_load_max_i64(i64 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_max_i64:
+; CHECK-ARM-LE-LABEL: test_atomic_load_max_i64:
+; CHECK-ARM-LE: @ %bb.0:
+; CHECK-ARM-LE-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-LE-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-LE-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-LE-NEXT: .LBB31_1: @ %atomicrmw.start
+; CHECK-ARM-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-LE-NEXT: ldrexd r4, r5, [r2]
+; CHECK-ARM-LE-NEXT: mov r7, r1
+; CHECK-ARM-LE-NEXT: subs r3, r0, r4
+; CHECK-ARM-LE-NEXT: sbcs r3, r1, r5
+; CHECK-ARM-LE-NEXT: movlt r7, r5
+; CHECK-ARM-LE-NEXT: mov r6, r0
+; CHECK-ARM-LE-NEXT: movlt r6, r4
+; CHECK-ARM-LE-NEXT: strexd r3, r6, r7, [r2]
+; CHECK-ARM-LE-NEXT: cmp r3, #0
+; CHECK-ARM-LE-NEXT: bne .LBB31_1
+; CHECK-ARM-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-LE-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-LE-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-ARM-BE-LABEL: test_atomic_load_max_i64:
+; CHECK-ARM-BE: @ %bb.0:
+; CHECK-ARM-BE-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-BE-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-BE-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-BE-NEXT: .LBB31_1: @ %atomicrmw.start
+; CHECK-ARM-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-BE-NEXT: ldrexd r4, r5, [r2]
+; CHECK-ARM-BE-NEXT: mov r7, r1
+; CHECK-ARM-BE-NEXT: subs r3, r1, r5
+; CHECK-ARM-BE-NEXT: sbcs r3, r0, r4
+; CHECK-ARM-BE-NEXT: movlt r7, r5
+; CHECK-ARM-BE-NEXT: mov r6, r0
+; CHECK-ARM-BE-NEXT: movlt r6, r4
+; CHECK-ARM-BE-NEXT: strexd r3, r6, r7, [r2]
+; CHECK-ARM-BE-NEXT: cmp r3, #0
+; CHECK-ARM-BE-NEXT: bne .LBB31_1
+; CHECK-ARM-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-BE-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-BE-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-THUMB-LE-LABEL: test_atomic_load_max_i64:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-LE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-LE-NEXT: .LBB31_1: @ %atomicrmw.start
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: ldrexd r3, lr, [r12]
+; CHECK-THUMB-LE-NEXT: mov r4, r0
+; CHECK-THUMB-LE-NEXT: subs r2, r0, r3
+; CHECK-THUMB-LE-NEXT: sbcs.w r2, r1, lr
+; CHECK-THUMB-LE-NEXT: mov r2, r1
+; CHECK-THUMB-LE-NEXT: itt lt
+; CHECK-THUMB-LE-NEXT: movlt r2, lr
+; CHECK-THUMB-LE-NEXT: movlt r4, r3
+; CHECK-THUMB-LE-NEXT: strexd r5, r4, r2, [r12]
+; CHECK-THUMB-LE-NEXT: cmp r5, #0
+; CHECK-THUMB-LE-NEXT: bne .LBB31_1
+; CHECK-THUMB-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-LE-NEXT: strd r3, lr, [r12]
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-THUMB-BE-LABEL: test_atomic_load_max_i64:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-BE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-BE-NEXT: .LBB31_1: @ %atomicrmw.start
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: ldrexd r3, lr, [r12]
+; CHECK-THUMB-BE-NEXT: mov r4, r0
+; CHECK-THUMB-BE-NEXT: subs.w r2, r1, lr
+; CHECK-THUMB-BE-NEXT: sbcs.w r2, r0, r3
+; CHECK-THUMB-BE-NEXT: mov r2, r1
+; CHECK-THUMB-BE-NEXT: itt lt
+; CHECK-THUMB-BE-NEXT: movlt r2, lr
+; CHECK-THUMB-BE-NEXT: movlt r4, r3
+; CHECK-THUMB-BE-NEXT: strexd r5, r4, r2, [r12]
+; CHECK-THUMB-BE-NEXT: cmp r5, #0
+; CHECK-THUMB-BE-NEXT: bne .LBB31_1
+; CHECK-THUMB-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-BE-NEXT: strd r3, lr, [r12]
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r7, pc}
%old = atomicrmw max ptr @var64, i64 %offset monotonic
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
-; CHECK: movt r[[ADDR]], :upper16:var64
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexd [[OLD1:r[0-9]+]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1
-; CHECK-ARM-LE: subs {{[^,]+}}, r0, [[OLD1]]
-; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]]
-; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]]
-; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]]
-; CHECK-ARM: movlt [[MINHI]], [[OLD2]]
-; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0
-; CHECK-ARM: movlt [[MINLO]], [[OLD1]]
-; CHECK-ARM: strexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
-; CHECK-THUMB: strexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]]
+
store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_umin_i8(i8 zeroext %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_umin_i8:
+; CHECK-ARM-LABEL: test_atomic_load_umin_i8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var8
+; CHECK-ARM-NEXT: movt r12, :upper16:var8
+; CHECK-ARM-NEXT: .LBB32_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrexb r1, [r12]
+; CHECK-ARM-NEXT: mov r3, r0
+; CHECK-ARM-NEXT: cmp r1, r0
+; CHECK-ARM-NEXT: movlo r3, r1
+; CHECK-ARM-NEXT: strexb r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB32_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_umin_i8:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var8
+; CHECK-THUMB-NEXT: movt r12, :upper16:var8
+; CHECK-THUMB-NEXT: .LBB32_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexb r1, [r12]
+; CHECK-THUMB-NEXT: mov r3, r0
+; CHECK-THUMB-NEXT: cmp r1, r0
+; CHECK-THUMB-NEXT: it lo
+; CHECK-THUMB-NEXT: movlo r3, r1
+; CHECK-THUMB-NEXT: strexb r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB32_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw umin ptr @var8, i8 %offset monotonic
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var8
-; CHECK: movt [[ADDR]], :upper16:var8
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0
-; CHECK-NEXT: cmp r[[OLD]], r0
; Thumb mode: it ls
-; CHECK: movls r[[NEW]], r[[OLD]]
-; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i8 %old
}
define i16 @test_atomic_load_umin_i16(i16 zeroext %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_umin_i16:
+; CHECK-ARM-LABEL: test_atomic_load_umin_i16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var16
+; CHECK-ARM-NEXT: movt r12, :upper16:var16
+; CHECK-ARM-NEXT: .LBB33_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaexh r1, [r12]
+; CHECK-ARM-NEXT: mov r3, r0
+; CHECK-ARM-NEXT: cmp r1, r0
+; CHECK-ARM-NEXT: movlo r3, r1
+; CHECK-ARM-NEXT: strexh r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB33_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_umin_i16:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var16
+; CHECK-THUMB-NEXT: movt r12, :upper16:var16
+; CHECK-THUMB-NEXT: .LBB33_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaexh r1, [r12]
+; CHECK-THUMB-NEXT: mov r3, r0
+; CHECK-THUMB-NEXT: cmp r1, r0
+; CHECK-THUMB-NEXT: it lo
+; CHECK-THUMB-NEXT: movlo r3, r1
+; CHECK-THUMB-NEXT: strexh r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB33_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw umin ptr @var16, i16 %offset acquire
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var16
-; CHECK: movt [[ADDR]], :upper16:var16
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0
-; CHECK-NEXT: cmp r[[OLD]], r0
; Thumb mode: it ls
-; CHECK: movls r[[NEW]], r[[OLD]]
-; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i16 %old
}
define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_umin_i32:
+; CHECK-ARM-LABEL: test_atomic_load_umin_i32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var32
+; CHECK-ARM-NEXT: movt r12, :upper16:var32
+; CHECK-ARM-NEXT: .LBB34_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaex r1, [r12]
+; CHECK-ARM-NEXT: mov r3, r0
+; CHECK-ARM-NEXT: cmp r1, r0
+; CHECK-ARM-NEXT: movlo r3, r1
+; CHECK-ARM-NEXT: stlex r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB34_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_umin_i32:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var32
+; CHECK-THUMB-NEXT: movt r12, :upper16:var32
+; CHECK-THUMB-NEXT: .LBB34_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaex r1, [r12]
+; CHECK-THUMB-NEXT: mov r3, r0
+; CHECK-THUMB-NEXT: cmp r1, r0
+; CHECK-THUMB-NEXT: it lo
+; CHECK-THUMB-NEXT: movlo r3, r1
+; CHECK-THUMB-NEXT: stlex r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB34_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw umin ptr @var32, i32 %offset seq_cst
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
-; CHECK: movt r[[ADDR]], :upper16:var32
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0
-; CHECK-NEXT: cmp r[[OLD]], r0
; Thumb mode: it ls
-; CHECK: movls r[[NEW]], r[[OLD]]
-; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i32 %old
}
define void @test_atomic_load_umin_i64(i64 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_umin_i64:
+; CHECK-ARM-LE-LABEL: test_atomic_load_umin_i64:
+; CHECK-ARM-LE: @ %bb.0:
+; CHECK-ARM-LE-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-LE-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-LE-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-LE-NEXT: .LBB35_1: @ %atomicrmw.start
+; CHECK-ARM-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-LE-NEXT: ldaexd r4, r5, [r2]
+; CHECK-ARM-LE-NEXT: mov r7, r1
+; CHECK-ARM-LE-NEXT: subs r3, r4, r0
+; CHECK-ARM-LE-NEXT: sbcs r3, r5, r1
+; CHECK-ARM-LE-NEXT: movlo r7, r5
+; CHECK-ARM-LE-NEXT: mov r6, r0
+; CHECK-ARM-LE-NEXT: movlo r6, r4
+; CHECK-ARM-LE-NEXT: stlexd r3, r6, r7, [r2]
+; CHECK-ARM-LE-NEXT: cmp r3, #0
+; CHECK-ARM-LE-NEXT: bne .LBB35_1
+; CHECK-ARM-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-LE-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-LE-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-ARM-BE-LABEL: test_atomic_load_umin_i64:
+; CHECK-ARM-BE: @ %bb.0:
+; CHECK-ARM-BE-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-BE-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-BE-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-BE-NEXT: .LBB35_1: @ %atomicrmw.start
+; CHECK-ARM-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-BE-NEXT: ldaexd r4, r5, [r2]
+; CHECK-ARM-BE-NEXT: mov r7, r1
+; CHECK-ARM-BE-NEXT: subs r3, r5, r1
+; CHECK-ARM-BE-NEXT: sbcs r3, r4, r0
+; CHECK-ARM-BE-NEXT: movlo r7, r5
+; CHECK-ARM-BE-NEXT: mov r6, r0
+; CHECK-ARM-BE-NEXT: movlo r6, r4
+; CHECK-ARM-BE-NEXT: stlexd r3, r6, r7, [r2]
+; CHECK-ARM-BE-NEXT: cmp r3, #0
+; CHECK-ARM-BE-NEXT: bne .LBB35_1
+; CHECK-ARM-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-BE-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-BE-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-THUMB-LE-LABEL: test_atomic_load_umin_i64:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-LE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-LE-NEXT: .LBB35_1: @ %atomicrmw.start
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: ldaexd r3, lr, [r12]
+; CHECK-THUMB-LE-NEXT: mov r4, r0
+; CHECK-THUMB-LE-NEXT: subs r2, r3, r0
+; CHECK-THUMB-LE-NEXT: sbcs.w r2, lr, r1
+; CHECK-THUMB-LE-NEXT: mov r2, r1
+; CHECK-THUMB-LE-NEXT: itt lo
+; CHECK-THUMB-LE-NEXT: movlo r2, lr
+; CHECK-THUMB-LE-NEXT: movlo r4, r3
+; CHECK-THUMB-LE-NEXT: stlexd r5, r4, r2, [r12]
+; CHECK-THUMB-LE-NEXT: cmp r5, #0
+; CHECK-THUMB-LE-NEXT: bne .LBB35_1
+; CHECK-THUMB-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-LE-NEXT: strd r3, lr, [r12]
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-THUMB-BE-LABEL: test_atomic_load_umin_i64:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-BE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-BE-NEXT: .LBB35_1: @ %atomicrmw.start
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: ldaexd r3, lr, [r12]
+; CHECK-THUMB-BE-NEXT: mov r4, r0
+; CHECK-THUMB-BE-NEXT: subs.w r2, lr, r1
+; CHECK-THUMB-BE-NEXT: sbcs.w r2, r3, r0
+; CHECK-THUMB-BE-NEXT: mov r2, r1
+; CHECK-THUMB-BE-NEXT: itt lo
+; CHECK-THUMB-BE-NEXT: movlo r2, lr
+; CHECK-THUMB-BE-NEXT: movlo r4, r3
+; CHECK-THUMB-BE-NEXT: stlexd r5, r4, r2, [r12]
+; CHECK-THUMB-BE-NEXT: cmp r5, #0
+; CHECK-THUMB-BE-NEXT: bne .LBB35_1
+; CHECK-THUMB-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-BE-NEXT: strd r3, lr, [r12]
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r7, pc}
%old = atomicrmw umin ptr @var64, i64 %offset seq_cst
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
-; CHECK: movt r[[ADDR]], :upper16:var64
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1
-; CHECK-ARM-LE: subs {{[^,]+}}, r0, [[OLD1]]
-; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]]
-; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]]
-; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]]
-; CHECK-ARM: movhs [[MINHI]], [[OLD2]]
-; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0
-; CHECK-ARM: movhs [[MINLO]], [[OLD1]]
-; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
-; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]]
+
store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_umax_i8(i8 zeroext %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_umax_i8:
+; CHECK-ARM-LABEL: test_atomic_load_umax_i8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var8
+; CHECK-ARM-NEXT: movt r12, :upper16:var8
+; CHECK-ARM-NEXT: .LBB36_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaexb r1, [r12]
+; CHECK-ARM-NEXT: mov r3, r0
+; CHECK-ARM-NEXT: cmp r1, r0
+; CHECK-ARM-NEXT: movhi r3, r1
+; CHECK-ARM-NEXT: stlexb r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB36_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_umax_i8:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var8
+; CHECK-THUMB-NEXT: movt r12, :upper16:var8
+; CHECK-THUMB-NEXT: .LBB36_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaexb r1, [r12]
+; CHECK-THUMB-NEXT: mov r3, r0
+; CHECK-THUMB-NEXT: cmp r1, r0
+; CHECK-THUMB-NEXT: it hi
+; CHECK-THUMB-NEXT: movhi r3, r1
+; CHECK-THUMB-NEXT: stlexb r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB36_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw umax ptr @var8, i8 %offset acq_rel
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var8
-; CHECK: movt [[ADDR]], :upper16:var8
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexb r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0
-; CHECK-NEXT: cmp r[[OLD]], r0
; Thumb mode: it hi
-; CHECK: movhi r[[NEW]], r[[OLD]]
-; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i8 %old
}
define i16 @test_atomic_load_umax_i16(i16 zeroext %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_umax_i16:
+; CHECK-ARM-LABEL: test_atomic_load_umax_i16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var16
+; CHECK-ARM-NEXT: movt r12, :upper16:var16
+; CHECK-ARM-NEXT: .LBB37_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrexh r1, [r12]
+; CHECK-ARM-NEXT: mov r3, r0
+; CHECK-ARM-NEXT: cmp r1, r0
+; CHECK-ARM-NEXT: movhi r3, r1
+; CHECK-ARM-NEXT: strexh r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB37_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_umax_i16:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var16
+; CHECK-THUMB-NEXT: movt r12, :upper16:var16
+; CHECK-THUMB-NEXT: .LBB37_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexh r1, [r12]
+; CHECK-THUMB-NEXT: mov r3, r0
+; CHECK-THUMB-NEXT: cmp r1, r0
+; CHECK-THUMB-NEXT: it hi
+; CHECK-THUMB-NEXT: movhi r3, r1
+; CHECK-THUMB-NEXT: strexh r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB37_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw umax ptr @var16, i16 %offset monotonic
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var16
-; CHECK: movt [[ADDR]], :upper16:var16
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexh r[[OLD:[0-9]+]], {{.*}}[[ADDR]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0
-; CHECK-NEXT: cmp r[[OLD]], r0
; Thumb mode: it hi
-; CHECK: movhi r[[NEW]], r[[OLD]]
-; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[NEW]], {{.*}}[[ADDR]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i16 %old
}
define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_umax_i32:
+; CHECK-ARM-LABEL: test_atomic_load_umax_i32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var32
+; CHECK-ARM-NEXT: movt r12, :upper16:var32
+; CHECK-ARM-NEXT: .LBB38_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaex r1, [r12]
+; CHECK-ARM-NEXT: mov r3, r0
+; CHECK-ARM-NEXT: cmp r1, r0
+; CHECK-ARM-NEXT: movhi r3, r1
+; CHECK-ARM-NEXT: stlex r2, r3, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB38_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: mov r0, r1
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_load_umax_i32:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var32
+; CHECK-THUMB-NEXT: movt r12, :upper16:var32
+; CHECK-THUMB-NEXT: .LBB38_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaex r1, [r12]
+; CHECK-THUMB-NEXT: mov r3, r0
+; CHECK-THUMB-NEXT: cmp r1, r0
+; CHECK-THUMB-NEXT: it hi
+; CHECK-THUMB-NEXT: movhi r3, r1
+; CHECK-THUMB-NEXT: stlex r2, r3, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB38_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: mov r0, r1
+; CHECK-THUMB-NEXT: bx lr
%old = atomicrmw umax ptr @var32, i32 %offset seq_cst
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
-; CHECK: movt r[[ADDR]], :upper16:var32
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0
-; CHECK-NEXT: cmp r[[OLD]], r0
; Thumb mode: it hi
-; CHECK: movhi r[[NEW]], r[[OLD]]
-; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: mov r0, r[[OLD]]
+
ret i32 %old
}
define void @test_atomic_load_umax_i64(i64 %offset) nounwind {
-; CHECK-LABEL: test_atomic_load_umax_i64:
+; CHECK-ARM-LE-LABEL: test_atomic_load_umax_i64:
+; CHECK-ARM-LE: @ %bb.0:
+; CHECK-ARM-LE-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-LE-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-LE-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-LE-NEXT: .LBB39_1: @ %atomicrmw.start
+; CHECK-ARM-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-LE-NEXT: ldaexd r4, r5, [r2]
+; CHECK-ARM-LE-NEXT: mov r7, r1
+; CHECK-ARM-LE-NEXT: subs r3, r0, r4
+; CHECK-ARM-LE-NEXT: sbcs r3, r1, r5
+; CHECK-ARM-LE-NEXT: movlo r7, r5
+; CHECK-ARM-LE-NEXT: mov r6, r0
+; CHECK-ARM-LE-NEXT: movlo r6, r4
+; CHECK-ARM-LE-NEXT: stlexd r3, r6, r7, [r2]
+; CHECK-ARM-LE-NEXT: cmp r3, #0
+; CHECK-ARM-LE-NEXT: bne .LBB39_1
+; CHECK-ARM-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-LE-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-LE-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-ARM-BE-LABEL: test_atomic_load_umax_i64:
+; CHECK-ARM-BE: @ %bb.0:
+; CHECK-ARM-BE-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-ARM-BE-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-BE-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-BE-NEXT: .LBB39_1: @ %atomicrmw.start
+; CHECK-ARM-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-BE-NEXT: ldaexd r4, r5, [r2]
+; CHECK-ARM-BE-NEXT: mov r7, r1
+; CHECK-ARM-BE-NEXT: subs r3, r1, r5
+; CHECK-ARM-BE-NEXT: sbcs r3, r0, r4
+; CHECK-ARM-BE-NEXT: movlo r7, r5
+; CHECK-ARM-BE-NEXT: mov r6, r0
+; CHECK-ARM-BE-NEXT: movlo r6, r4
+; CHECK-ARM-BE-NEXT: stlexd r3, r6, r7, [r2]
+; CHECK-ARM-BE-NEXT: cmp r3, #0
+; CHECK-ARM-BE-NEXT: bne .LBB39_1
+; CHECK-ARM-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-BE-NEXT: strd r4, r5, [r2]
+; CHECK-ARM-BE-NEXT: pop {r4, r5, r6, r7, r11, pc}
+;
+; CHECK-THUMB-LE-LABEL: test_atomic_load_umax_i64:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-LE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-LE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-LE-NEXT: .LBB39_1: @ %atomicrmw.start
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: ldaexd r3, lr, [r12]
+; CHECK-THUMB-LE-NEXT: mov r4, r0
+; CHECK-THUMB-LE-NEXT: subs r2, r0, r3
+; CHECK-THUMB-LE-NEXT: sbcs.w r2, r1, lr
+; CHECK-THUMB-LE-NEXT: mov r2, r1
+; CHECK-THUMB-LE-NEXT: itt lo
+; CHECK-THUMB-LE-NEXT: movlo r2, lr
+; CHECK-THUMB-LE-NEXT: movlo r4, r3
+; CHECK-THUMB-LE-NEXT: stlexd r5, r4, r2, [r12]
+; CHECK-THUMB-LE-NEXT: cmp r5, #0
+; CHECK-THUMB-LE-NEXT: bne .LBB39_1
+; CHECK-THUMB-LE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-LE-NEXT: strd r3, lr, [r12]
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r7, pc}
+;
+; CHECK-THUMB-BE-LABEL: test_atomic_load_umax_i64:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r7, lr}
+; CHECK-THUMB-BE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-BE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-BE-NEXT: .LBB39_1: @ %atomicrmw.start
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: ldaexd r3, lr, [r12]
+; CHECK-THUMB-BE-NEXT: mov r4, r0
+; CHECK-THUMB-BE-NEXT: subs.w r2, r1, lr
+; CHECK-THUMB-BE-NEXT: sbcs.w r2, r0, r3
+; CHECK-THUMB-BE-NEXT: mov r2, r1
+; CHECK-THUMB-BE-NEXT: itt lo
+; CHECK-THUMB-BE-NEXT: movlo r2, lr
+; CHECK-THUMB-BE-NEXT: movlo r4, r3
+; CHECK-THUMB-BE-NEXT: stlexd r5, r4, r2, [r12]
+; CHECK-THUMB-BE-NEXT: cmp r5, #0
+; CHECK-THUMB-BE-NEXT: bne .LBB39_1
+; CHECK-THUMB-BE-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-BE-NEXT: strd r3, lr, [r12]
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r7, pc}
%old = atomicrmw umax ptr @var64, i64 %offset seq_cst
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
-; CHECK: movt r[[ADDR]], :upper16:var64
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-ARM: mov [[MINHI:r[0-9]+]], r1
-; CHECK-ARM-LE: subs {{[^,]+}}, r0, [[OLD1]]
-; CHECK-ARM-LE: sbcs {{[^,]+}}, r1, [[OLD2]]
-; CHECK-ARM-BE: subs {{[^,]+}}, r1, [[OLD2]]
-; CHECK-ARM-BE: sbcs {{[^,]+}}, r0, [[OLD1]]
-; CHECK-ARM: movlo [[MINHI]], [[OLD2]]
-; CHECK-ARM: mov [[MINLO:r[0-9]+]], r0
-; CHECK-ARM: movlo [[MINLO]], [[OLD1]]
-; CHECK-ARM: stlexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
-; CHECK-THUMB: stlexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]]
+
store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_cmpxchg_i8(i8 zeroext %wanted, i8 zeroext %new) nounwind {
-; CHECK-LABEL: test_atomic_cmpxchg_i8:
+; CHECK-ARM-LABEL: test_atomic_cmpxchg_i8:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var8
+; CHECK-ARM-NEXT: movt r12, :upper16:var8
+; CHECK-ARM-NEXT: .LBB40_1: @ %cmpxchg.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaexb r2, [r12]
+; CHECK-ARM-NEXT: cmp r2, r0
+; CHECK-ARM-NEXT: bne .LBB40_4
+; CHECK-ARM-NEXT: @ %bb.2: @ %cmpxchg.trystore
+; CHECK-ARM-NEXT: @ in Loop: Header=BB40_1 Depth=1
+; CHECK-ARM-NEXT: strexb r3, r1, [r12]
+; CHECK-ARM-NEXT: cmp r3, #0
+; CHECK-ARM-NEXT: bne .LBB40_1
+; CHECK-ARM-NEXT: @ %bb.3: @ %cmpxchg.end
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+; CHECK-ARM-NEXT: .LBB40_4: @ %cmpxchg.nostore
+; CHECK-ARM-NEXT: clrex
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_cmpxchg_i8:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var8
+; CHECK-THUMB-NEXT: mov r2, r0
+; CHECK-THUMB-NEXT: movt r12, :upper16:var8
+; CHECK-THUMB-NEXT: .LBB40_1: @ %cmpxchg.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaexb r0, [r12]
+; CHECK-THUMB-NEXT: cmp r0, r2
+; CHECK-THUMB-NEXT: bne .LBB40_3
+; CHECK-THUMB-NEXT: @ %bb.2: @ %cmpxchg.trystore
+; CHECK-THUMB-NEXT: @ in Loop: Header=BB40_1 Depth=1
+; CHECK-THUMB-NEXT: strexb r3, r1, [r12]
+; CHECK-THUMB-NEXT: cmp r3, #0
+; CHECK-THUMB-NEXT: it eq
+; CHECK-THUMB-NEXT: bxeq lr
+; CHECK-THUMB-NEXT: b .LBB40_1
+; CHECK-THUMB-NEXT: .LBB40_3: @ %cmpxchg.nostore
+; CHECK-THUMB-NEXT: clrex
+; CHECK-THUMB-NEXT: bx lr
%pair = cmpxchg ptr @var8, i8 %wanted, i8 %new acquire acquire
%old = extractvalue { i8, i1 } %pair, 0
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK-DAG: movw r[[ADDR:[0-9]+]], :lower16:var8
-; CHECK-DAG: movt r[[ADDR]], :upper16:var8
-; CHECK-THUMB-DAG: mov r[[WANTED:[0-9]+]], r0
-
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
+
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-ARM-NEXT: cmp r[[OLD]], r0
-; CHECK-THUMB-NEXT: cmp r[[OLD]], r[[WANTED]]
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_{{[0-9]}}
-; CHECK-NEXT: %bb.2:
; As above, r1 is a reasonable guess.
-; CHECK: strexb [[STATUS:r[0-9]+]], r1, [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-ARM-NEXT: bne .LBB{{[0-9]+}}_{{[0-9]}}
-; CHECK-THUMB-NEXT: it eq
-; CHECK-THUMB-NEXT: bxeq lr
-; CHECK-ARM: mov r0, r[[OLD]]
-; CHECK-ARM: clrex
-; CHECK: bx lr
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
ret i8 %old
}
define i16 @test_atomic_cmpxchg_i16(i16 zeroext %wanted, i16 zeroext %new) nounwind {
-; CHECK-LABEL: test_atomic_cmpxchg_i16:
+; CHECK-ARM-LABEL: test_atomic_cmpxchg_i16:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var16
+; CHECK-ARM-NEXT: movt r12, :upper16:var16
+; CHECK-ARM-NEXT: .LBB41_1: @ %cmpxchg.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldaexh r2, [r12]
+; CHECK-ARM-NEXT: cmp r2, r0
+; CHECK-ARM-NEXT: bne .LBB41_4
+; CHECK-ARM-NEXT: @ %bb.2: @ %cmpxchg.trystore
+; CHECK-ARM-NEXT: @ in Loop: Header=BB41_1 Depth=1
+; CHECK-ARM-NEXT: stlexh r3, r1, [r12]
+; CHECK-ARM-NEXT: cmp r3, #0
+; CHECK-ARM-NEXT: bne .LBB41_1
+; CHECK-ARM-NEXT: @ %bb.3: @ %cmpxchg.end
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+; CHECK-ARM-NEXT: .LBB41_4: @ %cmpxchg.nostore
+; CHECK-ARM-NEXT: clrex
+; CHECK-ARM-NEXT: mov r0, r2
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_cmpxchg_i16:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var16
+; CHECK-THUMB-NEXT: mov r2, r0
+; CHECK-THUMB-NEXT: movt r12, :upper16:var16
+; CHECK-THUMB-NEXT: .LBB41_1: @ %cmpxchg.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldaexh r0, [r12]
+; CHECK-THUMB-NEXT: cmp r0, r2
+; CHECK-THUMB-NEXT: bne .LBB41_3
+; CHECK-THUMB-NEXT: @ %bb.2: @ %cmpxchg.trystore
+; CHECK-THUMB-NEXT: @ in Loop: Header=BB41_1 Depth=1
+; CHECK-THUMB-NEXT: stlexh r3, r1, [r12]
+; CHECK-THUMB-NEXT: cmp r3, #0
+; CHECK-THUMB-NEXT: it eq
+; CHECK-THUMB-NEXT: bxeq lr
+; CHECK-THUMB-NEXT: b .LBB41_1
+; CHECK-THUMB-NEXT: .LBB41_3: @ %cmpxchg.nostore
+; CHECK-THUMB-NEXT: clrex
+; CHECK-THUMB-NEXT: bx lr
%pair = cmpxchg ptr @var16, i16 %wanted, i16 %new seq_cst seq_cst
%old = extractvalue { i16, i1 } %pair, 0
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK-DAG: movw r[[ADDR:[0-9]+]], :lower16:var16
-; CHECK-DAG: movt r[[ADDR]], :upper16:var16
-; CHECK-THUMB-DAG: mov r[[WANTED:[0-9]+]], r0
-
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
+
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-ARM-NEXT: cmp r[[OLD]], r0
-; CHECK-THUMB-NEXT: cmp r[[OLD]], r[[WANTED]]
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_{{[0-9]}}
-; CHECK-NEXT: %bb.2:
; As above, r1 is a reasonable guess.
-; CHECK: stlexh [[STATUS:r[0-9]+]], r1, [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-ARM-NEXT: bne .LBB{{[0-9]+}}_{{[0-9]}}
-; CHECK-THUMB-NEXT: it eq
-; CHECK-THUMB-NEXT: bxeq lr
-; CHECK-ARM: mov r0, r[[OLD]]
-; CHECK: bx lr
-; CHECK-ARM-NEXT: .LBB{{[0-9]+}}_{{[0-9]}}
-; CHECK-ARM-NEXT: clrex
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK-ARM: mov r0, r[[OLD]]
-; CHECK-ARM-NEXT: bx lr
+
ret i16 %old
}
define void @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
-; CHECK-LABEL: test_atomic_cmpxchg_i32:
+; CHECK-ARM-LABEL: test_atomic_cmpxchg_i32:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: movw r12, :lower16:var32
+; CHECK-ARM-NEXT: movt r12, :upper16:var32
+; CHECK-ARM-NEXT: .LBB42_1: @ %cmpxchg.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrex r3, [r12]
+; CHECK-ARM-NEXT: cmp r3, r0
+; CHECK-ARM-NEXT: bne .LBB42_4
+; CHECK-ARM-NEXT: @ %bb.2: @ %cmpxchg.trystore
+; CHECK-ARM-NEXT: @ in Loop: Header=BB42_1 Depth=1
+; CHECK-ARM-NEXT: stlex r2, r1, [r12]
+; CHECK-ARM-NEXT: cmp r2, #0
+; CHECK-ARM-NEXT: bne .LBB42_1
+; CHECK-ARM-NEXT: @ %bb.3: @ %cmpxchg.end
+; CHECK-ARM-NEXT: str r3, [r12]
+; CHECK-ARM-NEXT: bx lr
+; CHECK-ARM-NEXT: .LBB42_4: @ %cmpxchg.nostore
+; CHECK-ARM-NEXT: clrex
+; CHECK-ARM-NEXT: str r3, [r12]
+; CHECK-ARM-NEXT: bx lr
+;
+; CHECK-THUMB-LABEL: test_atomic_cmpxchg_i32:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var32
+; CHECK-THUMB-NEXT: movt r12, :upper16:var32
+; CHECK-THUMB-NEXT: .LBB42_1: @ %cmpxchg.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrex r3, [r12]
+; CHECK-THUMB-NEXT: cmp r3, r0
+; CHECK-THUMB-NEXT: bne .LBB42_4
+; CHECK-THUMB-NEXT: @ %bb.2: @ %cmpxchg.trystore
+; CHECK-THUMB-NEXT: @ in Loop: Header=BB42_1 Depth=1
+; CHECK-THUMB-NEXT: stlex r2, r1, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB42_1
+; CHECK-THUMB-NEXT: @ %bb.3: @ %cmpxchg.end
+; CHECK-THUMB-NEXT: str.w r3, [r12]
+; CHECK-THUMB-NEXT: bx lr
+; CHECK-THUMB-NEXT: .LBB42_4: @ %cmpxchg.nostore
+; CHECK-THUMB-NEXT: clrex
+; CHECK-THUMB-NEXT: str.w r3, [r12]
+; CHECK-THUMB-NEXT: bx lr
%pair = cmpxchg ptr @var32, i32 %wanted, i32 %new release monotonic
%old = extractvalue { i32, i1 } %pair, 0
store i32 %old, ptr @var32
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
-; CHECK: movt r[[ADDR]], :upper16:var32
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]
; r0 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-NEXT: cmp r[[OLD]], r0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_4
-; CHECK-NEXT: %bb.2:
; As above, r1 is a reasonable guess.
-; CHECK: stlex [[STATUS:r[0-9]+]], r1, [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK: str{{(.w)?}} r[[OLD]],
-; CHECK-NEXT: bx lr
-; CHECK-NEXT: .LBB{{[0-9]+}}_4:
-; CHECK-NEXT: clrex
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK: str{{(.w)?}} r[[OLD]],
-; CHECK-ARM-NEXT: bx lr
+
ret void
}
define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
-; CHECK-LABEL: test_atomic_cmpxchg_i64:
+; CHECK-ARM-LE-LABEL: test_atomic_cmpxchg_i64:
+; CHECK-ARM-LE: @ %bb.0:
+; CHECK-ARM-LE-NEXT: push {r4, r5, r6, lr}
+; CHECK-ARM-LE-NEXT: movw r12, :lower16:var64
+; CHECK-ARM-LE-NEXT: @ kill: def $r3 killed $r3 killed $r2_r3 def $r2_r3
+; CHECK-ARM-LE-NEXT: movt r12, :upper16:var64
+; CHECK-ARM-LE-NEXT: @ kill: def $r2 killed $r2 killed $r2_r3 def $r2_r3
+; CHECK-ARM-LE-NEXT: .LBB43_1: @ %cmpxchg.start
+; CHECK-ARM-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-LE-NEXT: ldrexd r4, r5, [r12]
+; CHECK-ARM-LE-NEXT: eor lr, r5, r1
+; CHECK-ARM-LE-NEXT: eor r6, r4, r0
+; CHECK-ARM-LE-NEXT: orrs r6, r6, lr
+; CHECK-ARM-LE-NEXT: bne .LBB43_4
+; CHECK-ARM-LE-NEXT: @ %bb.2: @ %cmpxchg.trystore
+; CHECK-ARM-LE-NEXT: @ in Loop: Header=BB43_1 Depth=1
+; CHECK-ARM-LE-NEXT: strexd r6, r2, r3, [r12]
+; CHECK-ARM-LE-NEXT: cmp r6, #0
+; CHECK-ARM-LE-NEXT: bne .LBB43_1
+; CHECK-ARM-LE-NEXT: @ %bb.3: @ %cmpxchg.end
+; CHECK-ARM-LE-NEXT: strd r4, r5, [r12]
+; CHECK-ARM-LE-NEXT: pop {r4, r5, r6, pc}
+; CHECK-ARM-LE-NEXT: .LBB43_4: @ %cmpxchg.nostore
+; CHECK-ARM-LE-NEXT: clrex
+; CHECK-ARM-LE-NEXT: strd r4, r5, [r12]
+; CHECK-ARM-LE-NEXT: pop {r4, r5, r6, pc}
+;
+; CHECK-ARM-BE-LABEL: test_atomic_cmpxchg_i64:
+; CHECK-ARM-BE: @ %bb.0:
+; CHECK-ARM-BE-NEXT: push {r4, r5, r6, lr}
+; CHECK-ARM-BE-NEXT: movw r12, :lower16:var64
+; CHECK-ARM-BE-NEXT: @ kill: def $r3 killed $r3 killed $r2_r3 def $r2_r3
+; CHECK-ARM-BE-NEXT: movt r12, :upper16:var64
+; CHECK-ARM-BE-NEXT: @ kill: def $r2 killed $r2 killed $r2_r3 def $r2_r3
+; CHECK-ARM-BE-NEXT: .LBB43_1: @ %cmpxchg.start
+; CHECK-ARM-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-BE-NEXT: ldrexd r4, r5, [r12]
+; CHECK-ARM-BE-NEXT: eor lr, r4, r0
+; CHECK-ARM-BE-NEXT: eor r6, r5, r1
+; CHECK-ARM-BE-NEXT: orrs r6, r6, lr
+; CHECK-ARM-BE-NEXT: bne .LBB43_4
+; CHECK-ARM-BE-NEXT: @ %bb.2: @ %cmpxchg.trystore
+; CHECK-ARM-BE-NEXT: @ in Loop: Header=BB43_1 Depth=1
+; CHECK-ARM-BE-NEXT: strexd r6, r2, r3, [r12]
+; CHECK-ARM-BE-NEXT: cmp r6, #0
+; CHECK-ARM-BE-NEXT: bne .LBB43_1
+; CHECK-ARM-BE-NEXT: @ %bb.3: @ %cmpxchg.end
+; CHECK-ARM-BE-NEXT: strd r4, r5, [r12]
+; CHECK-ARM-BE-NEXT: pop {r4, r5, r6, pc}
+; CHECK-ARM-BE-NEXT: .LBB43_4: @ %cmpxchg.nostore
+; CHECK-ARM-BE-NEXT: clrex
+; CHECK-ARM-BE-NEXT: strd r4, r5, [r12]
+; CHECK-ARM-BE-NEXT: pop {r4, r5, r6, pc}
+;
+; CHECK-THUMB-LE-LABEL: test_atomic_cmpxchg_i64:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: push {r4, r5, r6, lr}
+; CHECK-THUMB-LE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-LE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-LE-NEXT: .LBB43_1: @ %cmpxchg.start
+; CHECK-THUMB-LE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-LE-NEXT: ldrexd lr, r4, [r12]
+; CHECK-THUMB-LE-NEXT: eor.w r5, r4, r1
+; CHECK-THUMB-LE-NEXT: eor.w r6, lr, r0
+; CHECK-THUMB-LE-NEXT: orrs r5, r6
+; CHECK-THUMB-LE-NEXT: bne .LBB43_4
+; CHECK-THUMB-LE-NEXT: @ %bb.2: @ %cmpxchg.trystore
+; CHECK-THUMB-LE-NEXT: @ in Loop: Header=BB43_1 Depth=1
+; CHECK-THUMB-LE-NEXT: strexd r5, r2, r3, [r12]
+; CHECK-THUMB-LE-NEXT: cmp r5, #0
+; CHECK-THUMB-LE-NEXT: bne .LBB43_1
+; CHECK-THUMB-LE-NEXT: @ %bb.3: @ %cmpxchg.end
+; CHECK-THUMB-LE-NEXT: strd lr, r4, [r12]
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r6, pc}
+; CHECK-THUMB-LE-NEXT: .LBB43_4: @ %cmpxchg.nostore
+; CHECK-THUMB-LE-NEXT: clrex
+; CHECK-THUMB-LE-NEXT: strd lr, r4, [r12]
+; CHECK-THUMB-LE-NEXT: pop {r4, r5, r6, pc}
+;
+; CHECK-THUMB-BE-LABEL: test_atomic_cmpxchg_i64:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: push {r4, r5, r6, lr}
+; CHECK-THUMB-BE-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-BE-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-BE-NEXT: .LBB43_1: @ %cmpxchg.start
+; CHECK-THUMB-BE-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-BE-NEXT: ldrexd lr, r4, [r12]
+; CHECK-THUMB-BE-NEXT: eor.w r5, lr, r0
+; CHECK-THUMB-BE-NEXT: eor.w r6, r4, r1
+; CHECK-THUMB-BE-NEXT: orrs r5, r6
+; CHECK-THUMB-BE-NEXT: bne .LBB43_4
+; CHECK-THUMB-BE-NEXT: @ %bb.2: @ %cmpxchg.trystore
+; CHECK-THUMB-BE-NEXT: @ in Loop: Header=BB43_1 Depth=1
+; CHECK-THUMB-BE-NEXT: strexd r5, r2, r3, [r12]
+; CHECK-THUMB-BE-NEXT: cmp r5, #0
+; CHECK-THUMB-BE-NEXT: bne .LBB43_1
+; CHECK-THUMB-BE-NEXT: @ %bb.3: @ %cmpxchg.end
+; CHECK-THUMB-BE-NEXT: strd lr, r4, [r12]
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r6, pc}
+; CHECK-THUMB-BE-NEXT: .LBB43_4: @ %cmpxchg.nostore
+; CHECK-THUMB-BE-NEXT: clrex
+; CHECK-THUMB-BE-NEXT: strd lr, r4, [r12]
+; CHECK-THUMB-BE-NEXT: pop {r4, r5, r6, pc}
%pair = cmpxchg ptr @var64, i64 %wanted, i64 %new monotonic monotonic
%old = extractvalue { i64, i1 } %pair, 0
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
-; CHECK: movt r[[ADDR]], :upper16:var64
-; CHECK: .LBB{{[0-9]+}}_1:
-; CHECK: ldrexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]]
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK-LE-DAG: eor{{(\.w)?}} [[MISMATCH_LO:r[0-9]+|lr]], [[OLD1]], r0
-; CHECK-LE-DAG: eor{{(\.w)?}} [[MISMATCH_HI:r[0-9]+|lr]], [[OLD2]], r1
-; CHECK-ARM-LE: orrs{{(\.w)?}} {{r[0-9]+}}, [[MISMATCH_LO]], [[MISMATCH_HI]]
-; CHECK-THUMB-LE: orrs{{(\.w)?}} {{(r[0-9]+, )?}}[[MISMATCH_HI]], [[MISMATCH_LO]]
-; CHECK-BE-DAG: eor{{(\.w)?}} [[MISMATCH_HI:r[0-9]+|lr]], [[OLD2]], r1
-; CHECK-BE-DAG: eor{{(\.w)?}} [[MISMATCH_LO:r[0-9]+|lr]], [[OLD1]], r0
-; CHECK-ARM-BE: orrs{{(\.w)?}} {{r[0-9]+}}, [[MISMATCH_HI]], [[MISMATCH_LO]]
-; CHECK-THUMB-BE: orrs{{(\.w)?}} {{(r[0-9]+, )?}}[[MISMATCH_LO]], [[MISMATCH_HI]]
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_4
-; CHECK-NEXT: %bb.2:
; As above, r2, r3 is a reasonable guess.
-; CHECK: strexd [[STATUS:r[0-9]+]], r2, r3, [r[[ADDR]]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK: strd [[OLD1]], [[OLD2]], [r[[ADDR]]]
-; CHECK-NEXT: pop
-; CHECK-NEXT: .LBB{{[0-9]+}}_4:
-; CHECK-NEXT: clrex
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-
-; CHECK-ARM: strd [[OLD1]], [[OLD2]], [r[[ADDR]]]
+
store i64 %old, ptr @var64
ret void
}
define i8 @test_atomic_load_monotonic_i8() nounwind {
; CHECK-LABEL: test_atomic_load_monotonic_i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r0, :lower16:var8
+; CHECK-NEXT: movt r0, :upper16:var8
+; CHECK-NEXT: ldrb r0, [r0]
+; CHECK-NEXT: bx lr
%val = load atomic i8, ptr @var8 monotonic, align 1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
-; CHECK: movt r[[ADDR]], :upper16:var8
-; CHECK: ldrb r0, [r[[ADDR]]]
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
ret i8 %val
}
define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
-; CHECK-LABEL: test_atomic_load_monotonic_regoff_i8:
+; CHECK-LE-LABEL: test_atomic_load_monotonic_regoff_i8:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: ldrb r0, [r0, r2]
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_atomic_load_monotonic_regoff_i8:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: ldrb r0, [r1, r3]
+; CHECK-BE-NEXT: bx lr
%addr_int = add i64 %base, %off
%addr = inttoptr i64 %addr_int to ptr
%val = load atomic i8, ptr %addr monotonic, align 1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK-LE: ldrb r0, [r0, r2]
-; CHECK-BE: ldrb r0, [r1, r3]
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
ret i8 %val
}
define i8 @test_atomic_load_acquire_i8() nounwind {
; CHECK-LABEL: test_atomic_load_acquire_i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r0, :lower16:var8
+; CHECK-NEXT: movt r0, :upper16:var8
+; CHECK-NEXT: ldab r0, [r0]
+; CHECK-NEXT: bx lr
%val = load atomic i8, ptr @var8 acquire, align 1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movt r[[ADDR]], :upper16:var8
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: ldab r0, [r[[ADDR]]]
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
ret i8 %val
}
define i8 @test_atomic_load_seq_cst_i8() nounwind {
; CHECK-LABEL: test_atomic_load_seq_cst_i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r0, :lower16:var8
+; CHECK-NEXT: movt r0, :upper16:var8
+; CHECK-NEXT: ldab r0, [r0]
+; CHECK-NEXT: bx lr
%val = load atomic i8, ptr @var8 seq_cst, align 1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movt r[[ADDR]], :upper16:var8
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: ldab r0, [r[[ADDR]]]
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
ret i8 %val
}
define i16 @test_atomic_load_monotonic_i16() nounwind {
; CHECK-LABEL: test_atomic_load_monotonic_i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r0, :lower16:var16
+; CHECK-NEXT: movt r0, :upper16:var16
+; CHECK-NEXT: ldrh r0, [r0]
+; CHECK-NEXT: bx lr
%val = load atomic i16, ptr @var16 monotonic, align 2
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movt r[[ADDR]], :upper16:var16
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: ldrh r0, [r[[ADDR]]]
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
ret i16 %val
}
define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind {
-; CHECK-LABEL: test_atomic_load_monotonic_regoff_i32:
+; CHECK-LE-LABEL: test_atomic_load_monotonic_regoff_i32:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: ldr r0, [r0, r2]
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_atomic_load_monotonic_regoff_i32:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: ldr r0, [r1, r3]
+; CHECK-BE-NEXT: bx lr
%addr_int = add i64 %base, %off
%addr = inttoptr i64 %addr_int to ptr
%val = load atomic i32, ptr %addr monotonic, align 4
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK-LE: ldr r0, [r0, r2]
-; CHECK-BE: ldr r0, [r1, r3]
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
ret i32 %val
}
define i64 @test_atomic_load_seq_cst_i64() nounwind {
; CHECK-LABEL: test_atomic_load_seq_cst_i64:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r0, :lower16:var64
+; CHECK-NEXT: movt r0, :upper16:var64
+; CHECK-NEXT: ldaexd r0, r1, [r0]
+; CHECK-NEXT: clrex
+; CHECK-NEXT: bx lr
%val = load atomic i64, ptr @var64 seq_cst, align 8
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movt r[[ADDR]], :upper16:var64
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: ldaexd r0, r1, [r[[ADDR]]]
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
ret i64 %val
}
define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
; CHECK-LABEL: test_atomic_store_monotonic_i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r1, :lower16:var8
+; CHECK-NEXT: movt r1, :upper16:var8
+; CHECK-NEXT: strb r0, [r1]
+; CHECK-NEXT: bx lr
store atomic i8 %val, ptr @var8 monotonic, align 1
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
-; CHECK: movt r[[ADDR]], :upper16:var8
-; CHECK: strb r0, [r[[ADDR]]]
ret void
}
define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind {
-; CHECK-LABEL: test_atomic_store_monotonic_regoff_i8:
+; CHECK-ARM-LE-LABEL: test_atomic_store_monotonic_regoff_i8:
+; CHECK-ARM-LE: @ %bb.0:
+; CHECK-ARM-LE-NEXT: ldrb r1, [sp]
+; CHECK-ARM-LE-NEXT: strb r1, [r0, r2]
+; CHECK-ARM-LE-NEXT: bx lr
+;
+; CHECK-ARM-BE-LABEL: test_atomic_store_monotonic_regoff_i8:
+; CHECK-ARM-BE: @ %bb.0:
+; CHECK-ARM-BE-NEXT: ldrb r0, [sp, #3]
+; CHECK-ARM-BE-NEXT: strb r0, [r1, r3]
+; CHECK-ARM-BE-NEXT: bx lr
+;
+; CHECK-THUMB-LE-LABEL: test_atomic_store_monotonic_regoff_i8:
+; CHECK-THUMB-LE: @ %bb.0:
+; CHECK-THUMB-LE-NEXT: ldrb.w r1, [sp]
+; CHECK-THUMB-LE-NEXT: strb r1, [r0, r2]
+; CHECK-THUMB-LE-NEXT: bx lr
+;
+; CHECK-THUMB-BE-LABEL: test_atomic_store_monotonic_regoff_i8:
+; CHECK-THUMB-BE: @ %bb.0:
+; CHECK-THUMB-BE-NEXT: ldrb.w r0, [sp, #3]
+; CHECK-THUMB-BE-NEXT: strb r0, [r1, r3]
+; CHECK-THUMB-BE-NEXT: bx lr
%addr_int = add i64 %base, %off
%addr = inttoptr i64 %addr_int to ptr
store atomic i8 %val, ptr %addr monotonic, align 1
-; CHECK-LE: ldr{{b?(\.w)?}} [[VAL:r[0-9]+]], [sp]
-; CHECK-LE: strb [[VAL]], [r0, r2]
-; CHECK-BE: ldrb{{(\.w)?}} [[VAL:r[0-9]+]], [sp, #3]
-; CHECK-BE: strb [[VAL]], [r1, r3]
ret void
}
define void @test_atomic_store_release_i8(i8 %val) nounwind {
; CHECK-LABEL: test_atomic_store_release_i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r1, :lower16:var8
+; CHECK-NEXT: movt r1, :upper16:var8
+; CHECK-NEXT: stlb r0, [r1]
+; CHECK-NEXT: bx lr
store atomic i8 %val, ptr @var8 release, align 1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movt r[[ADDR]], :upper16:var8
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: stlb r0, [r[[ADDR]]]
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
ret void
}
define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
; CHECK-LABEL: test_atomic_store_seq_cst_i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r1, :lower16:var8
+; CHECK-NEXT: movt r1, :upper16:var8
+; CHECK-NEXT: stlb r0, [r1]
+; CHECK-NEXT: bx lr
store atomic i8 %val, ptr @var8 seq_cst, align 1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movt r[[ADDR]], :upper16:var8
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: stlb r0, [r[[ADDR]]]
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
ret void
}
define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
; CHECK-LABEL: test_atomic_store_monotonic_i16:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: movw r1, :lower16:var16
+; CHECK-NEXT: movt r1, :upper16:var16
+; CHECK-NEXT: strh r0, [r1]
+; CHECK-NEXT: bx lr
store atomic i16 %val, ptr @var16 monotonic, align 2
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movt r[[ADDR]], :upper16:var16
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: strh r0, [r[[ADDR]]]
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
ret void
}
define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind {
-; CHECK-LABEL: test_atomic_store_monotonic_regoff_i32:
+; CHECK-LE-LABEL: test_atomic_store_monotonic_regoff_i32:
+; CHECK-LE: @ %bb.0:
+; CHECK-LE-NEXT: ldr r1, [sp]
+; CHECK-LE-NEXT: str r1, [r0, r2]
+; CHECK-LE-NEXT: bx lr
+;
+; CHECK-BE-LABEL: test_atomic_store_monotonic_regoff_i32:
+; CHECK-BE: @ %bb.0:
+; CHECK-BE-NEXT: ldr r0, [sp]
+; CHECK-BE-NEXT: str r0, [r1, r3]
+; CHECK-BE-NEXT: bx lr
%addr_int = add i64 %base, %off
%addr = inttoptr i64 %addr_int to ptr
store atomic i32 %val, ptr %addr monotonic, align 4
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: ldr [[VAL:r[0-9]+]], [sp]
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK-LE: str [[VAL]], [r0, r2]
-; CHECK-BE: str [[VAL]], [r1, r3]
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
ret void
}
define void @test_atomic_store_release_i64(i64 %val) nounwind {
-; CHECK-LABEL: test_atomic_store_release_i64:
+; CHECK-ARM-LABEL: test_atomic_store_release_i64:
+; CHECK-ARM: @ %bb.0:
+; CHECK-ARM-NEXT: push {r4, r5, r11, lr}
+; CHECK-ARM-NEXT: movw r2, :lower16:var64
+; CHECK-ARM-NEXT: @ kill: def $r1 killed $r1 killed $r0_r1 def $r0_r1
+; CHECK-ARM-NEXT: movt r2, :upper16:var64
+; CHECK-ARM-NEXT: @ kill: def $r0 killed $r0 killed $r0_r1 def $r0_r1
+; CHECK-ARM-NEXT: .LBB57_1: @ %atomicrmw.start
+; CHECK-ARM-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-ARM-NEXT: ldrexd r4, r5, [r2]
+; CHECK-ARM-NEXT: stlexd r3, r0, r1, [r2]
+; CHECK-ARM-NEXT: cmp r3, #0
+; CHECK-ARM-NEXT: bne .LBB57_1
+; CHECK-ARM-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-ARM-NEXT: pop {r4, r5, r11, pc}
+;
+; CHECK-THUMB-LABEL: test_atomic_store_release_i64:
+; CHECK-THUMB: @ %bb.0:
+; CHECK-THUMB-NEXT: movw r12, :lower16:var64
+; CHECK-THUMB-NEXT: movt r12, :upper16:var64
+; CHECK-THUMB-NEXT: .LBB57_1: @ %atomicrmw.start
+; CHECK-THUMB-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-THUMB-NEXT: ldrexd r3, r2, [r12]
+; CHECK-THUMB-NEXT: stlexd r2, r0, r1, [r12]
+; CHECK-THUMB-NEXT: cmp r2, #0
+; CHECK-THUMB-NEXT: bne .LBB57_1
+; CHECK-THUMB-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-THUMB-NEXT: bx lr
store atomic i64 %val, ptr @var64 release, align 8
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
-; CHECK: movw [[ADDR:r[0-9]+|lr]], :lower16:var64
-; CHECK: movt [[ADDR]], :upper16:var64
-; CHECK: .LBB{{[0-9]+}}_1:
; r0, r1 below is a reasonable guess but could change: it certainly comes into the
; function there.
-; CHECK: stlexd [[STATUS:r[0-9]+]], r0, r1, {{.*}}[[ADDR]]
-; CHECK-NEXT: cmp [[STATUS]], #0
-; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
-; CHECK-NOT: dmb
-; CHECK-NOT: mcr
ret void
}
define i32 @not.barriers(ptr %var, i1 %cond) {
-; CHECK-LABEL: not.barriers:
br i1 %cond, label %atomic_ver, label %simple_ver
simple_ver:
%oldval = load i32, ptr %var
@@ -1401,13 +2394,9 @@ atomic_ver:
%val = atomicrmw add ptr %var, i32 -1 monotonic
fence seq_cst
br label %somewhere
-; CHECK: dmb
-; CHECK: ldrex
-; CHECK: dmb
; The key point here is that the second dmb isn't immediately followed by the
; simple_ver basic block, which LLVM attempted to do when DMB had been marked
; with isBarrier. For now, look for something that looks like "somewhere".
-; CHECK-NEXT: {{mov|bx}}
somewhere:
%combined = phi i32 [ %val, %atomic_ver ], [ %newval, %simple_ver]
ret i32 %combined
diff --git a/llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll b/llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
index c3219c8fabbf3..4f27f93a4b571 100644
--- a/llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
+++ b/llvm/test/CodeGen/ARM/atomicrmw_exclusive_monitor_ints.ll
@@ -1424,7 +1424,7 @@ define i8 @test_max_i8() {
; CHECK-ARM8-NEXT: sxtb r0, r1
; CHECK-ARM8-NEXT: cmp r0, #1
; CHECK-ARM8-NEXT: mov r12, #1
-; CHECK-ARM8-NEXT: movgt r12, r1
+; CHECK-ARM8-NEXT: movgt r12, r0
; CHECK-ARM8-NEXT: movw r3, :lower16:atomic_i8
; CHECK-ARM8-NEXT: movt r3, :upper16:atomic_i8
; CHECK-ARM8-NEXT: uxtb r1, r1
@@ -1470,7 +1470,7 @@ define i8 @test_max_i8() {
; CHECK-ARM6-NEXT: sxtb r0, r1
; CHECK-ARM6-NEXT: cmp r0, #1
; CHECK-ARM6-NEXT: mov r12, #1
-; CHECK-ARM6-NEXT: movgt r12, r1
+; CHECK-ARM6-NEXT: movgt r12, r0
; CHECK-ARM6-NEXT: ldr r3, .LCPI7_0
; CHECK-ARM6-NEXT: uxtb r1, r1
; CHECK-ARM6-NEXT: .LBB7_2: @ %atomicrmw.start
@@ -1521,7 +1521,7 @@ define i8 @test_max_i8() {
; CHECK-THUMB7-NEXT: cmp r0, #1
; CHECK-THUMB7-NEXT: mov.w r12, #1
; CHECK-THUMB7-NEXT: it gt
-; CHECK-THUMB7-NEXT: movgt r12, r1
+; CHECK-THUMB7-NEXT: movgt r12, r0
; CHECK-THUMB7-NEXT: movw r3, :lower16:atomic_i8
; CHECK-THUMB7-NEXT: movt r3, :upper16:atomic_i8
; CHECK-THUMB7-NEXT: uxtb r1, r1
@@ -1581,10 +1581,10 @@ define i8 @test_max_i8() {
; CHECK-THUMB8BASE-NEXT: @ Child Loop BB7_4 Depth 2
; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #4] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: sxtb r1, r0
-; CHECK-THUMB8BASE-NEXT: movs r2, #1
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #8] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: cmp r1, #1
+; CHECK-THUMB8BASE-NEXT: sxtb r0, r0
+; CHECK-THUMB8BASE-NEXT: movs r1, #1
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #8] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: cmp r0, #1
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: bgt .LBB7_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
@@ -1643,9 +1643,9 @@ define i8 @test_min_i8() {
; CHECK-ARM8-NEXT: @ Child Loop BB8_2 Depth 2
; CHECK-ARM8-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; CHECK-ARM8-NEXT: sxtb r0, r1
-; CHECK-ARM8-NEXT: cmp r0, #2
+; CHECK-ARM8-NEXT: cmp r0, #1
; CHECK-ARM8-NEXT: mov r12, #1
-; CHECK-ARM8-NEXT: movlt r12, r1
+; CHECK-ARM8-NEXT: movlt r12, r0
; CHECK-ARM8-NEXT: movw r3, :lower16:atomic_i8
; CHECK-ARM8-NEXT: movt r3, :upper16:atomic_i8
; CHECK-ARM8-NEXT: uxtb r1, r1
@@ -1689,9 +1689,9 @@ define i8 @test_min_i8() {
; CHECK-ARM6-NEXT: @ Child Loop BB8_2 Depth 2
; CHECK-ARM6-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; CHECK-ARM6-NEXT: sxtb r0, r1
-; CHECK-ARM6-NEXT: cmp r0, #2
+; CHECK-ARM6-NEXT: cmp r0, #1
; CHECK-ARM6-NEXT: mov r12, #1
-; CHECK-ARM6-NEXT: movlt r12, r1
+; CHECK-ARM6-NEXT: movlt r12, r0
; CHECK-ARM6-NEXT: ldr r3, .LCPI8_0
; CHECK-ARM6-NEXT: uxtb r1, r1
; CHECK-ARM6-NEXT: .LBB8_2: @ %atomicrmw.start
@@ -1739,10 +1739,10 @@ define i8 @test_min_i8() {
; CHECK-THUMB7-NEXT: @ Child Loop BB8_2 Depth 2
; CHECK-THUMB7-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; CHECK-THUMB7-NEXT: sxtb r0, r1
-; CHECK-THUMB7-NEXT: cmp r0, #2
+; CHECK-THUMB7-NEXT: cmp r0, #1
; CHECK-THUMB7-NEXT: mov.w r12, #1
; CHECK-THUMB7-NEXT: it lt
-; CHECK-THUMB7-NEXT: movlt r12, r1
+; CHECK-THUMB7-NEXT: movlt r12, r0
; CHECK-THUMB7-NEXT: movw r3, :lower16:atomic_i8
; CHECK-THUMB7-NEXT: movt r3, :upper16:atomic_i8
; CHECK-THUMB7-NEXT: uxtb r1, r1
@@ -1802,10 +1802,10 @@ define i8 @test_min_i8() {
; CHECK-THUMB8BASE-NEXT: @ Child Loop BB8_4 Depth 2
; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #4] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: sxtb r1, r0
-; CHECK-THUMB8BASE-NEXT: movs r2, #1
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #8] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: cmp r1, #2
+; CHECK-THUMB8BASE-NEXT: sxtb r0, r0
+; CHECK-THUMB8BASE-NEXT: movs r1, #1
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #8] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: cmp r0, #1
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: blt .LBB8_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
@@ -1868,7 +1868,7 @@ define i8 @test_umax_i8() {
; CHECK-ARM8-NEXT: uxtb r1, r12
; CHECK-ARM8-NEXT: cmp r1, #1
; CHECK-ARM8-NEXT: mov lr, #1
-; CHECK-ARM8-NEXT: movhi lr, r12
+; CHECK-ARM8-NEXT: movhi lr, r1
; CHECK-ARM8-NEXT: movw r3, :lower16:atomic_i8
; CHECK-ARM8-NEXT: movt r3, :upper16:atomic_i8
; CHECK-ARM8-NEXT: uxtb r12, r12
@@ -1915,7 +1915,7 @@ define i8 @test_umax_i8() {
; CHECK-ARM6-NEXT: uxtb r1, r12
; CHECK-ARM6-NEXT: cmp r1, #1
; CHECK-ARM6-NEXT: mov lr, #1
-; CHECK-ARM6-NEXT: movhi lr, r12
+; CHECK-ARM6-NEXT: movhi lr, r1
; CHECK-ARM6-NEXT: ldr r3, .LCPI9_0
; CHECK-ARM6-NEXT: uxtb r12, r12
; CHECK-ARM6-NEXT: .LBB9_2: @ %atomicrmw.start
@@ -1967,7 +1967,7 @@ define i8 @test_umax_i8() {
; CHECK-THUMB7-NEXT: cmp r1, #1
; CHECK-THUMB7-NEXT: mov.w r12, #1
; CHECK-THUMB7-NEXT: it hi
-; CHECK-THUMB7-NEXT: movhi r12, r4
+; CHECK-THUMB7-NEXT: movhi r12, r1
; CHECK-THUMB7-NEXT: movw r3, :lower16:atomic_i8
; CHECK-THUMB7-NEXT: movt r3, :upper16:atomic_i8
; CHECK-THUMB7-NEXT: uxtb r4, r4
@@ -2026,11 +2026,11 @@ define i8 @test_umax_i8() {
; CHECK-THUMB8BASE-NEXT: @ Child Loop BB9_4 Depth 2
; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #4] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: uxtb r1, r0
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #8] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: movs r2, #1
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #12] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: cmp r1, #1
+; CHECK-THUMB8BASE-NEXT: uxtb r0, r0
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #8] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: movs r1, #1
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #12] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: cmp r0, #1
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #16] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: bhi .LBB9_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
@@ -2091,9 +2091,9 @@ define i8 @test_umin_i8() {
; CHECK-ARM8-NEXT: @ Child Loop BB10_2 Depth 2
; CHECK-ARM8-NEXT: ldr r12, [sp, #4] @ 4-byte Reload
; CHECK-ARM8-NEXT: uxtb r1, r12
-; CHECK-ARM8-NEXT: cmp r1, #2
+; CHECK-ARM8-NEXT: cmp r1, #1
; CHECK-ARM8-NEXT: mov lr, #1
-; CHECK-ARM8-NEXT: movlo lr, r12
+; CHECK-ARM8-NEXT: movlo lr, r1
; CHECK-ARM8-NEXT: movw r3, :lower16:atomic_i8
; CHECK-ARM8-NEXT: movt r3, :upper16:atomic_i8
; CHECK-ARM8-NEXT: uxtb r12, r12
@@ -2138,9 +2138,9 @@ define i8 @test_umin_i8() {
; CHECK-ARM6-NEXT: @ Child Loop BB10_2 Depth 2
; CHECK-ARM6-NEXT: ldr r12, [sp, #4] @ 4-byte Reload
; CHECK-ARM6-NEXT: uxtb r1, r12
-; CHECK-ARM6-NEXT: cmp r1, #2
+; CHECK-ARM6-NEXT: cmp r1, #1
; CHECK-ARM6-NEXT: mov lr, #1
-; CHECK-ARM6-NEXT: movlo lr, r12
+; CHECK-ARM6-NEXT: movlo lr, r1
; CHECK-ARM6-NEXT: ldr r3, .LCPI10_0
; CHECK-ARM6-NEXT: uxtb r12, r12
; CHECK-ARM6-NEXT: .LBB10_2: @ %atomicrmw.start
@@ -2189,10 +2189,10 @@ define i8 @test_umin_i8() {
; CHECK-THUMB7-NEXT: @ Child Loop BB10_2 Depth 2
; CHECK-THUMB7-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
; CHECK-THUMB7-NEXT: uxtb r1, r4
-; CHECK-THUMB7-NEXT: cmp r1, #2
+; CHECK-THUMB7-NEXT: cmp r1, #1
; CHECK-THUMB7-NEXT: mov.w r12, #1
; CHECK-THUMB7-NEXT: it lo
-; CHECK-THUMB7-NEXT: movlo r12, r4
+; CHECK-THUMB7-NEXT: movlo r12, r1
; CHECK-THUMB7-NEXT: movw r3, :lower16:atomic_i8
; CHECK-THUMB7-NEXT: movt r3, :upper16:atomic_i8
; CHECK-THUMB7-NEXT: uxtb r4, r4
@@ -2251,11 +2251,11 @@ define i8 @test_umin_i8() {
; CHECK-THUMB8BASE-NEXT: @ Child Loop BB10_4 Depth 2
; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #4] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: uxtb r1, r0
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #8] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: movs r2, #1
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #12] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: cmp r1, #2
+; CHECK-THUMB8BASE-NEXT: uxtb r0, r0
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #8] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: movs r1, #1
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #12] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: cmp r0, #1
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #16] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: blo .LBB10_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
@@ -3711,7 +3711,7 @@ define i16 @test_max_i16() {
; CHECK-ARM8-NEXT: sxth r0, r1
; CHECK-ARM8-NEXT: cmp r0, #1
; CHECK-ARM8-NEXT: mov r12, #1
-; CHECK-ARM8-NEXT: movgt r12, r1
+; CHECK-ARM8-NEXT: movgt r12, r0
; CHECK-ARM8-NEXT: movw r3, :lower16:atomic_i16
; CHECK-ARM8-NEXT: movt r3, :upper16:atomic_i16
; CHECK-ARM8-NEXT: uxth r1, r1
@@ -3757,7 +3757,7 @@ define i16 @test_max_i16() {
; CHECK-ARM6-NEXT: sxth r0, r1
; CHECK-ARM6-NEXT: cmp r0, #1
; CHECK-ARM6-NEXT: mov r12, #1
-; CHECK-ARM6-NEXT: movgt r12, r1
+; CHECK-ARM6-NEXT: movgt r12, r0
; CHECK-ARM6-NEXT: ldr r3, .LCPI18_0
; CHECK-ARM6-NEXT: uxth r1, r1
; CHECK-ARM6-NEXT: .LBB18_2: @ %atomicrmw.start
@@ -3808,7 +3808,7 @@ define i16 @test_max_i16() {
; CHECK-THUMB7-NEXT: cmp r0, #1
; CHECK-THUMB7-NEXT: mov.w r12, #1
; CHECK-THUMB7-NEXT: it gt
-; CHECK-THUMB7-NEXT: movgt r12, r1
+; CHECK-THUMB7-NEXT: movgt r12, r0
; CHECK-THUMB7-NEXT: movw r3, :lower16:atomic_i16
; CHECK-THUMB7-NEXT: movt r3, :upper16:atomic_i16
; CHECK-THUMB7-NEXT: uxth r1, r1
@@ -3868,10 +3868,10 @@ define i16 @test_max_i16() {
; CHECK-THUMB8BASE-NEXT: @ Child Loop BB18_4 Depth 2
; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #4] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: sxth r1, r0
-; CHECK-THUMB8BASE-NEXT: movs r2, #1
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #8] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: cmp r1, #1
+; CHECK-THUMB8BASE-NEXT: sxth r0, r0
+; CHECK-THUMB8BASE-NEXT: movs r1, #1
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #8] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: cmp r0, #1
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: bgt .LBB18_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
@@ -3930,9 +3930,9 @@ define i16 @test_min_i16() {
; CHECK-ARM8-NEXT: @ Child Loop BB19_2 Depth 2
; CHECK-ARM8-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; CHECK-ARM8-NEXT: sxth r0, r1
-; CHECK-ARM8-NEXT: cmp r0, #2
+; CHECK-ARM8-NEXT: cmp r0, #1
; CHECK-ARM8-NEXT: mov r12, #1
-; CHECK-ARM8-NEXT: movlt r12, r1
+; CHECK-ARM8-NEXT: movlt r12, r0
; CHECK-ARM8-NEXT: movw r3, :lower16:atomic_i16
; CHECK-ARM8-NEXT: movt r3, :upper16:atomic_i16
; CHECK-ARM8-NEXT: uxth r1, r1
@@ -3976,9 +3976,9 @@ define i16 @test_min_i16() {
; CHECK-ARM6-NEXT: @ Child Loop BB19_2 Depth 2
; CHECK-ARM6-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; CHECK-ARM6-NEXT: sxth r0, r1
-; CHECK-ARM6-NEXT: cmp r0, #2
+; CHECK-ARM6-NEXT: cmp r0, #1
; CHECK-ARM6-NEXT: mov r12, #1
-; CHECK-ARM6-NEXT: movlt r12, r1
+; CHECK-ARM6-NEXT: movlt r12, r0
; CHECK-ARM6-NEXT: ldr r3, .LCPI19_0
; CHECK-ARM6-NEXT: uxth r1, r1
; CHECK-ARM6-NEXT: .LBB19_2: @ %atomicrmw.start
@@ -4026,10 +4026,10 @@ define i16 @test_min_i16() {
; CHECK-THUMB7-NEXT: @ Child Loop BB19_2 Depth 2
; CHECK-THUMB7-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; CHECK-THUMB7-NEXT: sxth r0, r1
-; CHECK-THUMB7-NEXT: cmp r0, #2
+; CHECK-THUMB7-NEXT: cmp r0, #1
; CHECK-THUMB7-NEXT: mov.w r12, #1
; CHECK-THUMB7-NEXT: it lt
-; CHECK-THUMB7-NEXT: movlt r12, r1
+; CHECK-THUMB7-NEXT: movlt r12, r0
; CHECK-THUMB7-NEXT: movw r3, :lower16:atomic_i16
; CHECK-THUMB7-NEXT: movt r3, :upper16:atomic_i16
; CHECK-THUMB7-NEXT: uxth r1, r1
@@ -4089,10 +4089,10 @@ define i16 @test_min_i16() {
; CHECK-THUMB8BASE-NEXT: @ Child Loop BB19_4 Depth 2
; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #4] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: sxth r1, r0
-; CHECK-THUMB8BASE-NEXT: movs r2, #1
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #8] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: cmp r1, #2
+; CHECK-THUMB8BASE-NEXT: sxth r0, r0
+; CHECK-THUMB8BASE-NEXT: movs r1, #1
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #8] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: cmp r0, #1
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: blt .LBB19_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
@@ -4155,7 +4155,7 @@ define i16 @test_umax_i16() {
; CHECK-ARM8-NEXT: uxth r1, r12
; CHECK-ARM8-NEXT: cmp r1, #1
; CHECK-ARM8-NEXT: mov lr, #1
-; CHECK-ARM8-NEXT: movhi lr, r12
+; CHECK-ARM8-NEXT: movhi lr, r1
; CHECK-ARM8-NEXT: movw r3, :lower16:atomic_i16
; CHECK-ARM8-NEXT: movt r3, :upper16:atomic_i16
; CHECK-ARM8-NEXT: uxth r12, r12
@@ -4202,7 +4202,7 @@ define i16 @test_umax_i16() {
; CHECK-ARM6-NEXT: uxth r1, r12
; CHECK-ARM6-NEXT: cmp r1, #1
; CHECK-ARM6-NEXT: mov lr, #1
-; CHECK-ARM6-NEXT: movhi lr, r12
+; CHECK-ARM6-NEXT: movhi lr, r1
; CHECK-ARM6-NEXT: ldr r3, .LCPI20_0
; CHECK-ARM6-NEXT: uxth r12, r12
; CHECK-ARM6-NEXT: .LBB20_2: @ %atomicrmw.start
@@ -4254,7 +4254,7 @@ define i16 @test_umax_i16() {
; CHECK-THUMB7-NEXT: cmp r1, #1
; CHECK-THUMB7-NEXT: mov.w r12, #1
; CHECK-THUMB7-NEXT: it hi
-; CHECK-THUMB7-NEXT: movhi r12, r4
+; CHECK-THUMB7-NEXT: movhi r12, r1
; CHECK-THUMB7-NEXT: movw r3, :lower16:atomic_i16
; CHECK-THUMB7-NEXT: movt r3, :upper16:atomic_i16
; CHECK-THUMB7-NEXT: uxth r4, r4
@@ -4313,11 +4313,11 @@ define i16 @test_umax_i16() {
; CHECK-THUMB8BASE-NEXT: @ Child Loop BB20_4 Depth 2
; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #4] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: uxth r1, r0
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #8] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: movs r2, #1
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #12] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: cmp r1, #1
+; CHECK-THUMB8BASE-NEXT: uxth r0, r0
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #8] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: movs r1, #1
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #12] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: cmp r0, #1
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #16] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: bhi .LBB20_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
@@ -4378,9 +4378,9 @@ define i16 @test_umin_i16() {
; CHECK-ARM8-NEXT: @ Child Loop BB21_2 Depth 2
; CHECK-ARM8-NEXT: ldr r12, [sp, #4] @ 4-byte Reload
; CHECK-ARM8-NEXT: uxth r1, r12
-; CHECK-ARM8-NEXT: cmp r1, #2
+; CHECK-ARM8-NEXT: cmp r1, #1
; CHECK-ARM8-NEXT: mov lr, #1
-; CHECK-ARM8-NEXT: movlo lr, r12
+; CHECK-ARM8-NEXT: movlo lr, r1
; CHECK-ARM8-NEXT: movw r3, :lower16:atomic_i16
; CHECK-ARM8-NEXT: movt r3, :upper16:atomic_i16
; CHECK-ARM8-NEXT: uxth r12, r12
@@ -4425,9 +4425,9 @@ define i16 @test_umin_i16() {
; CHECK-ARM6-NEXT: @ Child Loop BB21_2 Depth 2
; CHECK-ARM6-NEXT: ldr r12, [sp, #4] @ 4-byte Reload
; CHECK-ARM6-NEXT: uxth r1, r12
-; CHECK-ARM6-NEXT: cmp r1, #2
+; CHECK-ARM6-NEXT: cmp r1, #1
; CHECK-ARM6-NEXT: mov lr, #1
-; CHECK-ARM6-NEXT: movlo lr, r12
+; CHECK-ARM6-NEXT: movlo lr, r1
; CHECK-ARM6-NEXT: ldr r3, .LCPI21_0
; CHECK-ARM6-NEXT: uxth r12, r12
; CHECK-ARM6-NEXT: .LBB21_2: @ %atomicrmw.start
@@ -4476,10 +4476,10 @@ define i16 @test_umin_i16() {
; CHECK-THUMB7-NEXT: @ Child Loop BB21_2 Depth 2
; CHECK-THUMB7-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
; CHECK-THUMB7-NEXT: uxth r1, r4
-; CHECK-THUMB7-NEXT: cmp r1, #2
+; CHECK-THUMB7-NEXT: cmp r1, #1
; CHECK-THUMB7-NEXT: mov.w r12, #1
; CHECK-THUMB7-NEXT: it lo
-; CHECK-THUMB7-NEXT: movlo r12, r4
+; CHECK-THUMB7-NEXT: movlo r12, r1
; CHECK-THUMB7-NEXT: movw r3, :lower16:atomic_i16
; CHECK-THUMB7-NEXT: movt r3, :upper16:atomic_i16
; CHECK-THUMB7-NEXT: uxth r4, r4
@@ -4538,11 +4538,11 @@ define i16 @test_umin_i16() {
; CHECK-THUMB8BASE-NEXT: @ Child Loop BB21_4 Depth 2
; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #4] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: uxth r1, r0
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #8] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: movs r2, #1
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #12] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: cmp r1, #2
+; CHECK-THUMB8BASE-NEXT: uxth r0, r0
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #8] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: movs r1, #1
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #12] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: cmp r0, #1
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #16] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: blo .LBB21_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
@@ -6148,7 +6148,7 @@ define i32 @test_min_i32() {
; CHECK-ARM8-NEXT: @ =>This Loop Header: Depth=1
; CHECK-ARM8-NEXT: @ Child Loop BB30_2 Depth 2
; CHECK-ARM8-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
-; CHECK-ARM8-NEXT: cmp r1, #2
+; CHECK-ARM8-NEXT: cmp r1, #1
; CHECK-ARM8-NEXT: mov r12, #1
; CHECK-ARM8-NEXT: movlt r12, r1
; CHECK-ARM8-NEXT: movw r3, :lower16:atomic_i32
@@ -6191,7 +6191,7 @@ define i32 @test_min_i32() {
; CHECK-ARM6-NEXT: @ =>This Loop Header: Depth=1
; CHECK-ARM6-NEXT: @ Child Loop BB30_2 Depth 2
; CHECK-ARM6-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
-; CHECK-ARM6-NEXT: cmp r1, #2
+; CHECK-ARM6-NEXT: cmp r1, #1
; CHECK-ARM6-NEXT: mov r12, #1
; CHECK-ARM6-NEXT: movlt r12, r1
; CHECK-ARM6-NEXT: ldr r3, .LCPI30_0
@@ -6238,7 +6238,7 @@ define i32 @test_min_i32() {
; CHECK-THUMB7-NEXT: @ =>This Loop Header: Depth=1
; CHECK-THUMB7-NEXT: @ Child Loop BB30_2 Depth 2
; CHECK-THUMB7-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
-; CHECK-THUMB7-NEXT: cmp r1, #2
+; CHECK-THUMB7-NEXT: cmp r1, #1
; CHECK-THUMB7-NEXT: mov.w r12, #1
; CHECK-THUMB7-NEXT: it lt
; CHECK-THUMB7-NEXT: movlt r12, r1
@@ -6301,7 +6301,7 @@ define i32 @test_min_i32() {
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #4] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: movs r1, #1
; CHECK-THUMB8BASE-NEXT: str r1, [sp, #8] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: cmp r0, #2
+; CHECK-THUMB8BASE-NEXT: cmp r0, #1
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: blt .LBB30_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
@@ -6566,7 +6566,7 @@ define i32 @test_umin_i32() {
; CHECK-ARM8-NEXT: @ =>This Loop Header: Depth=1
; CHECK-ARM8-NEXT: @ Child Loop BB32_2 Depth 2
; CHECK-ARM8-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
-; CHECK-ARM8-NEXT: cmp r1, #2
+; CHECK-ARM8-NEXT: cmp r1, #1
; CHECK-ARM8-NEXT: mov r12, #1
; CHECK-ARM8-NEXT: movlo r12, r1
; CHECK-ARM8-NEXT: movw r3, :lower16:atomic_i32
@@ -6609,7 +6609,7 @@ define i32 @test_umin_i32() {
; CHECK-ARM6-NEXT: @ =>This Loop Header: Depth=1
; CHECK-ARM6-NEXT: @ Child Loop BB32_2 Depth 2
; CHECK-ARM6-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
-; CHECK-ARM6-NEXT: cmp r1, #2
+; CHECK-ARM6-NEXT: cmp r1, #1
; CHECK-ARM6-NEXT: mov r12, #1
; CHECK-ARM6-NEXT: movlo r12, r1
; CHECK-ARM6-NEXT: ldr r3, .LCPI32_0
@@ -6656,7 +6656,7 @@ define i32 @test_umin_i32() {
; CHECK-THUMB7-NEXT: @ =>This Loop Header: Depth=1
; CHECK-THUMB7-NEXT: @ Child Loop BB32_2 Depth 2
; CHECK-THUMB7-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
-; CHECK-THUMB7-NEXT: cmp r1, #2
+; CHECK-THUMB7-NEXT: cmp r1, #1
; CHECK-THUMB7-NEXT: mov.w r12, #1
; CHECK-THUMB7-NEXT: it lo
; CHECK-THUMB7-NEXT: movlo r12, r1
@@ -6719,7 +6719,7 @@ define i32 @test_umin_i32() {
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #4] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: movs r1, #1
; CHECK-THUMB8BASE-NEXT: str r1, [sp, #8] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: cmp r0, #2
+; CHECK-THUMB8BASE-NEXT: cmp r0, #1
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #12] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: blo .LBB32_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
@@ -8362,10 +8362,10 @@ define i64 @test_max_i64() {
; CHECK-ARM8-NEXT: mov r9, r1
; CHECK-ARM8-NEXT: rsbs r0, r2, #1
; CHECK-ARM8-NEXT: rscs r0, r1, #0
-; CHECK-ARM8-NEXT: mov r0, #0
-; CHECK-ARM8-NEXT: movwlt r0, #1
; CHECK-ARM8-NEXT: mov r10, #1
; CHECK-ARM8-NEXT: movlt r10, r2
+; CHECK-ARM8-NEXT: mov r0, #0
+; CHECK-ARM8-NEXT: movwlt r0, #1
; CHECK-ARM8-NEXT: cmp r0, #0
; CHECK-ARM8-NEXT: movne r0, r1
; CHECK-ARM8-NEXT: @ kill: def $r10 killed $r10 def $r10_r11
@@ -8430,10 +8430,10 @@ define i64 @test_max_i64() {
; CHECK-ARM6-NEXT: mov r9, r1
; CHECK-ARM6-NEXT: rsbs r0, r2, #1
; CHECK-ARM6-NEXT: rscs r0, r1, #0
-; CHECK-ARM6-NEXT: mov r0, #0
-; CHECK-ARM6-NEXT: movlt r0, #1
; CHECK-ARM6-NEXT: mov r10, #1
; CHECK-ARM6-NEXT: movlt r10, r2
+; CHECK-ARM6-NEXT: mov r0, #0
+; CHECK-ARM6-NEXT: movlt r0, #1
; CHECK-ARM6-NEXT: cmp r0, #0
; CHECK-ARM6-NEXT: movne r0, r1
; CHECK-ARM6-NEXT: @ kill: def $r10 killed $r10 def $r10_r11
@@ -8497,16 +8497,15 @@ define i64 @test_max_i64() {
; CHECK-THUMB7-NEXT: @ Child Loop BB40_2 Depth 2
; CHECK-THUMB7-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
; CHECK-THUMB7-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
+; CHECK-THUMB7-NEXT: mov r8, r2
+; CHECK-THUMB7-NEXT: mov r9, r1
; CHECK-THUMB7-NEXT: rsbs.w r0, r2, #1
; CHECK-THUMB7-NEXT: mov.w r0, #0
; CHECK-THUMB7-NEXT: sbcs.w r3, r0, r1
-; CHECK-THUMB7-NEXT: it lt
-; CHECK-THUMB7-NEXT: movlt r0, #1
-; CHECK-THUMB7-NEXT: mov r8, r2
-; CHECK-THUMB7-NEXT: mov r9, r1
; CHECK-THUMB7-NEXT: mov.w r10, #1
-; CHECK-THUMB7-NEXT: it lt
+; CHECK-THUMB7-NEXT: itt lt
; CHECK-THUMB7-NEXT: movlt r10, r2
+; CHECK-THUMB7-NEXT: movlt r0, #1
; CHECK-THUMB7-NEXT: cmp r0, #0
; CHECK-THUMB7-NEXT: it ne
; CHECK-THUMB7-NEXT: movne r0, r1
@@ -8580,48 +8579,47 @@ define i64 @test_max_i64() {
; CHECK-THUMB8BASE-NEXT: b .LBB40_1
; CHECK-THUMB8BASE-NEXT: .LBB40_1: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r3, [sp, #56] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #56] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r2, [sp, #60] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r2, [sp, #36] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: str r3, [sp, #40] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #40] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: movs r1, #0
; CHECK-THUMB8BASE-NEXT: str r1, [sp, #44] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: movs r0, #1
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #48] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: subs r3, r0, r3
+; CHECK-THUMB8BASE-NEXT: movs r3, #1
+; CHECK-THUMB8BASE-NEXT: str r3, [sp, #48] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: subs r3, r3, r0
; CHECK-THUMB8BASE-NEXT: sbcs r1, r2
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #52] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: blt .LBB40_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB40_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #48] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #52] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: .LBB40_3: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB40_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #40] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #48] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #52] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r1, [sp, #28] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #32] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: blt .LBB40_5
; CHECK-THUMB8BASE-NEXT: @ %bb.4: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB40_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #48] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #32] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: .LBB40_5: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB40_1 Depth=1
; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #36] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #28] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r2, [sp, #32] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #20] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #32] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #20] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #24] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: cbnz r1, .LBB40_7
; CHECK-THUMB8BASE-NEXT: @ %bb.6: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB40_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #28] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #24] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: .LBB40_7: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB40_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r2, [sp, #28] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #36] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r4, [sp, #40] @ 4-byte Reload
@@ -8676,12 +8674,12 @@ define i64 @test_min_i64() {
; CHECK-ARM8-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; CHECK-ARM8-NEXT: mov r8, r2
; CHECK-ARM8-NEXT: mov r9, r1
-; CHECK-ARM8-NEXT: subs r0, r2, #2
+; CHECK-ARM8-NEXT: subs r0, r2, #1
; CHECK-ARM8-NEXT: sbcs r0, r1, #0
-; CHECK-ARM8-NEXT: mov r0, #0
-; CHECK-ARM8-NEXT: movwlt r0, #1
; CHECK-ARM8-NEXT: mov r10, #1
; CHECK-ARM8-NEXT: movlt r10, r2
+; CHECK-ARM8-NEXT: mov r0, #0
+; CHECK-ARM8-NEXT: movwlt r0, #1
; CHECK-ARM8-NEXT: cmp r0, #0
; CHECK-ARM8-NEXT: movne r0, r1
; CHECK-ARM8-NEXT: @ kill: def $r10 killed $r10 def $r10_r11
@@ -8744,12 +8742,12 @@ define i64 @test_min_i64() {
; CHECK-ARM6-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; CHECK-ARM6-NEXT: mov r8, r2
; CHECK-ARM6-NEXT: mov r9, r1
-; CHECK-ARM6-NEXT: subs r0, r2, #2
+; CHECK-ARM6-NEXT: subs r0, r2, #1
; CHECK-ARM6-NEXT: sbcs r0, r1, #0
-; CHECK-ARM6-NEXT: mov r0, #0
-; CHECK-ARM6-NEXT: movlt r0, #1
; CHECK-ARM6-NEXT: mov r10, #1
; CHECK-ARM6-NEXT: movlt r10, r2
+; CHECK-ARM6-NEXT: mov r0, #0
+; CHECK-ARM6-NEXT: movlt r0, #1
; CHECK-ARM6-NEXT: cmp r0, #0
; CHECK-ARM6-NEXT: movne r0, r1
; CHECK-ARM6-NEXT: @ kill: def $r10 killed $r10 def $r10_r11
@@ -8815,14 +8813,14 @@ define i64 @test_min_i64() {
; CHECK-THUMB7-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; CHECK-THUMB7-NEXT: mov r8, r2
; CHECK-THUMB7-NEXT: mov r9, r1
-; CHECK-THUMB7-NEXT: subs r0, r2, #2
+; CHECK-THUMB7-NEXT: subs r0, r2, #1
; CHECK-THUMB7-NEXT: sbcs r0, r1, #0
-; CHECK-THUMB7-NEXT: mov.w r0, #0
-; CHECK-THUMB7-NEXT: it lt
-; CHECK-THUMB7-NEXT: movlt r0, #1
; CHECK-THUMB7-NEXT: mov.w r10, #1
; CHECK-THUMB7-NEXT: it lt
; CHECK-THUMB7-NEXT: movlt r10, r2
+; CHECK-THUMB7-NEXT: mov.w r0, #0
+; CHECK-THUMB7-NEXT: it lt
+; CHECK-THUMB7-NEXT: movlt r0, #1
; CHECK-THUMB7-NEXT: cmp r0, #0
; CHECK-THUMB7-NEXT: it ne
; CHECK-THUMB7-NEXT: movne r0, r1
@@ -8896,48 +8894,47 @@ define i64 @test_min_i64() {
; CHECK-THUMB8BASE-NEXT: b .LBB41_1
; CHECK-THUMB8BASE-NEXT: .LBB41_1: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r3, [sp, #56] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #56] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #60] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r1, [sp, #36] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: str r3, [sp, #40] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: movs r0, #1
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #44] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #40] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: movs r2, #1
+; CHECK-THUMB8BASE-NEXT: str r2, [sp, #44] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: movs r2, #0
; CHECK-THUMB8BASE-NEXT: str r2, [sp, #48] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: subs r3, r3, #2
+; CHECK-THUMB8BASE-NEXT: subs r3, r0, #1
; CHECK-THUMB8BASE-NEXT: sbcs r1, r2
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #52] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: blt .LBB41_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB41_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #48] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #52] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: .LBB41_3: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB41_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #40] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #52] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r1, [sp, #28] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #32] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: blt .LBB41_5
; CHECK-THUMB8BASE-NEXT: @ %bb.4: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB41_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #48] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #32] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: .LBB41_5: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB41_1 Depth=1
; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #36] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #28] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r2, [sp, #32] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #20] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #32] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #20] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #24] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: cbnz r1, .LBB41_7
; CHECK-THUMB8BASE-NEXT: @ %bb.6: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB41_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #28] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #24] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: .LBB41_7: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB41_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r2, [sp, #28] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #48] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #36] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r4, [sp, #40] @ 4-byte Reload
@@ -8992,16 +8989,15 @@ define i64 @test_umax_i64() {
; CHECK-ARM8-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; CHECK-ARM8-NEXT: mov r8, r2
; CHECK-ARM8-NEXT: mov r9, r1
-; CHECK-ARM8-NEXT: rsbs r0, r2, #1
-; CHECK-ARM8-NEXT: rscs r0, r1, #0
-; CHECK-ARM8-NEXT: mov r0, #0
-; CHECK-ARM8-NEXT: movwlo r0, #1
+; CHECK-ARM8-NEXT: cmp r2, #1
; CHECK-ARM8-NEXT: mov r10, #1
-; CHECK-ARM8-NEXT: movlo r10, r2
-; CHECK-ARM8-NEXT: cmp r0, #0
-; CHECK-ARM8-NEXT: movne r0, r1
+; CHECK-ARM8-NEXT: mov r0, r10
+; CHECK-ARM8-NEXT: movhi r0, r2
+; CHECK-ARM8-NEXT: cmp r1, #0
+; CHECK-ARM8-NEXT: movne r10, r2
+; CHECK-ARM8-NEXT: moveq r10, r0
; CHECK-ARM8-NEXT: @ kill: def $r10 killed $r10 def $r10_r11
-; CHECK-ARM8-NEXT: mov r11, r0
+; CHECK-ARM8-NEXT: mov r11, r1
; CHECK-ARM8-NEXT: movw r6, :lower16:atomic_i64
; CHECK-ARM8-NEXT: movt r6, :upper16:atomic_i64
; CHECK-ARM8-NEXT: @ implicit-def: $r0
@@ -9060,16 +9056,15 @@ define i64 @test_umax_i64() {
; CHECK-ARM6-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; CHECK-ARM6-NEXT: mov r8, r2
; CHECK-ARM6-NEXT: mov r9, r1
-; CHECK-ARM6-NEXT: rsbs r0, r2, #1
-; CHECK-ARM6-NEXT: rscs r0, r1, #0
-; CHECK-ARM6-NEXT: mov r0, #0
-; CHECK-ARM6-NEXT: movlo r0, #1
+; CHECK-ARM6-NEXT: cmp r2, #1
; CHECK-ARM6-NEXT: mov r10, #1
-; CHECK-ARM6-NEXT: movlo r10, r2
-; CHECK-ARM6-NEXT: cmp r0, #0
-; CHECK-ARM6-NEXT: movne r0, r1
+; CHECK-ARM6-NEXT: mov r0, r10
+; CHECK-ARM6-NEXT: movhi r0, r2
+; CHECK-ARM6-NEXT: cmp r1, #0
+; CHECK-ARM6-NEXT: movne r10, r2
+; CHECK-ARM6-NEXT: moveq r10, r0
; CHECK-ARM6-NEXT: @ kill: def $r10 killed $r10 def $r10_r11
-; CHECK-ARM6-NEXT: mov r11, r0
+; CHECK-ARM6-NEXT: mov r11, r1
; CHECK-ARM6-NEXT: ldr r6, .LCPI42_0
; CHECK-ARM6-NEXT: @ implicit-def: $r0
; CHECK-ARM6-NEXT: @ implicit-def: $r3
@@ -9129,21 +9124,19 @@ define i64 @test_umax_i64() {
; CHECK-THUMB7-NEXT: @ Child Loop BB42_2 Depth 2
; CHECK-THUMB7-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
; CHECK-THUMB7-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
-; CHECK-THUMB7-NEXT: rsbs.w r0, r2, #1
-; CHECK-THUMB7-NEXT: mov.w r0, #0
-; CHECK-THUMB7-NEXT: sbcs.w r3, r0, r1
-; CHECK-THUMB7-NEXT: it lo
-; CHECK-THUMB7-NEXT: movlo r0, #1
; CHECK-THUMB7-NEXT: mov r8, r2
; CHECK-THUMB7-NEXT: mov r9, r1
+; CHECK-THUMB7-NEXT: cmp r2, #1
; CHECK-THUMB7-NEXT: mov.w r10, #1
-; CHECK-THUMB7-NEXT: it lo
-; CHECK-THUMB7-NEXT: movlo r10, r2
-; CHECK-THUMB7-NEXT: cmp r0, #0
-; CHECK-THUMB7-NEXT: it ne
-; CHECK-THUMB7-NEXT: movne r0, r1
+; CHECK-THUMB7-NEXT: mov r0, r10
+; CHECK-THUMB7-NEXT: it hi
+; CHECK-THUMB7-NEXT: movhi r0, r2
+; CHECK-THUMB7-NEXT: cmp r1, #0
+; CHECK-THUMB7-NEXT: ite ne
+; CHECK-THUMB7-NEXT: movne r10, r2
+; CHECK-THUMB7-NEXT: moveq r10, r0
; CHECK-THUMB7-NEXT: @ kill: def $r10 killed $r10 def $r10_r11
-; CHECK-THUMB7-NEXT: mov r11, r0
+; CHECK-THUMB7-NEXT: mov r11, r1
; CHECK-THUMB7-NEXT: movw r6, :lower16:atomic_i64
; CHECK-THUMB7-NEXT: movt r6, :upper16:atomic_i64
; CHECK-THUMB7-NEXT: @ implicit-def: $r0
@@ -9199,88 +9192,85 @@ define i64 @test_umax_i64() {
;
; CHECK-THUMB8BASE-LABEL: test_umax_i64:
; CHECK-THUMB8BASE: @ %bb.0: @ %entry
-; CHECK-THUMB8BASE-NEXT: .save {r4, lr}
-; CHECK-THUMB8BASE-NEXT: push {r4, lr}
-; CHECK-THUMB8BASE-NEXT: .pad #72
-; CHECK-THUMB8BASE-NEXT: sub sp, #72
+; CHECK-THUMB8BASE-NEXT: .save {r7, lr}
+; CHECK-THUMB8BASE-NEXT: push {r7, lr}
+; CHECK-THUMB8BASE-NEXT: .pad #64
+; CHECK-THUMB8BASE-NEXT: sub sp, #64
; CHECK-THUMB8BASE-NEXT: movw r0, :lower16:atomic_i64
; CHECK-THUMB8BASE-NEXT: movt r0, :upper16:atomic_i64
; CHECK-THUMB8BASE-NEXT: movs r1, #0
; CHECK-THUMB8BASE-NEXT: bl __atomic_load_8
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #56] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #60] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #48] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #52] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: b .LBB42_1
; CHECK-THUMB8BASE-NEXT: .LBB42_1: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r3, [sp, #56] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r2, [sp, #60] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #36] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: str r3, [sp, #40] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: movs r1, #0
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #44] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: movs r0, #1
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #48] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: subs r3, r0, r3
-; CHECK-THUMB8BASE-NEXT: sbcs r1, r2
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #52] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: blo .LBB42_3
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #48] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #52] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #32] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #36] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: movs r1, #1
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #40] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: cmp r0, #1
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #44] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: bhi .LBB42_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB42_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #52] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #40] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #44] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: .LBB42_3: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB42_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #40] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #52] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #28] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #32] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: blo .LBB42_5
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #36] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #32] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r2, [sp, #44] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: str r2, [sp, #24] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: cmp r1, #0
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #28] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: bne .LBB42_5
; CHECK-THUMB8BASE-NEXT: @ %bb.4: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB42_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #48] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #32] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #40] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #28] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: .LBB42_5: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB42_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #36] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #28] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r2, [sp, #32] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #20] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #24] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: cbnz r1, .LBB42_7
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #16] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #20] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: beq .LBB42_7
; CHECK-THUMB8BASE-NEXT: @ %bb.6: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB42_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #28] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #24] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #20] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: .LBB42_7: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB42_1 Depth=1
+; CHECK-THUMB8BASE-NEXT: ldr r3, [sp, #32] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #36] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #36] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r4, [sp, #40] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r3, [sp, #24] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r4, [sp, #64]
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #68]
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #56]
+; CHECK-THUMB8BASE-NEXT: str r3, [sp, #60]
+; CHECK-THUMB8BASE-NEXT: movs r0, #0
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #4]
; CHECK-THUMB8BASE-NEXT: str r0, [sp]
; CHECK-THUMB8BASE-NEXT: movw r0, :lower16:atomic_i64
; CHECK-THUMB8BASE-NEXT: movt r0, :upper16:atomic_i64
-; CHECK-THUMB8BASE-NEXT: add r1, sp, #64
+; CHECK-THUMB8BASE-NEXT: add r1, sp, #56
; CHECK-THUMB8BASE-NEXT: bl __atomic_compare_exchange_8
; CHECK-THUMB8BASE-NEXT: mov r2, r0
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #68]
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #12] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #64]
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #16] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #60]
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #8] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #56]
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #12] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: cmp r2, #0
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #56] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #60] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #48] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #52] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: beq .LBB42_1
; CHECK-THUMB8BASE-NEXT: b .LBB42_8
; CHECK-THUMB8BASE-NEXT: .LBB42_8: @ %atomicrmw.end
-; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: add sp, #72
-; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
+; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: add sp, #64
+; CHECK-THUMB8BASE-NEXT: pop {r7, pc}
entry:
%0 = atomicrmw umax ptr @atomic_i64, i64 1 monotonic
ret i64 %0
@@ -9308,14 +9298,13 @@ define i64 @test_umin_i64() {
; CHECK-ARM8-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; CHECK-ARM8-NEXT: mov r8, r2
; CHECK-ARM8-NEXT: mov r9, r1
-; CHECK-ARM8-NEXT: subs r0, r2, #2
-; CHECK-ARM8-NEXT: sbcs r0, r1, #0
-; CHECK-ARM8-NEXT: mov r0, #0
-; CHECK-ARM8-NEXT: movwlo r0, #1
+; CHECK-ARM8-NEXT: cmp r2, #1
; CHECK-ARM8-NEXT: mov r10, #1
-; CHECK-ARM8-NEXT: movlo r10, r2
-; CHECK-ARM8-NEXT: cmp r0, #0
-; CHECK-ARM8-NEXT: movne r0, r1
+; CHECK-ARM8-NEXT: mov r0, r10
+; CHECK-ARM8-NEXT: movlo r0, r2
+; CHECK-ARM8-NEXT: cmp r1, #0
+; CHECK-ARM8-NEXT: moveq r10, r0
+; CHECK-ARM8-NEXT: mov r0, #0
; CHECK-ARM8-NEXT: @ kill: def $r10 killed $r10 def $r10_r11
; CHECK-ARM8-NEXT: mov r11, r0
; CHECK-ARM8-NEXT: movw r6, :lower16:atomic_i64
@@ -9376,14 +9365,13 @@ define i64 @test_umin_i64() {
; CHECK-ARM6-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; CHECK-ARM6-NEXT: mov r8, r2
; CHECK-ARM6-NEXT: mov r9, r1
-; CHECK-ARM6-NEXT: subs r0, r2, #2
-; CHECK-ARM6-NEXT: sbcs r0, r1, #0
-; CHECK-ARM6-NEXT: mov r0, #0
-; CHECK-ARM6-NEXT: movlo r0, #1
+; CHECK-ARM6-NEXT: cmp r2, #1
; CHECK-ARM6-NEXT: mov r10, #1
-; CHECK-ARM6-NEXT: movlo r10, r2
-; CHECK-ARM6-NEXT: cmp r0, #0
-; CHECK-ARM6-NEXT: movne r0, r1
+; CHECK-ARM6-NEXT: mov r0, r10
+; CHECK-ARM6-NEXT: movlo r0, r2
+; CHECK-ARM6-NEXT: cmp r1, #0
+; CHECK-ARM6-NEXT: moveq r10, r0
+; CHECK-ARM6-NEXT: mov r0, #0
; CHECK-ARM6-NEXT: @ kill: def $r10 killed $r10 def $r10_r11
; CHECK-ARM6-NEXT: mov r11, r0
; CHECK-ARM6-NEXT: ldr r6, .LCPI43_0
@@ -9447,17 +9435,15 @@ define i64 @test_umin_i64() {
; CHECK-THUMB7-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; CHECK-THUMB7-NEXT: mov r8, r2
; CHECK-THUMB7-NEXT: mov r9, r1
-; CHECK-THUMB7-NEXT: subs r0, r2, #2
-; CHECK-THUMB7-NEXT: sbcs r0, r1, #0
-; CHECK-THUMB7-NEXT: mov.w r0, #0
-; CHECK-THUMB7-NEXT: it lo
-; CHECK-THUMB7-NEXT: movlo r0, #1
+; CHECK-THUMB7-NEXT: cmp r2, #1
; CHECK-THUMB7-NEXT: mov.w r10, #1
+; CHECK-THUMB7-NEXT: mov r0, r10
; CHECK-THUMB7-NEXT: it lo
-; CHECK-THUMB7-NEXT: movlo r10, r2
-; CHECK-THUMB7-NEXT: cmp r0, #0
-; CHECK-THUMB7-NEXT: it ne
-; CHECK-THUMB7-NEXT: movne r0, r1
+; CHECK-THUMB7-NEXT: movlo r0, r2
+; CHECK-THUMB7-NEXT: cmp r1, #0
+; CHECK-THUMB7-NEXT: it eq
+; CHECK-THUMB7-NEXT: moveq r10, r0
+; CHECK-THUMB7-NEXT: movs r0, #0
; CHECK-THUMB7-NEXT: @ kill: def $r10 killed $r10 def $r10_r11
; CHECK-THUMB7-NEXT: mov r11, r0
; CHECK-THUMB7-NEXT: movw r6, :lower16:atomic_i64
@@ -9515,88 +9501,71 @@ define i64 @test_umin_i64() {
;
; CHECK-THUMB8BASE-LABEL: test_umin_i64:
; CHECK-THUMB8BASE: @ %bb.0: @ %entry
-; CHECK-THUMB8BASE-NEXT: .save {r4, lr}
-; CHECK-THUMB8BASE-NEXT: push {r4, lr}
-; CHECK-THUMB8BASE-NEXT: .pad #72
-; CHECK-THUMB8BASE-NEXT: sub sp, #72
+; CHECK-THUMB8BASE-NEXT: .save {r7, lr}
+; CHECK-THUMB8BASE-NEXT: push {r7, lr}
+; CHECK-THUMB8BASE-NEXT: .pad #56
+; CHECK-THUMB8BASE-NEXT: sub sp, #56
; CHECK-THUMB8BASE-NEXT: movw r0, :lower16:atomic_i64
; CHECK-THUMB8BASE-NEXT: movt r0, :upper16:atomic_i64
; CHECK-THUMB8BASE-NEXT: movs r1, #0
; CHECK-THUMB8BASE-NEXT: bl __atomic_load_8
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #56] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #60] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #40] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #44] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: b .LBB43_1
; CHECK-THUMB8BASE-NEXT: .LBB43_1: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r3, [sp, #56] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #60] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #36] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: str r3, [sp, #40] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: movs r0, #1
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #44] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: movs r2, #0
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #48] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: subs r3, r3, #2
-; CHECK-THUMB8BASE-NEXT: sbcs r1, r2
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #52] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #40] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #44] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #24] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #28] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: movs r1, #1
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #32] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: cmp r0, #1
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #36] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: blo .LBB43_3
; CHECK-THUMB8BASE-NEXT: @ %bb.2: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB43_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #48] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #52] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #32] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #36] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: .LBB43_3: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB43_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #40] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #52] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #28] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #32] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: blo .LBB43_5
+; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #36] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #20] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: cbz r1, .LBB43_5
; CHECK-THUMB8BASE-NEXT: @ %bb.4: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB43_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #44] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #32] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #32] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #20] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: .LBB43_5: @ %atomicrmw.start
; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB43_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #36] @ 4-byte Reload
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #28] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r2, [sp, #32] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r2, [sp, #20] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #24] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: cbnz r1, .LBB43_7
-; CHECK-THUMB8BASE-NEXT: @ %bb.6: @ %atomicrmw.start
-; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB43_1 Depth=1
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #28] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #24] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: .LBB43_7: @ %atomicrmw.start
-; CHECK-THUMB8BASE-NEXT: @ in Loop: Header=BB43_1 Depth=1
; CHECK-THUMB8BASE-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #48] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #36] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r4, [sp, #40] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: ldr r3, [sp, #24] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: str r4, [sp, #64]
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #68]
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #4]
-; CHECK-THUMB8BASE-NEXT: str r0, [sp]
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #48]
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #52]
+; CHECK-THUMB8BASE-NEXT: movs r3, #0
+; CHECK-THUMB8BASE-NEXT: str r3, [sp, #4]
+; CHECK-THUMB8BASE-NEXT: str r3, [sp]
; CHECK-THUMB8BASE-NEXT: movw r0, :lower16:atomic_i64
; CHECK-THUMB8BASE-NEXT: movt r0, :upper16:atomic_i64
-; CHECK-THUMB8BASE-NEXT: add r1, sp, #64
+; CHECK-THUMB8BASE-NEXT: add r1, sp, #48
; CHECK-THUMB8BASE-NEXT: bl __atomic_compare_exchange_8
; CHECK-THUMB8BASE-NEXT: mov r2, r0
-; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #68]
+; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #52]
; CHECK-THUMB8BASE-NEXT: str r0, [sp, #12] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #64]
+; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #48]
; CHECK-THUMB8BASE-NEXT: str r1, [sp, #16] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: cmp r2, #0
-; CHECK-THUMB8BASE-NEXT: str r1, [sp, #56] @ 4-byte Spill
-; CHECK-THUMB8BASE-NEXT: str r0, [sp, #60] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: str r1, [sp, #40] @ 4-byte Spill
+; CHECK-THUMB8BASE-NEXT: str r0, [sp, #44] @ 4-byte Spill
; CHECK-THUMB8BASE-NEXT: beq .LBB43_1
-; CHECK-THUMB8BASE-NEXT: b .LBB43_8
-; CHECK-THUMB8BASE-NEXT: .LBB43_8: @ %atomicrmw.end
+; CHECK-THUMB8BASE-NEXT: b .LBB43_6
+; CHECK-THUMB8BASE-NEXT: .LBB43_6: @ %atomicrmw.end
; CHECK-THUMB8BASE-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
; CHECK-THUMB8BASE-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
-; CHECK-THUMB8BASE-NEXT: add sp, #72
-; CHECK-THUMB8BASE-NEXT: pop {r4, pc}
+; CHECK-THUMB8BASE-NEXT: add sp, #56
+; CHECK-THUMB8BASE-NEXT: pop {r7, pc}
entry:
%0 = atomicrmw umin ptr @atomic_i64, i64 1 monotonic
ret i64 %0
diff --git a/llvm/test/CodeGen/ARM/atomicrmw_minmax.ll b/llvm/test/CodeGen/ARM/atomicrmw_minmax.ll
index 2866b1a356782..74b402c832982 100644
--- a/llvm/test/CodeGen/ARM/atomicrmw_minmax.ll
+++ b/llvm/test/CodeGen/ARM/atomicrmw_minmax.ll
@@ -1,21 +1,40 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s
-; CHECK-LABEL: max:
define i32 @max(i8 %ctx, ptr %ptr, i32 %val)
+; CHECK-LABEL: max:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .LBB0_1: @ %atomicrmw.start
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ldrex r0, [r1]
+; CHECK-NEXT: mov r3, r2
+; CHECK-NEXT: cmp r0, r2
+; CHECK-NEXT: movhi r3, r0
+; CHECK-NEXT: strex r12, r3, [r1]
+; CHECK-NEXT: cmp r12, #0
+; CHECK-NEXT: bne .LBB0_1
+; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-NEXT: bx lr
{
-; CHECK: ldrex
-; CHECK: cmp [[old:r[0-9]*]], [[val:r[0-9]*]]
-; CHECK: movhi {{r[0-9]*}}, [[old]]
%old = atomicrmw umax ptr %ptr, i32 %val monotonic
ret i32 %old
}
-; CHECK-LABEL: min:
define i32 @min(i8 %ctx, ptr %ptr, i32 %val)
+; CHECK-LABEL: min:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .LBB1_1: @ %atomicrmw.start
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ldrex r0, [r1]
+; CHECK-NEXT: mov r3, r2
+; CHECK-NEXT: cmp r0, r2
+; CHECK-NEXT: movlo r3, r0
+; CHECK-NEXT: strex r12, r3, [r1]
+; CHECK-NEXT: cmp r12, #0
+; CHECK-NEXT: bne .LBB1_1
+; CHECK-NEXT: @ %bb.2: @ %atomicrmw.end
+; CHECK-NEXT: bx lr
{
-; CHECK: ldrex
-; CHECK: cmp [[old:r[0-9]*]], [[val:r[0-9]*]]
-; CHECK: movls {{r[0-9]*}}, [[old]]
%old = atomicrmw umin ptr %ptr, i32 %val monotonic
ret i32 %old
}
diff --git a/llvm/test/CodeGen/ARM/commute-movcc.ll b/llvm/test/CodeGen/ARM/commute-movcc.ll
index 0a276a50b3f2e..a0cfc02cfacc7 100644
--- a/llvm/test/CodeGen/ARM/commute-movcc.ll
+++ b/llvm/test/CodeGen/ARM/commute-movcc.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=thumbv7-apple-ios -disable-block-placement < %s | FileCheck %s
; RUN: llc -mtriple=armv7-apple-ios -disable-block-placement < %s | FileCheck %s
@@ -12,10 +13,9 @@
; CHECK-NOT: mov
; CHECK: %if.else
-; CHECK-NOT: mov
-; CHECK: movls
+; CHECK: mov
+; CHECK: movlo
; CHECK: movls
-; CHECK-NOT: mov
; This is really an LSR test: Make sure that cmp is using the incremented
; induction variable.
@@ -61,3 +61,5 @@ if.end8: ; preds = %if.else, %if.then
for.end: ; preds = %if.end8
ret i32 %BestIdx.1
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
diff --git a/llvm/test/CodeGen/ARM/fpclamptosat.ll b/llvm/test/CodeGen/ARM/fpclamptosat.ll
index a6f0a03fc7e5b..80e31bef198ab 100644
--- a/llvm/test/CodeGen/ARM/fpclamptosat.ll
+++ b/llvm/test/CodeGen/ARM/fpclamptosat.ll
@@ -45,16 +45,17 @@ define i32 @stest_f64i32(double %x) {
; VFP2-NEXT: push {r7, lr}
; VFP2-NEXT: vmov r0, r1, d0
; VFP2-NEXT: bl __aeabi_d2lz
-; VFP2-NEXT: mvn r12, #-2147483648
-; VFP2-NEXT: subs.w r3, r0, r12
-; VFP2-NEXT: mov.w r2, #0
+; VFP2-NEXT: mvn r2, #-2147483648
+; VFP2-NEXT: subs r3, r0, r2
; VFP2-NEXT: sbcs r3, r1, #0
+; VFP2-NEXT: it ge
+; VFP2-NEXT: movge r0, r2
+; VFP2-NEXT: mov.w r2, #0
; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r2, #1
; VFP2-NEXT: cmp r2, #0
-; VFP2-NEXT: ite ne
+; VFP2-NEXT: it ne
; VFP2-NEXT: movne r2, r1
-; VFP2-NEXT: moveq r0, r12
; VFP2-NEXT: mov.w r1, #-1
; VFP2-NEXT: rsbs.w r3, r0, #-2147483648
; VFP2-NEXT: sbcs r1, r2
@@ -120,38 +121,33 @@ entry:
define i32 @ustest_f64i32(double %x) {
; SOFT-LABEL: ustest_f64i32:
; SOFT: @ %bb.0: @ %entry
-; SOFT-NEXT: .save {r4, lr}
-; SOFT-NEXT: push {r4, lr}
+; SOFT-NEXT: .save {r7, lr}
+; SOFT-NEXT: push {r7, lr}
; SOFT-NEXT: bl __aeabi_d2lz
+; SOFT-NEXT: asrs r3, r1, #31
+; SOFT-NEXT: ands r3, r1
; SOFT-NEXT: movs r2, #0
-; SOFT-NEXT: mvns r3, r2
-; SOFT-NEXT: adds r4, r0, #1
-; SOFT-NEXT: mov r4, r1
-; SOFT-NEXT: sbcs r4, r2
+; SOFT-NEXT: cmp r1, #1
; SOFT-NEXT: blt .LBB2_2
; SOFT-NEXT: @ %bb.1: @ %entry
-; SOFT-NEXT: mov r1, r2
+; SOFT-NEXT: mvns r0, r2
; SOFT-NEXT: .LBB2_2: @ %entry
-; SOFT-NEXT: blt .LBB2_4
+; SOFT-NEXT: rsbs r1, r0, #0
+; SOFT-NEXT: mov r1, r2
+; SOFT-NEXT: sbcs r1, r3
+; SOFT-NEXT: blt .LBB2_5
; SOFT-NEXT: @ %bb.3: @ %entry
-; SOFT-NEXT: mov r0, r3
-; SOFT-NEXT: .LBB2_4: @ %entry
-; SOFT-NEXT: rsbs r3, r0, #0
-; SOFT-NEXT: mov r3, r2
-; SOFT-NEXT: sbcs r3, r1
-; SOFT-NEXT: blt .LBB2_7
-; SOFT-NEXT: @ %bb.5: @ %entry
; SOFT-NEXT: cmp r2, #0
-; SOFT-NEXT: beq .LBB2_8
-; SOFT-NEXT: .LBB2_6: @ %entry
-; SOFT-NEXT: pop {r4, pc}
-; SOFT-NEXT: .LBB2_7:
+; SOFT-NEXT: beq .LBB2_6
+; SOFT-NEXT: .LBB2_4: @ %entry
+; SOFT-NEXT: pop {r7, pc}
+; SOFT-NEXT: .LBB2_5:
; SOFT-NEXT: movs r2, #1
; SOFT-NEXT: cmp r2, #0
-; SOFT-NEXT: bne .LBB2_6
-; SOFT-NEXT: .LBB2_8: @ %entry
+; SOFT-NEXT: bne .LBB2_4
+; SOFT-NEXT: .LBB2_6: @ %entry
; SOFT-NEXT: mov r0, r2
-; SOFT-NEXT: pop {r4, pc}
+; SOFT-NEXT: pop {r7, pc}
;
; VFP2-LABEL: ustest_f64i32:
; VFP2: @ %bb.0: @ %entry
@@ -159,18 +155,13 @@ define i32 @ustest_f64i32(double %x) {
; VFP2-NEXT: push {r7, lr}
; VFP2-NEXT: vmov r0, r1, d0
; VFP2-NEXT: bl __aeabi_d2lz
-; VFP2-NEXT: subs.w r3, r0, #-1
+; VFP2-NEXT: cmp r1, #1
+; VFP2-NEXT: it ge
+; VFP2-NEXT: movge.w r0, #-1
+; VFP2-NEXT: and.w r1, r1, r1, asr #31
+; VFP2-NEXT: rsbs r3, r0, #0
; VFP2-NEXT: mov.w r2, #0
-; VFP2-NEXT: sbcs r3, r1, #0
-; VFP2-NEXT: mov.w r3, #0
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r3, #1
-; VFP2-NEXT: cmp r3, #0
-; VFP2-NEXT: ite ne
-; VFP2-NEXT: movne r3, r1
-; VFP2-NEXT: moveq.w r0, #-1
-; VFP2-NEXT: rsbs r1, r0, #0
-; VFP2-NEXT: sbcs.w r1, r2, r3
+; VFP2-NEXT: sbcs.w r1, r2, r1
; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r2, #1
; VFP2-NEXT: cmp r2, #0
@@ -273,38 +264,33 @@ entry:
define i32 @ustest_f32i32(float %x) {
; SOFT-LABEL: ustest_f32i32:
; SOFT: @ %bb.0: @ %entry
-; SOFT-NEXT: .save {r4, lr}
-; SOFT-NEXT: push {r4, lr}
+; SOFT-NEXT: .save {r7, lr}
+; SOFT-NEXT: push {r7, lr}
; SOFT-NEXT: bl __aeabi_f2lz
; SOFT-NEXT: movs r2, #0
-; SOFT-NEXT: mvns r3, r2
-; SOFT-NEXT: adds r4, r0, #1
-; SOFT-NEXT: mov r4, r1
-; SOFT-NEXT: sbcs r4, r2
+; SOFT-NEXT: cmp r1, #1
; SOFT-NEXT: blt .LBB5_2
; SOFT-NEXT: @ %bb.1: @ %entry
-; SOFT-NEXT: mov r1, r2
+; SOFT-NEXT: mvns r0, r2
; SOFT-NEXT: .LBB5_2: @ %entry
-; SOFT-NEXT: blt .LBB5_4
+; SOFT-NEXT: asrs r3, r1, #31
+; SOFT-NEXT: ands r3, r1
+; SOFT-NEXT: rsbs r1, r0, #0
+; SOFT-NEXT: mov r1, r2
+; SOFT-NEXT: sbcs r1, r3
+; SOFT-NEXT: blt .LBB5_5
; SOFT-NEXT: @ %bb.3: @ %entry
-; SOFT-NEXT: mov r0, r3
-; SOFT-NEXT: .LBB5_4: @ %entry
-; SOFT-NEXT: rsbs r3, r0, #0
-; SOFT-NEXT: mov r3, r2
-; SOFT-NEXT: sbcs r3, r1
-; SOFT-NEXT: blt .LBB5_7
-; SOFT-NEXT: @ %bb.5: @ %entry
; SOFT-NEXT: cmp r2, #0
-; SOFT-NEXT: beq .LBB5_8
-; SOFT-NEXT: .LBB5_6: @ %entry
-; SOFT-NEXT: pop {r4, pc}
-; SOFT-NEXT: .LBB5_7:
+; SOFT-NEXT: beq .LBB5_6
+; SOFT-NEXT: .LBB5_4: @ %entry
+; SOFT-NEXT: pop {r7, pc}
+; SOFT-NEXT: .LBB5_5:
; SOFT-NEXT: movs r2, #1
; SOFT-NEXT: cmp r2, #0
-; SOFT-NEXT: bne .LBB5_6
-; SOFT-NEXT: .LBB5_8: @ %entry
+; SOFT-NEXT: bne .LBB5_4
+; SOFT-NEXT: .LBB5_6: @ %entry
; SOFT-NEXT: mov r0, r2
-; SOFT-NEXT: pop {r4, pc}
+; SOFT-NEXT: pop {r7, pc}
;
; VFP-LABEL: ustest_f32i32:
; VFP: @ %bb.0: @ %entry
@@ -427,40 +413,35 @@ entry:
define i32 @ustest_f16i32(half %x) {
; SOFT-LABEL: ustest_f16i32:
; SOFT: @ %bb.0: @ %entry
-; SOFT-NEXT: .save {r4, lr}
-; SOFT-NEXT: push {r4, lr}
+; SOFT-NEXT: .save {r7, lr}
+; SOFT-NEXT: push {r7, lr}
; SOFT-NEXT: uxth r0, r0
; SOFT-NEXT: bl __aeabi_h2f
; SOFT-NEXT: bl __aeabi_f2lz
; SOFT-NEXT: movs r2, #0
-; SOFT-NEXT: mvns r3, r2
-; SOFT-NEXT: adds r4, r0, #1
-; SOFT-NEXT: mov r4, r1
-; SOFT-NEXT: sbcs r4, r2
+; SOFT-NEXT: cmp r1, #1
; SOFT-NEXT: blt .LBB8_2
; SOFT-NEXT: @ %bb.1: @ %entry
-; SOFT-NEXT: mov r1, r2
+; SOFT-NEXT: mvns r0, r2
; SOFT-NEXT: .LBB8_2: @ %entry
-; SOFT-NEXT: blt .LBB8_4
+; SOFT-NEXT: asrs r3, r1, #31
+; SOFT-NEXT: ands r3, r1
+; SOFT-NEXT: rsbs r1, r0, #0
+; SOFT-NEXT: mov r1, r2
+; SOFT-NEXT: sbcs r1, r3
+; SOFT-NEXT: blt .LBB8_5
; SOFT-NEXT: @ %bb.3: @ %entry
-; SOFT-NEXT: mov r0, r3
-; SOFT-NEXT: .LBB8_4: @ %entry
-; SOFT-NEXT: rsbs r3, r0, #0
-; SOFT-NEXT: mov r3, r2
-; SOFT-NEXT: sbcs r3, r1
-; SOFT-NEXT: blt .LBB8_7
-; SOFT-NEXT: @ %bb.5: @ %entry
; SOFT-NEXT: cmp r2, #0
-; SOFT-NEXT: beq .LBB8_8
-; SOFT-NEXT: .LBB8_6: @ %entry
-; SOFT-NEXT: pop {r4, pc}
-; SOFT-NEXT: .LBB8_7:
+; SOFT-NEXT: beq .LBB8_6
+; SOFT-NEXT: .LBB8_4: @ %entry
+; SOFT-NEXT: pop {r7, pc}
+; SOFT-NEXT: .LBB8_5:
; SOFT-NEXT: movs r2, #1
; SOFT-NEXT: cmp r2, #0
-; SOFT-NEXT: bne .LBB8_6
-; SOFT-NEXT: .LBB8_8: @ %entry
+; SOFT-NEXT: bne .LBB8_4
+; SOFT-NEXT: .LBB8_6: @ %entry
; SOFT-NEXT: mov r0, r2
-; SOFT-NEXT: pop {r4, pc}
+; SOFT-NEXT: pop {r7, pc}
;
; VFP2-LABEL: ustest_f16i32:
; VFP2: @ %bb.0: @ %entry
@@ -613,21 +594,14 @@ define i16 @ustest_f64i16(double %x) {
; VFP2-NEXT: push {r7, lr}
; VFP2-NEXT: vmov r0, r1, d0
; VFP2-NEXT: bl __aeabi_d2iz
-; VFP2-NEXT: movw r1, #65535
-; VFP2-NEXT: cmp r0, r1
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r1, r0
-; VFP2-NEXT: bic.w r0, r1, r1, asr #31
+; VFP2-NEXT: usat r0, #16, r0
; VFP2-NEXT: pop {r7, pc}
;
; FULL-LABEL: ustest_f64i16:
; FULL: @ %bb.0: @ %entry
; FULL-NEXT: vcvt.s32.f64 s0, d0
-; FULL-NEXT: movw r1, #65535
; FULL-NEXT: vmov r0, s0
-; FULL-NEXT: cmp r0, r1
-; FULL-NEXT: csel r0, r0, r1, lt
-; FULL-NEXT: bic.w r0, r0, r0, asr #31
+; FULL-NEXT: usat r0, #16, r0
; FULL-NEXT: bx lr
entry:
%conv = fptosi double %x to i32
@@ -745,26 +719,12 @@ define i16 @ustest_f32i16(float %x) {
; SOFT-NEXT: .LCPI14_0:
; SOFT-NEXT: .long 65535 @ 0xffff
;
-; VFP2-LABEL: ustest_f32i16:
-; VFP2: @ %bb.0: @ %entry
-; VFP2-NEXT: vcvt.s32.f32 s0, s0
-; VFP2-NEXT: movw r1, #65535
-; VFP2-NEXT: vmov r0, s0
-; VFP2-NEXT: cmp r0, r1
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r1, r0
-; VFP2-NEXT: bic.w r0, r1, r1, asr #31
-; VFP2-NEXT: bx lr
-;
-; FULL-LABEL: ustest_f32i16:
-; FULL: @ %bb.0: @ %entry
-; FULL-NEXT: vcvt.s32.f32 s0, s0
-; FULL-NEXT: movw r1, #65535
-; FULL-NEXT: vmov r0, s0
-; FULL-NEXT: cmp r0, r1
-; FULL-NEXT: csel r0, r0, r1, lt
-; FULL-NEXT: bic.w r0, r0, r0, asr #31
-; FULL-NEXT: bx lr
+; VFP-LABEL: ustest_f32i16:
+; VFP: @ %bb.0: @ %entry
+; VFP-NEXT: vcvt.s32.f32 s0, s0
+; VFP-NEXT: vmov r0, s0
+; VFP-NEXT: usat r0, #16, r0
+; VFP-NEXT: bx lr
entry:
%conv = fptosi float %x to i32
%0 = icmp slt i32 %conv, 65535
@@ -911,23 +871,16 @@ define i16 @ustest_f16i16(half %x) {
; VFP2-NEXT: vmov r0, s0
; VFP2-NEXT: bl __aeabi_h2f
; VFP2-NEXT: vmov s0, r0
-; VFP2-NEXT: movw r1, #65535
; VFP2-NEXT: vcvt.s32.f32 s0, s0
; VFP2-NEXT: vmov r0, s0
-; VFP2-NEXT: cmp r0, r1
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r1, r0
-; VFP2-NEXT: bic.w r0, r1, r1, asr #31
+; VFP2-NEXT: usat r0, #16, r0
; VFP2-NEXT: pop {r7, pc}
;
; FULL-LABEL: ustest_f16i16:
; FULL: @ %bb.0: @ %entry
; FULL-NEXT: vcvt.s32.f16 s0, s0
-; FULL-NEXT: movw r1, #65535
; FULL-NEXT: vmov r0, s0
-; FULL-NEXT: cmp r0, r1
-; FULL-NEXT: csel r0, r0, r1, lt
-; FULL-NEXT: bic.w r0, r0, r0, asr #31
+; FULL-NEXT: usat r0, #16, r0
; FULL-NEXT: bx lr
entry:
%conv = fptosi half %x to i32
@@ -1132,29 +1085,41 @@ define i64 @ustest_f64i64(double %x) {
; SOFT-NEXT: .save {r4, lr}
; SOFT-NEXT: push {r4, lr}
; SOFT-NEXT: bl __fixdfti
-; SOFT-NEXT: movs r4, #0
+; SOFT-NEXT: mov r4, r1
+; SOFT-NEXT: movs r1, #0
; SOFT-NEXT: subs r2, r2, #1
; SOFT-NEXT: mov r2, r3
-; SOFT-NEXT: sbcs r2, r4
-; SOFT-NEXT: bge .LBB20_5
+; SOFT-NEXT: sbcs r2, r1
+; SOFT-NEXT: bge .LBB20_7
; SOFT-NEXT: @ %bb.1: @ %entry
-; SOFT-NEXT: bge .LBB20_6
+; SOFT-NEXT: bge .LBB20_8
; SOFT-NEXT: .LBB20_2: @ %entry
; SOFT-NEXT: blt .LBB20_4
; SOFT-NEXT: .LBB20_3: @ %entry
-; SOFT-NEXT: mov r3, r4
+; SOFT-NEXT: mov r3, r1
; SOFT-NEXT: .LBB20_4: @ %entry
-; SOFT-NEXT: asrs r2, r3, #31
-; SOFT-NEXT: bics r0, r2
-; SOFT-NEXT: bics r1, r2
+; SOFT-NEXT: cmp r3, #0
+; SOFT-NEXT: mov r2, r1
+; SOFT-NEXT: bpl .LBB20_9
+; SOFT-NEXT: @ %bb.5: @ %entry
+; SOFT-NEXT: bpl .LBB20_10
+; SOFT-NEXT: .LBB20_6: @ %entry
+; SOFT-NEXT: mov r0, r2
; SOFT-NEXT: pop {r4, pc}
-; SOFT-NEXT: .LBB20_5: @ %entry
-; SOFT-NEXT: mov r1, r4
+; SOFT-NEXT: .LBB20_7: @ %entry
+; SOFT-NEXT: mov r4, r1
; SOFT-NEXT: blt .LBB20_2
-; SOFT-NEXT: .LBB20_6: @ %entry
-; SOFT-NEXT: mov r0, r4
+; SOFT-NEXT: .LBB20_8: @ %entry
+; SOFT-NEXT: mov r0, r1
; SOFT-NEXT: bge .LBB20_3
; SOFT-NEXT: b .LBB20_4
+; SOFT-NEXT: .LBB20_9: @ %entry
+; SOFT-NEXT: mov r2, r0
+; SOFT-NEXT: bmi .LBB20_6
+; SOFT-NEXT: .LBB20_10: @ %entry
+; SOFT-NEXT: mov r1, r4
+; SOFT-NEXT: mov r0, r2
+; SOFT-NEXT: pop {r4, pc}
;
; VFP2-LABEL: ustest_f64i64:
; VFP2: @ %bb.0: @ %entry
@@ -1164,13 +1129,14 @@ define i64 @ustest_f64i64(double %x) {
; VFP2-NEXT: subs r2, #1
; VFP2-NEXT: mov.w r12, #0
; VFP2-NEXT: sbcs r2, r3, #0
-; VFP2-NEXT: itt ge
-; VFP2-NEXT: movge r3, r12
-; VFP2-NEXT: movge r0, r12
-; VFP2-NEXT: it ge
+; VFP2-NEXT: itte ge
; VFP2-NEXT: movge r1, r12
-; VFP2-NEXT: bic.w r0, r0, r3, asr #31
-; VFP2-NEXT: bic.w r1, r1, r3, asr #31
+; VFP2-NEXT: movge r0, r12
+; VFP2-NEXT: movlt r12, r3
+; VFP2-NEXT: cmp.w r12, #0
+; VFP2-NEXT: itt mi
+; VFP2-NEXT: movmi r0, #0
+; VFP2-NEXT: movmi r1, #0
; VFP2-NEXT: pop {r7, pc}
;
; FULL-LABEL: ustest_f64i64:
@@ -1181,11 +1147,13 @@ define i64 @ustest_f64i64(double %x) {
; FULL-NEXT: subs r2, #1
; FULL-NEXT: mov.w r12, #0
; FULL-NEXT: sbcs r2, r3, #0
-; FULL-NEXT: csel r2, r3, r12, lt
-; FULL-NEXT: csel r0, r0, r12, lt
; FULL-NEXT: csel r1, r1, r12, lt
-; FULL-NEXT: bic.w r0, r0, r2, asr #31
-; FULL-NEXT: bic.w r1, r1, r2, asr #31
+; FULL-NEXT: csel r0, r0, r12, lt
+; FULL-NEXT: csel r2, r3, r12, lt
+; FULL-NEXT: cmp r2, #0
+; FULL-NEXT: itt mi
+; FULL-NEXT: movmi r0, #0
+; FULL-NEXT: movmi r1, #0
; FULL-NEXT: pop {r7, pc}
entry:
%conv = fptosi double %x to i128
@@ -1388,29 +1356,41 @@ define i64 @ustest_f32i64(float %x) {
; SOFT-NEXT: .save {r4, lr}
; SOFT-NEXT: push {r4, lr}
; SOFT-NEXT: bl __fixsfti
-; SOFT-NEXT: movs r4, #0
+; SOFT-NEXT: mov r4, r1
+; SOFT-NEXT: movs r1, #0
; SOFT-NEXT: subs r2, r2, #1
; SOFT-NEXT: mov r2, r3
-; SOFT-NEXT: sbcs r2, r4
-; SOFT-NEXT: bge .LBB23_5
+; SOFT-NEXT: sbcs r2, r1
+; SOFT-NEXT: bge .LBB23_7
; SOFT-NEXT: @ %bb.1: @ %entry
-; SOFT-NEXT: bge .LBB23_6
+; SOFT-NEXT: bge .LBB23_8
; SOFT-NEXT: .LBB23_2: @ %entry
; SOFT-NEXT: blt .LBB23_4
; SOFT-NEXT: .LBB23_3: @ %entry
-; SOFT-NEXT: mov r3, r4
+; SOFT-NEXT: mov r3, r1
; SOFT-NEXT: .LBB23_4: @ %entry
-; SOFT-NEXT: asrs r2, r3, #31
-; SOFT-NEXT: bics r0, r2
-; SOFT-NEXT: bics r1, r2
+; SOFT-NEXT: cmp r3, #0
+; SOFT-NEXT: mov r2, r1
+; SOFT-NEXT: bpl .LBB23_9
+; SOFT-NEXT: @ %bb.5: @ %entry
+; SOFT-NEXT: bpl .LBB23_10
+; SOFT-NEXT: .LBB23_6: @ %entry
+; SOFT-NEXT: mov r0, r2
; SOFT-NEXT: pop {r4, pc}
-; SOFT-NEXT: .LBB23_5: @ %entry
-; SOFT-NEXT: mov r1, r4
+; SOFT-NEXT: .LBB23_7: @ %entry
+; SOFT-NEXT: mov r4, r1
; SOFT-NEXT: blt .LBB23_2
-; SOFT-NEXT: .LBB23_6: @ %entry
-; SOFT-NEXT: mov r0, r4
+; SOFT-NEXT: .LBB23_8: @ %entry
+; SOFT-NEXT: mov r0, r1
; SOFT-NEXT: bge .LBB23_3
; SOFT-NEXT: b .LBB23_4
+; SOFT-NEXT: .LBB23_9: @ %entry
+; SOFT-NEXT: mov r2, r0
+; SOFT-NEXT: bmi .LBB23_6
+; SOFT-NEXT: .LBB23_10: @ %entry
+; SOFT-NEXT: mov r1, r4
+; SOFT-NEXT: mov r0, r2
+; SOFT-NEXT: pop {r4, pc}
;
; VFP2-LABEL: ustest_f32i64:
; VFP2: @ %bb.0: @ %entry
@@ -1420,13 +1400,14 @@ define i64 @ustest_f32i64(float %x) {
; VFP2-NEXT: subs r2, #1
; VFP2-NEXT: mov.w r12, #0
; VFP2-NEXT: sbcs r2, r3, #0
-; VFP2-NEXT: itt ge
-; VFP2-NEXT: movge r3, r12
-; VFP2-NEXT: movge r0, r12
-; VFP2-NEXT: it ge
+; VFP2-NEXT: itte ge
; VFP2-NEXT: movge r1, r12
-; VFP2-NEXT: bic.w r0, r0, r3, asr #31
-; VFP2-NEXT: bic.w r1, r1, r3, asr #31
+; VFP2-NEXT: movge r0, r12
+; VFP2-NEXT: movlt r12, r3
+; VFP2-NEXT: cmp.w r12, #0
+; VFP2-NEXT: itt mi
+; VFP2-NEXT: movmi r0, #0
+; VFP2-NEXT: movmi r1, #0
; VFP2-NEXT: pop {r7, pc}
;
; FULL-LABEL: ustest_f32i64:
@@ -1437,11 +1418,13 @@ define i64 @ustest_f32i64(float %x) {
; FULL-NEXT: subs r2, #1
; FULL-NEXT: mov.w r12, #0
; FULL-NEXT: sbcs r2, r3, #0
-; FULL-NEXT: csel r2, r3, r12, lt
-; FULL-NEXT: csel r0, r0, r12, lt
; FULL-NEXT: csel r1, r1, r12, lt
-; FULL-NEXT: bic.w r0, r0, r2, asr #31
-; FULL-NEXT: bic.w r1, r1, r2, asr #31
+; FULL-NEXT: csel r0, r0, r12, lt
+; FULL-NEXT: csel r2, r3, r12, lt
+; FULL-NEXT: cmp r2, #0
+; FULL-NEXT: itt mi
+; FULL-NEXT: movmi r0, #0
+; FULL-NEXT: movmi r1, #0
; FULL-NEXT: pop {r7, pc}
entry:
%conv = fptosi float %x to i128
@@ -1660,29 +1643,41 @@ define i64 @ustest_f16i64(half %x) {
; SOFT-NEXT: uxth r0, r0
; SOFT-NEXT: bl __aeabi_h2f
; SOFT-NEXT: bl __fixsfti
-; SOFT-NEXT: movs r4, #0
+; SOFT-NEXT: mov r4, r1
+; SOFT-NEXT: movs r1, #0
; SOFT-NEXT: subs r2, r2, #1
; SOFT-NEXT: mov r2, r3
-; SOFT-NEXT: sbcs r2, r4
-; SOFT-NEXT: bge .LBB26_5
+; SOFT-NEXT: sbcs r2, r1
+; SOFT-NEXT: bge .LBB26_7
; SOFT-NEXT: @ %bb.1: @ %entry
-; SOFT-NEXT: bge .LBB26_6
+; SOFT-NEXT: bge .LBB26_8
; SOFT-NEXT: .LBB26_2: @ %entry
; SOFT-NEXT: blt .LBB26_4
; SOFT-NEXT: .LBB26_3: @ %entry
-; SOFT-NEXT: mov r3, r4
+; SOFT-NEXT: mov r3, r1
; SOFT-NEXT: .LBB26_4: @ %entry
-; SOFT-NEXT: asrs r2, r3, #31
-; SOFT-NEXT: bics r0, r2
-; SOFT-NEXT: bics r1, r2
+; SOFT-NEXT: cmp r3, #0
+; SOFT-NEXT: mov r2, r1
+; SOFT-NEXT: bpl .LBB26_9
+; SOFT-NEXT: @ %bb.5: @ %entry
+; SOFT-NEXT: bpl .LBB26_10
+; SOFT-NEXT: .LBB26_6: @ %entry
+; SOFT-NEXT: mov r0, r2
; SOFT-NEXT: pop {r4, pc}
-; SOFT-NEXT: .LBB26_5: @ %entry
-; SOFT-NEXT: mov r1, r4
+; SOFT-NEXT: .LBB26_7: @ %entry
+; SOFT-NEXT: mov r4, r1
; SOFT-NEXT: blt .LBB26_2
-; SOFT-NEXT: .LBB26_6: @ %entry
-; SOFT-NEXT: mov r0, r4
+; SOFT-NEXT: .LBB26_8: @ %entry
+; SOFT-NEXT: mov r0, r1
; SOFT-NEXT: bge .LBB26_3
; SOFT-NEXT: b .LBB26_4
+; SOFT-NEXT: .LBB26_9: @ %entry
+; SOFT-NEXT: mov r2, r0
+; SOFT-NEXT: bmi .LBB26_6
+; SOFT-NEXT: .LBB26_10: @ %entry
+; SOFT-NEXT: mov r1, r4
+; SOFT-NEXT: mov r0, r2
+; SOFT-NEXT: pop {r4, pc}
;
; VFP2-LABEL: ustest_f16i64:
; VFP2: @ %bb.0: @ %entry
@@ -1695,13 +1690,14 @@ define i64 @ustest_f16i64(half %x) {
; VFP2-NEXT: subs r2, #1
; VFP2-NEXT: mov.w r12, #0
; VFP2-NEXT: sbcs r2, r3, #0
-; VFP2-NEXT: itt ge
-; VFP2-NEXT: movge r3, r12
-; VFP2-NEXT: movge r0, r12
-; VFP2-NEXT: it ge
+; VFP2-NEXT: itte ge
; VFP2-NEXT: movge r1, r12
-; VFP2-NEXT: bic.w r0, r0, r3, asr #31
-; VFP2-NEXT: bic.w r1, r1, r3, asr #31
+; VFP2-NEXT: movge r0, r12
+; VFP2-NEXT: movlt r12, r3
+; VFP2-NEXT: cmp.w r12, #0
+; VFP2-NEXT: itt mi
+; VFP2-NEXT: movmi r0, #0
+; VFP2-NEXT: movmi r1, #0
; VFP2-NEXT: pop {r7, pc}
;
; FULL-LABEL: ustest_f16i64:
@@ -1714,11 +1710,13 @@ define i64 @ustest_f16i64(half %x) {
; FULL-NEXT: subs r2, #1
; FULL-NEXT: mov.w r12, #0
; FULL-NEXT: sbcs r2, r3, #0
-; FULL-NEXT: csel r2, r3, r12, lt
-; FULL-NEXT: csel r0, r0, r12, lt
; FULL-NEXT: csel r1, r1, r12, lt
-; FULL-NEXT: bic.w r0, r0, r2, asr #31
-; FULL-NEXT: bic.w r1, r1, r2, asr #31
+; FULL-NEXT: csel r0, r0, r12, lt
+; FULL-NEXT: csel r2, r3, r12, lt
+; FULL-NEXT: cmp r2, #0
+; FULL-NEXT: itt mi
+; FULL-NEXT: movmi r0, #0
+; FULL-NEXT: movmi r1, #0
; FULL-NEXT: pop {r7, pc}
entry:
%conv = fptosi half %x to i128
@@ -3613,15 +3611,15 @@ define void @unroll_maxmin(ptr nocapture %0, ptr nocapture readonly %1, i32 %2)
; SOFT-NEXT: mov r2, r1
; SOFT-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: sbcs r2, r3
-; SOFT-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; SOFT-NEXT: bge .LBB54_16
; SOFT-NEXT: @ %bb.9: @ in Loop: Header=BB54_2 Depth=1
-; SOFT-NEXT: cmp r2, #0
-; SOFT-NEXT: beq .LBB54_17
+; SOFT-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
+; SOFT-NEXT: bge .LBB54_17
; SOFT-NEXT: .LBB54_10: @ in Loop: Header=BB54_2 Depth=1
+; SOFT-NEXT: cmp r2, #0
; SOFT-NEXT: bne .LBB54_12
; SOFT-NEXT: .LBB54_11: @ in Loop: Header=BB54_2 Depth=1
-; SOFT-NEXT: ldr r0, .LCPI54_0
+; SOFT-NEXT: mov r1, r2
; SOFT-NEXT: .LBB54_12: @ in Loop: Header=BB54_2 Depth=1
; SOFT-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; SOFT-NEXT: subs r2, r2, r0
@@ -3641,11 +3639,12 @@ define void @unroll_maxmin(ptr nocapture %0, ptr nocapture readonly %1, i32 %2)
; SOFT-NEXT: beq .LBB54_5
; SOFT-NEXT: b .LBB54_6
; SOFT-NEXT: .LBB54_16: @ in Loop: Header=BB54_2 Depth=1
+; SOFT-NEXT: ldr r0, .LCPI54_0
+; SOFT-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
+; SOFT-NEXT: blt .LBB54_10
+; SOFT-NEXT: .LBB54_17: @ in Loop: Header=BB54_2 Depth=1
; SOFT-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
; SOFT-NEXT: cmp r2, #0
-; SOFT-NEXT: bne .LBB54_10
-; SOFT-NEXT: .LBB54_17: @ in Loop: Header=BB54_2 Depth=1
-; SOFT-NEXT: mov r1, r2
; SOFT-NEXT: beq .LBB54_11
; SOFT-NEXT: b .LBB54_12
; SOFT-NEXT: .LBB54_18:
diff --git a/llvm/test/CodeGen/ARM/fpclamptosat_vec.ll b/llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
index 40b360e9158ff..d32ecad5ab3ab 100644
--- a/llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
@@ -1145,13 +1145,13 @@ define <2 x i16> @stest_f64i16(<2 x double> %x) {
; CHECK-NEXT: vcvt.s32.f64 s4, d0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vcvt.s32.f64 s0, d1
-; CHECK-NEXT: vmov.i32 d17, #0x7fff
-; CHECK-NEXT: vmvn.i32 d18, #0x7fff
+; CHECK-NEXT: vmvn.i32 d17, #0x7fff
+; CHECK-NEXT: vmov.i32 d18, #0x7fff
; CHECK-NEXT: vmov.32 d16[0], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.32 d16[1], r0
-; CHECK-NEXT: vmin.s32 d16, d16, d17
-; CHECK-NEXT: vmax.s32 d0, d16, d18
+; CHECK-NEXT: vmax.s32 d16, d16, d17
+; CHECK-NEXT: vmin.s32 d0, d16, d18
; CHECK-NEXT: bx lr
entry:
%conv = fptosi <2 x double> %x to <2 x i32>
@@ -1189,13 +1189,13 @@ define <2 x i16> @ustest_f64i16(<2 x double> %x) {
; CHECK-NEXT: vcvt.s32.f64 s4, d0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vcvt.s32.f64 s0, d1
-; CHECK-NEXT: vmov.i32 d17, #0xffff
-; CHECK-NEXT: vmov.i32 d18, #0x0
+; CHECK-NEXT: vmov.i32 d17, #0x0
+; CHECK-NEXT: vmov.i32 d18, #0xffff
; CHECK-NEXT: vmov.32 d16[0], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.32 d16[1], r0
-; CHECK-NEXT: vmin.s32 d16, d16, d17
-; CHECK-NEXT: vmax.s32 d0, d16, d18
+; CHECK-NEXT: vmax.s32 d16, d16, d17
+; CHECK-NEXT: vmin.s32 d0, d16, d18
; CHECK-NEXT: bx lr
entry:
%conv = fptosi <2 x double> %x to <2 x i32>
@@ -1211,10 +1211,10 @@ define <4 x i16> @stest_f32i16(<4 x float> %x) {
; CHECK-LABEL: stest_f32i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcvt.s32.f32 q8, q0
-; CHECK-NEXT: vmov.i32 q9, #0x7fff
-; CHECK-NEXT: vmvn.i32 q10, #0x7fff
-; CHECK-NEXT: vmin.s32 q8, q8, q9
-; CHECK-NEXT: vmax.s32 q8, q8, q10
+; CHECK-NEXT: vmvn.i32 q9, #0x7fff
+; CHECK-NEXT: vmov.i32 q10, #0x7fff
+; CHECK-NEXT: vmax.s32 q8, q8, q9
+; CHECK-NEXT: vmin.s32 q8, q8, q10
; CHECK-NEXT: vmovn.i32 d0, q8
; CHECK-NEXT: bx lr
entry:
@@ -1247,10 +1247,10 @@ define <4 x i16> @ustest_f32i16(<4 x float> %x) {
; CHECK-LABEL: ustest_f32i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcvt.s32.f32 q8, q0
-; CHECK-NEXT: vmov.i32 q9, #0xffff
-; CHECK-NEXT: vmov.i32 q10, #0x0
-; CHECK-NEXT: vmin.s32 q8, q8, q9
-; CHECK-NEXT: vmax.s32 q8, q8, q10
+; CHECK-NEXT: vmov.i32 q9, #0x0
+; CHECK-NEXT: vmov.i32 q10, #0xffff
+; CHECK-NEXT: vmax.s32 q8, q8, q9
+; CHECK-NEXT: vmin.s32 q8, q8, q10
; CHECK-NEXT: vmovn.i32 d0, q8
; CHECK-NEXT: bx lr
entry:
@@ -1321,22 +1321,22 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) {
; CHECK-NEON-NEXT: vmov r0, s20
; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0
; CHECK-NEON-NEXT: vmov s2, r4
-; CHECK-NEON-NEXT: vmov.i32 q8, #0x7fff
+; CHECK-NEON-NEXT: vmvn.i32 q8, #0x7fff
; CHECK-NEON-NEXT: vcvt.s32.f32 s2, s2
-; CHECK-NEON-NEXT: vmvn.i32 q9, #0x7fff
+; CHECK-NEON-NEXT: vmov.i32 q9, #0x7fff
; CHECK-NEON-NEXT: vmov.32 d9[0], r0
; CHECK-NEON-NEXT: vmov r0, s0
; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s22
; CHECK-NEON-NEXT: vmov.32 d12[1], r0
; CHECK-NEON-NEXT: vmov r0, s0
-; CHECK-NEON-NEXT: vmin.s32 q10, q6, q8
-; CHECK-NEON-NEXT: vmax.s32 q10, q10, q9
+; CHECK-NEON-NEXT: vmax.s32 q10, q6, q8
+; CHECK-NEON-NEXT: vmin.s32 q10, q10, q9
; CHECK-NEON-NEXT: vmov.32 d9[1], r0
; CHECK-NEON-NEXT: vmov r0, s2
; CHECK-NEON-NEXT: vmovn.i32 d1, q10
; CHECK-NEON-NEXT: vmov.32 d8[1], r0
-; CHECK-NEON-NEXT: vmin.s32 q8, q4, q8
-; CHECK-NEON-NEXT: vmax.s32 q8, q8, q9
+; CHECK-NEON-NEXT: vmax.s32 q8, q4, q8
+; CHECK-NEON-NEXT: vmin.s32 q8, q8, q9
; CHECK-NEON-NEXT: vmovn.i32 d0, q8
; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r11, pc}
@@ -1356,8 +1356,8 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) {
; CHECK-FP16-NEXT: vmovx.f16 s6, s1
; CHECK-FP16-NEXT: vcvt.s32.f16 s4, s4
; CHECK-FP16-NEXT: vcvt.s32.f16 s6, s6
-; CHECK-FP16-NEXT: vmov.i32 q10, #0x7fff
-; CHECK-FP16-NEXT: vmvn.i32 q11, #0x7fff
+; CHECK-FP16-NEXT: vmvn.i32 q10, #0x7fff
+; CHECK-FP16-NEXT: vmov.i32 q11, #0x7fff
; CHECK-FP16-NEXT: vmov.32 d17[0], r0
; CHECK-FP16-NEXT: vmov r0, s5
; CHECK-FP16-NEXT: vmov.32 d16[0], r0
@@ -1370,14 +1370,14 @@ define <8 x i16> @stest_f16i16(<8 x half> %x) {
; CHECK-FP16-NEXT: vmov r0, s8
; CHECK-FP16-NEXT: vmov.32 d16[1], r0
; CHECK-FP16-NEXT: vmov r0, s6
-; CHECK-FP16-NEXT: vmin.s32 q8, q8, q10
-; CHECK-FP16-NEXT: vmax.s32 q8, q8, q11
+; CHECK-FP16-NEXT: vmax.s32 q8, q8, q10
+; CHECK-FP16-NEXT: vmin.s32 q8, q8, q11
; CHECK-FP16-NEXT: vmovn.i32 d1, q8
; CHECK-FP16-NEXT: vmov.32 d19[1], r0
; CHECK-FP16-NEXT: vmov r0, s4
; CHECK-FP16-NEXT: vmov.32 d18[1], r0
-; CHECK-FP16-NEXT: vmin.s32 q9, q9, q10
-; CHECK-FP16-NEXT: vmax.s32 q9, q9, q11
+; CHECK-FP16-NEXT: vmax.s32 q9, q9, q10
+; CHECK-FP16-NEXT: vmin.s32 q9, q9, q11
; CHECK-FP16-NEXT: vmovn.i32 d0, q9
; CHECK-FP16-NEXT: bx lr
entry:
@@ -1567,22 +1567,22 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) {
; CHECK-NEON-NEXT: vmov r0, s20
; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0
; CHECK-NEON-NEXT: vmov s2, r4
-; CHECK-NEON-NEXT: vmov.i32 q8, #0xffff
+; CHECK-NEON-NEXT: vmov.i32 q8, #0x0
; CHECK-NEON-NEXT: vcvt.s32.f32 s2, s2
-; CHECK-NEON-NEXT: vmov.i32 q9, #0x0
+; CHECK-NEON-NEXT: vmov.i32 q9, #0xffff
; CHECK-NEON-NEXT: vmov.32 d9[0], r0
; CHECK-NEON-NEXT: vmov r0, s0
; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s22
; CHECK-NEON-NEXT: vmov.32 d12[1], r0
; CHECK-NEON-NEXT: vmov r0, s0
-; CHECK-NEON-NEXT: vmin.s32 q10, q6, q8
-; CHECK-NEON-NEXT: vmax.s32 q10, q10, q9
+; CHECK-NEON-NEXT: vmax.s32 q10, q6, q8
+; CHECK-NEON-NEXT: vmin.s32 q10, q10, q9
; CHECK-NEON-NEXT: vmov.32 d9[1], r0
; CHECK-NEON-NEXT: vmov r0, s2
; CHECK-NEON-NEXT: vmovn.i32 d1, q10
; CHECK-NEON-NEXT: vmov.32 d8[1], r0
-; CHECK-NEON-NEXT: vmin.s32 q8, q4, q8
-; CHECK-NEON-NEXT: vmax.s32 q8, q8, q9
+; CHECK-NEON-NEXT: vmax.s32 q8, q4, q8
+; CHECK-NEON-NEXT: vmin.s32 q8, q8, q9
; CHECK-NEON-NEXT: vmovn.i32 d0, q8
; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r11, pc}
@@ -1602,8 +1602,8 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) {
; CHECK-FP16-NEXT: vmovx.f16 s6, s1
; CHECK-FP16-NEXT: vcvt.s32.f16 s4, s4
; CHECK-FP16-NEXT: vcvt.s32.f16 s6, s6
-; CHECK-FP16-NEXT: vmov.i32 q10, #0xffff
-; CHECK-FP16-NEXT: vmov.i32 q11, #0x0
+; CHECK-FP16-NEXT: vmov.i32 q10, #0x0
+; CHECK-FP16-NEXT: vmov.i32 q11, #0xffff
; CHECK-FP16-NEXT: vmov.32 d17[0], r0
; CHECK-FP16-NEXT: vmov r0, s5
; CHECK-FP16-NEXT: vmov.32 d16[0], r0
@@ -1616,14 +1616,14 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) {
; CHECK-FP16-NEXT: vmov r0, s8
; CHECK-FP16-NEXT: vmov.32 d16[1], r0
; CHECK-FP16-NEXT: vmov r0, s6
-; CHECK-FP16-NEXT: vmin.s32 q8, q8, q10
-; CHECK-FP16-NEXT: vmax.s32 q8, q8, q11
+; CHECK-FP16-NEXT: vmax.s32 q8, q8, q10
+; CHECK-FP16-NEXT: vmin.s32 q8, q8, q11
; CHECK-FP16-NEXT: vmovn.i32 d1, q8
; CHECK-FP16-NEXT: vmov.32 d19[1], r0
; CHECK-FP16-NEXT: vmov r0, s4
; CHECK-FP16-NEXT: vmov.32 d18[1], r0
-; CHECK-FP16-NEXT: vmin.s32 q9, q9, q10
-; CHECK-FP16-NEXT: vmax.s32 q9, q9, q11
+; CHECK-FP16-NEXT: vmax.s32 q9, q9, q10
+; CHECK-FP16-NEXT: vmin.s32 q9, q9, q11
; CHECK-FP16-NEXT: vmovn.i32 d0, q9
; CHECK-FP16-NEXT: bx lr
entry:
@@ -2342,44 +2342,38 @@ entry:
define <2 x i32> @stest_f64i32_mm(<2 x double> %x) {
; CHECK-LABEL: stest_f64i32_mm:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vorr q4, q0, q0
; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: bl __aeabi_d2lz
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: mov r8, r1
-; CHECK-NEXT: vmov r0, r1, d9
-; CHECK-NEXT: mvn r6, #-2147483648
-; CHECK-NEXT: subs r2, r4, r6
-; CHECK-NEXT: mov r5, #0
-; CHECK-NEXT: sbcs r2, r8, #0
-; CHECK-NEXT: mov r7, #0
+; CHECK-NEXT: vmov r0, r2, d9
+; CHECK-NEXT: rsbs r3, r4, #-2147483648
+; CHECK-NEXT: mvn r5, #0
+; CHECK-NEXT: sbcs r3, r5, r1
+; CHECK-NEXT: mov r6, #-2147483648
+; CHECK-NEXT: movge r1, r5
; CHECK-NEXT: movge r4, r6
-; CHECK-NEXT: movwlt r5, #1
+; CHECK-NEXT: mvn r7, #-2147483648
+; CHECK-NEXT: subs r3, r4, r7
+; CHECK-NEXT: sbcs r1, r1, #0
+; CHECK-NEXT: movge r4, r7
+; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: bl __aeabi_d2lz
-; CHECK-NEXT: subs r2, r0, r6
-; CHECK-NEXT: sbcs r2, r1, #0
-; CHECK-NEXT: movlt r6, r0
-; CHECK-NEXT: movwlt r7, #1
-; CHECK-NEXT: cmp r7, #0
-; CHECK-NEXT: mov r0, #-2147483648
-; CHECK-NEXT: movne r7, r1
-; CHECK-NEXT: cmp r5, #0
-; CHECK-NEXT: movne r5, r8
-; CHECK-NEXT: rsbs r2, r4, #-2147483648
-; CHECK-NEXT: mvn r1, #0
-; CHECK-NEXT: sbcs r2, r1, r5
-; CHECK-NEXT: movge r4, r0
-; CHECK-NEXT: rsbs r2, r6, #-2147483648
+; CHECK-NEXT: rsbs r2, r0, #-2147483648
; CHECK-NEXT: vmov.32 d0[0], r4
-; CHECK-NEXT: sbcs r1, r1, r7
-; CHECK-NEXT: movge r6, r0
+; CHECK-NEXT: sbcs r2, r5, r1
+; CHECK-NEXT: movlt r5, r1
+; CHECK-NEXT: movlt r6, r0
+; CHECK-NEXT: subs r0, r6, r7
+; CHECK-NEXT: sbcs r0, r5, #0
+; CHECK-NEXT: movge r6, r7
; CHECK-NEXT: vmov.32 d0[1], r6
; CHECK-NEXT: vpop {d8, d9}
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
entry:
%conv = fptosi <2 x double> %x to <2 x i64>
%spec.store.select = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %conv, <2 x i64> <i64 2147483647, i64 2147483647>)
@@ -2429,39 +2423,33 @@ define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) {
; CHECK-NEXT: vorr q4, q0, q0
; CHECK-NEXT: vmov r0, r1, d8
; CHECK-NEXT: bl __aeabi_d2lz
-; CHECK-NEXT: vmov r2, r12, d9
-; CHECK-NEXT: mvn r4, #0
-; CHECK-NEXT: subs r5, r0, r4
-; CHECK-NEXT: mov r3, #0
-; CHECK-NEXT: sbcs r5, r1, #0
-; CHECK-NEXT: mov r6, #0
-; CHECK-NEXT: movge r0, r4
-; CHECK-NEXT: movwlt r3, #1
-; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: vmov r2, r3, d9
+; CHECK-NEXT: rsbs r5, r0, #0
+; CHECK-NEXT: rscs r5, r1, #0
+; CHECK-NEXT: mvn r6, #0
; CHECK-NEXT: mov r5, #0
-; CHECK-NEXT: movne r3, r1
-; CHECK-NEXT: rsbs r1, r0, #0
-; CHECK-NEXT: rscs r1, r3, #0
-; CHECK-NEXT: movwlt r6, #1
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: movne r6, r0
-; CHECK-NEXT: mov r0, r2
-; CHECK-NEXT: mov r1, r12
-; CHECK-NEXT: bl __aeabi_d2lz
-; CHECK-NEXT: subs r2, r0, r4
-; CHECK-NEXT: vmov.32 d0[0], r6
-; CHECK-NEXT: sbcs r2, r1, #0
-; CHECK-NEXT: movlt r4, r0
-; CHECK-NEXT: mov r0, #0
-; CHECK-NEXT: movwlt r0, #1
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: movne r0, r1
-; CHECK-NEXT: rsbs r1, r4, #0
-; CHECK-NEXT: rscs r0, r0, #0
+; CHECK-NEXT: mov r4, #0
; CHECK-NEXT: movwlt r5, #1
; CHECK-NEXT: cmp r5, #0
-; CHECK-NEXT: movne r5, r4
-; CHECK-NEXT: vmov.32 d0[1], r5
+; CHECK-NEXT: moveq r1, r5
+; CHECK-NEXT: movne r5, r0
+; CHECK-NEXT: subs r0, r5, r6
+; CHECK-NEXT: sbcs r0, r1, #0
+; CHECK-NEXT: movge r5, r6
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: mov r1, r3
+; CHECK-NEXT: bl __aeabi_d2lz
+; CHECK-NEXT: rsbs r2, r0, #0
+; CHECK-NEXT: vmov.32 d0[0], r5
+; CHECK-NEXT: rscs r2, r1, #0
+; CHECK-NEXT: movwlt r4, #1
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: moveq r1, r4
+; CHECK-NEXT: movne r4, r0
+; CHECK-NEXT: subs r0, r4, r6
+; CHECK-NEXT: sbcs r0, r1, #0
+; CHECK-NEXT: movge r4, r6
+; CHECK-NEXT: vmov.32 d0[1], r4
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r6, pc}
entry:
@@ -2475,81 +2463,61 @@ entry:
define <4 x i32> @stest_f32i32_mm(<4 x float> %x) {
; CHECK-LABEL: stest_f32i32_mm:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: .pad #4
-; CHECK-NEXT: sub sp, sp, #4
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #8
-; CHECK-NEXT: sub sp, sp, #8
; CHECK-NEXT: vorr q4, q0, q0
+; CHECK-NEXT: mvn r7, #0
; CHECK-NEXT: vmov r0, s19
+; CHECK-NEXT: vmov r5, s16
+; CHECK-NEXT: vmov r6, s18
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vmov r2, s18
-; CHECK-NEXT: mov r11, r0
-; CHECK-NEXT: vmov r0, s17
-; CHECK-NEXT: mvn r6, #-2147483648
-; CHECK-NEXT: mov r3, #-2147483648
-; CHECK-NEXT: mvn r10, #0
-; CHECK-NEXT: vmov r7, s16
-; CHECK-NEXT: mov r4, #0
-; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT: subs r2, r11, r6
-; CHECK-NEXT: sbcs r2, r1, #0
-; CHECK-NEXT: mov r2, #0
-; CHECK-NEXT: movge r11, r6
-; CHECK-NEXT: movwlt r2, #1
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: movne r2, r1
-; CHECK-NEXT: rsbs r1, r11, #-2147483648
-; CHECK-NEXT: sbcs r1, r10, r2
-; CHECK-NEXT: movge r11, r3
+; CHECK-NEXT: mov r8, r0
+; CHECK-NEXT: rsbs r0, r0, #-2147483648
+; CHECK-NEXT: sbcs r0, r7, r1
+; CHECK-NEXT: mov r4, #-2147483648
+; CHECK-NEXT: movge r1, r7
+; CHECK-NEXT: movge r8, r4
+; CHECK-NEXT: mvn r9, #-2147483648
+; CHECK-NEXT: subs r0, r8, r9
+; CHECK-NEXT: sbcs r0, r1, #0
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: movge r8, r9
; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: mov r5, r0
-; CHECK-NEXT: subs r0, r0, r6
+; CHECK-NEXT: rsbs r0, r0, #-2147483648
+; CHECK-NEXT: sbcs r0, r7, r1
+; CHECK-NEXT: movge r1, r7
+; CHECK-NEXT: movge r5, r4
+; CHECK-NEXT: subs r0, r5, r9
; CHECK-NEXT: sbcs r0, r1, #0
-; CHECK-NEXT: mov r9, #0
-; CHECK-NEXT: mov r0, r7
-; CHECK-NEXT: movge r5, r6
-; CHECK-NEXT: movwlt r9, #1
-; CHECK-NEXT: cmp r9, #0
-; CHECK-NEXT: movne r9, r1
+; CHECK-NEXT: mov r0, r6
+; CHECK-NEXT: movge r5, r9
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: subs r0, r0, r6
-; CHECK-NEXT: sbcs r0, r1, #0
-; CHECK-NEXT: mov r8, #0
-; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: movge r7, r6
-; CHECK-NEXT: movwlt r8, #1
-; CHECK-NEXT: cmp r8, #0
-; CHECK-NEXT: movne r8, r1
+; CHECK-NEXT: mov r6, r0
+; CHECK-NEXT: rsbs r0, r0, #-2147483648
+; CHECK-NEXT: sbcs r0, r7, r1
+; CHECK-NEXT: vmov r0, s17
+; CHECK-NEXT: movge r1, r7
+; CHECK-NEXT: movge r6, r4
+; CHECK-NEXT: subs r2, r6, r9
+; CHECK-NEXT: sbcs r1, r1, #0
+; CHECK-NEXT: movge r6, r9
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: subs r2, r0, r6
-; CHECK-NEXT: sbcs r2, r1, #0
-; CHECK-NEXT: movlt r6, r0
-; CHECK-NEXT: movwlt r4, #1
-; CHECK-NEXT: cmp r4, #0
-; CHECK-NEXT: movne r4, r1
-; CHECK-NEXT: rsbs r0, r6, #-2147483648
-; CHECK-NEXT: sbcs r0, r10, r4
-; CHECK-NEXT: mov r1, #-2147483648
-; CHECK-NEXT: movge r6, r1
-; CHECK-NEXT: rsbs r0, r7, #-2147483648
-; CHECK-NEXT: sbcs r0, r10, r8
+; CHECK-NEXT: rsbs r2, r0, #-2147483648
; CHECK-NEXT: vmov.32 d1[0], r6
-; CHECK-NEXT: movge r7, r1
-; CHECK-NEXT: rsbs r0, r5, #-2147483648
-; CHECK-NEXT: vmov.32 d0[0], r7
-; CHECK-NEXT: sbcs r0, r10, r9
-; CHECK-NEXT: movge r5, r1
-; CHECK-NEXT: vmov.32 d1[1], r11
-; CHECK-NEXT: vmov.32 d0[1], r5
-; CHECK-NEXT: add sp, sp, #8
+; CHECK-NEXT: sbcs r2, r7, r1
+; CHECK-NEXT: movlt r7, r1
+; CHECK-NEXT: movlt r4, r0
+; CHECK-NEXT: subs r0, r4, r9
+; CHECK-NEXT: vmov.32 d0[0], r5
+; CHECK-NEXT: sbcs r0, r7, #0
+; CHECK-NEXT: vmov.32 d1[1], r8
+; CHECK-NEXT: movge r4, r9
+; CHECK-NEXT: vmov.32 d0[1], r4
; CHECK-NEXT: vpop {d8, d9}
-; CHECK-NEXT: add sp, sp, #4
-; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
entry:
%conv = fptosi <4 x float> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
@@ -2615,71 +2583,59 @@ define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {
; CHECK-NEXT: vmov r0, s19
; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: vmov r2, s16
-; CHECK-NEXT: mvn r6, #0
-; CHECK-NEXT: subs r3, r0, r6
-; CHECK-NEXT: mov r4, #0
-; CHECK-NEXT: sbcs r3, r1, #0
-; CHECK-NEXT: vmov r8, s17
-; CHECK-NEXT: mov r3, #0
-; CHECK-NEXT: movge r0, r6
-; CHECK-NEXT: movwlt r3, #1
-; CHECK-NEXT: cmp r3, #0
-; CHECK-NEXT: movne r3, r1
-; CHECK-NEXT: rsbs r1, r0, #0
-; CHECK-NEXT: rscs r1, r3, #0
+; CHECK-NEXT: rsbs r3, r0, #0
+; CHECK-NEXT: rscs r3, r1, #0
+; CHECK-NEXT: mov r7, #0
+; CHECK-NEXT: movwlt r7, #1
+; CHECK-NEXT: cmp r7, #0
+; CHECK-NEXT: moveq r1, r7
+; CHECK-NEXT: movne r7, r0
+; CHECK-NEXT: mvn r10, #0
+; CHECK-NEXT: subs r0, r7, r10
+; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: vmov r9, s18
-; CHECK-NEXT: movwlt r4, #1
-; CHECK-NEXT: cmp r4, #0
-; CHECK-NEXT: movne r4, r0
-; CHECK-NEXT: mov r10, #0
+; CHECK-NEXT: mov r6, #0
+; CHECK-NEXT: vmov r8, s17
+; CHECK-NEXT: movge r7, r10
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: subs r2, r0, r6
+; CHECK-NEXT: rsbs r2, r0, #0
; CHECK-NEXT: mov r5, #0
-; CHECK-NEXT: sbcs r2, r1, #0
-; CHECK-NEXT: mov r2, #0
-; CHECK-NEXT: movge r0, r6
-; CHECK-NEXT: movwlt r2, #1
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: movne r2, r1
-; CHECK-NEXT: rsbs r1, r0, #0
-; CHECK-NEXT: rscs r1, r2, #0
+; CHECK-NEXT: rscs r2, r1, #0
; CHECK-NEXT: movwlt r5, #1
; CHECK-NEXT: cmp r5, #0
+; CHECK-NEXT: moveq r1, r5
; CHECK-NEXT: movne r5, r0
+; CHECK-NEXT: subs r0, r5, r10
+; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: movge r5, r10
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: subs r2, r0, r6
-; CHECK-NEXT: mov r7, #0
-; CHECK-NEXT: sbcs r2, r1, #0
-; CHECK-NEXT: mov r2, #0
-; CHECK-NEXT: movge r0, r6
-; CHECK-NEXT: movwlt r2, #1
-; CHECK-NEXT: cmp r2, #0
-; CHECK-NEXT: movne r2, r1
-; CHECK-NEXT: rsbs r1, r0, #0
-; CHECK-NEXT: rscs r1, r2, #0
-; CHECK-NEXT: movwlt r7, #1
-; CHECK-NEXT: cmp r7, #0
-; CHECK-NEXT: movne r7, r0
+; CHECK-NEXT: rsbs r2, r0, #0
+; CHECK-NEXT: mov r4, #0
+; CHECK-NEXT: rscs r2, r1, #0
+; CHECK-NEXT: movwlt r4, #1
+; CHECK-NEXT: cmp r4, #0
+; CHECK-NEXT: moveq r1, r4
+; CHECK-NEXT: movne r4, r0
+; CHECK-NEXT: subs r0, r4, r10
+; CHECK-NEXT: sbcs r0, r1, #0
; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: movge r4, r10
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: subs r2, r0, r6
-; CHECK-NEXT: vmov.32 d1[0], r7
-; CHECK-NEXT: sbcs r2, r1, #0
-; CHECK-NEXT: movlt r6, r0
-; CHECK-NEXT: mov r0, #0
-; CHECK-NEXT: movwlt r0, #1
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: movne r0, r1
-; CHECK-NEXT: rsbs r1, r6, #0
-; CHECK-NEXT: rscs r0, r0, #0
+; CHECK-NEXT: rsbs r2, r0, #0
+; CHECK-NEXT: vmov.32 d1[0], r4
+; CHECK-NEXT: rscs r2, r1, #0
+; CHECK-NEXT: movwlt r6, #1
+; CHECK-NEXT: cmp r6, #0
+; CHECK-NEXT: moveq r1, r6
+; CHECK-NEXT: movne r6, r0
+; CHECK-NEXT: subs r0, r6, r10
; CHECK-NEXT: vmov.32 d0[0], r5
-; CHECK-NEXT: movwlt r10, #1
-; CHECK-NEXT: cmp r10, #0
-; CHECK-NEXT: vmov.32 d1[1], r4
-; CHECK-NEXT: movne r10, r6
-; CHECK-NEXT: vmov.32 d0[1], r10
+; CHECK-NEXT: sbcs r0, r1, #0
+; CHECK-NEXT: vmov.32 d1[1], r7
+; CHECK-NEXT: movge r6, r10
+; CHECK-NEXT: vmov.32 d0[1], r6
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
entry:
@@ -2693,164 +2649,128 @@ entry:
define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
; CHECK-NEON-LABEL: stest_f16i32_mm:
; CHECK-NEON: @ %bb.0: @ %entry
-; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEON-NEXT: .pad #4
-; CHECK-NEON-NEXT: sub sp, sp, #4
+; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
; CHECK-NEON-NEXT: .vsave {d8, d9, d10}
; CHECK-NEON-NEXT: vpush {d8, d9, d10}
-; CHECK-NEON-NEXT: .pad #8
-; CHECK-NEON-NEXT: sub sp, sp, #8
; CHECK-NEON-NEXT: vmov r0, s3
-; CHECK-NEON-NEXT: vmov.f32 s16, s2
-; CHECK-NEON-NEXT: vmov.f32 s18, s1
+; CHECK-NEON-NEXT: vmov.f32 s18, s2
+; CHECK-NEON-NEXT: vmov.f32 s16, s1
; CHECK-NEON-NEXT: vmov.f32 s20, s0
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: vmov r2, s16
-; CHECK-NEON-NEXT: mov r11, r0
-; CHECK-NEON-NEXT: vmov r0, s18
-; CHECK-NEON-NEXT: mvn r6, #-2147483648
-; CHECK-NEON-NEXT: mov r3, #-2147483648
-; CHECK-NEON-NEXT: mvn r10, #0
-; CHECK-NEON-NEXT: vmov r7, s20
-; CHECK-NEON-NEXT: mov r4, #0
-; CHECK-NEON-NEXT: str r2, [sp, #4] @ 4-byte Spill
-; CHECK-NEON-NEXT: subs r2, r11, r6
-; CHECK-NEON-NEXT: sbcs r2, r1, #0
-; CHECK-NEON-NEXT: mov r2, #0
-; CHECK-NEON-NEXT: movge r11, r6
-; CHECK-NEON-NEXT: movwlt r2, #1
-; CHECK-NEON-NEXT: cmp r2, #0
-; CHECK-NEON-NEXT: movne r2, r1
-; CHECK-NEON-NEXT: rsbs r1, r11, #-2147483648
-; CHECK-NEON-NEXT: sbcs r1, r10, r2
-; CHECK-NEON-NEXT: movge r11, r3
+; CHECK-NEON-NEXT: mov r8, r0
+; CHECK-NEON-NEXT: vmov r0, s20
+; CHECK-NEON-NEXT: rsbs r2, r8, #-2147483648
+; CHECK-NEON-NEXT: mvn r4, #0
+; CHECK-NEON-NEXT: sbcs r2, r4, r1
+; CHECK-NEON-NEXT: mov r7, #-2147483648
+; CHECK-NEON-NEXT: movge r1, r4
+; CHECK-NEON-NEXT: movge r8, r7
+; CHECK-NEON-NEXT: mvn r9, #-2147483648
+; CHECK-NEON-NEXT: subs r2, r8, r9
+; CHECK-NEON-NEXT: sbcs r1, r1, #0
+; CHECK-NEON-NEXT: vmov r6, s18
+; CHECK-NEON-NEXT: movge r8, r9
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
; CHECK-NEON-NEXT: mov r5, r0
-; CHECK-NEON-NEXT: subs r0, r0, r6
+; CHECK-NEON-NEXT: rsbs r0, r0, #-2147483648
+; CHECK-NEON-NEXT: sbcs r0, r4, r1
+; CHECK-NEON-NEXT: movge r1, r4
+; CHECK-NEON-NEXT: movge r5, r7
+; CHECK-NEON-NEXT: subs r0, r5, r9
; CHECK-NEON-NEXT: sbcs r0, r1, #0
-; CHECK-NEON-NEXT: mov r8, #0
-; CHECK-NEON-NEXT: mov r0, r7
-; CHECK-NEON-NEXT: movge r5, r6
-; CHECK-NEON-NEXT: movwlt r8, #1
-; CHECK-NEON-NEXT: cmp r8, #0
-; CHECK-NEON-NEXT: movne r8, r1
+; CHECK-NEON-NEXT: mov r0, r6
+; CHECK-NEON-NEXT: movge r5, r9
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: mov r7, r0
-; CHECK-NEON-NEXT: subs r0, r0, r6
-; CHECK-NEON-NEXT: sbcs r0, r1, #0
-; CHECK-NEON-NEXT: mov r9, #0
-; CHECK-NEON-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
-; CHECK-NEON-NEXT: movge r7, r6
-; CHECK-NEON-NEXT: movwlt r9, #1
-; CHECK-NEON-NEXT: cmp r9, #0
-; CHECK-NEON-NEXT: movne r9, r1
+; CHECK-NEON-NEXT: mov r6, r0
+; CHECK-NEON-NEXT: rsbs r0, r0, #-2147483648
+; CHECK-NEON-NEXT: sbcs r0, r4, r1
+; CHECK-NEON-NEXT: vmov r0, s16
+; CHECK-NEON-NEXT: movge r1, r4
+; CHECK-NEON-NEXT: movge r6, r7
+; CHECK-NEON-NEXT: subs r2, r6, r9
+; CHECK-NEON-NEXT: sbcs r1, r1, #0
+; CHECK-NEON-NEXT: movge r6, r9
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: subs r2, r0, r6
-; CHECK-NEON-NEXT: sbcs r2, r1, #0
-; CHECK-NEON-NEXT: movlt r6, r0
-; CHECK-NEON-NEXT: movwlt r4, #1
-; CHECK-NEON-NEXT: cmp r4, #0
-; CHECK-NEON-NEXT: movne r4, r1
-; CHECK-NEON-NEXT: rsbs r0, r6, #-2147483648
-; CHECK-NEON-NEXT: sbcs r0, r10, r4
-; CHECK-NEON-NEXT: mov r1, #-2147483648
-; CHECK-NEON-NEXT: movge r6, r1
-; CHECK-NEON-NEXT: rsbs r0, r7, #-2147483648
-; CHECK-NEON-NEXT: sbcs r0, r10, r9
+; CHECK-NEON-NEXT: rsbs r2, r0, #-2147483648
; CHECK-NEON-NEXT: vmov.32 d1[0], r6
-; CHECK-NEON-NEXT: movge r7, r1
-; CHECK-NEON-NEXT: rsbs r0, r5, #-2147483648
-; CHECK-NEON-NEXT: vmov.32 d0[0], r7
-; CHECK-NEON-NEXT: sbcs r0, r10, r8
-; CHECK-NEON-NEXT: movge r5, r1
-; CHECK-NEON-NEXT: vmov.32 d1[1], r11
-; CHECK-NEON-NEXT: vmov.32 d0[1], r5
-; CHECK-NEON-NEXT: add sp, sp, #8
+; CHECK-NEON-NEXT: sbcs r2, r4, r1
+; CHECK-NEON-NEXT: movlt r4, r1
+; CHECK-NEON-NEXT: movlt r7, r0
+; CHECK-NEON-NEXT: subs r0, r7, r9
+; CHECK-NEON-NEXT: vmov.32 d0[0], r5
+; CHECK-NEON-NEXT: sbcs r0, r4, #0
+; CHECK-NEON-NEXT: vmov.32 d1[1], r8
+; CHECK-NEON-NEXT: movge r7, r9
+; CHECK-NEON-NEXT: vmov.32 d0[1], r7
; CHECK-NEON-NEXT: vpop {d8, d9, d10}
-; CHECK-NEON-NEXT: add sp, sp, #4
-; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
;
; CHECK-FP16-LABEL: stest_f16i32_mm:
; CHECK-FP16: @ %bb.0: @ %entry
-; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-FP16-NEXT: .pad #4
-; CHECK-FP16-NEXT: sub sp, sp, #4
+; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r8, r9, r11, lr}
; CHECK-FP16-NEXT: .vsave {d8, d9}
; CHECK-FP16-NEXT: vpush {d8, d9}
; CHECK-FP16-NEXT: vmov.u16 r0, d0[3]
-; CHECK-FP16-NEXT: vmov.u16 r4, d0[2]
-; CHECK-FP16-NEXT: vmov.u16 r5, d0[0]
-; CHECK-FP16-NEXT: vmov.u16 r6, d0[1]
+; CHECK-FP16-NEXT: vorr d8, d0, d0
+; CHECK-FP16-NEXT: vmov.u16 r4, d0[0]
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfdi
-; CHECK-FP16-NEXT: mov r10, r0
-; CHECK-FP16-NEXT: mvn r7, #-2147483648
-; CHECK-FP16-NEXT: subs r0, r0, r7
-; CHECK-FP16-NEXT: vmov s0, r6
+; CHECK-FP16-NEXT: mov r8, r0
+; CHECK-FP16-NEXT: vmov.u16 r0, d8[1]
+; CHECK-FP16-NEXT: vmov.u16 r2, d8[2]
+; CHECK-FP16-NEXT: vmov s0, r4
+; CHECK-FP16-NEXT: mvn r7, #0
+; CHECK-FP16-NEXT: mov r4, #-2147483648
+; CHECK-FP16-NEXT: mvn r9, #-2147483648
+; CHECK-FP16-NEXT: vmov s16, r0
+; CHECK-FP16-NEXT: rsbs r0, r8, #-2147483648
+; CHECK-FP16-NEXT: sbcs r0, r7, r1
+; CHECK-FP16-NEXT: vmov s18, r2
+; CHECK-FP16-NEXT: movge r1, r7
+; CHECK-FP16-NEXT: movge r8, r4
+; CHECK-FP16-NEXT: subs r0, r8, r9
; CHECK-FP16-NEXT: sbcs r0, r1, #0
-; CHECK-FP16-NEXT: mov r2, #-2147483648
-; CHECK-FP16-NEXT: mov r0, #0
-; CHECK-FP16-NEXT: movge r10, r7
-; CHECK-FP16-NEXT: movwlt r0, #1
-; CHECK-FP16-NEXT: cmp r0, #0
-; CHECK-FP16-NEXT: movne r0, r1
-; CHECK-FP16-NEXT: rsbs r1, r10, #-2147483648
-; CHECK-FP16-NEXT: mvn r9, #0
-; CHECK-FP16-NEXT: sbcs r0, r9, r0
-; CHECK-FP16-NEXT: vmov s16, r4
-; CHECK-FP16-NEXT: mov r11, #0
-; CHECK-FP16-NEXT: vmov s18, r5
-; CHECK-FP16-NEXT: movge r10, r2
+; CHECK-FP16-NEXT: movge r8, r9
; CHECK-FP16-NEXT: bl __fixhfdi
; CHECK-FP16-NEXT: vmov.f32 s0, s18
; CHECK-FP16-NEXT: mov r5, r0
-; CHECK-FP16-NEXT: subs r0, r0, r7
-; CHECK-FP16-NEXT: mov r4, #0
+; CHECK-FP16-NEXT: rsbs r0, r0, #-2147483648
+; CHECK-FP16-NEXT: sbcs r0, r7, r1
+; CHECK-FP16-NEXT: movge r1, r7
+; CHECK-FP16-NEXT: movge r5, r4
+; CHECK-FP16-NEXT: subs r0, r5, r9
; CHECK-FP16-NEXT: sbcs r0, r1, #0
-; CHECK-FP16-NEXT: movge r5, r7
-; CHECK-FP16-NEXT: movwlt r4, #1
-; CHECK-FP16-NEXT: cmp r4, #0
-; CHECK-FP16-NEXT: movne r4, r1
+; CHECK-FP16-NEXT: movge r5, r9
; CHECK-FP16-NEXT: bl __fixhfdi
; CHECK-FP16-NEXT: vmov.f32 s0, s16
; CHECK-FP16-NEXT: mov r6, r0
-; CHECK-FP16-NEXT: subs r0, r0, r7
-; CHECK-FP16-NEXT: mov r8, #0
+; CHECK-FP16-NEXT: rsbs r0, r0, #-2147483648
+; CHECK-FP16-NEXT: sbcs r0, r7, r1
+; CHECK-FP16-NEXT: movge r1, r7
+; CHECK-FP16-NEXT: movge r6, r4
+; CHECK-FP16-NEXT: subs r0, r6, r9
; CHECK-FP16-NEXT: sbcs r0, r1, #0
-; CHECK-FP16-NEXT: movge r6, r7
-; CHECK-FP16-NEXT: movwlt r8, #1
-; CHECK-FP16-NEXT: cmp r8, #0
-; CHECK-FP16-NEXT: movne r8, r1
+; CHECK-FP16-NEXT: movge r6, r9
; CHECK-FP16-NEXT: bl __fixhfdi
-; CHECK-FP16-NEXT: subs r2, r0, r7
-; CHECK-FP16-NEXT: sbcs r2, r1, #0
-; CHECK-FP16-NEXT: movlt r7, r0
-; CHECK-FP16-NEXT: movwlt r11, #1
-; CHECK-FP16-NEXT: cmp r11, #0
-; CHECK-FP16-NEXT: movne r11, r1
-; CHECK-FP16-NEXT: rsbs r0, r7, #-2147483648
-; CHECK-FP16-NEXT: sbcs r0, r9, r11
-; CHECK-FP16-NEXT: mov r1, #-2147483648
-; CHECK-FP16-NEXT: movge r7, r1
-; CHECK-FP16-NEXT: rsbs r0, r6, #-2147483648
-; CHECK-FP16-NEXT: sbcs r0, r9, r8
-; CHECK-FP16-NEXT: vmov.32 d1[0], r7
-; CHECK-FP16-NEXT: movge r6, r1
-; CHECK-FP16-NEXT: rsbs r0, r5, #-2147483648
-; CHECK-FP16-NEXT: vmov.32 d0[0], r6
-; CHECK-FP16-NEXT: sbcs r0, r9, r4
-; CHECK-FP16-NEXT: movge r5, r1
-; CHECK-FP16-NEXT: vmov.32 d1[1], r10
-; CHECK-FP16-NEXT: vmov.32 d0[1], r5
+; CHECK-FP16-NEXT: rsbs r2, r0, #-2147483648
+; CHECK-FP16-NEXT: vmov.32 d1[0], r6
+; CHECK-FP16-NEXT: sbcs r2, r7, r1
+; CHECK-FP16-NEXT: movlt r7, r1
+; CHECK-FP16-NEXT: movlt r4, r0
+; CHECK-FP16-NEXT: subs r0, r4, r9
+; CHECK-FP16-NEXT: vmov.32 d0[0], r5
+; CHECK-FP16-NEXT: sbcs r0, r7, #0
+; CHECK-FP16-NEXT: vmov.32 d1[1], r8
+; CHECK-FP16-NEXT: movge r4, r9
+; CHECK-FP16-NEXT: vmov.32 d0[1], r4
; CHECK-FP16-NEXT: vpop {d8, d9}
-; CHECK-FP16-NEXT: add sp, sp, #4
-; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, r9, r11, pc}
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
@@ -2968,74 +2888,62 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
; CHECK-NEON-NEXT: vmov r2, s20
-; CHECK-NEON-NEXT: mvn r6, #0
-; CHECK-NEON-NEXT: subs r3, r0, r6
-; CHECK-NEON-NEXT: mov r4, #0
-; CHECK-NEON-NEXT: sbcs r3, r1, #0
-; CHECK-NEON-NEXT: vmov r8, s18
-; CHECK-NEON-NEXT: mov r3, #0
-; CHECK-NEON-NEXT: movge r0, r6
-; CHECK-NEON-NEXT: movwlt r3, #1
-; CHECK-NEON-NEXT: cmp r3, #0
-; CHECK-NEON-NEXT: movne r3, r1
-; CHECK-NEON-NEXT: rsbs r1, r0, #0
-; CHECK-NEON-NEXT: rscs r1, r3, #0
+; CHECK-NEON-NEXT: rsbs r3, r0, #0
+; CHECK-NEON-NEXT: rscs r3, r1, #0
+; CHECK-NEON-NEXT: mov r7, #0
+; CHECK-NEON-NEXT: movwlt r7, #1
+; CHECK-NEON-NEXT: cmp r7, #0
+; CHECK-NEON-NEXT: moveq r1, r7
+; CHECK-NEON-NEXT: movne r7, r0
+; CHECK-NEON-NEXT: mvn r10, #0
+; CHECK-NEON-NEXT: subs r0, r7, r10
+; CHECK-NEON-NEXT: sbcs r0, r1, #0
; CHECK-NEON-NEXT: vmov r9, s16
-; CHECK-NEON-NEXT: movwlt r4, #1
-; CHECK-NEON-NEXT: cmp r4, #0
-; CHECK-NEON-NEXT: movne r4, r0
-; CHECK-NEON-NEXT: mov r10, #0
+; CHECK-NEON-NEXT: mov r6, #0
+; CHECK-NEON-NEXT: vmov r8, s18
+; CHECK-NEON-NEXT: movge r7, r10
; CHECK-NEON-NEXT: mov r0, r2
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: subs r2, r0, r6
+; CHECK-NEON-NEXT: rsbs r2, r0, #0
; CHECK-NEON-NEXT: mov r5, #0
-; CHECK-NEON-NEXT: sbcs r2, r1, #0
-; CHECK-NEON-NEXT: mov r2, #0
-; CHECK-NEON-NEXT: movge r0, r6
-; CHECK-NEON-NEXT: movwlt r2, #1
-; CHECK-NEON-NEXT: cmp r2, #0
-; CHECK-NEON-NEXT: movne r2, r1
-; CHECK-NEON-NEXT: rsbs r1, r0, #0
-; CHECK-NEON-NEXT: rscs r1, r2, #0
+; CHECK-NEON-NEXT: rscs r2, r1, #0
; CHECK-NEON-NEXT: movwlt r5, #1
; CHECK-NEON-NEXT: cmp r5, #0
+; CHECK-NEON-NEXT: moveq r1, r5
; CHECK-NEON-NEXT: movne r5, r0
+; CHECK-NEON-NEXT: subs r0, r5, r10
+; CHECK-NEON-NEXT: sbcs r0, r1, #0
; CHECK-NEON-NEXT: mov r0, r9
+; CHECK-NEON-NEXT: movge r5, r10
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: subs r2, r0, r6
-; CHECK-NEON-NEXT: mov r7, #0
-; CHECK-NEON-NEXT: sbcs r2, r1, #0
-; CHECK-NEON-NEXT: mov r2, #0
-; CHECK-NEON-NEXT: movge r0, r6
-; CHECK-NEON-NEXT: movwlt r2, #1
-; CHECK-NEON-NEXT: cmp r2, #0
-; CHECK-NEON-NEXT: movne r2, r1
-; CHECK-NEON-NEXT: rsbs r1, r0, #0
-; CHECK-NEON-NEXT: rscs r1, r2, #0
-; CHECK-NEON-NEXT: movwlt r7, #1
-; CHECK-NEON-NEXT: cmp r7, #0
-; CHECK-NEON-NEXT: movne r7, r0
+; CHECK-NEON-NEXT: rsbs r2, r0, #0
+; CHECK-NEON-NEXT: mov r4, #0
+; CHECK-NEON-NEXT: rscs r2, r1, #0
+; CHECK-NEON-NEXT: movwlt r4, #1
+; CHECK-NEON-NEXT: cmp r4, #0
+; CHECK-NEON-NEXT: moveq r1, r4
+; CHECK-NEON-NEXT: movne r4, r0
+; CHECK-NEON-NEXT: subs r0, r4, r10
+; CHECK-NEON-NEXT: sbcs r0, r1, #0
; CHECK-NEON-NEXT: mov r0, r8
+; CHECK-NEON-NEXT: movge r4, r10
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: bl __aeabi_f2lz
-; CHECK-NEON-NEXT: subs r2, r0, r6
-; CHECK-NEON-NEXT: vmov.32 d1[0], r7
-; CHECK-NEON-NEXT: sbcs r2, r1, #0
-; CHECK-NEON-NEXT: movlt r6, r0
-; CHECK-NEON-NEXT: mov r0, #0
-; CHECK-NEON-NEXT: movwlt r0, #1
-; CHECK-NEON-NEXT: cmp r0, #0
-; CHECK-NEON-NEXT: movne r0, r1
-; CHECK-NEON-NEXT: rsbs r1, r6, #0
-; CHECK-NEON-NEXT: rscs r0, r0, #0
+; CHECK-NEON-NEXT: rsbs r2, r0, #0
+; CHECK-NEON-NEXT: vmov.32 d1[0], r4
+; CHECK-NEON-NEXT: rscs r2, r1, #0
+; CHECK-NEON-NEXT: movwlt r6, #1
+; CHECK-NEON-NEXT: cmp r6, #0
+; CHECK-NEON-NEXT: moveq r1, r6
+; CHECK-NEON-NEXT: movne r6, r0
+; CHECK-NEON-NEXT: subs r0, r6, r10
; CHECK-NEON-NEXT: vmov.32 d0[0], r5
-; CHECK-NEON-NEXT: movwlt r10, #1
-; CHECK-NEON-NEXT: cmp r10, #0
-; CHECK-NEON-NEXT: vmov.32 d1[1], r4
-; CHECK-NEON-NEXT: movne r10, r6
-; CHECK-NEON-NEXT: vmov.32 d0[1], r10
+; CHECK-NEON-NEXT: sbcs r0, r1, #0
+; CHECK-NEON-NEXT: vmov.32 d1[1], r7
+; CHECK-NEON-NEXT: movge r6, r10
+; CHECK-NEON-NEXT: vmov.32 d0[1], r6
; CHECK-NEON-NEXT: vpop {d8, d9, d10}
; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
;
@@ -3051,72 +2959,60 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfdi
; CHECK-FP16-NEXT: vmov.u16 r2, d8[1]
-; CHECK-FP16-NEXT: mvn r4, #0
-; CHECK-FP16-NEXT: vmov.u16 r3, d8[2]
; CHECK-FP16-NEXT: vmov s0, r5
-; CHECK-FP16-NEXT: mov r6, #0
-; CHECK-FP16-NEXT: mov r8, #0
+; CHECK-FP16-NEXT: vmov.u16 r3, d8[2]
+; CHECK-FP16-NEXT: mov r5, #0
+; CHECK-FP16-NEXT: mvn r8, #0
+; CHECK-FP16-NEXT: mov r4, #0
; CHECK-FP16-NEXT: vmov s16, r2
-; CHECK-FP16-NEXT: subs r2, r0, r4
-; CHECK-FP16-NEXT: sbcs r2, r1, #0
+; CHECK-FP16-NEXT: rsbs r2, r0, #0
+; CHECK-FP16-NEXT: rscs r2, r1, #0
; CHECK-FP16-NEXT: vmov s18, r3
-; CHECK-FP16-NEXT: mov r2, #0
-; CHECK-FP16-NEXT: movge r0, r4
-; CHECK-FP16-NEXT: movwlt r2, #1
-; CHECK-FP16-NEXT: cmp r2, #0
-; CHECK-FP16-NEXT: movne r2, r1
-; CHECK-FP16-NEXT: rsbs r1, r0, #0
-; CHECK-FP16-NEXT: rscs r1, r2, #0
-; CHECK-FP16-NEXT: movwlt r6, #1
-; CHECK-FP16-NEXT: cmp r6, #0
-; CHECK-FP16-NEXT: movne r6, r0
+; CHECK-FP16-NEXT: movwlt r5, #1
+; CHECK-FP16-NEXT: cmp r5, #0
+; CHECK-FP16-NEXT: moveq r1, r5
+; CHECK-FP16-NEXT: movne r5, r0
+; CHECK-FP16-NEXT: subs r0, r5, r8
+; CHECK-FP16-NEXT: sbcs r0, r1, #0
+; CHECK-FP16-NEXT: movge r5, r8
; CHECK-FP16-NEXT: bl __fixhfdi
-; CHECK-FP16-NEXT: subs r2, r0, r4
; CHECK-FP16-NEXT: vmov.f32 s0, s18
-; CHECK-FP16-NEXT: sbcs r2, r1, #0
+; CHECK-FP16-NEXT: rsbs r2, r0, #0
+; CHECK-FP16-NEXT: rscs r2, r1, #0
; CHECK-FP16-NEXT: mov r7, #0
-; CHECK-FP16-NEXT: mov r2, #0
-; CHECK-FP16-NEXT: movge r0, r4
-; CHECK-FP16-NEXT: movwlt r2, #1
-; CHECK-FP16-NEXT: cmp r2, #0
-; CHECK-FP16-NEXT: movne r2, r1
-; CHECK-FP16-NEXT: rsbs r1, r0, #0
-; CHECK-FP16-NEXT: rscs r1, r2, #0
; CHECK-FP16-NEXT: movwlt r7, #1
; CHECK-FP16-NEXT: cmp r7, #0
+; CHECK-FP16-NEXT: moveq r1, r7
; CHECK-FP16-NEXT: movne r7, r0
+; CHECK-FP16-NEXT: subs r0, r7, r8
+; CHECK-FP16-NEXT: sbcs r0, r1, #0
+; CHECK-FP16-NEXT: movge r7, r8
; CHECK-FP16-NEXT: bl __fixhfdi
-; CHECK-FP16-NEXT: subs r2, r0, r4
; CHECK-FP16-NEXT: vmov.f32 s0, s16
-; CHECK-FP16-NEXT: sbcs r2, r1, #0
-; CHECK-FP16-NEXT: mov r5, #0
-; CHECK-FP16-NEXT: mov r2, #0
-; CHECK-FP16-NEXT: movge r0, r4
-; CHECK-FP16-NEXT: movwlt r2, #1
-; CHECK-FP16-NEXT: cmp r2, #0
-; CHECK-FP16-NEXT: movne r2, r1
-; CHECK-FP16-NEXT: rsbs r1, r0, #0
-; CHECK-FP16-NEXT: rscs r1, r2, #0
-; CHECK-FP16-NEXT: movwlt r5, #1
-; CHECK-FP16-NEXT: cmp r5, #0
-; CHECK-FP16-NEXT: movne r5, r0
+; CHECK-FP16-NEXT: rsbs r2, r0, #0
+; CHECK-FP16-NEXT: rscs r2, r1, #0
+; CHECK-FP16-NEXT: mov r6, #0
+; CHECK-FP16-NEXT: movwlt r6, #1
+; CHECK-FP16-NEXT: cmp r6, #0
+; CHECK-FP16-NEXT: moveq r1, r6
+; CHECK-FP16-NEXT: movne r6, r0
+; CHECK-FP16-NEXT: subs r0, r6, r8
+; CHECK-FP16-NEXT: sbcs r0, r1, #0
+; CHECK-FP16-NEXT: movge r6, r8
; CHECK-FP16-NEXT: bl __fixhfdi
-; CHECK-FP16-NEXT: subs r2, r0, r4
-; CHECK-FP16-NEXT: vmov.32 d1[0], r5
-; CHECK-FP16-NEXT: sbcs r2, r1, #0
-; CHECK-FP16-NEXT: movlt r4, r0
-; CHECK-FP16-NEXT: mov r0, #0
-; CHECK-FP16-NEXT: movwlt r0, #1
-; CHECK-FP16-NEXT: cmp r0, #0
-; CHECK-FP16-NEXT: movne r0, r1
-; CHECK-FP16-NEXT: rsbs r1, r4, #0
-; CHECK-FP16-NEXT: rscs r0, r0, #0
+; CHECK-FP16-NEXT: rsbs r2, r0, #0
+; CHECK-FP16-NEXT: vmov.32 d1[0], r6
+; CHECK-FP16-NEXT: rscs r2, r1, #0
+; CHECK-FP16-NEXT: movwlt r4, #1
+; CHECK-FP16-NEXT: cmp r4, #0
+; CHECK-FP16-NEXT: moveq r1, r4
+; CHECK-FP16-NEXT: movne r4, r0
+; CHECK-FP16-NEXT: subs r0, r4, r8
; CHECK-FP16-NEXT: vmov.32 d0[0], r7
-; CHECK-FP16-NEXT: movwlt r8, #1
-; CHECK-FP16-NEXT: cmp r8, #0
-; CHECK-FP16-NEXT: vmov.32 d1[1], r6
-; CHECK-FP16-NEXT: movne r8, r4
-; CHECK-FP16-NEXT: vmov.32 d0[1], r8
+; CHECK-FP16-NEXT: sbcs r0, r1, #0
+; CHECK-FP16-NEXT: vmov.32 d1[1], r5
+; CHECK-FP16-NEXT: movge r4, r8
+; CHECK-FP16-NEXT: vmov.32 d0[1], r4
; CHECK-FP16-NEXT: vpop {d8, d9}
; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, pc}
entry:
@@ -3135,13 +3031,13 @@ define <2 x i16> @stest_f64i16_mm(<2 x double> %x) {
; CHECK-NEXT: vcvt.s32.f64 s4, d0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vcvt.s32.f64 s0, d1
-; CHECK-NEXT: vmov.i32 d17, #0x7fff
-; CHECK-NEXT: vmvn.i32 d18, #0x7fff
+; CHECK-NEXT: vmvn.i32 d17, #0x7fff
+; CHECK-NEXT: vmov.i32 d18, #0x7fff
; CHECK-NEXT: vmov.32 d16[0], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.32 d16[1], r0
-; CHECK-NEXT: vmin.s32 d16, d16, d17
-; CHECK-NEXT: vmax.s32 d0, d16, d18
+; CHECK-NEXT: vmax.s32 d16, d16, d17
+; CHECK-NEXT: vmin.s32 d0, d16, d18
; CHECK-NEXT: bx lr
entry:
%conv = fptosi <2 x double> %x to <2 x i32>
@@ -3176,13 +3072,13 @@ define <2 x i16> @ustest_f64i16_mm(<2 x double> %x) {
; CHECK-NEXT: vcvt.s32.f64 s4, d0
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vcvt.s32.f64 s0, d1
-; CHECK-NEXT: vmov.i32 d17, #0xffff
-; CHECK-NEXT: vmov.i32 d18, #0x0
+; CHECK-NEXT: vmov.i32 d17, #0x0
+; CHECK-NEXT: vmov.i32 d18, #0xffff
; CHECK-NEXT: vmov.32 d16[0], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.32 d16[1], r0
-; CHECK-NEXT: vmin.s32 d16, d16, d17
-; CHECK-NEXT: vmax.s32 d0, d16, d18
+; CHECK-NEXT: vmax.s32 d16, d16, d17
+; CHECK-NEXT: vmin.s32 d0, d16, d18
; CHECK-NEXT: bx lr
entry:
%conv = fptosi <2 x double> %x to <2 x i32>
@@ -3196,10 +3092,10 @@ define <4 x i16> @stest_f32i16_mm(<4 x float> %x) {
; CHECK-LABEL: stest_f32i16_mm:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcvt.s32.f32 q8, q0
-; CHECK-NEXT: vmov.i32 q9, #0x7fff
-; CHECK-NEXT: vmvn.i32 q10, #0x7fff
-; CHECK-NEXT: vmin.s32 q8, q8, q9
-; CHECK-NEXT: vmax.s32 q8, q8, q10
+; CHECK-NEXT: vmvn.i32 q9, #0x7fff
+; CHECK-NEXT: vmov.i32 q10, #0x7fff
+; CHECK-NEXT: vmax.s32 q8, q8, q9
+; CHECK-NEXT: vmin.s32 q8, q8, q10
; CHECK-NEXT: vmovn.i32 d0, q8
; CHECK-NEXT: bx lr
entry:
@@ -3229,10 +3125,10 @@ define <4 x i16> @ustest_f32i16_mm(<4 x float> %x) {
; CHECK-LABEL: ustest_f32i16_mm:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vcvt.s32.f32 q8, q0
-; CHECK-NEXT: vmov.i32 q9, #0xffff
-; CHECK-NEXT: vmov.i32 q10, #0x0
-; CHECK-NEXT: vmin.s32 q8, q8, q9
-; CHECK-NEXT: vmax.s32 q8, q8, q10
+; CHECK-NEXT: vmov.i32 q9, #0x0
+; CHECK-NEXT: vmov.i32 q10, #0xffff
+; CHECK-NEXT: vmax.s32 q8, q8, q9
+; CHECK-NEXT: vmin.s32 q8, q8, q10
; CHECK-NEXT: vmovn.i32 d0, q8
; CHECK-NEXT: bx lr
entry:
@@ -3301,22 +3197,22 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) {
; CHECK-NEON-NEXT: vmov r0, s20
; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0
; CHECK-NEON-NEXT: vmov s2, r4
-; CHECK-NEON-NEXT: vmov.i32 q8, #0x7fff
+; CHECK-NEON-NEXT: vmvn.i32 q8, #0x7fff
; CHECK-NEON-NEXT: vcvt.s32.f32 s2, s2
-; CHECK-NEON-NEXT: vmvn.i32 q9, #0x7fff
+; CHECK-NEON-NEXT: vmov.i32 q9, #0x7fff
; CHECK-NEON-NEXT: vmov.32 d9[0], r0
; CHECK-NEON-NEXT: vmov r0, s0
; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s22
; CHECK-NEON-NEXT: vmov.32 d12[1], r0
; CHECK-NEON-NEXT: vmov r0, s0
-; CHECK-NEON-NEXT: vmin.s32 q10, q6, q8
-; CHECK-NEON-NEXT: vmax.s32 q10, q10, q9
+; CHECK-NEON-NEXT: vmax.s32 q10, q6, q8
+; CHECK-NEON-NEXT: vmin.s32 q10, q10, q9
; CHECK-NEON-NEXT: vmov.32 d9[1], r0
; CHECK-NEON-NEXT: vmov r0, s2
; CHECK-NEON-NEXT: vmovn.i32 d1, q10
; CHECK-NEON-NEXT: vmov.32 d8[1], r0
-; CHECK-NEON-NEXT: vmin.s32 q8, q4, q8
-; CHECK-NEON-NEXT: vmax.s32 q8, q8, q9
+; CHECK-NEON-NEXT: vmax.s32 q8, q4, q8
+; CHECK-NEON-NEXT: vmin.s32 q8, q8, q9
; CHECK-NEON-NEXT: vmovn.i32 d0, q8
; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r11, pc}
@@ -3336,8 +3232,8 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) {
; CHECK-FP16-NEXT: vmovx.f16 s6, s1
; CHECK-FP16-NEXT: vcvt.s32.f16 s4, s4
; CHECK-FP16-NEXT: vcvt.s32.f16 s6, s6
-; CHECK-FP16-NEXT: vmov.i32 q10, #0x7fff
-; CHECK-FP16-NEXT: vmvn.i32 q11, #0x7fff
+; CHECK-FP16-NEXT: vmvn.i32 q10, #0x7fff
+; CHECK-FP16-NEXT: vmov.i32 q11, #0x7fff
; CHECK-FP16-NEXT: vmov.32 d17[0], r0
; CHECK-FP16-NEXT: vmov r0, s5
; CHECK-FP16-NEXT: vmov.32 d16[0], r0
@@ -3350,14 +3246,14 @@ define <8 x i16> @stest_f16i16_mm(<8 x half> %x) {
; CHECK-FP16-NEXT: vmov r0, s8
; CHECK-FP16-NEXT: vmov.32 d16[1], r0
; CHECK-FP16-NEXT: vmov r0, s6
-; CHECK-FP16-NEXT: vmin.s32 q8, q8, q10
-; CHECK-FP16-NEXT: vmax.s32 q8, q8, q11
+; CHECK-FP16-NEXT: vmax.s32 q8, q8, q10
+; CHECK-FP16-NEXT: vmin.s32 q8, q8, q11
; CHECK-FP16-NEXT: vmovn.i32 d1, q8
; CHECK-FP16-NEXT: vmov.32 d19[1], r0
; CHECK-FP16-NEXT: vmov r0, s4
; CHECK-FP16-NEXT: vmov.32 d18[1], r0
-; CHECK-FP16-NEXT: vmin.s32 q9, q9, q10
-; CHECK-FP16-NEXT: vmax.s32 q9, q9, q11
+; CHECK-FP16-NEXT: vmax.s32 q9, q9, q10
+; CHECK-FP16-NEXT: vmin.s32 q9, q9, q11
; CHECK-FP16-NEXT: vmovn.i32 d0, q9
; CHECK-FP16-NEXT: bx lr
entry:
@@ -3544,22 +3440,22 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {
; CHECK-NEON-NEXT: vmov r0, s20
; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s0
; CHECK-NEON-NEXT: vmov s2, r4
-; CHECK-NEON-NEXT: vmov.i32 q8, #0xffff
+; CHECK-NEON-NEXT: vmov.i32 q8, #0x0
; CHECK-NEON-NEXT: vcvt.s32.f32 s2, s2
-; CHECK-NEON-NEXT: vmov.i32 q9, #0x0
+; CHECK-NEON-NEXT: vmov.i32 q9, #0xffff
; CHECK-NEON-NEXT: vmov.32 d9[0], r0
; CHECK-NEON-NEXT: vmov r0, s0
; CHECK-NEON-NEXT: vcvt.s32.f32 s0, s22
; CHECK-NEON-NEXT: vmov.32 d12[1], r0
; CHECK-NEON-NEXT: vmov r0, s0
-; CHECK-NEON-NEXT: vmin.s32 q10, q6, q8
-; CHECK-NEON-NEXT: vmax.s32 q10, q10, q9
+; CHECK-NEON-NEXT: vmax.s32 q10, q6, q8
+; CHECK-NEON-NEXT: vmin.s32 q10, q10, q9
; CHECK-NEON-NEXT: vmov.32 d9[1], r0
; CHECK-NEON-NEXT: vmov r0, s2
; CHECK-NEON-NEXT: vmovn.i32 d1, q10
; CHECK-NEON-NEXT: vmov.32 d8[1], r0
-; CHECK-NEON-NEXT: vmin.s32 q8, q4, q8
-; CHECK-NEON-NEXT: vmax.s32 q8, q8, q9
+; CHECK-NEON-NEXT: vmax.s32 q8, q4, q8
+; CHECK-NEON-NEXT: vmin.s32 q8, q8, q9
; CHECK-NEON-NEXT: vmovn.i32 d0, q8
; CHECK-NEON-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r11, pc}
@@ -3579,8 +3475,8 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {
; CHECK-FP16-NEXT: vmovx.f16 s6, s1
; CHECK-FP16-NEXT: vcvt.s32.f16 s4, s4
; CHECK-FP16-NEXT: vcvt.s32.f16 s6, s6
-; CHECK-FP16-NEXT: vmov.i32 q10, #0xffff
-; CHECK-FP16-NEXT: vmov.i32 q11, #0x0
+; CHECK-FP16-NEXT: vmov.i32 q10, #0x0
+; CHECK-FP16-NEXT: vmov.i32 q11, #0xffff
; CHECK-FP16-NEXT: vmov.32 d17[0], r0
; CHECK-FP16-NEXT: vmov r0, s5
; CHECK-FP16-NEXT: vmov.32 d16[0], r0
@@ -3593,14 +3489,14 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {
; CHECK-FP16-NEXT: vmov r0, s8
; CHECK-FP16-NEXT: vmov.32 d16[1], r0
; CHECK-FP16-NEXT: vmov r0, s6
-; CHECK-FP16-NEXT: vmin.s32 q8, q8, q10
-; CHECK-FP16-NEXT: vmax.s32 q8, q8, q11
+; CHECK-FP16-NEXT: vmax.s32 q8, q8, q10
+; CHECK-FP16-NEXT: vmin.s32 q8, q8, q11
; CHECK-FP16-NEXT: vmovn.i32 d1, q8
; CHECK-FP16-NEXT: vmov.32 d19[1], r0
; CHECK-FP16-NEXT: vmov r0, s4
; CHECK-FP16-NEXT: vmov.32 d18[1], r0
-; CHECK-FP16-NEXT: vmin.s32 q9, q9, q10
-; CHECK-FP16-NEXT: vmax.s32 q9, q9, q11
+; CHECK-FP16-NEXT: vmax.s32 q9, q9, q10
+; CHECK-FP16-NEXT: vmin.s32 q9, q9, q11
; CHECK-FP16-NEXT: vmovn.i32 d0, q9
; CHECK-FP16-NEXT: bx lr
entry:
@@ -3623,56 +3519,50 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) {
; CHECK-NEXT: vorr q4, q0, q0
; CHECK-NEXT: vorr d0, d9, d9
; CHECK-NEXT: bl __fixdfti
-; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: mvn r9, #0
-; CHECK-NEXT: subs r1, r0, r9
-; CHECK-NEXT: mvn r5, #-2147483648
-; CHECK-NEXT: sbcs r1, r4, r5
+; CHECK-NEXT: mov r10, r1
+; CHECK-NEXT: rsbs r1, r0, #0
+; CHECK-NEXT: rscs r1, r10, #-2147483648
+; CHECK-NEXT: mvn r8, #0
+; CHECK-NEXT: sbcs r1, r8, r2
+; CHECK-NEXT: mov r5, #0
+; CHECK-NEXT: sbcs r1, r8, r3
+; CHECK-NEXT: mov r7, #-2147483648
+; CHECK-NEXT: movge r3, r8
+; CHECK-NEXT: movge r2, r8
+; CHECK-NEXT: movwlt r5, #1
+; CHECK-NEXT: cmp r5, #0
+; CHECK-NEXT: movne r5, r0
+; CHECK-NEXT: moveq r10, r7
+; CHECK-NEXT: subs r0, r5, r8
+; CHECK-NEXT: mvn r9, #-2147483648
+; CHECK-NEXT: sbcs r0, r10, r9
; CHECK-NEXT: vorr d0, d8, d8
-; CHECK-NEXT: sbcs r1, r2, #0
-; CHECK-NEXT: mov r7, #0
-; CHECK-NEXT: sbcs r1, r3, #0
-; CHECK-NEXT: mov r8, #-2147483648
-; CHECK-NEXT: mov r1, #0
-; CHECK-NEXT: mov r10, #0
-; CHECK-NEXT: movwlt r1, #1
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: moveq r3, r1
-; CHECK-NEXT: movne r1, r2
-; CHECK-NEXT: moveq r4, r5
-; CHECK-NEXT: moveq r0, r9
-; CHECK-NEXT: rsbs r2, r0, #0
-; CHECK-NEXT: rscs r2, r4, #-2147483648
-; CHECK-NEXT: sbcs r1, r9, r1
-; CHECK-NEXT: sbcs r1, r9, r3
-; CHECK-NEXT: movwlt r7, #1
-; CHECK-NEXT: cmp r7, #0
-; CHECK-NEXT: movne r7, r0
-; CHECK-NEXT: moveq r4, r8
-; CHECK-NEXT: bl __fixdfti
-; CHECK-NEXT: subs r6, r0, r9
-; CHECK-NEXT: vmov.32 d1[0], r7
-; CHECK-NEXT: sbcs r6, r1, r5
-; CHECK-NEXT: sbcs r6, r2, #0
-; CHECK-NEXT: sbcs r6, r3, #0
+; CHECK-NEXT: sbcs r0, r2, #0
; CHECK-NEXT: mov r6, #0
+; CHECK-NEXT: sbcs r0, r3, #0
+; CHECK-NEXT: movge r5, r8
+; CHECK-NEXT: movge r10, r9
+; CHECK-NEXT: bl __fixdfti
+; CHECK-NEXT: rsbs r4, r0, #0
+; CHECK-NEXT: vmov.32 d1[0], r5
+; CHECK-NEXT: rscs r4, r1, #-2147483648
+; CHECK-NEXT: sbcs r4, r8, r2
+; CHECK-NEXT: sbcs r4, r8, r3
; CHECK-NEXT: movwlt r6, #1
+; CHECK-NEXT: movge r3, r8
+; CHECK-NEXT: movge r2, r8
; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: moveq r3, r6
-; CHECK-NEXT: movne r6, r2
-; CHECK-NEXT: movne r5, r1
-; CHECK-NEXT: moveq r0, r9
-; CHECK-NEXT: rsbs r1, r0, #0
-; CHECK-NEXT: rscs r1, r5, #-2147483648
-; CHECK-NEXT: sbcs r1, r9, r6
-; CHECK-NEXT: sbcs r1, r9, r3
-; CHECK-NEXT: movwlt r10, #1
-; CHECK-NEXT: cmp r10, #0
-; CHECK-NEXT: movne r10, r0
-; CHECK-NEXT: moveq r5, r8
-; CHECK-NEXT: vmov.32 d0[0], r10
-; CHECK-NEXT: vmov.32 d1[1], r4
-; CHECK-NEXT: vmov.32 d0[1], r5
+; CHECK-NEXT: movne r6, r0
+; CHECK-NEXT: movne r7, r1
+; CHECK-NEXT: subs r0, r6, r8
+; CHECK-NEXT: sbcs r0, r7, r9
+; CHECK-NEXT: sbcs r0, r2, #0
+; CHECK-NEXT: sbcs r0, r3, #0
+; CHECK-NEXT: movge r6, r8
+; CHECK-NEXT: movge r7, r9
+; CHECK-NEXT: vmov.32 d0[0], r6
+; CHECK-NEXT: vmov.32 d1[1], r10
+; CHECK-NEXT: vmov.32 d0[1], r7
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
entry:
@@ -3733,36 +3623,37 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) {
; CHECK-NEXT: vorr q4, q0, q0
; CHECK-NEXT: vorr d0, d9, d9
; CHECK-NEXT: bl __fixdfti
-; CHECK-NEXT: mov r5, r0
-; CHECK-NEXT: subs r0, r2, #1
-; CHECK-NEXT: sbcs r0, r3, #0
-; CHECK-NEXT: vorr d0, d8, d8
-; CHECK-NEXT: mov r0, #0
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: movwlt r0, #1
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: moveq r5, r0
-; CHECK-NEXT: moveq r4, r0
-; CHECK-NEXT: movne r0, r3
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: mov r6, #0
+; CHECK-NEXT: movwmi r2, #0
+; CHECK-NEXT: vorr d0, d8, d8
+; CHECK-NEXT: movwmi r0, #0
; CHECK-NEXT: movwmi r4, #0
-; CHECK-NEXT: movwmi r5, #0
-; CHECK-NEXT: bl __fixdfti
+; CHECK-NEXT: bic r1, r3, r3, asr #31
; CHECK-NEXT: subs r2, r2, #1
-; CHECK-NEXT: vmov.32 d1[0], r5
-; CHECK-NEXT: sbcs r2, r3, #0
+; CHECK-NEXT: sbcs r1, r1, #0
+; CHECK-NEXT: mov r6, #0
; CHECK-NEXT: movwlt r6, #1
; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: moveq r1, r6
-; CHECK-NEXT: moveq r0, r6
-; CHECK-NEXT: movne r6, r3
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: movwmi r0, #0
+; CHECK-NEXT: moveq r4, r6
+; CHECK-NEXT: mov r5, #0
+; CHECK-NEXT: movne r6, r0
+; CHECK-NEXT: bl __fixdfti
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: bic r3, r3, r3, asr #31
+; CHECK-NEXT: movwmi r2, #0
; CHECK-NEXT: movwmi r1, #0
+; CHECK-NEXT: movwmi r0, #0
+; CHECK-NEXT: subs r2, r2, #1
+; CHECK-NEXT: sbcs r2, r3, #0
+; CHECK-NEXT: vmov.32 d1[0], r6
+; CHECK-NEXT: movwlt r5, #1
+; CHECK-NEXT: cmp r5, #0
+; CHECK-NEXT: moveq r0, r5
+; CHECK-NEXT: movne r5, r1
; CHECK-NEXT: vmov.32 d0[0], r0
; CHECK-NEXT: vmov.32 d1[1], r4
-; CHECK-NEXT: vmov.32 d0[1], r1
+; CHECK-NEXT: vmov.32 d0[1], r5
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r6, pc}
entry:
@@ -3783,56 +3674,50 @@ define <2 x i64> @stest_f32i64_mm(<2 x float> %x) {
; CHECK-NEXT: vmov.f64 d8, d0
; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: mvn r9, #0
-; CHECK-NEXT: subs r1, r0, r9
-; CHECK-NEXT: mvn r5, #-2147483648
-; CHECK-NEXT: sbcs r1, r4, r5
+; CHECK-NEXT: mov r10, r1
+; CHECK-NEXT: rsbs r1, r0, #0
+; CHECK-NEXT: rscs r1, r10, #-2147483648
+; CHECK-NEXT: mvn r8, #0
+; CHECK-NEXT: sbcs r1, r8, r2
; CHECK-NEXT: vmov.f32 s0, s16
-; CHECK-NEXT: sbcs r1, r2, #0
-; CHECK-NEXT: mov r7, #0
-; CHECK-NEXT: sbcs r1, r3, #0
-; CHECK-NEXT: mov r8, #-2147483648
-; CHECK-NEXT: mov r1, #0
-; CHECK-NEXT: mov r10, #0
-; CHECK-NEXT: movwlt r1, #1
-; CHECK-NEXT: cmp r1, #0
-; CHECK-NEXT: moveq r3, r1
-; CHECK-NEXT: movne r1, r2
-; CHECK-NEXT: moveq r4, r5
-; CHECK-NEXT: moveq r0, r9
-; CHECK-NEXT: rsbs r2, r0, #0
-; CHECK-NEXT: rscs r2, r4, #-2147483648
-; CHECK-NEXT: sbcs r1, r9, r1
-; CHECK-NEXT: sbcs r1, r9, r3
-; CHECK-NEXT: movwlt r7, #1
-; CHECK-NEXT: cmp r7, #0
-; CHECK-NEXT: movne r7, r0
-; CHECK-NEXT: moveq r4, r8
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: subs r6, r0, r9
-; CHECK-NEXT: vmov.32 d1[0], r7
-; CHECK-NEXT: sbcs r6, r1, r5
-; CHECK-NEXT: sbcs r6, r2, #0
-; CHECK-NEXT: sbcs r6, r3, #0
+; CHECK-NEXT: sbcs r1, r8, r3
+; CHECK-NEXT: mov r5, #0
+; CHECK-NEXT: movge r3, r8
+; CHECK-NEXT: movge r2, r8
+; CHECK-NEXT: movwlt r5, #1
+; CHECK-NEXT: cmp r5, #0
+; CHECK-NEXT: mov r7, #-2147483648
+; CHECK-NEXT: movne r5, r0
+; CHECK-NEXT: moveq r10, r7
+; CHECK-NEXT: subs r0, r5, r8
+; CHECK-NEXT: mvn r9, #-2147483648
+; CHECK-NEXT: sbcs r0, r10, r9
+; CHECK-NEXT: sbcs r0, r2, #0
; CHECK-NEXT: mov r6, #0
+; CHECK-NEXT: sbcs r0, r3, #0
+; CHECK-NEXT: movge r5, r8
+; CHECK-NEXT: movge r10, r9
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: rsbs r4, r0, #0
+; CHECK-NEXT: vmov.32 d1[0], r5
+; CHECK-NEXT: rscs r4, r1, #-2147483648
+; CHECK-NEXT: sbcs r4, r8, r2
+; CHECK-NEXT: sbcs r4, r8, r3
; CHECK-NEXT: movwlt r6, #1
+; CHECK-NEXT: movge r3, r8
+; CHECK-NEXT: movge r2, r8
; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: moveq r3, r6
-; CHECK-NEXT: movne r6, r2
-; CHECK-NEXT: movne r5, r1
-; CHECK-NEXT: moveq r0, r9
-; CHECK-NEXT: rsbs r1, r0, #0
-; CHECK-NEXT: rscs r1, r5, #-2147483648
-; CHECK-NEXT: sbcs r1, r9, r6
-; CHECK-NEXT: sbcs r1, r9, r3
-; CHECK-NEXT: movwlt r10, #1
-; CHECK-NEXT: cmp r10, #0
-; CHECK-NEXT: movne r10, r0
-; CHECK-NEXT: moveq r5, r8
-; CHECK-NEXT: vmov.32 d0[0], r10
-; CHECK-NEXT: vmov.32 d1[1], r4
-; CHECK-NEXT: vmov.32 d0[1], r5
+; CHECK-NEXT: movne r6, r0
+; CHECK-NEXT: movne r7, r1
+; CHECK-NEXT: subs r0, r6, r8
+; CHECK-NEXT: sbcs r0, r7, r9
+; CHECK-NEXT: sbcs r0, r2, #0
+; CHECK-NEXT: sbcs r0, r3, #0
+; CHECK-NEXT: movge r6, r8
+; CHECK-NEXT: movge r7, r9
+; CHECK-NEXT: vmov.32 d0[0], r6
+; CHECK-NEXT: vmov.32 d1[1], r10
+; CHECK-NEXT: vmov.32 d0[1], r7
; CHECK-NEXT: vpop {d8}
; CHECK-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
entry:
@@ -3894,35 +3779,36 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) {
; CHECK-NEXT: vmov.f32 s0, s17
; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: vmov.f32 s0, s16
-; CHECK-NEXT: mov r5, r0
-; CHECK-NEXT: subs r0, r2, #1
+; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: sbcs r0, r3, #0
-; CHECK-NEXT: mov r6, #0
-; CHECK-NEXT: mov r0, #0
-; CHECK-NEXT: movwlt r0, #1
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: moveq r5, r0
-; CHECK-NEXT: moveq r4, r0
-; CHECK-NEXT: movne r0, r3
-; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: movwmi r2, #0
+; CHECK-NEXT: movwmi r0, #0
; CHECK-NEXT: movwmi r4, #0
-; CHECK-NEXT: movwmi r5, #0
-; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: bic r1, r3, r3, asr #31
; CHECK-NEXT: subs r2, r2, #1
-; CHECK-NEXT: vmov.32 d1[0], r5
-; CHECK-NEXT: sbcs r2, r3, #0
+; CHECK-NEXT: sbcs r1, r1, #0
+; CHECK-NEXT: mov r6, #0
; CHECK-NEXT: movwlt r6, #1
; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: moveq r1, r6
-; CHECK-NEXT: moveq r0, r6
-; CHECK-NEXT: movne r6, r3
-; CHECK-NEXT: cmp r6, #0
-; CHECK-NEXT: movwmi r0, #0
+; CHECK-NEXT: moveq r4, r6
+; CHECK-NEXT: mov r5, #0
+; CHECK-NEXT: movne r6, r0
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: cmp r3, #0
+; CHECK-NEXT: bic r3, r3, r3, asr #31
+; CHECK-NEXT: movwmi r2, #0
; CHECK-NEXT: movwmi r1, #0
+; CHECK-NEXT: movwmi r0, #0
+; CHECK-NEXT: subs r2, r2, #1
+; CHECK-NEXT: sbcs r2, r3, #0
+; CHECK-NEXT: vmov.32 d1[0], r6
+; CHECK-NEXT: movwlt r5, #1
+; CHECK-NEXT: cmp r5, #0
+; CHECK-NEXT: moveq r0, r5
+; CHECK-NEXT: movne r5, r1
; CHECK-NEXT: vmov.32 d0[0], r0
; CHECK-NEXT: vmov.32 d1[1], r4
-; CHECK-NEXT: vmov.32 d0[1], r1
+; CHECK-NEXT: vmov.32 d0[1], r5
; CHECK-NEXT: vpop {d8}
; CHECK-NEXT: pop {r4, r5, r6, pc}
entry:
@@ -3943,61 +3829,55 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
; CHECK-NEON-NEXT: vmov r0, s0
; CHECK-NEON-NEXT: vmov.f32 s16, s1
; CHECK-NEON-NEXT: bl __aeabi_h2f
-; CHECK-NEON-NEXT: mov r8, r0
+; CHECK-NEON-NEXT: mov r5, r0
; CHECK-NEON-NEXT: vmov r0, s16
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: vmov s0, r0
; CHECK-NEON-NEXT: bl __fixsfti
-; CHECK-NEON-NEXT: mov r4, r1
-; CHECK-NEON-NEXT: mvn r9, #0
-; CHECK-NEON-NEXT: subs r1, r0, r9
-; CHECK-NEON-NEXT: mvn r6, #-2147483648
-; CHECK-NEON-NEXT: sbcs r1, r4, r6
-; CHECK-NEON-NEXT: vmov s0, r8
-; CHECK-NEON-NEXT: sbcs r1, r2, #0
+; CHECK-NEON-NEXT: mov r10, r1
+; CHECK-NEON-NEXT: rsbs r1, r0, #0
+; CHECK-NEON-NEXT: rscs r1, r10, #-2147483648
+; CHECK-NEON-NEXT: mvn r8, #0
+; CHECK-NEON-NEXT: sbcs r1, r8, r2
+; CHECK-NEON-NEXT: mov r6, #0
+; CHECK-NEON-NEXT: sbcs r1, r8, r3
+; CHECK-NEON-NEXT: mov r7, #-2147483648
+; CHECK-NEON-NEXT: movge r3, r8
+; CHECK-NEON-NEXT: movge r2, r8
+; CHECK-NEON-NEXT: movwlt r6, #1
+; CHECK-NEON-NEXT: cmp r6, #0
+; CHECK-NEON-NEXT: movne r6, r0
+; CHECK-NEON-NEXT: moveq r10, r7
+; CHECK-NEON-NEXT: subs r0, r6, r8
+; CHECK-NEON-NEXT: mvn r9, #-2147483648
+; CHECK-NEON-NEXT: sbcs r0, r10, r9
+; CHECK-NEON-NEXT: vmov s0, r5
+; CHECK-NEON-NEXT: sbcs r0, r2, #0
; CHECK-NEON-NEXT: mov r5, #0
-; CHECK-NEON-NEXT: sbcs r1, r3, #0
-; CHECK-NEON-NEXT: mov r8, #-2147483648
-; CHECK-NEON-NEXT: mov r1, #0
-; CHECK-NEON-NEXT: mov r10, #0
-; CHECK-NEON-NEXT: movwlt r1, #1
-; CHECK-NEON-NEXT: cmp r1, #0
-; CHECK-NEON-NEXT: moveq r3, r1
-; CHECK-NEON-NEXT: movne r1, r2
-; CHECK-NEON-NEXT: moveq r4, r6
-; CHECK-NEON-NEXT: moveq r0, r9
-; CHECK-NEON-NEXT: rsbs r2, r0, #0
-; CHECK-NEON-NEXT: rscs r2, r4, #-2147483648
-; CHECK-NEON-NEXT: sbcs r1, r9, r1
-; CHECK-NEON-NEXT: sbcs r1, r9, r3
+; CHECK-NEON-NEXT: sbcs r0, r3, #0
+; CHECK-NEON-NEXT: movge r6, r8
+; CHECK-NEON-NEXT: movge r10, r9
+; CHECK-NEON-NEXT: bl __fixsfti
+; CHECK-NEON-NEXT: rsbs r4, r0, #0
+; CHECK-NEON-NEXT: vmov.32 d1[0], r6
+; CHECK-NEON-NEXT: rscs r4, r1, #-2147483648
+; CHECK-NEON-NEXT: sbcs r4, r8, r2
+; CHECK-NEON-NEXT: sbcs r4, r8, r3
; CHECK-NEON-NEXT: movwlt r5, #1
+; CHECK-NEON-NEXT: movge r3, r8
+; CHECK-NEON-NEXT: movge r2, r8
; CHECK-NEON-NEXT: cmp r5, #0
; CHECK-NEON-NEXT: movne r5, r0
-; CHECK-NEON-NEXT: moveq r4, r8
-; CHECK-NEON-NEXT: bl __fixsfti
-; CHECK-NEON-NEXT: subs r7, r0, r9
-; CHECK-NEON-NEXT: vmov.32 d1[0], r5
-; CHECK-NEON-NEXT: sbcs r7, r1, r6
-; CHECK-NEON-NEXT: sbcs r7, r2, #0
-; CHECK-NEON-NEXT: sbcs r7, r3, #0
-; CHECK-NEON-NEXT: mov r7, #0
-; CHECK-NEON-NEXT: movwlt r7, #1
-; CHECK-NEON-NEXT: cmp r7, #0
-; CHECK-NEON-NEXT: moveq r3, r7
-; CHECK-NEON-NEXT: movne r7, r2
-; CHECK-NEON-NEXT: movne r6, r1
-; CHECK-NEON-NEXT: moveq r0, r9
-; CHECK-NEON-NEXT: rsbs r1, r0, #0
-; CHECK-NEON-NEXT: rscs r1, r6, #-2147483648
-; CHECK-NEON-NEXT: sbcs r1, r9, r7
-; CHECK-NEON-NEXT: sbcs r1, r9, r3
-; CHECK-NEON-NEXT: movwlt r10, #1
-; CHECK-NEON-NEXT: cmp r10, #0
-; CHECK-NEON-NEXT: movne r10, r0
-; CHECK-NEON-NEXT: moveq r6, r8
-; CHECK-NEON-NEXT: vmov.32 d0[0], r10
-; CHECK-NEON-NEXT: vmov.32 d1[1], r4
-; CHECK-NEON-NEXT: vmov.32 d0[1], r6
+; CHECK-NEON-NEXT: movne r7, r1
+; CHECK-NEON-NEXT: subs r0, r5, r8
+; CHECK-NEON-NEXT: sbcs r0, r7, r9
+; CHECK-NEON-NEXT: sbcs r0, r2, #0
+; CHECK-NEON-NEXT: sbcs r0, r3, #0
+; CHECK-NEON-NEXT: movge r5, r8
+; CHECK-NEON-NEXT: movge r7, r9
+; CHECK-NEON-NEXT: vmov.32 d0[0], r5
+; CHECK-NEON-NEXT: vmov.32 d1[1], r10
+; CHECK-NEON-NEXT: vmov.32 d0[1], r7
; CHECK-NEON-NEXT: vpop {d8}
; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
;
@@ -4006,59 +3886,53 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r8, r9, r10, lr}
; CHECK-FP16-NEXT: vmov.u16 r0, d0[1]
-; CHECK-FP16-NEXT: vmov.u16 r7, d0[0]
+; CHECK-FP16-NEXT: vmov.u16 r5, d0[0]
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfti
-; CHECK-FP16-NEXT: mov r4, r1
-; CHECK-FP16-NEXT: mvn r9, #0
-; CHECK-FP16-NEXT: subs r1, r0, r9
-; CHECK-FP16-NEXT: mvn r5, #-2147483648
-; CHECK-FP16-NEXT: sbcs r1, r4, r5
-; CHECK-FP16-NEXT: vmov s0, r7
-; CHECK-FP16-NEXT: sbcs r1, r2, #0
-; CHECK-FP16-NEXT: mov r7, #0
-; CHECK-FP16-NEXT: sbcs r1, r3, #0
-; CHECK-FP16-NEXT: mov r8, #-2147483648
-; CHECK-FP16-NEXT: mov r1, #0
-; CHECK-FP16-NEXT: mov r10, #0
-; CHECK-FP16-NEXT: movwlt r1, #1
-; CHECK-FP16-NEXT: cmp r1, #0
-; CHECK-FP16-NEXT: moveq r3, r1
-; CHECK-FP16-NEXT: movne r1, r2
-; CHECK-FP16-NEXT: moveq r4, r5
-; CHECK-FP16-NEXT: moveq r0, r9
-; CHECK-FP16-NEXT: rsbs r2, r0, #0
-; CHECK-FP16-NEXT: rscs r2, r4, #-2147483648
-; CHECK-FP16-NEXT: sbcs r1, r9, r1
-; CHECK-FP16-NEXT: sbcs r1, r9, r3
-; CHECK-FP16-NEXT: movwlt r7, #1
-; CHECK-FP16-NEXT: cmp r7, #0
-; CHECK-FP16-NEXT: movne r7, r0
-; CHECK-FP16-NEXT: moveq r4, r8
-; CHECK-FP16-NEXT: bl __fixhfti
-; CHECK-FP16-NEXT: subs r6, r0, r9
-; CHECK-FP16-NEXT: vmov.32 d1[0], r7
-; CHECK-FP16-NEXT: sbcs r6, r1, r5
-; CHECK-FP16-NEXT: sbcs r6, r2, #0
-; CHECK-FP16-NEXT: sbcs r6, r3, #0
+; CHECK-FP16-NEXT: mov r10, r1
+; CHECK-FP16-NEXT: rsbs r1, r0, #0
+; CHECK-FP16-NEXT: rscs r1, r10, #-2147483648
+; CHECK-FP16-NEXT: mvn r8, #0
+; CHECK-FP16-NEXT: sbcs r1, r8, r2
+; CHECK-FP16-NEXT: vmov s0, r5
+; CHECK-FP16-NEXT: sbcs r1, r8, r3
+; CHECK-FP16-NEXT: mov r5, #0
+; CHECK-FP16-NEXT: movge r3, r8
+; CHECK-FP16-NEXT: movge r2, r8
+; CHECK-FP16-NEXT: movwlt r5, #1
+; CHECK-FP16-NEXT: cmp r5, #0
+; CHECK-FP16-NEXT: mov r7, #-2147483648
+; CHECK-FP16-NEXT: movne r5, r0
+; CHECK-FP16-NEXT: moveq r10, r7
+; CHECK-FP16-NEXT: subs r0, r5, r8
+; CHECK-FP16-NEXT: mvn r9, #-2147483648
+; CHECK-FP16-NEXT: sbcs r0, r10, r9
+; CHECK-FP16-NEXT: sbcs r0, r2, #0
; CHECK-FP16-NEXT: mov r6, #0
+; CHECK-FP16-NEXT: sbcs r0, r3, #0
+; CHECK-FP16-NEXT: movge r5, r8
+; CHECK-FP16-NEXT: movge r10, r9
+; CHECK-FP16-NEXT: bl __fixhfti
+; CHECK-FP16-NEXT: rsbs r4, r0, #0
+; CHECK-FP16-NEXT: vmov.32 d1[0], r5
+; CHECK-FP16-NEXT: rscs r4, r1, #-2147483648
+; CHECK-FP16-NEXT: sbcs r4, r8, r2
+; CHECK-FP16-NEXT: sbcs r4, r8, r3
; CHECK-FP16-NEXT: movwlt r6, #1
+; CHECK-FP16-NEXT: movge r3, r8
+; CHECK-FP16-NEXT: movge r2, r8
; CHECK-FP16-NEXT: cmp r6, #0
-; CHECK-FP16-NEXT: moveq r3, r6
-; CHECK-FP16-NEXT: movne r6, r2
-; CHECK-FP16-NEXT: movne r5, r1
-; CHECK-FP16-NEXT: moveq r0, r9
-; CHECK-FP16-NEXT: rsbs r1, r0, #0
-; CHECK-FP16-NEXT: rscs r1, r5, #-2147483648
-; CHECK-FP16-NEXT: sbcs r1, r9, r6
-; CHECK-FP16-NEXT: sbcs r1, r9, r3
-; CHECK-FP16-NEXT: movwlt r10, #1
-; CHECK-FP16-NEXT: cmp r10, #0
-; CHECK-FP16-NEXT: movne r10, r0
-; CHECK-FP16-NEXT: moveq r5, r8
-; CHECK-FP16-NEXT: vmov.32 d0[0], r10
-; CHECK-FP16-NEXT: vmov.32 d1[1], r4
-; CHECK-FP16-NEXT: vmov.32 d0[1], r5
+; CHECK-FP16-NEXT: movne r6, r0
+; CHECK-FP16-NEXT: movne r7, r1
+; CHECK-FP16-NEXT: subs r0, r6, r8
+; CHECK-FP16-NEXT: sbcs r0, r7, r9
+; CHECK-FP16-NEXT: sbcs r0, r2, #0
+; CHECK-FP16-NEXT: sbcs r0, r3, #0
+; CHECK-FP16-NEXT: movge r6, r8
+; CHECK-FP16-NEXT: movge r7, r9
+; CHECK-FP16-NEXT: vmov.32 d0[0], r6
+; CHECK-FP16-NEXT: vmov.32 d1[1], r10
+; CHECK-FP16-NEXT: vmov.32 d0[1], r7
; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, pc}
entry:
%conv = fptosi <2 x half> %x to <2 x i128>
@@ -4147,90 +4021,92 @@ entry:
define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) {
; CHECK-NEON-LABEL: ustest_f16i64_mm:
; CHECK-NEON: @ %bb.0: @ %entry
-; CHECK-NEON-NEXT: .save {r4, r5, r6, r7, r11, lr}
-; CHECK-NEON-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-NEON-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEON-NEXT: push {r4, r5, r6, lr}
; CHECK-NEON-NEXT: .vsave {d8}
; CHECK-NEON-NEXT: vpush {d8}
; CHECK-NEON-NEXT: vmov r0, s0
; CHECK-NEON-NEXT: vmov.f32 s16, s1
; CHECK-NEON-NEXT: bl __aeabi_h2f
-; CHECK-NEON-NEXT: mov r6, r0
+; CHECK-NEON-NEXT: mov r5, r0
; CHECK-NEON-NEXT: vmov r0, s16
; CHECK-NEON-NEXT: bl __aeabi_h2f
; CHECK-NEON-NEXT: vmov s0, r0
; CHECK-NEON-NEXT: bl __fixsfti
-; CHECK-NEON-NEXT: mov r5, r0
-; CHECK-NEON-NEXT: subs r0, r2, #1
-; CHECK-NEON-NEXT: sbcs r0, r3, #0
-; CHECK-NEON-NEXT: vmov s0, r6
-; CHECK-NEON-NEXT: mov r0, #0
+; CHECK-NEON-NEXT: cmp r3, #0
; CHECK-NEON-NEXT: mov r4, r1
-; CHECK-NEON-NEXT: movwlt r0, #1
-; CHECK-NEON-NEXT: cmp r0, #0
-; CHECK-NEON-NEXT: moveq r5, r0
-; CHECK-NEON-NEXT: moveq r4, r0
-; CHECK-NEON-NEXT: movne r0, r3
-; CHECK-NEON-NEXT: cmp r0, #0
-; CHECK-NEON-NEXT: mov r7, #0
+; CHECK-NEON-NEXT: movwmi r2, #0
+; CHECK-NEON-NEXT: movwmi r0, #0
; CHECK-NEON-NEXT: movwmi r4, #0
-; CHECK-NEON-NEXT: movwmi r5, #0
+; CHECK-NEON-NEXT: bic r1, r3, r3, asr #31
+; CHECK-NEON-NEXT: subs r2, r2, #1
+; CHECK-NEON-NEXT: vmov s0, r5
+; CHECK-NEON-NEXT: sbcs r1, r1, #0
+; CHECK-NEON-NEXT: mov r6, #0
+; CHECK-NEON-NEXT: movwlt r6, #1
+; CHECK-NEON-NEXT: cmp r6, #0
+; CHECK-NEON-NEXT: moveq r4, r6
+; CHECK-NEON-NEXT: mov r5, #0
+; CHECK-NEON-NEXT: movne r6, r0
; CHECK-NEON-NEXT: bl __fixsfti
+; CHECK-NEON-NEXT: cmp r3, #0
+; CHECK-NEON-NEXT: bic r3, r3, r3, asr #31
+; CHECK-NEON-NEXT: movwmi r2, #0
+; CHECK-NEON-NEXT: movwmi r1, #0
+; CHECK-NEON-NEXT: movwmi r0, #0
; CHECK-NEON-NEXT: subs r2, r2, #1
-; CHECK-NEON-NEXT: vmov.32 d1[0], r5
; CHECK-NEON-NEXT: sbcs r2, r3, #0
-; CHECK-NEON-NEXT: movwlt r7, #1
-; CHECK-NEON-NEXT: cmp r7, #0
-; CHECK-NEON-NEXT: moveq r1, r7
-; CHECK-NEON-NEXT: moveq r0, r7
-; CHECK-NEON-NEXT: movne r7, r3
-; CHECK-NEON-NEXT: cmp r7, #0
-; CHECK-NEON-NEXT: movwmi r0, #0
-; CHECK-NEON-NEXT: movwmi r1, #0
+; CHECK-NEON-NEXT: vmov.32 d1[0], r6
+; CHECK-NEON-NEXT: movwlt r5, #1
+; CHECK-NEON-NEXT: cmp r5, #0
+; CHECK-NEON-NEXT: moveq r0, r5
+; CHECK-NEON-NEXT: movne r5, r1
; CHECK-NEON-NEXT: vmov.32 d0[0], r0
; CHECK-NEON-NEXT: vmov.32 d1[1], r4
-; CHECK-NEON-NEXT: vmov.32 d0[1], r1
+; CHECK-NEON-NEXT: vmov.32 d0[1], r5
; CHECK-NEON-NEXT: vpop {d8}
-; CHECK-NEON-NEXT: pop {r4, r5, r6, r7, r11, pc}
+; CHECK-NEON-NEXT: pop {r4, r5, r6, pc}
;
; CHECK-FP16-LABEL: ustest_f16i64_mm:
; CHECK-FP16: @ %bb.0: @ %entry
-; CHECK-FP16-NEXT: .save {r4, r5, r6, r7, r11, lr}
-; CHECK-FP16-NEXT: push {r4, r5, r6, r7, r11, lr}
+; CHECK-FP16-NEXT: .save {r4, r5, r6, lr}
+; CHECK-FP16-NEXT: push {r4, r5, r6, lr}
; CHECK-FP16-NEXT: vmov.u16 r0, d0[1]
-; CHECK-FP16-NEXT: vmov.u16 r7, d0[0]
+; CHECK-FP16-NEXT: vmov.u16 r5, d0[0]
; CHECK-FP16-NEXT: vmov s0, r0
; CHECK-FP16-NEXT: bl __fixhfti
-; CHECK-FP16-NEXT: mov r5, r0
-; CHECK-FP16-NEXT: subs r0, r2, #1
-; CHECK-FP16-NEXT: sbcs r0, r3, #0
-; CHECK-FP16-NEXT: vmov s0, r7
-; CHECK-FP16-NEXT: mov r0, #0
+; CHECK-FP16-NEXT: cmp r3, #0
; CHECK-FP16-NEXT: mov r4, r1
-; CHECK-FP16-NEXT: movwlt r0, #1
-; CHECK-FP16-NEXT: cmp r0, #0
-; CHECK-FP16-NEXT: moveq r5, r0
-; CHECK-FP16-NEXT: moveq r4, r0
-; CHECK-FP16-NEXT: movne r0, r3
-; CHECK-FP16-NEXT: cmp r0, #0
-; CHECK-FP16-NEXT: mov r6, #0
+; CHECK-FP16-NEXT: movwmi r2, #0
+; CHECK-FP16-NEXT: movwmi r0, #0
; CHECK-FP16-NEXT: movwmi r4, #0
-; CHECK-FP16-NEXT: movwmi r5, #0
-; CHECK-FP16-NEXT: bl __fixhfti
+; CHECK-FP16-NEXT: bic r1, r3, r3, asr #31
; CHECK-FP16-NEXT: subs r2, r2, #1
-; CHECK-FP16-NEXT: vmov.32 d1[0], r5
-; CHECK-FP16-NEXT: sbcs r2, r3, #0
+; CHECK-FP16-NEXT: vmov s0, r5
+; CHECK-FP16-NEXT: sbcs r1, r1, #0
+; CHECK-FP16-NEXT: mov r6, #0
; CHECK-FP16-NEXT: movwlt r6, #1
; CHECK-FP16-NEXT: cmp r6, #0
-; CHECK-FP16-NEXT: moveq r1, r6
-; CHECK-FP16-NEXT: moveq r0, r6
-; CHECK-FP16-NEXT: movne r6, r3
-; CHECK-FP16-NEXT: cmp r6, #0
-; CHECK-FP16-NEXT: movwmi r0, #0
+; CHECK-FP16-NEXT: moveq r4, r6
+; CHECK-FP16-NEXT: mov r5, #0
+; CHECK-FP16-NEXT: movne r6, r0
+; CHECK-FP16-NEXT: bl __fixhfti
+; CHECK-FP16-NEXT: cmp r3, #0
+; CHECK-FP16-NEXT: bic r3, r3, r3, asr #31
+; CHECK-FP16-NEXT: movwmi r2, #0
; CHECK-FP16-NEXT: movwmi r1, #0
+; CHECK-FP16-NEXT: movwmi r0, #0
+; CHECK-FP16-NEXT: subs r2, r2, #1
+; CHECK-FP16-NEXT: sbcs r2, r3, #0
+; CHECK-FP16-NEXT: vmov.32 d1[0], r6
+; CHECK-FP16-NEXT: movwlt r5, #1
+; CHECK-FP16-NEXT: cmp r5, #0
+; CHECK-FP16-NEXT: moveq r0, r5
+; CHECK-FP16-NEXT: movne r5, r1
; CHECK-FP16-NEXT: vmov.32 d0[0], r0
; CHECK-FP16-NEXT: vmov.32 d1[1], r4
-; CHECK-FP16-NEXT: vmov.32 d0[1], r1
-; CHECK-FP16-NEXT: pop {r4, r5, r6, r7, r11, pc}
+; CHECK-FP16-NEXT: vmov.32 d0[1], r5
+; CHECK-FP16-NEXT: pop {r4, r5, r6, pc}
entry:
%conv = fptosi <2 x half> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
diff --git a/llvm/test/CodeGen/ARM/sadd_sat.ll b/llvm/test/CodeGen/ARM/sadd_sat.ll
index f0366fe459abb..ac0d694fad683 100644
--- a/llvm/test/CodeGen/ARM/sadd_sat.ll
+++ b/llvm/test/CodeGen/ARM/sadd_sat.ll
@@ -144,28 +144,28 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
}
define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
-; CHECK-T1-LABEL: func16:
-; CHECK-T1: @ %bb.0:
-; CHECK-T1-NEXT: adds r0, r0, r1
-; CHECK-T1-NEXT: ldr r1, .LCPI2_0
-; CHECK-T1-NEXT: cmp r0, r1
-; CHECK-T1-NEXT: blt .LBB2_2
-; CHECK-T1-NEXT: @ %bb.1:
-; CHECK-T1-NEXT: {{movs|mov}} r0, r1
-; CHECK-T1-NEXT: .LBB2_2:
-; CHECK-T1-NEXT: ldr r1, .LCPI2_1
-; CHECK-T1-NEXT: cmp r0, r1
-; CHECK-T1-NEXT: bgt .LBB2_4
-; CHECK-T1-NEXT: @ %bb.3:
-; CHECK-T1-NEXT: {{movs|mov}} r0, r1
-; CHECK-T1-NEXT: .LBB2_4:
-; CHECK-T1-NEXT: bx lr
-; CHECK-T1-NEXT: .p2align 2
-; CHECK-T1-NEXT: @ %bb.5:
-; CHECK-T1-NEXT: .LCPI2_0:
-; CHECK-T1-NEXT: .long 32767 @ 0x7fff
-; CHECK-T1-NEXT: .LCPI2_1:
-; CHECK-T1-NEXT: .long 4294934528 @ 0xffff8000
+; CHECK-T16-LABEL: func16:
+; CHECK-T16: @ %bb.0:
+; CHECK-T16-NEXT: adds r0, r0, r1
+; CHECK-T16-NEXT: ldr r1, .LCPI2_0
+; CHECK-T16-NEXT: cmp r0, r1
+; CHECK-T16-NEXT: bgt .LBB2_2
+; CHECK-T16-NEXT: @ %bb.1:
+; CHECK-T16-NEXT: mov r0, r1
+; CHECK-T16-NEXT: .LBB2_2:
+; CHECK-T16-NEXT: ldr r1, .LCPI2_1
+; CHECK-T16-NEXT: cmp r0, r1
+; CHECK-T16-NEXT: blt .LBB2_4
+; CHECK-T16-NEXT: @ %bb.3:
+; CHECK-T16-NEXT: mov r0, r1
+; CHECK-T16-NEXT: .LBB2_4:
+; CHECK-T16-NEXT: bx lr
+; CHECK-T16-NEXT: .p2align 2
+; CHECK-T16-NEXT: @ %bb.5:
+; CHECK-T16-NEXT: .LCPI2_0:
+; CHECK-T16-NEXT: .long 4294934528 @ 0xffff8000
+; CHECK-T16-NEXT: .LCPI2_1:
+; CHECK-T16-NEXT: .long 32767 @ 0x7fff
;
; CHECK-T2NODSP-LABEL: func16:
; CHECK-T2NODSP: @ %bb.0:
@@ -181,14 +181,14 @@ define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
;
; CHECK-ARMNODPS-LABEL: func16:
; CHECK-ARMNODPS: @ %bb.0:
-; CHECK-ARMNODPS-NEXT: add r0, r0, r1
-; CHECK-ARMNODPS-NEXT: mov r1, #255
-; CHECK-ARMNODPS-NEXT: orr r1, r1, #32512
-; CHECK-ARMNODPS-NEXT: cmp r0, r1
-; CHECK-ARMNODPS-NEXT: movlt r1, r0
+; CHECK-ARMNODPS-NEXT: add r1, r0, r1
; CHECK-ARMNODPS-NEXT: ldr r0, .LCPI2_0
; CHECK-ARMNODPS-NEXT: cmn r1, #32768
; CHECK-ARMNODPS-NEXT: movgt r0, r1
+; CHECK-ARMNODPS-NEXT: mov r1, #255
+; CHECK-ARMNODPS-NEXT: orr r1, r1, #32512
+; CHECK-ARMNODPS-NEXT: cmp r0, r1
+; CHECK-ARMNODPS-NEXT: movge r0, r1
; CHECK-ARMNODPS-NEXT: bx lr
; CHECK-ARMNODPS-NEXT: .p2align 2
; CHECK-ARMNODPS-NEXT: @ %bb.1:
@@ -203,6 +203,29 @@ define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #16
; CHECK-ARMBASEDSP-NEXT: bx lr
;
+; CHECK-T15TE-LABEL: func16:
+; CHECK-T15TE: @ %bb.0:
+; CHECK-T15TE-NEXT: adds r0, r0, r1
+; CHECK-T15TE-NEXT: ldr r1, .LCPI2_0
+; CHECK-T15TE-NEXT: cmp r0, r1
+; CHECK-T15TE-NEXT: bgt .LBB2_2
+; CHECK-T15TE-NEXT: @ %bb.1:
+; CHECK-T15TE-NEXT: movs r0, r1
+; CHECK-T15TE-NEXT: .LBB2_2:
+; CHECK-T15TE-NEXT: ldr r1, .LCPI2_1
+; CHECK-T15TE-NEXT: cmp r0, r1
+; CHECK-T15TE-NEXT: blt .LBB2_4
+; CHECK-T15TE-NEXT: @ %bb.3:
+; CHECK-T15TE-NEXT: movs r0, r1
+; CHECK-T15TE-NEXT: .LBB2_4:
+; CHECK-T15TE-NEXT: bx lr
+; CHECK-T15TE-NEXT: .p2align 2
+; CHECK-T15TE-NEXT: @ %bb.5:
+; CHECK-T15TE-NEXT: .LCPI2_0:
+; CHECK-T15TE-NEXT: .long 4294934528 @ 0xffff8000
+; CHECK-T15TE-NEXT: .LCPI2_1:
+; CHECK-T15TE-NEXT: .long 32767 @ 0x7fff
+;
; CHECK-ARMDSP-LABEL: func16:
; CHECK-ARMDSP: @ %bb.0:
; CHECK-ARMDSP-NEXT: qadd16 r0, r0, r1
@@ -213,22 +236,25 @@ define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
}
define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
-; CHECK-T1-LABEL: func8:
-; CHECK-T1: @ %bb.0:
-; CHECK-T1-NEXT: adds r0, r0, r1
-; CHECK-T1-NEXT: movs r1, #127
-; CHECK-T1-NEXT: cmp r0, #127
-; CHECK-T1-NEXT: blt .LBB3_2
-; CHECK-T1-NEXT: @ %bb.1:
-; CHECK-T1-NEXT: {{movs|mov}} r0, r1
-; CHECK-T1-NEXT: .LBB3_2:
-; CHECK-T1-NEXT: mvns r1, r1
-; CHECK-T1-NEXT: cmp r0, r1
-; CHECK-T1-NEXT: bgt .LBB3_4
-; CHECK-T1-NEXT: @ %bb.3:
-; CHECK-T1-NEXT: {{movs|mov}} r0, r1
-; CHECK-T1-NEXT: .LBB3_4:
-; CHECK-T1-NEXT: bx lr
+; CHECK-T16-LABEL: func8:
+; CHECK-T16: @ %bb.0:
+; CHECK-T16-NEXT: adds r0, r0, r1
+; CHECK-T16-NEXT: movs r1, #127
+; CHECK-T16-NEXT: mvns r2, r1
+; CHECK-T16-NEXT: cmp r0, r2
+; CHECK-T16-NEXT: ble .LBB3_3
+; CHECK-T16-NEXT: @ %bb.1:
+; CHECK-T16-NEXT: cmp r0, #127
+; CHECK-T16-NEXT: bge .LBB3_4
+; CHECK-T16-NEXT: .LBB3_2:
+; CHECK-T16-NEXT: bx lr
+; CHECK-T16-NEXT: .LBB3_3:
+; CHECK-T16-NEXT: mov r0, r2
+; CHECK-T16-NEXT: cmp r0, #127
+; CHECK-T16-NEXT: blt .LBB3_2
+; CHECK-T16-NEXT: .LBB3_4:
+; CHECK-T16-NEXT: mov r0, r1
+; CHECK-T16-NEXT: bx lr
;
; CHECK-T2NODSP-LABEL: func8:
; CHECK-T2NODSP: @ %bb.0:
@@ -245,10 +271,10 @@ define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
; CHECK-ARMNODPS-LABEL: func8:
; CHECK-ARMNODPS: @ %bb.0:
; CHECK-ARMNODPS-NEXT: add r0, r0, r1
-; CHECK-ARMNODPS-NEXT: cmp r0, #127
-; CHECK-ARMNODPS-NEXT: movge r0, #127
; CHECK-ARMNODPS-NEXT: cmn r0, #128
; CHECK-ARMNODPS-NEXT: mvnle r0, #127
+; CHECK-ARMNODPS-NEXT: cmp r0, #127
+; CHECK-ARMNODPS-NEXT: movge r0, #127
; CHECK-ARMNODPS-NEXT: bx lr
;
; CHECK-ARMBASEDSP-LABEL: func8:
@@ -259,6 +285,26 @@ define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #24
; CHECK-ARMBASEDSP-NEXT: bx lr
;
+; CHECK-T15TE-LABEL: func8:
+; CHECK-T15TE: @ %bb.0:
+; CHECK-T15TE-NEXT: adds r0, r0, r1
+; CHECK-T15TE-NEXT: movs r1, #127
+; CHECK-T15TE-NEXT: mvns r2, r1
+; CHECK-T15TE-NEXT: cmp r0, r2
+; CHECK-T15TE-NEXT: ble .LBB3_3
+; CHECK-T15TE-NEXT: @ %bb.1:
+; CHECK-T15TE-NEXT: cmp r0, #127
+; CHECK-T15TE-NEXT: bge .LBB3_4
+; CHECK-T15TE-NEXT: .LBB3_2:
+; CHECK-T15TE-NEXT: bx lr
+; CHECK-T15TE-NEXT: .LBB3_3:
+; CHECK-T15TE-NEXT: movs r0, r2
+; CHECK-T15TE-NEXT: cmp r0, #127
+; CHECK-T15TE-NEXT: blt .LBB3_2
+; CHECK-T15TE-NEXT: .LBB3_4:
+; CHECK-T15TE-NEXT: movs r0, r1
+; CHECK-T15TE-NEXT: bx lr
+;
; CHECK-ARMDSP-LABEL: func8:
; CHECK-ARMDSP: @ %bb.0:
; CHECK-ARMDSP-NEXT: qadd8 r0, r0, r1
@@ -269,22 +315,25 @@ define signext i8 @func8(i8 signext %x, i8 signext %y) nounwind {
}
define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
-; CHECK-T1-LABEL: func3:
-; CHECK-T1: @ %bb.0:
-; CHECK-T1-NEXT: adds r0, r0, r1
-; CHECK-T1-NEXT: movs r1, #7
-; CHECK-T1-NEXT: cmp r0, #7
-; CHECK-T1-NEXT: blt .LBB4_2
-; CHECK-T1-NEXT: @ %bb.1:
-; CHECK-T1-NEXT: {{movs|mov}} r0, r1
-; CHECK-T1-NEXT: .LBB4_2:
-; CHECK-T1-NEXT: mvns r1, r1
-; CHECK-T1-NEXT: cmp r0, r1
-; CHECK-T1-NEXT: bgt .LBB4_4
-; CHECK-T1-NEXT: @ %bb.3:
-; CHECK-T1-NEXT: {{movs|mov}} r0, r1
-; CHECK-T1-NEXT: .LBB4_4:
-; CHECK-T1-NEXT: bx lr
+; CHECK-T16-LABEL: func3:
+; CHECK-T16: @ %bb.0:
+; CHECK-T16-NEXT: adds r0, r0, r1
+; CHECK-T16-NEXT: movs r1, #7
+; CHECK-T16-NEXT: mvns r2, r1
+; CHECK-T16-NEXT: cmp r0, r2
+; CHECK-T16-NEXT: ble .LBB4_3
+; CHECK-T16-NEXT: @ %bb.1:
+; CHECK-T16-NEXT: cmp r0, #7
+; CHECK-T16-NEXT: bge .LBB4_4
+; CHECK-T16-NEXT: .LBB4_2:
+; CHECK-T16-NEXT: bx lr
+; CHECK-T16-NEXT: .LBB4_3:
+; CHECK-T16-NEXT: mov r0, r2
+; CHECK-T16-NEXT: cmp r0, #7
+; CHECK-T16-NEXT: blt .LBB4_2
+; CHECK-T16-NEXT: .LBB4_4:
+; CHECK-T16-NEXT: mov r0, r1
+; CHECK-T16-NEXT: bx lr
;
; CHECK-T2NODSP-LABEL: func3:
; CHECK-T2NODSP: @ %bb.0:
@@ -303,10 +352,10 @@ define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
; CHECK-ARMNODPS-LABEL: func3:
; CHECK-ARMNODPS: @ %bb.0:
; CHECK-ARMNODPS-NEXT: add r0, r0, r1
-; CHECK-ARMNODPS-NEXT: cmp r0, #7
-; CHECK-ARMNODPS-NEXT: movge r0, #7
; CHECK-ARMNODPS-NEXT: cmn r0, #8
; CHECK-ARMNODPS-NEXT: mvnle r0, #7
+; CHECK-ARMNODPS-NEXT: cmp r0, #7
+; CHECK-ARMNODPS-NEXT: movge r0, #7
; CHECK-ARMNODPS-NEXT: bx lr
;
; CHECK-ARMBASEDSP-LABEL: func3:
@@ -317,6 +366,26 @@ define signext i4 @func3(i4 signext %x, i4 signext %y) nounwind {
; CHECK-ARMBASEDSP-NEXT: asr r0, r0, #28
; CHECK-ARMBASEDSP-NEXT: bx lr
;
+; CHECK-T15TE-LABEL: func3:
+; CHECK-T15TE: @ %bb.0:
+; CHECK-T15TE-NEXT: adds r0, r0, r1
+; CHECK-T15TE-NEXT: movs r1, #7
+; CHECK-T15TE-NEXT: mvns r2, r1
+; CHECK-T15TE-NEXT: cmp r0, r2
+; CHECK-T15TE-NEXT: ble .LBB4_3
+; CHECK-T15TE-NEXT: @ %bb.1:
+; CHECK-T15TE-NEXT: cmp r0, #7
+; CHECK-T15TE-NEXT: bge .LBB4_4
+; CHECK-T15TE-NEXT: .LBB4_2:
+; CHECK-T15TE-NEXT: bx lr
+; CHECK-T15TE-NEXT: .LBB4_3:
+; CHECK-T15TE-NEXT: movs r0, r2
+; CHECK-T15TE-NEXT: cmp r0, #7
+; CHECK-T15TE-NEXT: blt .LBB4_2
+; CHECK-T15TE-NEXT: .LBB4_4:
+; CHECK-T15TE-NEXT: movs r0, r1
+; CHECK-T15TE-NEXT: bx lr
+;
; CHECK-ARMDSP-LABEL: func3:
; CHECK-ARMDSP: @ %bb.0:
; CHECK-ARMDSP-NEXT: lsl r0, r0, #28
diff --git a/llvm/test/CodeGen/ARM/sat-to-bitop.ll b/llvm/test/CodeGen/ARM/sat-to-bitop.ll
index dcd396749ce57..e9b7cb6730f23 100644
--- a/llvm/test/CodeGen/ARM/sat-to-bitop.ll
+++ b/llvm/test/CodeGen/ARM/sat-to-bitop.ll
@@ -36,27 +36,23 @@ entry:
define i16 @sat0_base_16bit(i16 %x) #0 {
; CHECK-ARM-LABEL: sat0_base_16bit:
; CHECK-ARM: @ %bb.0: @ %entry
-; CHECK-ARM-NEXT: lsl r1, r0, #16
-; CHECK-ARM-NEXT: asrs r1, r1, #16
-; CHECK-ARM-NEXT: movmi r0, #0
+; CHECK-ARM-NEXT: lsl r0, r0, #16
+; CHECK-ARM-NEXT: asr r1, r0, #16
+; CHECK-ARM-NEXT: bic r0, r1, r0, asr #31
; CHECK-ARM-NEXT: mov pc, lr
;
; CHECK-T-LABEL: sat0_base_16bit:
; CHECK-T: @ %bb.0: @ %entry
-; CHECK-T-NEXT: lsls r1, r0, #16
-; CHECK-T-NEXT: asrs r1, r1, #16
-; CHECK-T-NEXT: bpl .LBB1_2
-; CHECK-T-NEXT: @ %bb.1:
-; CHECK-T-NEXT: movs r0, #0
-; CHECK-T-NEXT: .LBB1_2: @ %entry
+; CHECK-T-NEXT: lsls r0, r0, #16
+; CHECK-T-NEXT: asrs r1, r0, #31
+; CHECK-T-NEXT: asrs r0, r0, #16
+; CHECK-T-NEXT: bics r0, r1
; CHECK-T-NEXT: bx lr
;
; CHECK-T2-LABEL: sat0_base_16bit:
; CHECK-T2: @ %bb.0: @ %entry
; CHECK-T2-NEXT: sxth r1, r0
-; CHECK-T2-NEXT: cmp r1, #0
-; CHECK-T2-NEXT: it mi
-; CHECK-T2-NEXT: movmi r0, #0
+; CHECK-T2-NEXT: bic.w r0, r0, r1, asr #15
; CHECK-T2-NEXT: bx lr
entry:
%cmpLow = icmp slt i16 %x, 0
@@ -69,27 +65,23 @@ entry:
define i8 @sat0_base_8bit(i8 %x) #0 {
; CHECK-ARM-LABEL: sat0_base_8bit:
; CHECK-ARM: @ %bb.0: @ %entry
-; CHECK-ARM-NEXT: lsl r1, r0, #24
-; CHECK-ARM-NEXT: asrs r1, r1, #24
-; CHECK-ARM-NEXT: movmi r0, #0
+; CHECK-ARM-NEXT: lsl r0, r0, #24
+; CHECK-ARM-NEXT: asr r1, r0, #24
+; CHECK-ARM-NEXT: bic r0, r1, r0, asr #31
; CHECK-ARM-NEXT: mov pc, lr
;
; CHECK-T-LABEL: sat0_base_8bit:
; CHECK-T: @ %bb.0: @ %entry
-; CHECK-T-NEXT: lsls r1, r0, #24
-; CHECK-T-NEXT: asrs r1, r1, #24
-; CHECK-T-NEXT: bpl .LBB2_2
-; CHECK-T-NEXT: @ %bb.1:
-; CHECK-T-NEXT: movs r0, #0
-; CHECK-T-NEXT: .LBB2_2: @ %entry
+; CHECK-T-NEXT: lsls r0, r0, #24
+; CHECK-T-NEXT: asrs r1, r0, #31
+; CHECK-T-NEXT: asrs r0, r0, #24
+; CHECK-T-NEXT: bics r0, r1
; CHECK-T-NEXT: bx lr
;
; CHECK-T2-LABEL: sat0_base_8bit:
; CHECK-T2: @ %bb.0: @ %entry
; CHECK-T2-NEXT: sxtb r1, r0
-; CHECK-T2-NEXT: cmp r1, #0
-; CHECK-T2-NEXT: it mi
-; CHECK-T2-NEXT: movmi r0, #0
+; CHECK-T2-NEXT: bic.w r0, r0, r1, asr #7
; CHECK-T2-NEXT: bx lr
entry:
%cmpLow = icmp slt i8 %x, 0
@@ -157,32 +149,23 @@ entry:
define i16 @sat1_base_16bit(i16 %x) #0 {
; CHECK-ARM-LABEL: sat1_base_16bit:
; CHECK-ARM: @ %bb.0: @ %entry
-; CHECK-ARM-NEXT: lsl r1, r0, #16
-; CHECK-ARM-NEXT: asr r1, r1, #16
-; CHECK-ARM-NEXT: cmn r1, #1
-; CHECK-ARM-NEXT: mvnlt r0, #0
+; CHECK-ARM-NEXT: lsl r0, r0, #16
+; CHECK-ARM-NEXT: asr r1, r0, #16
+; CHECK-ARM-NEXT: orr r0, r1, r0, asr #31
; CHECK-ARM-NEXT: mov pc, lr
;
; CHECK-T-LABEL: sat1_base_16bit:
; CHECK-T: @ %bb.0: @ %entry
-; CHECK-T-NEXT: movs r1, #0
-; CHECK-T-NEXT: mvns r1, r1
-; CHECK-T-NEXT: lsls r2, r0, #16
-; CHECK-T-NEXT: asrs r2, r2, #16
-; CHECK-T-NEXT: cmp r2, r1
-; CHECK-T-NEXT: blt .LBB5_2
-; CHECK-T-NEXT: @ %bb.1: @ %entry
-; CHECK-T-NEXT: movs r1, r0
-; CHECK-T-NEXT: .LBB5_2: @ %entry
-; CHECK-T-NEXT: movs r0, r1
+; CHECK-T-NEXT: lsls r0, r0, #16
+; CHECK-T-NEXT: asrs r1, r0, #31
+; CHECK-T-NEXT: asrs r0, r0, #16
+; CHECK-T-NEXT: orrs r0, r1
; CHECK-T-NEXT: bx lr
;
; CHECK-T2-LABEL: sat1_base_16bit:
; CHECK-T2: @ %bb.0: @ %entry
; CHECK-T2-NEXT: sxth r1, r0
-; CHECK-T2-NEXT: cmp.w r1, #-1
-; CHECK-T2-NEXT: it lt
-; CHECK-T2-NEXT: movlt.w r0, #-1
+; CHECK-T2-NEXT: orr.w r0, r0, r1, asr #15
; CHECK-T2-NEXT: bx lr
entry:
%cmpLow = icmp slt i16 %x, -1
@@ -195,32 +178,23 @@ entry:
define i8 @sat1_base_8bit(i8 %x) #0 {
; CHECK-ARM-LABEL: sat1_base_8bit:
; CHECK-ARM: @ %bb.0: @ %entry
-; CHECK-ARM-NEXT: lsl r1, r0, #24
-; CHECK-ARM-NEXT: asr r1, r1, #24
-; CHECK-ARM-NEXT: cmn r1, #1
-; CHECK-ARM-NEXT: mvnlt r0, #0
+; CHECK-ARM-NEXT: lsl r0, r0, #24
+; CHECK-ARM-NEXT: asr r1, r0, #24
+; CHECK-ARM-NEXT: orr r0, r1, r0, asr #31
; CHECK-ARM-NEXT: mov pc, lr
;
; CHECK-T-LABEL: sat1_base_8bit:
; CHECK-T: @ %bb.0: @ %entry
-; CHECK-T-NEXT: movs r1, #0
-; CHECK-T-NEXT: mvns r1, r1
-; CHECK-T-NEXT: lsls r2, r0, #24
-; CHECK-T-NEXT: asrs r2, r2, #24
-; CHECK-T-NEXT: cmp r2, r1
-; CHECK-T-NEXT: blt .LBB6_2
-; CHECK-T-NEXT: @ %bb.1: @ %entry
-; CHECK-T-NEXT: movs r1, r0
-; CHECK-T-NEXT: .LBB6_2: @ %entry
-; CHECK-T-NEXT: movs r0, r1
+; CHECK-T-NEXT: lsls r0, r0, #24
+; CHECK-T-NEXT: asrs r1, r0, #31
+; CHECK-T-NEXT: asrs r0, r0, #24
+; CHECK-T-NEXT: orrs r0, r1
; CHECK-T-NEXT: bx lr
;
; CHECK-T2-LABEL: sat1_base_8bit:
; CHECK-T2: @ %bb.0: @ %entry
; CHECK-T2-NEXT: sxtb r1, r0
-; CHECK-T2-NEXT: cmp.w r1, #-1
-; CHECK-T2-NEXT: it lt
-; CHECK-T2-NEXT: movlt.w r0, #-1
+; CHECK-T2-NEXT: orr.w r0, r0, r1, asr #7
; CHECK-T2-NEXT: bx lr
entry:
%cmpLow = icmp slt i8 %x, -1
diff --git a/llvm/test/CodeGen/ARM/ssat.ll b/llvm/test/CodeGen/ARM/ssat.ll
index ed777f2b1882b..4bbe4018ea631 100644
--- a/llvm/test/CodeGen/ARM/ssat.ll
+++ b/llvm/test/CodeGen/ARM/ssat.ll
@@ -19,13 +19,13 @@
define i32 @sat_base_32bit(i32 %x) #0 {
; V4T-LABEL: sat_base_32bit:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: ldr r1, .LCPI0_0
-; V4T-NEXT: cmp r0, r1
-; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r1, #1065353216
-; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: cmn r0, #8388608
+; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: movle r0, r1
+; V4T-NEXT: ldr r1, .LCPI0_0
+; V4T-NEXT: cmp r0, r1
+; V4T-NEXT: movge r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
@@ -49,17 +49,15 @@ entry:
define i16 @sat_base_16bit(i16 %x) #0 {
; V4T-LABEL: sat_base_16bit:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: mov r2, #255
; V4T-NEXT: lsl r1, r0, #16
-; V4T-NEXT: orr r2, r2, #1792
-; V4T-NEXT: asr r1, r1, #16
-; V4T-NEXT: cmp r1, r2
-; V4T-NEXT: movge r0, r2
-; V4T-NEXT: ldr r2, .LCPI1_0
-; V4T-NEXT: lsl r1, r0, #16
-; V4T-NEXT: asr r1, r1, #16
-; V4T-NEXT: cmn r1, #2048
-; V4T-NEXT: movle r0, r2
+; V4T-NEXT: ldr r0, .LCPI1_0
+; V4T-NEXT: asr r2, r1, #16
+; V4T-NEXT: cmn r2, #2048
+; V4T-NEXT: asrgt r0, r1, #16
+; V4T-NEXT: mov r1, #255
+; V4T-NEXT: orr r1, r1, #1792
+; V4T-NEXT: cmp r0, r1
+; V4T-NEXT: movge r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
@@ -68,15 +66,8 @@ define i16 @sat_base_16bit(i16 %x) #0 {
;
; V6T2-LABEL: sat_base_16bit:
; V6T2: @ %bb.0: @ %entry
-; V6T2-NEXT: sxth r1, r0
-; V6T2-NEXT: movw r2, #2047
-; V6T2-NEXT: cmp r1, r2
-; V6T2-NEXT: movge r0, r2
-; V6T2-NEXT: movw r2, #63488
-; V6T2-NEXT: sxth r1, r0
-; V6T2-NEXT: movt r2, #65535
-; V6T2-NEXT: cmn r1, #2048
-; V6T2-NEXT: movle r0, r2
+; V6T2-NEXT: sxth r0, r0
+; V6T2-NEXT: ssat r0, #12, r0
; V6T2-NEXT: bx lr
entry:
%0 = icmp slt i16 %x, 2047
@@ -92,23 +83,18 @@ define i8 @sat_base_8bit(i8 %x) #0 {
; V4T-LABEL: sat_base_8bit:
; V4T: @ %bb.0: @ %entry
; V4T-NEXT: lsl r1, r0, #24
-; V4T-NEXT: asr r1, r1, #24
-; V4T-NEXT: cmp r1, #31
+; V4T-NEXT: mvn r0, #31
+; V4T-NEXT: asr r2, r1, #24
+; V4T-NEXT: cmn r2, #32
+; V4T-NEXT: asrgt r0, r1, #24
+; V4T-NEXT: cmp r0, #31
; V4T-NEXT: movge r0, #31
-; V4T-NEXT: lsl r1, r0, #24
-; V4T-NEXT: asr r1, r1, #24
-; V4T-NEXT: cmn r1, #32
-; V4T-NEXT: mvnle r0, #31
; V4T-NEXT: bx lr
;
; V6T2-LABEL: sat_base_8bit:
; V6T2: @ %bb.0: @ %entry
-; V6T2-NEXT: sxtb r1, r0
-; V6T2-NEXT: cmp r1, #31
-; V6T2-NEXT: movge r0, #31
-; V6T2-NEXT: sxtb r1, r0
-; V6T2-NEXT: cmn r1, #32
-; V6T2-NEXT: mvnle r0, #31
+; V6T2-NEXT: sxtb r0, r0
+; V6T2-NEXT: ssat r0, #6, r0
; V6T2-NEXT: bx lr
entry:
%0 = icmp slt i8 %x, 31
@@ -128,13 +114,13 @@ entry:
define i32 @sat_lower_upper_1(i32 %x) #0 {
; V4T-LABEL: sat_lower_upper_1:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: ldr r1, .LCPI3_0
-; V4T-NEXT: cmp r0, r1
-; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r1, #1065353216
-; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: cmn r0, #8388608
+; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: movle r0, r1
+; V4T-NEXT: ldr r1, .LCPI3_0
+; V4T-NEXT: cmp r0, r1
+; V4T-NEXT: movge r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
@@ -157,13 +143,13 @@ entry:
define i32 @sat_lower_upper_2(i32 %x) #0 {
; V4T-LABEL: sat_lower_upper_2:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: ldr r1, .LCPI4_0
-; V4T-NEXT: cmp r0, r1
-; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r1, #1065353216
-; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: cmn r0, #8388608
+; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: movle r0, r1
+; V4T-NEXT: ldr r1, .LCPI4_0
+; V4T-NEXT: cmp r0, r1
+; V4T-NEXT: movge r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
@@ -540,26 +526,21 @@ define void @extended(i32 %xx, i16 signext %y, ptr nocapture %z) {
; V4T-LABEL: extended:
; V4T: @ %bb.0: @ %entry
; V4T-NEXT: add r0, r1, r0, lsr #16
-; V4T-NEXT: lsl r1, r0, #16
-; V4T-NEXT: asr r1, r1, #16
-; V4T-NEXT: cmp r1, #127
-; V4T-NEXT: movge r0, #127
-; V4T-NEXT: lsl r1, r0, #16
-; V4T-NEXT: asr r1, r1, #16
+; V4T-NEXT: mvn r3, #127
+; V4T-NEXT: lsl r0, r0, #16
+; V4T-NEXT: asr r1, r0, #16
; V4T-NEXT: cmn r1, #128
-; V4T-NEXT: mvnle r0, #127
-; V4T-NEXT: strb r0, [r2]
+; V4T-NEXT: asrgt r3, r0, #16
+; V4T-NEXT: cmp r3, #127
+; V4T-NEXT: movge r3, #127
+; V4T-NEXT: strb r3, [r2]
; V4T-NEXT: bx lr
;
; V6T2-LABEL: extended:
; V6T2: @ %bb.0: @ %entry
; V6T2-NEXT: add r0, r1, r0, lsr #16
-; V6T2-NEXT: sxth r1, r0
-; V6T2-NEXT: cmp r1, #127
-; V6T2-NEXT: movge r0, #127
-; V6T2-NEXT: sxth r1, r0
-; V6T2-NEXT: cmn r1, #128
-; V6T2-NEXT: mvnle r0, #127
+; V6T2-NEXT: sxth r0, r0
+; V6T2-NEXT: ssat r0, #8, r0
; V6T2-NEXT: strb r0, [r2]
; V6T2-NEXT: bx lr
entry:
@@ -654,13 +635,13 @@ define i32 @formulated_invalid(i32 %a) {
define i32 @mm_sat_base_32bit(i32 %x) {
; V4T-LABEL: mm_sat_base_32bit:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: ldr r1, .LCPI18_0
-; V4T-NEXT: cmp r0, r1
-; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r1, #1065353216
-; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: cmn r0, #8388608
+; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: movle r0, r1
+; V4T-NEXT: ldr r1, .LCPI18_0
+; V4T-NEXT: cmp r0, r1
+; V4T-NEXT: movge r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
@@ -680,15 +661,15 @@ entry:
define i16 @mm_sat_base_16bit(i16 %x) {
; V4T-LABEL: mm_sat_base_16bit:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: mov r2, #255
-; V4T-NEXT: lsl r0, r0, #16
-; V4T-NEXT: orr r2, r2, #1792
-; V4T-NEXT: asr r1, r0, #16
-; V4T-NEXT: cmp r1, r2
-; V4T-NEXT: asrlt r2, r0, #16
+; V4T-NEXT: lsl r1, r0, #16
; V4T-NEXT: ldr r0, .LCPI19_0
+; V4T-NEXT: asr r2, r1, #16
; V4T-NEXT: cmn r2, #2048
-; V4T-NEXT: movgt r0, r2
+; V4T-NEXT: asrgt r0, r1, #16
+; V4T-NEXT: mov r1, #255
+; V4T-NEXT: orr r1, r1, #1792
+; V4T-NEXT: cmp r0, r1
+; V4T-NEXT: movge r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
@@ -710,12 +691,12 @@ define i8 @mm_sat_base_8bit(i8 %x) {
; V4T-LABEL: mm_sat_base_8bit:
; V4T: @ %bb.0: @ %entry
; V4T-NEXT: lsl r1, r0, #24
-; V4T-NEXT: mov r0, #31
+; V4T-NEXT: mvn r0, #31
; V4T-NEXT: asr r2, r1, #24
-; V4T-NEXT: cmp r2, #31
-; V4T-NEXT: asrlt r0, r1, #24
-; V4T-NEXT: cmn r0, #32
-; V4T-NEXT: mvnle r0, #31
+; V4T-NEXT: cmn r2, #32
+; V4T-NEXT: asrgt r0, r1, #24
+; V4T-NEXT: cmp r0, #31
+; V4T-NEXT: movge r0, #31
; V4T-NEXT: bx lr
;
; V6T2-LABEL: mm_sat_base_8bit:
@@ -732,13 +713,13 @@ entry:
define i32 @mm_sat_lower_upper_1(i32 %x) {
; V4T-LABEL: mm_sat_lower_upper_1:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: ldr r1, .LCPI21_0
-; V4T-NEXT: cmp r0, r1
-; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r1, #1065353216
-; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: cmn r0, #8388608
+; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: movle r0, r1
+; V4T-NEXT: ldr r1, .LCPI21_0
+; V4T-NEXT: cmp r0, r1
+; V4T-NEXT: movge r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
@@ -758,13 +739,13 @@ entry:
define i32 @mm_sat_lower_upper_2(i32 %x) {
; V4T-LABEL: mm_sat_lower_upper_2:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: ldr r1, .LCPI22_0
-; V4T-NEXT: cmp r0, r1
-; V4T-NEXT: movge r0, r1
; V4T-NEXT: mov r1, #1065353216
-; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: cmn r0, #8388608
+; V4T-NEXT: orr r1, r1, #-1073741824
; V4T-NEXT: movle r0, r1
+; V4T-NEXT: ldr r1, .LCPI22_0
+; V4T-NEXT: cmp r0, r1
+; V4T-NEXT: movge r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
diff --git a/llvm/test/CodeGen/ARM/usat-with-shift.ll b/llvm/test/CodeGen/ARM/usat-with-shift.ll
index b9c083e498c0c..130abc742850b 100644
--- a/llvm/test/CodeGen/ARM/usat-with-shift.ll
+++ b/llvm/test/CodeGen/ARM/usat-with-shift.ll
@@ -25,24 +25,10 @@ entry:
}
define arm_aapcs_vfpcc i32 @usat_lsl2(i32 %num){
-; ARMV6-LABEL: usat_lsl2:
-; ARMV6: @ %bb.0: @ %entry
-; ARMV6-NEXT: lsl r0, r0, #15
-; ARMV6-NEXT: bic r1, r0, r0, asr #31
-; ARMV6-NEXT: mov r0, #255
-; ARMV6-NEXT: orr r0, r0, #32512
-; ARMV6-NEXT: cmp r1, r0
-; ARMV6-NEXT: movlt r0, r1
-; ARMV6-NEXT: bx lr
-;
-; THUMB-LABEL: usat_lsl2:
-; THUMB: @ %bb.0: @ %entry
-; THUMB-NEXT: lsls r0, r0, #15
-; THUMB-NEXT: movw r1, #32767
-; THUMB-NEXT: bic.w r0, r0, r0, asr #31
-; THUMB-NEXT: cmp r0, r1
-; THUMB-NEXT: csel r0, r0, r1, lt
-; THUMB-NEXT: bx lr
+; CHECK-LABEL: usat_lsl2:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: usat r0, #15, r0, lsl #15
+; CHECK-NEXT: bx lr
entry:
%shl = shl nsw i32 %num, 15
%0 = icmp sgt i32 %shl, 0
@@ -53,24 +39,10 @@ entry:
}
define arm_aapcs_vfpcc i32 @usat_asr2(i32 %num){
-; ARMV6-LABEL: usat_asr2:
-; ARMV6: @ %bb.0: @ %entry
-; ARMV6-NEXT: asr r1, r0, #15
-; ARMV6-NEXT: bic r1, r1, r0, asr #31
-; ARMV6-NEXT: mov r0, #255
-; ARMV6-NEXT: orr r0, r0, #32512
-; ARMV6-NEXT: cmp r1, r0
-; ARMV6-NEXT: movlt r0, r1
-; ARMV6-NEXT: bx lr
-;
-; THUMB-LABEL: usat_asr2:
-; THUMB: @ %bb.0: @ %entry
-; THUMB-NEXT: asrs r1, r0, #15
-; THUMB-NEXT: bic.w r0, r1, r0, asr #31
-; THUMB-NEXT: movw r1, #32767
-; THUMB-NEXT: cmp r0, r1
-; THUMB-NEXT: csel r0, r0, r1, lt
-; THUMB-NEXT: bx lr
+; CHECK-LABEL: usat_asr2:
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: usat r0, #15, r0, asr #15
+; CHECK-NEXT: bx lr
entry:
%shr = ashr i32 %num, 15
%0 = icmp sgt i32 %shr, 0
@@ -81,3 +53,6 @@ entry:
}
declare i32 @llvm.arm.usat(i32, i32)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; ARMV6: {{.*}}
+; THUMB: {{.*}}
diff --git a/llvm/test/CodeGen/ARM/usat.ll b/llvm/test/CodeGen/ARM/usat.ll
index 2e1d0283ebde2..b5b68677f8b19 100644
--- a/llvm/test/CodeGen/ARM/usat.ll
+++ b/llvm/test/CodeGen/ARM/usat.ll
@@ -20,10 +20,10 @@
define i32 @unsigned_sat_base_32bit(i32 %x) #0 {
; V4T-LABEL: unsigned_sat_base_32bit:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: ldr r1, .LCPI0_0
-; V4T-NEXT: cmp r0, r1
-; V4T-NEXT: movlt r1, r0
-; V4T-NEXT: bic r0, r1, r1, asr #31
+; V4T-NEXT: bic r1, r0, r0, asr #31
+; V4T-NEXT: ldr r0, .LCPI0_0
+; V4T-NEXT: cmp r1, r0
+; V4T-NEXT: movlt r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
@@ -63,35 +63,32 @@ entry:
define i16 @unsigned_sat_base_16bit(i16 %x) #0 {
; V4T-LABEL: unsigned_sat_base_16bit:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: mov r2, #255
-; V4T-NEXT: lsl r1, r0, #16
-; V4T-NEXT: orr r2, r2, #1792
-; V4T-NEXT: asr r1, r1, #16
-; V4T-NEXT: cmp r1, r2
-; V4T-NEXT: movlt r2, r0
-; V4T-NEXT: lsl r0, r2, #16
-; V4T-NEXT: bic r0, r2, r0, asr #31
+; V4T-NEXT: lsl r0, r0, #16
+; V4T-NEXT: asr r1, r0, #16
+; V4T-NEXT: bic r1, r1, r0, asr #31
+; V4T-NEXT: mov r0, #255
+; V4T-NEXT: orr r0, r0, #1792
+; V4T-NEXT: cmp r1, r0
+; V4T-NEXT: movlt r0, r1
; V4T-NEXT: bx lr
;
; V6-LABEL: unsigned_sat_base_16bit:
; V6: @ %bb.0: @ %entry
-; V6-NEXT: mov r2, #255
-; V6-NEXT: sxth r1, r0
-; V6-NEXT: orr r2, r2, #1792
-; V6-NEXT: cmp r1, r2
-; V6-NEXT: movlt r2, r0
-; V6-NEXT: sxth r0, r2
-; V6-NEXT: bic r0, r2, r0, asr #15
+; V6-NEXT: mov r1, #255
+; V6-NEXT: sxth r0, r0
+; V6-NEXT: orr r1, r1, #1792
+; V6-NEXT: cmp r0, r1
+; V6-NEXT: movlt r1, r0
+; V6-NEXT: bic r0, r1, r1, asr #15
; V6-NEXT: bx lr
;
; V6T2-LABEL: unsigned_sat_base_16bit:
; V6T2: @ %bb.0: @ %entry
-; V6T2-NEXT: sxth r1, r0
-; V6T2-NEXT: movw r2, #2047
-; V6T2-NEXT: cmp r1, r2
-; V6T2-NEXT: movlt r2, r0
-; V6T2-NEXT: sxth r0, r2
-; V6T2-NEXT: bic r0, r2, r0, asr #15
+; V6T2-NEXT: sxth r0, r0
+; V6T2-NEXT: movw r1, #2047
+; V6T2-NEXT: cmp r0, r1
+; V6T2-NEXT: movlt r1, r0
+; V6T2-NEXT: bic r0, r1, r1, asr #15
; V6T2-NEXT: bx lr
entry:
%0 = icmp slt i16 %x, 2047
@@ -106,30 +103,27 @@ entry:
define i8 @unsigned_sat_base_8bit(i8 %x) #0 {
; V4T-LABEL: unsigned_sat_base_8bit:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: lsl r1, r0, #24
-; V4T-NEXT: asr r1, r1, #24
-; V4T-NEXT: cmp r1, #31
+; V4T-NEXT: lsl r0, r0, #24
+; V4T-NEXT: asr r1, r0, #24
+; V4T-NEXT: bic r0, r1, r0, asr #31
+; V4T-NEXT: cmp r0, #31
; V4T-NEXT: movge r0, #31
-; V4T-NEXT: lsl r1, r0, #24
-; V4T-NEXT: bic r0, r0, r1, asr #31
; V4T-NEXT: bx lr
;
; V6-LABEL: unsigned_sat_base_8bit:
; V6: @ %bb.0: @ %entry
-; V6-NEXT: sxtb r1, r0
-; V6-NEXT: cmp r1, #31
+; V6-NEXT: sxtb r0, r0
+; V6-NEXT: cmp r0, #31
; V6-NEXT: movge r0, #31
-; V6-NEXT: sxtb r1, r0
-; V6-NEXT: bic r0, r0, r1, asr #7
+; V6-NEXT: bic r0, r0, r0, asr #7
; V6-NEXT: bx lr
;
; V6T2-LABEL: unsigned_sat_base_8bit:
; V6T2: @ %bb.0: @ %entry
-; V6T2-NEXT: sxtb r1, r0
-; V6T2-NEXT: cmp r1, #31
+; V6T2-NEXT: sxtb r0, r0
+; V6T2-NEXT: cmp r0, #31
; V6T2-NEXT: movge r0, #31
-; V6T2-NEXT: sxtb r1, r0
-; V6T2-NEXT: bic r0, r0, r1, asr #7
+; V6T2-NEXT: bic r0, r0, r0, asr #7
; V6T2-NEXT: bx lr
entry:
%0 = icmp slt i8 %x, 31
@@ -148,10 +142,10 @@ entry:
define i32 @unsigned_sat_lower_upper_1(i32 %x) #0 {
; V4T-LABEL: unsigned_sat_lower_upper_1:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: ldr r1, .LCPI3_0
-; V4T-NEXT: cmp r0, r1
-; V4T-NEXT: movlt r1, r0
-; V4T-NEXT: bic r0, r1, r1, asr #31
+; V4T-NEXT: bic r1, r0, r0, asr #31
+; V4T-NEXT: ldr r0, .LCPI3_0
+; V4T-NEXT: cmp r1, r0
+; V4T-NEXT: movlt r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
@@ -190,10 +184,10 @@ entry:
define i32 @unsigned_sat_lower_upper_2(i32 %x) #0 {
; V4T-LABEL: unsigned_sat_lower_upper_2:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: ldr r1, .LCPI4_0
-; V4T-NEXT: cmp r0, r1
-; V4T-NEXT: movlt r1, r0
-; V4T-NEXT: bic r0, r1, r1, asr #31
+; V4T-NEXT: bic r1, r0, r0, asr #31
+; V4T-NEXT: ldr r0, .LCPI4_0
+; V4T-NEXT: cmp r1, r0
+; V4T-NEXT: movlt r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
@@ -670,10 +664,10 @@ entry:
define i32 @mm_unsigned_sat_base_32bit(i32 %x) {
; V4T-LABEL: mm_unsigned_sat_base_32bit:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: ldr r1, .LCPI15_0
-; V4T-NEXT: cmp r0, r1
-; V4T-NEXT: movlt r1, r0
-; V4T-NEXT: bic r0, r1, r1, asr #31
+; V4T-NEXT: bic r1, r0, r0, asr #31
+; V4T-NEXT: ldr r0, .LCPI15_0
+; V4T-NEXT: cmp r1, r0
+; V4T-NEXT: movlt r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
@@ -698,25 +692,34 @@ entry:
define i16 @mm_unsigned_sat_base_16bit(i16 %x) {
; V4T-LABEL: mm_unsigned_sat_base_16bit:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: mov r2, #255
; V4T-NEXT: lsl r0, r0, #16
-; V4T-NEXT: orr r2, r2, #1792
; V4T-NEXT: asr r1, r0, #16
-; V4T-NEXT: cmp r1, r2
-; V4T-NEXT: asrlt r2, r0, #16
-; V4T-NEXT: bic r0, r2, r2, asr #31
+; V4T-NEXT: bic r1, r1, r0, asr #31
+; V4T-NEXT: mov r0, #255
+; V4T-NEXT: orr r0, r0, #1792
+; V4T-NEXT: cmp r1, r0
+; V4T-NEXT: movlt r0, r1
; V4T-NEXT: bx lr
;
; V6-LABEL: mm_unsigned_sat_base_16bit:
; V6: @ %bb.0: @ %entry
-; V6-NEXT: sxth r0, r0
-; V6-NEXT: usat r0, #11, r0
+; V6-NEXT: sxth r1, r0
+; V6-NEXT: bic r0, r0, r1, lsr #15
+; V6-NEXT: sxth r1, r0
+; V6-NEXT: mov r0, #255
+; V6-NEXT: orr r0, r0, #1792
+; V6-NEXT: cmp r1, r0
+; V6-NEXT: movlt r0, r1
; V6-NEXT: bx lr
;
; V6T2-LABEL: mm_unsigned_sat_base_16bit:
; V6T2: @ %bb.0: @ %entry
-; V6T2-NEXT: sxth r0, r0
-; V6T2-NEXT: usat r0, #11, r0
+; V6T2-NEXT: sxth r1, r0
+; V6T2-NEXT: bic r0, r0, r1, lsr #15
+; V6T2-NEXT: sxth r1, r0
+; V6T2-NEXT: movw r0, #2047
+; V6T2-NEXT: cmp r1, r0
+; V6T2-NEXT: movlt r0, r1
; V6T2-NEXT: bx lr
entry:
%0 = call i16 @llvm.smin.i16(i16 %x, i16 2047)
@@ -728,23 +731,28 @@ define i8 @mm_unsigned_sat_base_8bit(i8 %x) {
; V4T-LABEL: mm_unsigned_sat_base_8bit:
; V4T: @ %bb.0: @ %entry
; V4T-NEXT: lsl r0, r0, #24
-; V4T-NEXT: mov r2, #31
; V4T-NEXT: asr r1, r0, #24
-; V4T-NEXT: cmp r1, #31
-; V4T-NEXT: asrlt r2, r0, #24
-; V4T-NEXT: bic r0, r2, r2, asr #31
+; V4T-NEXT: bic r0, r1, r0, asr #31
+; V4T-NEXT: cmp r0, #31
+; V4T-NEXT: movge r0, #31
; V4T-NEXT: bx lr
;
; V6-LABEL: mm_unsigned_sat_base_8bit:
; V6: @ %bb.0: @ %entry
+; V6-NEXT: sxtb r1, r0
+; V6-NEXT: bic r0, r0, r1, lsr #7
; V6-NEXT: sxtb r0, r0
-; V6-NEXT: usat r0, #5, r0
+; V6-NEXT: cmp r0, #31
+; V6-NEXT: movge r0, #31
; V6-NEXT: bx lr
;
; V6T2-LABEL: mm_unsigned_sat_base_8bit:
; V6T2: @ %bb.0: @ %entry
+; V6T2-NEXT: sxtb r1, r0
+; V6T2-NEXT: bic r0, r0, r1, lsr #7
; V6T2-NEXT: sxtb r0, r0
-; V6T2-NEXT: usat r0, #5, r0
+; V6T2-NEXT: cmp r0, #31
+; V6T2-NEXT: movge r0, #31
; V6T2-NEXT: bx lr
entry:
%0 = call i8 @llvm.smin.i8(i8 %x, i8 31)
@@ -755,10 +763,10 @@ entry:
define i32 @mm_unsigned_sat_lower_upper_1(i32 %x) {
; V4T-LABEL: mm_unsigned_sat_lower_upper_1:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: ldr r1, .LCPI18_0
-; V4T-NEXT: cmp r0, r1
-; V4T-NEXT: movlt r1, r0
-; V4T-NEXT: bic r0, r1, r1, asr #31
+; V4T-NEXT: bic r1, r0, r0, asr #31
+; V4T-NEXT: ldr r0, .LCPI18_0
+; V4T-NEXT: cmp r1, r0
+; V4T-NEXT: movlt r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
@@ -783,10 +791,10 @@ entry:
define i32 @mm_unsigned_sat_lower_upper_2(i32 %x) {
; V4T-LABEL: mm_unsigned_sat_lower_upper_2:
; V4T: @ %bb.0: @ %entry
-; V4T-NEXT: ldr r1, .LCPI19_0
-; V4T-NEXT: cmp r0, r1
-; V4T-NEXT: movlt r1, r0
-; V4T-NEXT: bic r0, r1, r1, asr #31
+; V4T-NEXT: bic r1, r0, r0, asr #31
+; V4T-NEXT: ldr r0, .LCPI19_0
+; V4T-NEXT: cmp r1, r0
+; V4T-NEXT: movlt r0, r1
; V4T-NEXT: bx lr
; V4T-NEXT: .p2align 2
; V4T-NEXT: @ %bb.1:
diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-lamcas.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-lamcas.ll
index 990febfa05cd0..2451847083b85 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-lamcas.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-lamcas.ll
@@ -445,18 +445,18 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB10_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB10_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB10_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -464,18 +464,18 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB10_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB10_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB10_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b acquire
@@ -512,18 +512,18 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB11_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB11_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB11_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -531,18 +531,18 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB11_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB11_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB11_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b acquire
@@ -578,19 +578,18 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB12_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB12_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB12_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -598,19 +597,18 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB12_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB12_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB12_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b acquire
@@ -647,19 +645,18 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB13_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB13_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB13_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -667,19 +664,18 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB13_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB13_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB13_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b acquire
@@ -719,17 +715,17 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB14_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB14_1
+; LA64-LAMCAS-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB14_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -737,17 +733,17 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB14_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB14_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB14_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b acquire
@@ -789,17 +785,17 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB15_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB15_1
+; LA64-LAMCAS-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB15_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -807,17 +803,17 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB15_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB15_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB15_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b acquire
@@ -857,18 +853,17 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB16_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB16_1
+; LA64-LAMCAS-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB16_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -876,18 +871,17 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB16_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB16_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB16_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b acquire
@@ -929,18 +923,17 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB17_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB17_1
+; LA64-LAMCAS-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB17_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -948,18 +941,17 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB17_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB17_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB17_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b acquire
@@ -1837,18 +1829,18 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB38_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB38_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB38_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -1856,18 +1848,18 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB38_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB38_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB38_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b release
@@ -1904,18 +1896,18 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB39_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB39_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB39_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -1923,18 +1915,18 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB39_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB39_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB39_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b release
@@ -1970,19 +1962,18 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB40_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB40_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB40_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -1990,19 +1981,18 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB40_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB40_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB40_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b release
@@ -2039,19 +2029,18 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB41_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB41_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB41_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -2059,19 +2048,18 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB41_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB41_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB41_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b release
@@ -2111,17 +2099,17 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB42_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB42_1
+; LA64-LAMCAS-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB42_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -2129,17 +2117,17 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB42_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB42_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB42_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b release
@@ -2181,17 +2169,17 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB43_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB43_1
+; LA64-LAMCAS-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB43_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -2199,17 +2187,17 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB43_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB43_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB43_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b release
@@ -2249,18 +2237,17 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB44_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB44_1
+; LA64-LAMCAS-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB44_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -2268,18 +2255,17 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB44_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB44_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB44_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b release
@@ -2321,18 +2307,17 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB45_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB45_1
+; LA64-LAMCAS-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB45_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -2340,18 +2325,17 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB45_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB45_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB45_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b release
@@ -3229,18 +3213,18 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB66_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB66_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB66_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -3248,18 +3232,18 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB66_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB66_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB66_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b acq_rel
@@ -3296,18 +3280,18 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB67_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB67_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB67_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -3315,18 +3299,18 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB67_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB67_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB67_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b acq_rel
@@ -3362,19 +3346,18 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB68_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB68_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB68_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -3382,19 +3365,18 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB68_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB68_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB68_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b acq_rel
@@ -3431,19 +3413,18 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB69_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB69_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB69_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -3451,19 +3432,18 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB69_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB69_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB69_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b acq_rel
@@ -3503,17 +3483,17 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB70_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB70_1
+; LA64-LAMCAS-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB70_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -3521,17 +3501,17 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB70_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB70_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB70_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b acq_rel
@@ -3573,17 +3553,17 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB71_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB71_1
+; LA64-LAMCAS-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB71_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -3591,17 +3571,17 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB71_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB71_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB71_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b acq_rel
@@ -3641,18 +3621,17 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB72_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB72_1
+; LA64-LAMCAS-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB72_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -3660,18 +3639,17 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB72_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB72_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB72_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b acq_rel
@@ -3713,18 +3691,17 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB73_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB73_1
+; LA64-LAMCAS-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB73_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -3732,18 +3709,17 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB73_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB73_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB73_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b acq_rel
@@ -4623,18 +4599,18 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB94_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB94_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB94_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -4642,18 +4618,18 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB94_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB94_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB94_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b seq_cst
@@ -4690,18 +4666,18 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB95_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB95_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB95_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -4709,18 +4685,18 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB95_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB95_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB95_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b seq_cst
@@ -4756,19 +4732,18 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB96_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB96_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB96_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -4776,19 +4751,18 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB96_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB96_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB96_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b seq_cst
@@ -4825,19 +4799,18 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB97_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB97_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB97_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -4845,19 +4818,18 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB97_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB97_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB97_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b seq_cst
@@ -4897,17 +4869,17 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB98_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB98_1
+; LA64-LAMCAS-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB98_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -4915,17 +4887,17 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB98_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB98_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB98_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b seq_cst
@@ -4967,17 +4939,17 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB99_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB99_1
+; LA64-LAMCAS-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB99_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -4985,17 +4957,17 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB99_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB99_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB99_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b seq_cst
@@ -5035,18 +5007,17 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB100_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB100_1
+; LA64-LAMCAS-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB100_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -5054,18 +5025,17 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB100_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB100_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.b $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB100_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b seq_cst
@@ -5107,18 +5077,17 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB101_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB101_1
+; LA64-LAMCAS-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB101_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -5126,18 +5095,17 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB101_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB101_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas_db.h $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB101_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b seq_cst
@@ -6017,18 +5985,18 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB122_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-NEXT: amcas.b $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB122_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-NEXT: amcas.b $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB122_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -6036,18 +6004,18 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB122_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas.b $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB122_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas.b $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB122_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umax ptr %a, i8 %b monotonic
@@ -6084,18 +6052,18 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB123_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-NEXT: amcas.h $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB123_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-NEXT: amcas.h $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB123_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -6103,18 +6071,18 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB123_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a1, $a3
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas.h $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB123_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas.h $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB123_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umax ptr %a, i16 %b monotonic
@@ -6150,19 +6118,18 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB124_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-NEXT: amcas.b $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB124_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-NEXT: amcas.b $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB124_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -6170,19 +6137,18 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a1, 255
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a1, $a1, 255
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB124_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: andi $a4, $a0, 255
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-LAM-BH-NEXT: andi $a3, $a0, 255
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas.b $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB124_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas.b $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB124_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umin ptr %a, i8 %b monotonic
@@ -6219,19 +6185,18 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB125_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-NEXT: amcas.h $a0, $a4, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a5, .LBB125_1
+; LA64-LAMCAS-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-NEXT: amcas.h $a0, $a3, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB125_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -6239,19 +6204,18 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a1, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a1, $a1, 15, 0
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB125_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a4, $a0, 15, 0
-; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a4, $a4, 1
+; LA64-LAMCAS-LAM-BH-NEXT: bstrpick.d $a3, $a0, 15, 0
+; LA64-LAMCAS-LAM-BH-NEXT: sltu $a4, $a3, $a1
; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a0, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a5, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: amcas.h $a0, $a4, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a5, .LBB125_1
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a3, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a3, $a3, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: amcas.h $a0, $a3, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB125_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw umin ptr %a, i16 %b monotonic
@@ -6291,17 +6255,17 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB126_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas.b $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB126_1
+; LA64-LAMCAS-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas.b $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB126_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -6309,17 +6273,17 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB126_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas.b $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB126_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas.b $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB126_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw max ptr %a, i8 %b monotonic
@@ -6361,17 +6325,17 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB127_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas.h $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB127_1
+; LA64-LAMCAS-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas.h $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB127_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -6379,17 +6343,17 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB127_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas.h $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB127_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a1, $a3
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas.h $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB127_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw max ptr %a, i16 %b monotonic
@@ -6429,18 +6393,17 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB128_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas.b $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB128_1
+; LA64-LAMCAS-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas.b $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB128_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -6448,18 +6411,17 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.b $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB128_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas.b $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB128_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.b $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas.b $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB128_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw min ptr %a, i8 %b monotonic
@@ -6501,18 +6463,17 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS: # %bb.0:
; LA64-LAMCAS-NEXT: move $a2, $a0
; LA64-LAMCAS-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-NEXT: .p2align 4, , 16
; LA64-LAMCAS-NEXT: .LBB129_1: # %atomicrmw.start
; LA64-LAMCAS-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-NEXT: amcas.h $a0, $a5, $a2
-; LA64-LAMCAS-NEXT: bne $a0, $a4, .LBB129_1
+; LA64-LAMCAS-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-NEXT: amcas.h $a0, $a4, $a2
+; LA64-LAMCAS-NEXT: bne $a0, $a3, .LBB129_1
; LA64-LAMCAS-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-NEXT: ret
;
@@ -6520,18 +6481,17 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
; LA64-LAMCAS-LAM-BH: # %bb.0:
; LA64-LAMCAS-LAM-BH-NEXT: move $a2, $a0
; LA64-LAMCAS-LAM-BH-NEXT: ld.h $a0, $a0, 0
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a1, $a1
; LA64-LAMCAS-LAM-BH-NEXT: .p2align 4, , 16
; LA64-LAMCAS-LAM-BH-NEXT: .LBB129_1: # %atomicrmw.start
; LA64-LAMCAS-LAM-BH-NEXT: # =>This Inner Loop Header: Depth=1
-; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a4, $a0
-; LA64-LAMCAS-LAM-BH-NEXT: slt $a5, $a3, $a4
-; LA64-LAMCAS-LAM-BH-NEXT: xori $a5, $a5, 1
-; LA64-LAMCAS-LAM-BH-NEXT: masknez $a6, $a1, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a5, $a0, $a5
-; LA64-LAMCAS-LAM-BH-NEXT: or $a5, $a5, $a6
-; LA64-LAMCAS-LAM-BH-NEXT: amcas.h $a0, $a5, $a2
-; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a4, .LBB129_1
+; LA64-LAMCAS-LAM-BH-NEXT: ext.w.h $a3, $a0
+; LA64-LAMCAS-LAM-BH-NEXT: slt $a4, $a3, $a1
+; LA64-LAMCAS-LAM-BH-NEXT: masknez $a5, $a1, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: maskeqz $a4, $a3, $a4
+; LA64-LAMCAS-LAM-BH-NEXT: or $a4, $a4, $a5
+; LA64-LAMCAS-LAM-BH-NEXT: amcas.h $a0, $a4, $a2
+; LA64-LAMCAS-LAM-BH-NEXT: bne $a0, $a3, .LBB129_1
; LA64-LAMCAS-LAM-BH-NEXT: # %bb.2: # %atomicrmw.end
; LA64-LAMCAS-LAM-BH-NEXT: ret
%1 = atomicrmw min ptr %a, i16 %b monotonic
diff --git a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-minmax.ll b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-minmax.ll
index e8f5fdbb2f741..dad5f212f3c88 100644
--- a/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-minmax.ll
+++ b/llvm/test/CodeGen/LoongArch/ir-instruction/atomicrmw-minmax.ll
@@ -374,14 +374,13 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind {
; LA32-NEXT: beq $a1, $fp, .LBB7_4
; LA32-NEXT: # %bb.3: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB7_2 Depth=1
-; LA32-NEXT: sltu $a0, $fp, $a1
+; LA32-NEXT: sltu $a0, $a1, $fp
; LA32-NEXT: b .LBB7_5
; LA32-NEXT: .p2align 4, , 16
; LA32-NEXT: .LBB7_4: # in Loop: Header=BB7_2 Depth=1
-; LA32-NEXT: sltu $a0, $s0, $a4
+; LA32-NEXT: sltu $a0, $a4, $s0
; LA32-NEXT: .LBB7_5: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB7_2 Depth=1
-; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: move $a2, $a4
; LA32-NEXT: move $a3, $a1
; LA32-NEXT: bne $a0, $zero, .LBB7_1
@@ -819,14 +818,13 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind {
; LA32-NEXT: beq $a1, $fp, .LBB15_4
; LA32-NEXT: # %bb.3: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB15_2 Depth=1
-; LA32-NEXT: slt $a0, $fp, $a1
+; LA32-NEXT: slt $a0, $a1, $fp
; LA32-NEXT: b .LBB15_5
; LA32-NEXT: .p2align 4, , 16
; LA32-NEXT: .LBB15_4: # in Loop: Header=BB15_2 Depth=1
-; LA32-NEXT: sltu $a0, $s0, $a4
+; LA32-NEXT: sltu $a0, $a4, $s0
; LA32-NEXT: .LBB15_5: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB15_2 Depth=1
-; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: move $a2, $a4
; LA32-NEXT: move $a3, $a1
; LA32-NEXT: bne $a0, $zero, .LBB15_1
@@ -1224,14 +1222,13 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind {
; LA32-NEXT: beq $a1, $fp, .LBB23_4
; LA32-NEXT: # %bb.3: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB23_2 Depth=1
-; LA32-NEXT: sltu $a0, $fp, $a1
+; LA32-NEXT: sltu $a0, $a1, $fp
; LA32-NEXT: b .LBB23_5
; LA32-NEXT: .p2align 4, , 16
; LA32-NEXT: .LBB23_4: # in Loop: Header=BB23_2 Depth=1
-; LA32-NEXT: sltu $a0, $s0, $a4
+; LA32-NEXT: sltu $a0, $a4, $s0
; LA32-NEXT: .LBB23_5: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB23_2 Depth=1
-; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: move $a2, $a4
; LA32-NEXT: move $a3, $a1
; LA32-NEXT: bne $a0, $zero, .LBB23_1
@@ -1669,14 +1666,13 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind {
; LA32-NEXT: beq $a1, $fp, .LBB31_4
; LA32-NEXT: # %bb.3: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB31_2 Depth=1
-; LA32-NEXT: slt $a0, $fp, $a1
+; LA32-NEXT: slt $a0, $a1, $fp
; LA32-NEXT: b .LBB31_5
; LA32-NEXT: .p2align 4, , 16
; LA32-NEXT: .LBB31_4: # in Loop: Header=BB31_2 Depth=1
-; LA32-NEXT: sltu $a0, $s0, $a4
+; LA32-NEXT: sltu $a0, $a4, $s0
; LA32-NEXT: .LBB31_5: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB31_2 Depth=1
-; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: move $a2, $a4
; LA32-NEXT: move $a3, $a1
; LA32-NEXT: bne $a0, $zero, .LBB31_1
@@ -2074,14 +2070,13 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind {
; LA32-NEXT: beq $a1, $fp, .LBB39_4
; LA32-NEXT: # %bb.3: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB39_2 Depth=1
-; LA32-NEXT: sltu $a0, $fp, $a1
+; LA32-NEXT: sltu $a0, $a1, $fp
; LA32-NEXT: b .LBB39_5
; LA32-NEXT: .p2align 4, , 16
; LA32-NEXT: .LBB39_4: # in Loop: Header=BB39_2 Depth=1
-; LA32-NEXT: sltu $a0, $s0, $a4
+; LA32-NEXT: sltu $a0, $a4, $s0
; LA32-NEXT: .LBB39_5: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB39_2 Depth=1
-; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: move $a2, $a4
; LA32-NEXT: move $a3, $a1
; LA32-NEXT: bne $a0, $zero, .LBB39_1
@@ -2519,14 +2514,13 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind {
; LA32-NEXT: beq $a1, $fp, .LBB47_4
; LA32-NEXT: # %bb.3: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB47_2 Depth=1
-; LA32-NEXT: slt $a0, $fp, $a1
+; LA32-NEXT: slt $a0, $a1, $fp
; LA32-NEXT: b .LBB47_5
; LA32-NEXT: .p2align 4, , 16
; LA32-NEXT: .LBB47_4: # in Loop: Header=BB47_2 Depth=1
-; LA32-NEXT: sltu $a0, $s0, $a4
+; LA32-NEXT: sltu $a0, $a4, $s0
; LA32-NEXT: .LBB47_5: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB47_2 Depth=1
-; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: move $a2, $a4
; LA32-NEXT: move $a3, $a1
; LA32-NEXT: bne $a0, $zero, .LBB47_1
@@ -2924,14 +2918,13 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind {
; LA32-NEXT: beq $a1, $fp, .LBB55_4
; LA32-NEXT: # %bb.3: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB55_2 Depth=1
-; LA32-NEXT: sltu $a0, $fp, $a1
+; LA32-NEXT: sltu $a0, $a1, $fp
; LA32-NEXT: b .LBB55_5
; LA32-NEXT: .p2align 4, , 16
; LA32-NEXT: .LBB55_4: # in Loop: Header=BB55_2 Depth=1
-; LA32-NEXT: sltu $a0, $s0, $a4
+; LA32-NEXT: sltu $a0, $a4, $s0
; LA32-NEXT: .LBB55_5: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB55_2 Depth=1
-; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: move $a2, $a4
; LA32-NEXT: move $a3, $a1
; LA32-NEXT: bne $a0, $zero, .LBB55_1
@@ -3369,14 +3362,13 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind {
; LA32-NEXT: beq $a1, $fp, .LBB63_4
; LA32-NEXT: # %bb.3: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB63_2 Depth=1
-; LA32-NEXT: slt $a0, $fp, $a1
+; LA32-NEXT: slt $a0, $a1, $fp
; LA32-NEXT: b .LBB63_5
; LA32-NEXT: .p2align 4, , 16
; LA32-NEXT: .LBB63_4: # in Loop: Header=BB63_2 Depth=1
-; LA32-NEXT: sltu $a0, $s0, $a4
+; LA32-NEXT: sltu $a0, $a4, $s0
; LA32-NEXT: .LBB63_5: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB63_2 Depth=1
-; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: move $a2, $a4
; LA32-NEXT: move $a3, $a1
; LA32-NEXT: bne $a0, $zero, .LBB63_1
@@ -3774,14 +3766,13 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; LA32-NEXT: beq $a1, $fp, .LBB71_4
; LA32-NEXT: # %bb.3: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB71_2 Depth=1
-; LA32-NEXT: sltu $a0, $fp, $a1
+; LA32-NEXT: sltu $a0, $a1, $fp
; LA32-NEXT: b .LBB71_5
; LA32-NEXT: .p2align 4, , 16
; LA32-NEXT: .LBB71_4: # in Loop: Header=BB71_2 Depth=1
-; LA32-NEXT: sltu $a0, $s0, $a4
+; LA32-NEXT: sltu $a0, $a4, $s0
; LA32-NEXT: .LBB71_5: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB71_2 Depth=1
-; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: move $a2, $a4
; LA32-NEXT: move $a3, $a1
; LA32-NEXT: bne $a0, $zero, .LBB71_1
@@ -4219,14 +4210,13 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; LA32-NEXT: beq $a1, $fp, .LBB79_4
; LA32-NEXT: # %bb.3: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB79_2 Depth=1
-; LA32-NEXT: slt $a0, $fp, $a1
+; LA32-NEXT: slt $a0, $a1, $fp
; LA32-NEXT: b .LBB79_5
; LA32-NEXT: .p2align 4, , 16
; LA32-NEXT: .LBB79_4: # in Loop: Header=BB79_2 Depth=1
-; LA32-NEXT: sltu $a0, $s0, $a4
+; LA32-NEXT: sltu $a0, $a4, $s0
; LA32-NEXT: .LBB79_5: # %atomicrmw.start
; LA32-NEXT: # in Loop: Header=BB79_2 Depth=1
-; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: move $a2, $a4
; LA32-NEXT: move $a3, $a1
; LA32-NEXT: bne $a0, $zero, .LBB79_1
diff --git a/llvm/test/CodeGen/LoongArch/select-to-shiftand.ll b/llvm/test/CodeGen/LoongArch/select-to-shiftand.ll
index a6e7de83f3c3a..864e1d975ba51 100644
--- a/llvm/test/CodeGen/LoongArch/select-to-shiftand.ll
+++ b/llvm/test/CodeGen/LoongArch/select-to-shiftand.ll
@@ -77,13 +77,14 @@ define i64 @pos_sel_variable_and_zero_i64(i64 signext %a, i64 signext %b) {
define i8 @not_neg_not_zero_sel_same_variable_i8(i8 signext %a) {
; LA32-LABEL: not_neg_not_zero_sel_same_variable_i8:
; LA32: # %bb.0:
-; LA32-NEXT: srai.w $a1, $a0, 7
-; LA32-NEXT: andn $a0, $a0, $a1
+; LA32-NEXT: slt $a1, $zero, $a0
+; LA32-NEXT: sub.w $a1, $zero, $a1
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: not_neg_not_zero_sel_same_variable_i8:
; LA64: # %bb.0:
-; LA64-NEXT: srai.d $a1, $a0, 7
+; LA64-NEXT: srai.d $a1, $a0, 63
; LA64-NEXT: andn $a0, $a0, $a1
; LA64-NEXT: ret
%cmp = icmp sgt i8 %a, 0
@@ -94,13 +95,14 @@ define i8 @not_neg_not_zero_sel_same_variable_i8(i8 signext %a) {
define i16 @not_neg_not_zero_sel_same_variable_i16(i16 signext %a) {
; LA32-LABEL: not_neg_not_zero_sel_same_variable_i16:
; LA32: # %bb.0:
-; LA32-NEXT: srai.w $a1, $a0, 15
-; LA32-NEXT: andn $a0, $a0, $a1
+; LA32-NEXT: slt $a1, $zero, $a0
+; LA32-NEXT: sub.w $a1, $zero, $a1
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: not_neg_not_zero_sel_same_variable_i16:
; LA64: # %bb.0:
-; LA64-NEXT: srai.d $a1, $a0, 15
+; LA64-NEXT: srai.d $a1, $a0, 63
; LA64-NEXT: andn $a0, $a0, $a1
; LA64-NEXT: ret
%cmp = icmp sgt i16 %a, 0
@@ -111,13 +113,14 @@ define i16 @not_neg_not_zero_sel_same_variable_i16(i16 signext %a) {
define i32 @not_neg_not_zero_sel_same_variable_i32(i32 signext %a) {
; LA32-LABEL: not_neg_not_zero_sel_same_variable_i32:
; LA32: # %bb.0:
-; LA32-NEXT: srai.w $a1, $a0, 31
-; LA32-NEXT: andn $a0, $a0, $a1
+; LA32-NEXT: slt $a1, $zero, $a0
+; LA32-NEXT: sub.w $a1, $zero, $a1
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: not_neg_not_zero_sel_same_variable_i32:
; LA64: # %bb.0:
-; LA64-NEXT: srai.d $a1, $a0, 31
+; LA64-NEXT: srai.d $a1, $a0, 63
; LA64-NEXT: andn $a0, $a0, $a1
; LA64-NEXT: ret
%cmp = icmp sgt i32 %a, 0
@@ -128,9 +131,12 @@ define i32 @not_neg_not_zero_sel_same_variable_i32(i32 signext %a) {
define i64 @not_neg_not_zero_sel_same_variable_i64(i64 signext %a) {
; LA32-LABEL: not_neg_not_zero_sel_same_variable_i64:
; LA32: # %bb.0:
-; LA32-NEXT: srai.w $a2, $a1, 31
-; LA32-NEXT: andn $a0, $a0, $a2
-; LA32-NEXT: andn $a1, $a1, $a2
+; LA32-NEXT: slti $a2, $a1, 0
+; LA32-NEXT: addi.w $a2, $a2, -1
+; LA32-NEXT: and $a0, $a2, $a0
+; LA32-NEXT: slt $a2, $zero, $a1
+; LA32-NEXT: sub.w $a2, $zero, $a2
+; LA32-NEXT: and $a1, $a2, $a1
; LA32-NEXT: ret
;
; LA64-LABEL: not_neg_not_zero_sel_same_variable_i64:
@@ -148,16 +154,18 @@ define i8 @sub_clamp_zero_i8(i8 signext %x, i8 signext %y) {
; LA32-LABEL: sub_clamp_zero_i8:
; LA32: # %bb.0:
; LA32-NEXT: sub.w $a0, $a0, $a1
-; LA32-NEXT: slli.w $a1, $a0, 24
-; LA32-NEXT: srai.w $a1, $a1, 31
-; LA32-NEXT: andn $a0, $a0, $a1
+; LA32-NEXT: slli.w $a0, $a0, 24
+; LA32-NEXT: srai.w $a0, $a0, 24
+; LA32-NEXT: slt $a1, $zero, $a0
+; LA32-NEXT: sub.w $a1, $zero, $a1
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: sub_clamp_zero_i8:
; LA64: # %bb.0:
; LA64-NEXT: sub.d $a0, $a0, $a1
-; LA64-NEXT: ext.w.b $a1, $a0
-; LA64-NEXT: srai.d $a1, $a1, 7
+; LA64-NEXT: ext.w.b $a0, $a0
+; LA64-NEXT: srai.d $a1, $a0, 63
; LA64-NEXT: andn $a0, $a0, $a1
; LA64-NEXT: ret
%sub = sub nsw i8 %x, %y
@@ -170,16 +178,18 @@ define i16 @sub_clamp_zero_i16(i16 signext %x, i16 signext %y) {
; LA32-LABEL: sub_clamp_zero_i16:
; LA32: # %bb.0:
; LA32-NEXT: sub.w $a0, $a0, $a1
-; LA32-NEXT: slli.w $a1, $a0, 16
-; LA32-NEXT: srai.w $a1, $a1, 31
-; LA32-NEXT: andn $a0, $a0, $a1
+; LA32-NEXT: slli.w $a0, $a0, 16
+; LA32-NEXT: srai.w $a0, $a0, 16
+; LA32-NEXT: slt $a1, $zero, $a0
+; LA32-NEXT: sub.w $a1, $zero, $a1
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: sub_clamp_zero_i16:
; LA64: # %bb.0:
; LA64-NEXT: sub.d $a0, $a0, $a1
-; LA64-NEXT: ext.w.h $a1, $a0
-; LA64-NEXT: srai.d $a1, $a1, 15
+; LA64-NEXT: ext.w.h $a0, $a0
+; LA64-NEXT: srai.d $a1, $a0, 63
; LA64-NEXT: andn $a0, $a0, $a1
; LA64-NEXT: ret
%sub = sub nsw i16 %x, %y
@@ -192,14 +202,15 @@ define i32 @sub_clamp_zero_i32(i32 signext %x, i32 signext %y) {
; LA32-LABEL: sub_clamp_zero_i32:
; LA32: # %bb.0:
; LA32-NEXT: sub.w $a0, $a0, $a1
-; LA32-NEXT: srai.w $a1, $a0, 31
-; LA32-NEXT: andn $a0, $a0, $a1
+; LA32-NEXT: slt $a1, $zero, $a0
+; LA32-NEXT: sub.w $a1, $zero, $a1
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: sub_clamp_zero_i32:
; LA64: # %bb.0:
; LA64-NEXT: sub.w $a0, $a0, $a1
-; LA64-NEXT: srai.d $a1, $a0, 31
+; LA64-NEXT: srai.d $a1, $a0, 63
; LA64-NEXT: andn $a0, $a0, $a1
; LA64-NEXT: ret
%sub = sub nsw i32 %x, %y
@@ -213,11 +224,14 @@ define i64 @sub_clamp_zero_i64(i64 signext %x, i64 signext %y) {
; LA32: # %bb.0:
; LA32-NEXT: sltu $a4, $a0, $a2
; LA32-NEXT: sub.w $a1, $a1, $a3
-; LA32-NEXT: sub.w $a1, $a1, $a4
+; LA32-NEXT: sub.w $a3, $a1, $a4
; LA32-NEXT: sub.w $a0, $a0, $a2
-; LA32-NEXT: srai.w $a2, $a1, 31
-; LA32-NEXT: andn $a1, $a1, $a2
-; LA32-NEXT: andn $a0, $a0, $a2
+; LA32-NEXT: slt $a1, $zero, $a3
+; LA32-NEXT: sub.w $a1, $zero, $a1
+; LA32-NEXT: and $a1, $a1, $a3
+; LA32-NEXT: slti $a2, $a3, 0
+; LA32-NEXT: addi.w $a2, $a2, -1
+; LA32-NEXT: and $a0, $a2, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: sub_clamp_zero_i64:
diff --git a/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll b/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
index bfac2b4ffd431..32a8f9e07391b 100644
--- a/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
@@ -423,61 +423,51 @@ define <4 x i8> @test_smax(<4 x i8> %a, <4 x i8> %b) #0 {
define <4 x i8> @test_umax(<4 x i8> %a, <4 x i8> %b) #0 {
; O0-LABEL: test_umax(
; O0: {
-; O0-NEXT: .reg .pred %p<5>;
; O0-NEXT: .reg .b32 %r<18>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
; O0-NEXT: ld.param.b32 %r2, [test_umax_param_1];
; O0-NEXT: ld.param.b32 %r1, [test_umax_param_0];
; O0-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
-; O0-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
-; O0-NEXT: setp.gt.u32 %p1, %r4, %r3;
-; O0-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
-; O0-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
-; O0-NEXT: setp.gt.u32 %p2, %r6, %r5;
-; O0-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
-; O0-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
-; O0-NEXT: setp.gt.u32 %p3, %r8, %r7;
-; O0-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
-; O0-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
-; O0-NEXT: setp.gt.u32 %p4, %r10, %r9;
-; O0-NEXT: selp.b32 %r11, %r10, %r9, %p4;
-; O0-NEXT: selp.b32 %r12, %r8, %r7, %p3;
-; O0-NEXT: prmt.b32 %r13, %r12, %r11, 0x3340U;
-; O0-NEXT: selp.b32 %r14, %r6, %r5, %p2;
-; O0-NEXT: selp.b32 %r15, %r4, %r3, %p1;
-; O0-NEXT: prmt.b32 %r16, %r15, %r14, 0x3340U;
-; O0-NEXT: prmt.b32 %r17, %r16, %r13, 0x5410U;
+; O0-NEXT: prmt.b32 %r4, %r2, 0, 0x7771U;
+; O0-NEXT: prmt.b32 %r5, %r2, 0, 0x7772U;
+; O0-NEXT: prmt.b32 %r6, %r2, 0, 0x7773U;
+; O0-NEXT: prmt.b32 %r7, %r1, 0, 0x7773U;
+; O0-NEXT: max.u32 %r8, %r7, %r6;
+; O0-NEXT: prmt.b32 %r9, %r1, 0, 0x7772U;
+; O0-NEXT: max.u32 %r10, %r9, %r5;
+; O0-NEXT: prmt.b32 %r11, %r10, %r8, 0x3340U;
+; O0-NEXT: prmt.b32 %r12, %r1, 0, 0x7771U;
+; O0-NEXT: max.u32 %r13, %r12, %r4;
+; O0-NEXT: prmt.b32 %r14, %r1, 0, 0x7770U;
+; O0-NEXT: max.u32 %r15, %r14, %r3;
+; O0-NEXT: prmt.b32 %r16, %r15, %r13, 0x3340U;
+; O0-NEXT: prmt.b32 %r17, %r16, %r11, 0x5410U;
; O0-NEXT: st.param.b32 [func_retval0], %r17;
; O0-NEXT: ret;
;
; O3-LABEL: test_umax(
; O3: {
-; O3-NEXT: .reg .pred %p<5>;
; O3-NEXT: .reg .b32 %r<18>;
; O3-EMPTY:
; O3-NEXT: // %bb.0:
; O3-NEXT: ld.param.b32 %r1, [test_umax_param_0];
; O3-NEXT: ld.param.b32 %r2, [test_umax_param_1];
; O3-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
-; O3-NEXT: setp.gt.u32 %p1, %r4, %r3;
-; O3-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
-; O3-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
-; O3-NEXT: setp.gt.u32 %p2, %r6, %r5;
-; O3-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
-; O3-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
-; O3-NEXT: setp.gt.u32 %p3, %r8, %r7;
-; O3-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
-; O3-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
-; O3-NEXT: setp.gt.u32 %p4, %r10, %r9;
-; O3-NEXT: selp.b32 %r11, %r10, %r9, %p4;
-; O3-NEXT: selp.b32 %r12, %r8, %r7, %p3;
-; O3-NEXT: prmt.b32 %r13, %r12, %r11, 0x3340U;
-; O3-NEXT: selp.b32 %r14, %r6, %r5, %p2;
-; O3-NEXT: selp.b32 %r15, %r4, %r3, %p1;
-; O3-NEXT: prmt.b32 %r16, %r15, %r14, 0x3340U;
-; O3-NEXT: prmt.b32 %r17, %r16, %r13, 0x5410U;
+; O3-NEXT: prmt.b32 %r4, %r2, 0, 0x7771U;
+; O3-NEXT: prmt.b32 %r5, %r2, 0, 0x7772U;
+; O3-NEXT: prmt.b32 %r6, %r2, 0, 0x7773U;
+; O3-NEXT: prmt.b32 %r7, %r1, 0, 0x7773U;
+; O3-NEXT: max.u32 %r8, %r7, %r6;
+; O3-NEXT: prmt.b32 %r9, %r1, 0, 0x7772U;
+; O3-NEXT: max.u32 %r10, %r9, %r5;
+; O3-NEXT: prmt.b32 %r11, %r10, %r8, 0x3340U;
+; O3-NEXT: prmt.b32 %r12, %r1, 0, 0x7771U;
+; O3-NEXT: max.u32 %r13, %r12, %r4;
+; O3-NEXT: prmt.b32 %r14, %r1, 0, 0x7770U;
+; O3-NEXT: max.u32 %r15, %r14, %r3;
+; O3-NEXT: prmt.b32 %r16, %r15, %r13, 0x3340U;
+; O3-NEXT: prmt.b32 %r17, %r16, %r11, 0x5410U;
; O3-NEXT: st.param.b32 [func_retval0], %r17;
; O3-NEXT: ret;
%cmp = icmp ugt <4 x i8> %a, %b
@@ -569,61 +559,51 @@ define <4 x i8> @test_smin(<4 x i8> %a, <4 x i8> %b) #0 {
define <4 x i8> @test_umin(<4 x i8> %a, <4 x i8> %b) #0 {
; O0-LABEL: test_umin(
; O0: {
-; O0-NEXT: .reg .pred %p<5>;
; O0-NEXT: .reg .b32 %r<18>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
; O0-NEXT: ld.param.b32 %r2, [test_umin_param_1];
; O0-NEXT: ld.param.b32 %r1, [test_umin_param_0];
; O0-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
-; O0-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
-; O0-NEXT: setp.le.u32 %p1, %r4, %r3;
-; O0-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
-; O0-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
-; O0-NEXT: setp.le.u32 %p2, %r6, %r5;
-; O0-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
-; O0-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
-; O0-NEXT: setp.le.u32 %p3, %r8, %r7;
-; O0-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
-; O0-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
-; O0-NEXT: setp.le.u32 %p4, %r10, %r9;
-; O0-NEXT: selp.b32 %r11, %r10, %r9, %p4;
-; O0-NEXT: selp.b32 %r12, %r8, %r7, %p3;
-; O0-NEXT: prmt.b32 %r13, %r12, %r11, 0x3340U;
-; O0-NEXT: selp.b32 %r14, %r6, %r5, %p2;
-; O0-NEXT: selp.b32 %r15, %r4, %r3, %p1;
-; O0-NEXT: prmt.b32 %r16, %r15, %r14, 0x3340U;
-; O0-NEXT: prmt.b32 %r17, %r16, %r13, 0x5410U;
+; O0-NEXT: prmt.b32 %r4, %r2, 0, 0x7771U;
+; O0-NEXT: prmt.b32 %r5, %r2, 0, 0x7772U;
+; O0-NEXT: prmt.b32 %r6, %r2, 0, 0x7773U;
+; O0-NEXT: prmt.b32 %r7, %r1, 0, 0x7773U;
+; O0-NEXT: min.u32 %r8, %r7, %r6;
+; O0-NEXT: prmt.b32 %r9, %r1, 0, 0x7772U;
+; O0-NEXT: min.u32 %r10, %r9, %r5;
+; O0-NEXT: prmt.b32 %r11, %r10, %r8, 0x3340U;
+; O0-NEXT: prmt.b32 %r12, %r1, 0, 0x7771U;
+; O0-NEXT: min.u32 %r13, %r12, %r4;
+; O0-NEXT: prmt.b32 %r14, %r1, 0, 0x7770U;
+; O0-NEXT: min.u32 %r15, %r14, %r3;
+; O0-NEXT: prmt.b32 %r16, %r15, %r13, 0x3340U;
+; O0-NEXT: prmt.b32 %r17, %r16, %r11, 0x5410U;
; O0-NEXT: st.param.b32 [func_retval0], %r17;
; O0-NEXT: ret;
;
; O3-LABEL: test_umin(
; O3: {
-; O3-NEXT: .reg .pred %p<5>;
; O3-NEXT: .reg .b32 %r<18>;
; O3-EMPTY:
; O3-NEXT: // %bb.0:
; O3-NEXT: ld.param.b32 %r1, [test_umin_param_0];
; O3-NEXT: ld.param.b32 %r2, [test_umin_param_1];
; O3-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
-; O3-NEXT: setp.le.u32 %p1, %r4, %r3;
-; O3-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
-; O3-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
-; O3-NEXT: setp.le.u32 %p2, %r6, %r5;
-; O3-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
-; O3-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
-; O3-NEXT: setp.le.u32 %p3, %r8, %r7;
-; O3-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
-; O3-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
-; O3-NEXT: setp.le.u32 %p4, %r10, %r9;
-; O3-NEXT: selp.b32 %r11, %r10, %r9, %p4;
-; O3-NEXT: selp.b32 %r12, %r8, %r7, %p3;
-; O3-NEXT: prmt.b32 %r13, %r12, %r11, 0x3340U;
-; O3-NEXT: selp.b32 %r14, %r6, %r5, %p2;
-; O3-NEXT: selp.b32 %r15, %r4, %r3, %p1;
-; O3-NEXT: prmt.b32 %r16, %r15, %r14, 0x3340U;
-; O3-NEXT: prmt.b32 %r17, %r16, %r13, 0x5410U;
+; O3-NEXT: prmt.b32 %r4, %r2, 0, 0x7771U;
+; O3-NEXT: prmt.b32 %r5, %r2, 0, 0x7772U;
+; O3-NEXT: prmt.b32 %r6, %r2, 0, 0x7773U;
+; O3-NEXT: prmt.b32 %r7, %r1, 0, 0x7773U;
+; O3-NEXT: min.u32 %r8, %r7, %r6;
+; O3-NEXT: prmt.b32 %r9, %r1, 0, 0x7772U;
+; O3-NEXT: min.u32 %r10, %r9, %r5;
+; O3-NEXT: prmt.b32 %r11, %r10, %r8, 0x3340U;
+; O3-NEXT: prmt.b32 %r12, %r1, 0, 0x7771U;
+; O3-NEXT: min.u32 %r13, %r12, %r4;
+; O3-NEXT: prmt.b32 %r14, %r1, 0, 0x7770U;
+; O3-NEXT: min.u32 %r15, %r14, %r3;
+; O3-NEXT: prmt.b32 %r16, %r15, %r13, 0x3340U;
+; O3-NEXT: prmt.b32 %r17, %r16, %r11, 0x5410U;
; O3-NEXT: st.param.b32 [func_retval0], %r17;
; O3-NEXT: ret;
%cmp = icmp ule <4 x i8> %a, %b
diff --git a/llvm/test/CodeGen/PowerPC/optcmp.ll b/llvm/test/CodeGen/PowerPC/optcmp.ll
index 831bc97cc0e9f..89a199d6fcc97 100644
--- a/llvm/test/CodeGen/PowerPC/optcmp.ll
+++ b/llvm/test/CodeGen/PowerPC/optcmp.ll
@@ -89,7 +89,7 @@ define i64 @foolb(i64 %a, i64 %b, ptr nocapture %c) #0 {
; CHECK-LABEL: foolb:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sub. 6, 3, 4
-; CHECK-NEXT: iselgt 3, 4, 3
+; CHECK-NEXT: isellt 3, 3, 4
; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr
;
@@ -97,7 +97,7 @@ define i64 @foolb(i64 %a, i64 %b, ptr nocapture %c) #0 {
; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: sub. 6, 3, 4
; CHECK-NO-ISEL-NEXT: std 6, 0(5)
-; CHECK-NO-ISEL-NEXT: blelr 0
+; CHECK-NO-ISEL-NEXT: bltlr 0
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: mr 3, 4
; CHECK-NO-ISEL-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/sat-add.ll b/llvm/test/CodeGen/PowerPC/sat-add.ll
index 34b703a981105..b611d2946ac74 100644
--- a/llvm/test/CodeGen/PowerPC/sat-add.ll
+++ b/llvm/test/CodeGen/PowerPC/sat-add.ll
@@ -9,9 +9,9 @@
define i8 @unsigned_sat_constant_i8_using_min(i8 %x) {
; CHECK-LABEL: unsigned_sat_constant_i8_using_min:
; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 4, 3, 24
-; CHECK-NEXT: cmplwi 4, 213
-; CHECK-NEXT: li 4, -43
+; CHECK-NEXT: clrlwi 3, 3, 24
+; CHECK-NEXT: li 4, 213
+; CHECK-NEXT: cmplwi 3, 213
; CHECK-NEXT: isellt 3, 3, 4
; CHECK-NEXT: addi 3, 3, 42
; CHECK-NEXT: blr
@@ -54,9 +54,10 @@ define i8 @unsigned_sat_constant_i8_using_cmp_notval(i8 %x) {
define i16 @unsigned_sat_constant_i16_using_min(i16 %x) {
; CHECK-LABEL: unsigned_sat_constant_i16_using_min:
; CHECK: # %bb.0:
-; CHECK-NEXT: clrlwi 4, 3, 16
-; CHECK-NEXT: cmplwi 4, 65493
-; CHECK-NEXT: li 4, -43
+; CHECK-NEXT: clrlwi 3, 3, 16
+; CHECK-NEXT: lis 4, 0
+; CHECK-NEXT: cmplwi 3, 65493
+; CHECK-NEXT: ori 4, 4, 65493
; CHECK-NEXT: isellt 3, 3, 4
; CHECK-NEXT: addi 3, 3, 42
; CHECK-NEXT: blr
@@ -186,11 +187,11 @@ define i64 @unsigned_sat_constant_i64_using_cmp_notval(i64 %x) {
define i8 @unsigned_sat_variable_i8_using_min(i8 %x, i8 %y) {
; CHECK-LABEL: unsigned_sat_variable_i8_using_min:
; CHECK: # %bb.0:
-; CHECK-NEXT: not 6, 4
-; CHECK-NEXT: clrlwi 5, 3, 24
-; CHECK-NEXT: clrlwi 7, 6, 24
-; CHECK-NEXT: cmplw 5, 7
-; CHECK-NEXT: isellt 3, 3, 6
+; CHECK-NEXT: not 5, 4
+; CHECK-NEXT: clrlwi 3, 3, 24
+; CHECK-NEXT: clrlwi 5, 5, 24
+; CHECK-NEXT: cmplw 3, 5
+; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: blr
%noty = xor i8 %y, -1
@@ -237,11 +238,11 @@ define i8 @unsigned_sat_variable_i8_using_cmp_notval(i8 %x, i8 %y) {
define i16 @unsigned_sat_variable_i16_using_min(i16 %x, i16 %y) {
; CHECK-LABEL: unsigned_sat_variable_i16_using_min:
; CHECK: # %bb.0:
-; CHECK-NEXT: not 6, 4
-; CHECK-NEXT: clrlwi 5, 3, 16
-; CHECK-NEXT: clrlwi 7, 6, 16
-; CHECK-NEXT: cmplw 5, 7
-; CHECK-NEXT: isellt 3, 3, 6
+; CHECK-NEXT: not 5, 4
+; CHECK-NEXT: clrlwi 3, 3, 16
+; CHECK-NEXT: clrlwi 5, 5, 16
+; CHECK-NEXT: cmplw 3, 5
+; CHECK-NEXT: isellt 3, 3, 5
; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: blr
%noty = xor i16 %y, -1
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index 9e68d61df48fc..0b18839263932 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -8895,46 +8895,43 @@ define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 24
-; RV32I-NEXT: srai s2, a0, 24
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: srai s1, s1, 24
; RV32I-NEXT: j .LBB45_2
; RV32I-NEXT: .LBB45_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB45_4
; RV32I-NEXT: .LBB45_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
-; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s2, a0, .LBB45_1
+; RV32I-NEXT: slli a2, a1, 24
+; RV32I-NEXT: srai a2, a2, 24
+; RV32I-NEXT: blt s1, a2, .LBB45_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB45_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB45_1
; RV32I-NEXT: .LBB45_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_monotonic:
@@ -8997,46 +8994,43 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i8_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 56
-; RV64I-NEXT: srai s2, a0, 56
+; RV64I-NEXT: slli s1, s1, 56
+; RV64I-NEXT: srai s1, s1, 56
; RV64I-NEXT: j .LBB45_2
; RV64I-NEXT: .LBB45_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB45_4
; RV64I-NEXT: .LBB45_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
-; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB45_1
+; RV64I-NEXT: slli a2, a1, 56
+; RV64I-NEXT: srai a2, a2, 56
+; RV64I-NEXT: blt s1, a2, .LBB45_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB45_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB45_1
; RV64I-NEXT: .LBB45_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_monotonic:
@@ -9181,46 +9175,43 @@ define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_acquire:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 24
-; RV32I-NEXT: srai s2, a0, 24
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: srai s1, s1, 24
; RV32I-NEXT: j .LBB46_2
; RV32I-NEXT: .LBB46_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB46_4
; RV32I-NEXT: .LBB46_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
-; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s2, a0, .LBB46_1
+; RV32I-NEXT: slli a2, a1, 24
+; RV32I-NEXT: srai a2, a2, 24
+; RV32I-NEXT: blt s1, a2, .LBB46_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB46_1
; RV32I-NEXT: .LBB46_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_acquire:
@@ -9312,46 +9303,43 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i8_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 56
-; RV64I-NEXT: srai s2, a0, 56
+; RV64I-NEXT: slli s1, s1, 56
+; RV64I-NEXT: srai s1, s1, 56
; RV64I-NEXT: j .LBB46_2
; RV64I-NEXT: .LBB46_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB46_4
; RV64I-NEXT: .LBB46_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
-; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB46_1
+; RV64I-NEXT: slli a2, a1, 56
+; RV64I-NEXT: srai a2, a2, 56
+; RV64I-NEXT: blt s1, a2, .LBB46_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB46_1
; RV64I-NEXT: .LBB46_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_acquire:
@@ -9583,46 +9571,43 @@ define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_release:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 24
-; RV32I-NEXT: srai s2, a0, 24
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: srai s1, s1, 24
; RV32I-NEXT: j .LBB47_2
; RV32I-NEXT: .LBB47_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 3
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB47_4
; RV32I-NEXT: .LBB47_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
-; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s2, a0, .LBB47_1
+; RV32I-NEXT: slli a2, a1, 24
+; RV32I-NEXT: srai a2, a2, 24
+; RV32I-NEXT: blt s1, a2, .LBB47_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB47_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB47_1
; RV32I-NEXT: .LBB47_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_release:
@@ -9714,46 +9699,43 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i8_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 56
-; RV64I-NEXT: srai s2, a0, 56
+; RV64I-NEXT: slli s1, s1, 56
+; RV64I-NEXT: srai s1, s1, 56
; RV64I-NEXT: j .LBB47_2
; RV64I-NEXT: .LBB47_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 3
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB47_4
; RV64I-NEXT: .LBB47_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
-; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB47_1
+; RV64I-NEXT: slli a2, a1, 56
+; RV64I-NEXT: srai a2, a2, 56
+; RV64I-NEXT: blt s1, a2, .LBB47_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB47_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB47_1
; RV64I-NEXT: .LBB47_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_release:
@@ -9985,46 +9967,43 @@ define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_acq_rel:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 24
-; RV32I-NEXT: srai s2, a0, 24
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: srai s1, s1, 24
; RV32I-NEXT: j .LBB48_2
; RV32I-NEXT: .LBB48_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB48_4
; RV32I-NEXT: .LBB48_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
-; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s2, a0, .LBB48_1
+; RV32I-NEXT: slli a2, a1, 24
+; RV32I-NEXT: srai a2, a2, 24
+; RV32I-NEXT: blt s1, a2, .LBB48_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB48_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB48_1
; RV32I-NEXT: .LBB48_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_acq_rel:
@@ -10116,46 +10095,43 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i8_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 56
-; RV64I-NEXT: srai s2, a0, 56
+; RV64I-NEXT: slli s1, s1, 56
+; RV64I-NEXT: srai s1, s1, 56
; RV64I-NEXT: j .LBB48_2
; RV64I-NEXT: .LBB48_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB48_4
; RV64I-NEXT: .LBB48_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
-; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB48_1
+; RV64I-NEXT: slli a2, a1, 56
+; RV64I-NEXT: srai a2, a2, 56
+; RV64I-NEXT: blt s1, a2, .LBB48_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB48_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB48_1
; RV64I-NEXT: .LBB48_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_acq_rel:
@@ -10387,46 +10363,43 @@ define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_seq_cst:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 24
-; RV32I-NEXT: srai s2, a0, 24
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: srai s1, s1, 24
; RV32I-NEXT: j .LBB49_2
; RV32I-NEXT: .LBB49_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB49_4
; RV32I-NEXT: .LBB49_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
-; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s2, a0, .LBB49_1
+; RV32I-NEXT: slli a2, a1, 24
+; RV32I-NEXT: srai a2, a2, 24
+; RV32I-NEXT: blt s1, a2, .LBB49_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB49_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB49_1
; RV32I-NEXT: .LBB49_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_max_i8_seq_cst:
@@ -10489,46 +10462,43 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i8_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 56
-; RV64I-NEXT: srai s2, a0, 56
+; RV64I-NEXT: slli s1, s1, 56
+; RV64I-NEXT: srai s1, s1, 56
; RV64I-NEXT: j .LBB49_2
; RV64I-NEXT: .LBB49_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB49_4
; RV64I-NEXT: .LBB49_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
-; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB49_1
+; RV64I-NEXT: slli a2, a1, 56
+; RV64I-NEXT: srai a2, a2, 56
+; RV64I-NEXT: blt s1, a2, .LBB49_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB49_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB49_1
; RV64I-NEXT: .LBB49_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i8_seq_cst:
@@ -10673,46 +10643,43 @@ define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 24
-; RV32I-NEXT: srai s2, a0, 24
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: srai s1, s1, 24
; RV32I-NEXT: j .LBB50_2
; RV32I-NEXT: .LBB50_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB50_4
; RV32I-NEXT: .LBB50_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
-; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s2, a0, .LBB50_1
+; RV32I-NEXT: slli a2, a1, 24
+; RV32I-NEXT: srai a2, a2, 24
+; RV32I-NEXT: blt a2, s1, .LBB50_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB50_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB50_1
; RV32I-NEXT: .LBB50_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_monotonic:
@@ -10775,46 +10742,43 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i8_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 56
-; RV64I-NEXT: srai s2, a0, 56
+; RV64I-NEXT: slli s1, s1, 56
+; RV64I-NEXT: srai s1, s1, 56
; RV64I-NEXT: j .LBB50_2
; RV64I-NEXT: .LBB50_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB50_4
; RV64I-NEXT: .LBB50_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
-; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB50_1
+; RV64I-NEXT: slli a2, a1, 56
+; RV64I-NEXT: srai a2, a2, 56
+; RV64I-NEXT: blt a2, s1, .LBB50_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB50_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB50_1
; RV64I-NEXT: .LBB50_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_monotonic:
@@ -10959,46 +10923,43 @@ define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_acquire:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 24
-; RV32I-NEXT: srai s2, a0, 24
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: srai s1, s1, 24
; RV32I-NEXT: j .LBB51_2
; RV32I-NEXT: .LBB51_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB51_4
; RV32I-NEXT: .LBB51_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
-; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s2, a0, .LBB51_1
+; RV32I-NEXT: slli a2, a1, 24
+; RV32I-NEXT: srai a2, a2, 24
+; RV32I-NEXT: blt a2, s1, .LBB51_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB51_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB51_1
; RV32I-NEXT: .LBB51_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_acquire:
@@ -11090,46 +11051,43 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i8_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 56
-; RV64I-NEXT: srai s2, a0, 56
+; RV64I-NEXT: slli s1, s1, 56
+; RV64I-NEXT: srai s1, s1, 56
; RV64I-NEXT: j .LBB51_2
; RV64I-NEXT: .LBB51_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB51_4
; RV64I-NEXT: .LBB51_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
-; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB51_1
+; RV64I-NEXT: slli a2, a1, 56
+; RV64I-NEXT: srai a2, a2, 56
+; RV64I-NEXT: blt a2, s1, .LBB51_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB51_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB51_1
; RV64I-NEXT: .LBB51_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_acquire:
@@ -11361,46 +11319,43 @@ define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_release:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 24
-; RV32I-NEXT: srai s2, a0, 24
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: srai s1, s1, 24
; RV32I-NEXT: j .LBB52_2
; RV32I-NEXT: .LBB52_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 3
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB52_4
; RV32I-NEXT: .LBB52_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
-; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s2, a0, .LBB52_1
+; RV32I-NEXT: slli a2, a1, 24
+; RV32I-NEXT: srai a2, a2, 24
+; RV32I-NEXT: blt a2, s1, .LBB52_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB52_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB52_1
; RV32I-NEXT: .LBB52_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_release:
@@ -11492,46 +11447,43 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i8_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 56
-; RV64I-NEXT: srai s2, a0, 56
+; RV64I-NEXT: slli s1, s1, 56
+; RV64I-NEXT: srai s1, s1, 56
; RV64I-NEXT: j .LBB52_2
; RV64I-NEXT: .LBB52_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 3
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB52_4
; RV64I-NEXT: .LBB52_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
-; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB52_1
+; RV64I-NEXT: slli a2, a1, 56
+; RV64I-NEXT: srai a2, a2, 56
+; RV64I-NEXT: blt a2, s1, .LBB52_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB52_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB52_1
; RV64I-NEXT: .LBB52_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_release:
@@ -11763,46 +11715,43 @@ define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_acq_rel:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 24
-; RV32I-NEXT: srai s2, a0, 24
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: srai s1, s1, 24
; RV32I-NEXT: j .LBB53_2
; RV32I-NEXT: .LBB53_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB53_4
; RV32I-NEXT: .LBB53_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
-; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s2, a0, .LBB53_1
+; RV32I-NEXT: slli a2, a1, 24
+; RV32I-NEXT: srai a2, a2, 24
+; RV32I-NEXT: blt a2, s1, .LBB53_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB53_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB53_1
; RV32I-NEXT: .LBB53_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_acq_rel:
@@ -11894,46 +11843,43 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i8_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 56
-; RV64I-NEXT: srai s2, a0, 56
+; RV64I-NEXT: slli s1, s1, 56
+; RV64I-NEXT: srai s1, s1, 56
; RV64I-NEXT: j .LBB53_2
; RV64I-NEXT: .LBB53_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB53_4
; RV64I-NEXT: .LBB53_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
-; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB53_1
+; RV64I-NEXT: slli a2, a1, 56
+; RV64I-NEXT: srai a2, a2, 56
+; RV64I-NEXT: blt a2, s1, .LBB53_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB53_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB53_1
; RV64I-NEXT: .LBB53_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_acq_rel:
@@ -12165,46 +12111,43 @@ define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_seq_cst:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 24
-; RV32I-NEXT: srai s2, a0, 24
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: srai s1, s1, 24
; RV32I-NEXT: j .LBB54_2
; RV32I-NEXT: .LBB54_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB54_4
; RV32I-NEXT: .LBB54_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
-; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s2, a0, .LBB54_1
+; RV32I-NEXT: slli a2, a1, 24
+; RV32I-NEXT: srai a2, a2, 24
+; RV32I-NEXT: blt a2, s1, .LBB54_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB54_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB54_1
; RV32I-NEXT: .LBB54_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_min_i8_seq_cst:
@@ -12267,46 +12210,43 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i8_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 56
-; RV64I-NEXT: srai s2, a0, 56
+; RV64I-NEXT: slli s1, s1, 56
+; RV64I-NEXT: srai s1, s1, 56
; RV64I-NEXT: j .LBB54_2
; RV64I-NEXT: .LBB54_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB54_4
; RV64I-NEXT: .LBB54_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
-; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB54_1
+; RV64I-NEXT: slli a2, a1, 56
+; RV64I-NEXT: srai a2, a2, 56
+; RV64I-NEXT: blt a2, s1, .LBB54_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB54_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB54_1
; RV64I-NEXT: .LBB54_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i8_seq_cst:
@@ -12451,44 +12391,41 @@ define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: zext.b s2, s0
+; RV32I-NEXT: zext.b s1, s1
; RV32I-NEXT: j .LBB55_2
; RV32I-NEXT: .LBB55_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB55_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB55_4
; RV32I-NEXT: .LBB55_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: zext.b a0, a1
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu s2, a0, .LBB55_1
+; RV32I-NEXT: zext.b a2, a1
+; RV32I-NEXT: bltu s1, a2, .LBB55_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB55_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB55_1
; RV32I-NEXT: .LBB55_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_monotonic:
@@ -12541,44 +12478,41 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i8_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: zext.b s2, s0
+; RV64I-NEXT: zext.b s1, s1
; RV64I-NEXT: j .LBB55_2
; RV64I-NEXT: .LBB55_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB55_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB55_4
; RV64I-NEXT: .LBB55_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: zext.b a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s2, a0, .LBB55_1
+; RV64I-NEXT: zext.b a2, a1
+; RV64I-NEXT: bltu s1, a2, .LBB55_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB55_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB55_1
; RV64I-NEXT: .LBB55_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_monotonic:
@@ -12703,44 +12637,41 @@ define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_acquire:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: zext.b s2, s0
+; RV32I-NEXT: zext.b s1, s1
; RV32I-NEXT: j .LBB56_2
; RV32I-NEXT: .LBB56_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB56_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB56_4
; RV32I-NEXT: .LBB56_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: zext.b a0, a1
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu s2, a0, .LBB56_1
+; RV32I-NEXT: zext.b a2, a1
+; RV32I-NEXT: bltu s1, a2, .LBB56_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB56_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB56_1
; RV32I-NEXT: .LBB56_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_acquire:
@@ -12817,44 +12748,41 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i8_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: zext.b s2, s0
+; RV64I-NEXT: zext.b s1, s1
; RV64I-NEXT: j .LBB56_2
; RV64I-NEXT: .LBB56_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB56_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB56_4
; RV64I-NEXT: .LBB56_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: zext.b a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s2, a0, .LBB56_1
+; RV64I-NEXT: zext.b a2, a1
+; RV64I-NEXT: bltu s1, a2, .LBB56_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB56_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB56_1
; RV64I-NEXT: .LBB56_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_acquire:
@@ -13051,44 +12979,41 @@ define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_release:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: zext.b s2, s0
+; RV32I-NEXT: zext.b s1, s1
; RV32I-NEXT: j .LBB57_2
; RV32I-NEXT: .LBB57_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB57_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 3
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB57_4
; RV32I-NEXT: .LBB57_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: zext.b a0, a1
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu s2, a0, .LBB57_1
+; RV32I-NEXT: zext.b a2, a1
+; RV32I-NEXT: bltu s1, a2, .LBB57_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB57_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB57_1
; RV32I-NEXT: .LBB57_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_release:
@@ -13165,44 +13090,41 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i8_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: zext.b s2, s0
+; RV64I-NEXT: zext.b s1, s1
; RV64I-NEXT: j .LBB57_2
; RV64I-NEXT: .LBB57_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB57_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 3
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB57_4
; RV64I-NEXT: .LBB57_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: zext.b a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s2, a0, .LBB57_1
+; RV64I-NEXT: zext.b a2, a1
+; RV64I-NEXT: bltu s1, a2, .LBB57_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB57_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB57_1
; RV64I-NEXT: .LBB57_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_release:
@@ -13399,44 +13321,41 @@ define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_acq_rel:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: zext.b s2, s0
+; RV32I-NEXT: zext.b s1, s1
; RV32I-NEXT: j .LBB58_2
; RV32I-NEXT: .LBB58_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB58_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB58_4
; RV32I-NEXT: .LBB58_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: zext.b a0, a1
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu s2, a0, .LBB58_1
+; RV32I-NEXT: zext.b a2, a1
+; RV32I-NEXT: bltu s1, a2, .LBB58_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB58_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB58_1
; RV32I-NEXT: .LBB58_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_acq_rel:
@@ -13513,44 +13432,41 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i8_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: zext.b s2, s0
+; RV64I-NEXT: zext.b s1, s1
; RV64I-NEXT: j .LBB58_2
; RV64I-NEXT: .LBB58_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB58_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB58_4
; RV64I-NEXT: .LBB58_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: zext.b a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s2, a0, .LBB58_1
+; RV64I-NEXT: zext.b a2, a1
+; RV64I-NEXT: bltu s1, a2, .LBB58_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB58_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB58_1
; RV64I-NEXT: .LBB58_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_acq_rel:
@@ -13747,44 +13663,41 @@ define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_seq_cst:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: zext.b s2, s0
+; RV32I-NEXT: zext.b s1, s1
; RV32I-NEXT: j .LBB59_2
; RV32I-NEXT: .LBB59_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB59_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB59_4
; RV32I-NEXT: .LBB59_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: zext.b a0, a1
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu s2, a0, .LBB59_1
+; RV32I-NEXT: zext.b a2, a1
+; RV32I-NEXT: bltu s1, a2, .LBB59_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB59_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB59_1
; RV32I-NEXT: .LBB59_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_umax_i8_seq_cst:
@@ -13837,44 +13750,41 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i8_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: zext.b s2, s0
+; RV64I-NEXT: zext.b s1, s1
; RV64I-NEXT: j .LBB59_2
; RV64I-NEXT: .LBB59_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB59_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB59_4
; RV64I-NEXT: .LBB59_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: zext.b a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s2, a0, .LBB59_1
+; RV64I-NEXT: zext.b a2, a1
+; RV64I-NEXT: bltu s1, a2, .LBB59_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB59_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB59_1
; RV64I-NEXT: .LBB59_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i8_seq_cst:
@@ -13999,44 +13909,41 @@ define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: zext.b s2, s0
+; RV32I-NEXT: zext.b s1, s1
; RV32I-NEXT: j .LBB60_2
; RV32I-NEXT: .LBB60_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB60_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB60_4
; RV32I-NEXT: .LBB60_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: zext.b a0, a1
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s2, a0, .LBB60_1
+; RV32I-NEXT: zext.b a2, a1
+; RV32I-NEXT: bltu a2, s1, .LBB60_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB60_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB60_1
; RV32I-NEXT: .LBB60_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_monotonic:
@@ -14089,44 +13996,41 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i8_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: zext.b s2, s0
+; RV64I-NEXT: zext.b s1, s1
; RV64I-NEXT: j .LBB60_2
; RV64I-NEXT: .LBB60_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB60_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB60_4
; RV64I-NEXT: .LBB60_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: zext.b a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s2, a0, .LBB60_1
+; RV64I-NEXT: zext.b a2, a1
+; RV64I-NEXT: bltu a2, s1, .LBB60_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB60_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB60_1
; RV64I-NEXT: .LBB60_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_monotonic:
@@ -14251,44 +14155,41 @@ define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_acquire:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: zext.b s2, s0
+; RV32I-NEXT: zext.b s1, s1
; RV32I-NEXT: j .LBB61_2
; RV32I-NEXT: .LBB61_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB61_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB61_4
; RV32I-NEXT: .LBB61_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: zext.b a0, a1
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s2, a0, .LBB61_1
+; RV32I-NEXT: zext.b a2, a1
+; RV32I-NEXT: bltu a2, s1, .LBB61_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB61_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB61_1
; RV32I-NEXT: .LBB61_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_acquire:
@@ -14365,44 +14266,41 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i8_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: zext.b s2, s0
+; RV64I-NEXT: zext.b s1, s1
; RV64I-NEXT: j .LBB61_2
; RV64I-NEXT: .LBB61_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB61_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB61_4
; RV64I-NEXT: .LBB61_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: zext.b a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s2, a0, .LBB61_1
+; RV64I-NEXT: zext.b a2, a1
+; RV64I-NEXT: bltu a2, s1, .LBB61_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB61_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB61_1
; RV64I-NEXT: .LBB61_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_acquire:
@@ -14599,44 +14497,41 @@ define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_release:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: zext.b s2, s0
+; RV32I-NEXT: zext.b s1, s1
; RV32I-NEXT: j .LBB62_2
; RV32I-NEXT: .LBB62_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB62_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 3
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB62_4
; RV32I-NEXT: .LBB62_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: zext.b a0, a1
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s2, a0, .LBB62_1
+; RV32I-NEXT: zext.b a2, a1
+; RV32I-NEXT: bltu a2, s1, .LBB62_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB62_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB62_1
; RV32I-NEXT: .LBB62_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_release:
@@ -14713,44 +14608,41 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i8_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: zext.b s2, s0
+; RV64I-NEXT: zext.b s1, s1
; RV64I-NEXT: j .LBB62_2
; RV64I-NEXT: .LBB62_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB62_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 3
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB62_4
; RV64I-NEXT: .LBB62_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: zext.b a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s2, a0, .LBB62_1
+; RV64I-NEXT: zext.b a2, a1
+; RV64I-NEXT: bltu a2, s1, .LBB62_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB62_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB62_1
; RV64I-NEXT: .LBB62_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_release:
@@ -14947,44 +14839,41 @@ define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_acq_rel:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: zext.b s2, s0
+; RV32I-NEXT: zext.b s1, s1
; RV32I-NEXT: j .LBB63_2
; RV32I-NEXT: .LBB63_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB63_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB63_4
; RV32I-NEXT: .LBB63_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: zext.b a0, a1
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s2, a0, .LBB63_1
+; RV32I-NEXT: zext.b a2, a1
+; RV32I-NEXT: bltu a2, s1, .LBB63_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB63_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB63_1
; RV32I-NEXT: .LBB63_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_acq_rel:
@@ -15061,44 +14950,41 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i8_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: zext.b s2, s0
+; RV64I-NEXT: zext.b s1, s1
; RV64I-NEXT: j .LBB63_2
; RV64I-NEXT: .LBB63_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB63_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB63_4
; RV64I-NEXT: .LBB63_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: zext.b a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s2, a0, .LBB63_1
+; RV64I-NEXT: zext.b a2, a1
+; RV64I-NEXT: bltu a2, s1, .LBB63_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB63_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB63_1
; RV64I-NEXT: .LBB63_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_acq_rel:
@@ -15295,44 +15181,41 @@ define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind {
define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_seq_cst:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: zext.b s2, s0
+; RV32I-NEXT: zext.b s1, s1
; RV32I-NEXT: j .LBB64_2
; RV32I-NEXT: .LBB64_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB64_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB64_4
; RV32I-NEXT: .LBB64_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: zext.b a0, a1
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s2, a0, .LBB64_1
+; RV32I-NEXT: zext.b a2, a1
+; RV32I-NEXT: bltu a2, s1, .LBB64_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB64_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB64_1
; RV32I-NEXT: .LBB64_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_umin_i8_seq_cst:
@@ -15385,44 +15268,41 @@ define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i8_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: zext.b s2, s0
+; RV64I-NEXT: zext.b s1, s1
; RV64I-NEXT: j .LBB64_2
; RV64I-NEXT: .LBB64_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB64_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB64_4
; RV64I-NEXT: .LBB64_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: zext.b a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s2, a0, .LBB64_1
+; RV64I-NEXT: zext.b a2, a1
+; RV64I-NEXT: bltu a2, s1, .LBB64_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB64_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB64_1
; RV64I-NEXT: .LBB64_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i8_seq_cst:
@@ -24824,46 +24704,43 @@ define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind {
define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 16
-; RV32I-NEXT: srai s2, a0, 16
+; RV32I-NEXT: slli s1, s1, 16
+; RV32I-NEXT: srai s1, s1, 16
; RV32I-NEXT: j .LBB110_2
; RV32I-NEXT: .LBB110_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB110_2 Depth=1
-; RV32I-NEXT: sh a1, 14(sp)
-; RV32I-NEXT: addi a1, sp, 14
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sh a1, 2(sp)
+; RV32I-NEXT: addi a1, sp, 2
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 14(sp)
+; RV32I-NEXT: lh a1, 2(sp)
; RV32I-NEXT: bnez a0, .LBB110_4
; RV32I-NEXT: .LBB110_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
-; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s2, a0, .LBB110_1
+; RV32I-NEXT: slli a2, a1, 16
+; RV32I-NEXT: srai a2, a2, 16
+; RV32I-NEXT: blt s1, a2, .LBB110_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB110_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB110_1
; RV32I-NEXT: .LBB110_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_monotonic:
@@ -24930,46 +24807,43 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i16_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 48
-; RV64I-NEXT: srai s2, a0, 48
+; RV64I-NEXT: slli s1, s1, 48
+; RV64I-NEXT: srai s1, s1, 48
; RV64I-NEXT: j .LBB110_2
; RV64I-NEXT: .LBB110_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB110_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: addi a1, sp, 14
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB110_4
; RV64I-NEXT: .LBB110_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
-; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB110_1
+; RV64I-NEXT: slli a2, a1, 48
+; RV64I-NEXT: srai a2, a2, 48
+; RV64I-NEXT: blt s1, a2, .LBB110_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB110_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB110_1
; RV64I-NEXT: .LBB110_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_monotonic:
@@ -25122,46 +24996,43 @@ define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_acquire:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 16
-; RV32I-NEXT: srai s2, a0, 16
+; RV32I-NEXT: slli s1, s1, 16
+; RV32I-NEXT: srai s1, s1, 16
; RV32I-NEXT: j .LBB111_2
; RV32I-NEXT: .LBB111_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB111_2 Depth=1
-; RV32I-NEXT: sh a1, 14(sp)
-; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: sh a1, 2(sp)
+; RV32I-NEXT: addi a1, sp, 2
; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 14(sp)
+; RV32I-NEXT: lh a1, 2(sp)
; RV32I-NEXT: bnez a0, .LBB111_4
; RV32I-NEXT: .LBB111_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
-; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s2, a0, .LBB111_1
+; RV32I-NEXT: slli a2, a1, 16
+; RV32I-NEXT: srai a2, a2, 16
+; RV32I-NEXT: blt s1, a2, .LBB111_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB111_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB111_1
; RV32I-NEXT: .LBB111_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_acquire:
@@ -25259,46 +25130,43 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i16_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 48
-; RV64I-NEXT: srai s2, a0, 48
+; RV64I-NEXT: slli s1, s1, 48
+; RV64I-NEXT: srai s1, s1, 48
; RV64I-NEXT: j .LBB111_2
; RV64I-NEXT: .LBB111_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB111_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB111_4
; RV64I-NEXT: .LBB111_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
-; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB111_1
+; RV64I-NEXT: slli a2, a1, 48
+; RV64I-NEXT: srai a2, a2, 48
+; RV64I-NEXT: blt s1, a2, .LBB111_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB111_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB111_1
; RV64I-NEXT: .LBB111_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_acquire:
@@ -25544,46 +25412,43 @@ define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind {
define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_release:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 16
-; RV32I-NEXT: srai s2, a0, 16
+; RV32I-NEXT: slli s1, s1, 16
+; RV32I-NEXT: srai s1, s1, 16
; RV32I-NEXT: j .LBB112_2
; RV32I-NEXT: .LBB112_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB112_2 Depth=1
-; RV32I-NEXT: sh a1, 14(sp)
-; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: sh a1, 2(sp)
+; RV32I-NEXT: addi a1, sp, 2
; RV32I-NEXT: li a3, 3
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 14(sp)
+; RV32I-NEXT: lh a1, 2(sp)
; RV32I-NEXT: bnez a0, .LBB112_4
; RV32I-NEXT: .LBB112_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
-; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s2, a0, .LBB112_1
+; RV32I-NEXT: slli a2, a1, 16
+; RV32I-NEXT: srai a2, a2, 16
+; RV32I-NEXT: blt s1, a2, .LBB112_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB112_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB112_1
; RV32I-NEXT: .LBB112_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_release:
@@ -25681,46 +25546,43 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i16_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 48
-; RV64I-NEXT: srai s2, a0, 48
+; RV64I-NEXT: slli s1, s1, 48
+; RV64I-NEXT: srai s1, s1, 48
; RV64I-NEXT: j .LBB112_2
; RV64I-NEXT: .LBB112_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB112_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 3
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB112_4
; RV64I-NEXT: .LBB112_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
-; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB112_1
+; RV64I-NEXT: slli a2, a1, 48
+; RV64I-NEXT: srai a2, a2, 48
+; RV64I-NEXT: blt s1, a2, .LBB112_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB112_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB112_1
; RV64I-NEXT: .LBB112_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_release:
@@ -25966,46 +25828,43 @@ define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind {
define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_acq_rel:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 16
-; RV32I-NEXT: srai s2, a0, 16
+; RV32I-NEXT: slli s1, s1, 16
+; RV32I-NEXT: srai s1, s1, 16
; RV32I-NEXT: j .LBB113_2
; RV32I-NEXT: .LBB113_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB113_2 Depth=1
-; RV32I-NEXT: sh a1, 14(sp)
-; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: sh a1, 2(sp)
+; RV32I-NEXT: addi a1, sp, 2
; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 14(sp)
+; RV32I-NEXT: lh a1, 2(sp)
; RV32I-NEXT: bnez a0, .LBB113_4
; RV32I-NEXT: .LBB113_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
-; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s2, a0, .LBB113_1
+; RV32I-NEXT: slli a2, a1, 16
+; RV32I-NEXT: srai a2, a2, 16
+; RV32I-NEXT: blt s1, a2, .LBB113_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB113_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB113_1
; RV32I-NEXT: .LBB113_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_acq_rel:
@@ -26103,46 +25962,43 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i16_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 48
-; RV64I-NEXT: srai s2, a0, 48
+; RV64I-NEXT: slli s1, s1, 48
+; RV64I-NEXT: srai s1, s1, 48
; RV64I-NEXT: j .LBB113_2
; RV64I-NEXT: .LBB113_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB113_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB113_4
; RV64I-NEXT: .LBB113_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
-; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB113_1
+; RV64I-NEXT: slli a2, a1, 48
+; RV64I-NEXT: srai a2, a2, 48
+; RV64I-NEXT: blt s1, a2, .LBB113_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB113_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB113_1
; RV64I-NEXT: .LBB113_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_acq_rel:
@@ -26388,46 +26244,43 @@ define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind {
define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_seq_cst:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 16
-; RV32I-NEXT: srai s2, a0, 16
+; RV32I-NEXT: slli s1, s1, 16
+; RV32I-NEXT: srai s1, s1, 16
; RV32I-NEXT: j .LBB114_2
; RV32I-NEXT: .LBB114_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB114_2 Depth=1
-; RV32I-NEXT: sh a1, 14(sp)
-; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: sh a1, 2(sp)
+; RV32I-NEXT: addi a1, sp, 2
; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 14(sp)
+; RV32I-NEXT: lh a1, 2(sp)
; RV32I-NEXT: bnez a0, .LBB114_4
; RV32I-NEXT: .LBB114_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
-; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s2, a0, .LBB114_1
+; RV32I-NEXT: slli a2, a1, 16
+; RV32I-NEXT: srai a2, a2, 16
+; RV32I-NEXT: blt s1, a2, .LBB114_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB114_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB114_1
; RV32I-NEXT: .LBB114_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_max_i16_seq_cst:
@@ -26494,46 +26347,43 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i16_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 48
-; RV64I-NEXT: srai s2, a0, 48
+; RV64I-NEXT: slli s1, s1, 48
+; RV64I-NEXT: srai s1, s1, 48
; RV64I-NEXT: j .LBB114_2
; RV64I-NEXT: .LBB114_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB114_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB114_4
; RV64I-NEXT: .LBB114_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
-; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB114_1
+; RV64I-NEXT: slli a2, a1, 48
+; RV64I-NEXT: srai a2, a2, 48
+; RV64I-NEXT: blt s1, a2, .LBB114_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB114_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB114_1
; RV64I-NEXT: .LBB114_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i16_seq_cst:
@@ -26686,46 +26536,43 @@ define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind {
define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 16
-; RV32I-NEXT: srai s2, a0, 16
+; RV32I-NEXT: slli s1, s1, 16
+; RV32I-NEXT: srai s1, s1, 16
; RV32I-NEXT: j .LBB115_2
; RV32I-NEXT: .LBB115_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB115_2 Depth=1
-; RV32I-NEXT: sh a1, 14(sp)
-; RV32I-NEXT: addi a1, sp, 14
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sh a1, 2(sp)
+; RV32I-NEXT: addi a1, sp, 2
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 14(sp)
+; RV32I-NEXT: lh a1, 2(sp)
; RV32I-NEXT: bnez a0, .LBB115_4
; RV32I-NEXT: .LBB115_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
-; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s2, a0, .LBB115_1
+; RV32I-NEXT: slli a2, a1, 16
+; RV32I-NEXT: srai a2, a2, 16
+; RV32I-NEXT: blt a2, s1, .LBB115_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB115_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB115_1
; RV32I-NEXT: .LBB115_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_monotonic:
@@ -26792,46 +26639,43 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i16_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 48
-; RV64I-NEXT: srai s2, a0, 48
+; RV64I-NEXT: slli s1, s1, 48
+; RV64I-NEXT: srai s1, s1, 48
; RV64I-NEXT: j .LBB115_2
; RV64I-NEXT: .LBB115_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB115_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: addi a1, sp, 14
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB115_4
; RV64I-NEXT: .LBB115_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
-; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB115_1
+; RV64I-NEXT: slli a2, a1, 48
+; RV64I-NEXT: srai a2, a2, 48
+; RV64I-NEXT: blt a2, s1, .LBB115_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB115_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB115_1
; RV64I-NEXT: .LBB115_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_monotonic:
@@ -26984,46 +26828,43 @@ define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_acquire:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 16
-; RV32I-NEXT: srai s2, a0, 16
+; RV32I-NEXT: slli s1, s1, 16
+; RV32I-NEXT: srai s1, s1, 16
; RV32I-NEXT: j .LBB116_2
; RV32I-NEXT: .LBB116_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB116_2 Depth=1
-; RV32I-NEXT: sh a1, 14(sp)
-; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: sh a1, 2(sp)
+; RV32I-NEXT: addi a1, sp, 2
; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 14(sp)
+; RV32I-NEXT: lh a1, 2(sp)
; RV32I-NEXT: bnez a0, .LBB116_4
; RV32I-NEXT: .LBB116_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
-; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s2, a0, .LBB116_1
+; RV32I-NEXT: slli a2, a1, 16
+; RV32I-NEXT: srai a2, a2, 16
+; RV32I-NEXT: blt a2, s1, .LBB116_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB116_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB116_1
; RV32I-NEXT: .LBB116_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_acquire:
@@ -27121,46 +26962,43 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i16_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 48
-; RV64I-NEXT: srai s2, a0, 48
+; RV64I-NEXT: slli s1, s1, 48
+; RV64I-NEXT: srai s1, s1, 48
; RV64I-NEXT: j .LBB116_2
; RV64I-NEXT: .LBB116_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB116_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB116_4
; RV64I-NEXT: .LBB116_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
-; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB116_1
+; RV64I-NEXT: slli a2, a1, 48
+; RV64I-NEXT: srai a2, a2, 48
+; RV64I-NEXT: blt a2, s1, .LBB116_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB116_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB116_1
; RV64I-NEXT: .LBB116_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_acquire:
@@ -27406,46 +27244,43 @@ define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind {
define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_release:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 16
-; RV32I-NEXT: srai s2, a0, 16
+; RV32I-NEXT: slli s1, s1, 16
+; RV32I-NEXT: srai s1, s1, 16
; RV32I-NEXT: j .LBB117_2
; RV32I-NEXT: .LBB117_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB117_2 Depth=1
-; RV32I-NEXT: sh a1, 14(sp)
-; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: sh a1, 2(sp)
+; RV32I-NEXT: addi a1, sp, 2
; RV32I-NEXT: li a3, 3
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 14(sp)
+; RV32I-NEXT: lh a1, 2(sp)
; RV32I-NEXT: bnez a0, .LBB117_4
; RV32I-NEXT: .LBB117_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
-; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s2, a0, .LBB117_1
+; RV32I-NEXT: slli a2, a1, 16
+; RV32I-NEXT: srai a2, a2, 16
+; RV32I-NEXT: blt a2, s1, .LBB117_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB117_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB117_1
; RV32I-NEXT: .LBB117_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_release:
@@ -27543,46 +27378,43 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i16_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 48
-; RV64I-NEXT: srai s2, a0, 48
+; RV64I-NEXT: slli s1, s1, 48
+; RV64I-NEXT: srai s1, s1, 48
; RV64I-NEXT: j .LBB117_2
; RV64I-NEXT: .LBB117_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB117_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 3
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB117_4
; RV64I-NEXT: .LBB117_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
-; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB117_1
+; RV64I-NEXT: slli a2, a1, 48
+; RV64I-NEXT: srai a2, a2, 48
+; RV64I-NEXT: blt a2, s1, .LBB117_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB117_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB117_1
; RV64I-NEXT: .LBB117_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_release:
@@ -27828,46 +27660,43 @@ define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind {
define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_acq_rel:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 16
-; RV32I-NEXT: srai s2, a0, 16
+; RV32I-NEXT: slli s1, s1, 16
+; RV32I-NEXT: srai s1, s1, 16
; RV32I-NEXT: j .LBB118_2
; RV32I-NEXT: .LBB118_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB118_2 Depth=1
-; RV32I-NEXT: sh a1, 14(sp)
-; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: sh a1, 2(sp)
+; RV32I-NEXT: addi a1, sp, 2
; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 14(sp)
+; RV32I-NEXT: lh a1, 2(sp)
; RV32I-NEXT: bnez a0, .LBB118_4
; RV32I-NEXT: .LBB118_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
-; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s2, a0, .LBB118_1
+; RV32I-NEXT: slli a2, a1, 16
+; RV32I-NEXT: srai a2, a2, 16
+; RV32I-NEXT: blt a2, s1, .LBB118_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB118_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB118_1
; RV32I-NEXT: .LBB118_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_acq_rel:
@@ -27965,46 +27794,43 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i16_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 48
-; RV64I-NEXT: srai s2, a0, 48
+; RV64I-NEXT: slli s1, s1, 48
+; RV64I-NEXT: srai s1, s1, 48
; RV64I-NEXT: j .LBB118_2
; RV64I-NEXT: .LBB118_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB118_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB118_4
; RV64I-NEXT: .LBB118_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
-; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB118_1
+; RV64I-NEXT: slli a2, a1, 48
+; RV64I-NEXT: srai a2, a2, 48
+; RV64I-NEXT: blt a2, s1, .LBB118_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB118_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB118_1
; RV64I-NEXT: .LBB118_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_acq_rel:
@@ -28250,46 +28076,43 @@ define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind {
define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_seq_cst:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 16
-; RV32I-NEXT: srai s2, a0, 16
+; RV32I-NEXT: slli s1, s1, 16
+; RV32I-NEXT: srai s1, s1, 16
; RV32I-NEXT: j .LBB119_2
; RV32I-NEXT: .LBB119_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB119_2 Depth=1
-; RV32I-NEXT: sh a1, 14(sp)
-; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: sh a1, 2(sp)
+; RV32I-NEXT: addi a1, sp, 2
; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 14(sp)
+; RV32I-NEXT: lh a1, 2(sp)
; RV32I-NEXT: bnez a0, .LBB119_4
; RV32I-NEXT: .LBB119_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
-; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s2, a0, .LBB119_1
+; RV32I-NEXT: slli a2, a1, 16
+; RV32I-NEXT: srai a2, a2, 16
+; RV32I-NEXT: blt a2, s1, .LBB119_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB119_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB119_1
; RV32I-NEXT: .LBB119_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-ZALRSC-LABEL: atomicrmw_min_i16_seq_cst:
@@ -28356,46 +28179,43 @@ define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i16_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 48
-; RV64I-NEXT: srai s2, a0, 48
+; RV64I-NEXT: slli s1, s1, 48
+; RV64I-NEXT: srai s1, s1, 48
; RV64I-NEXT: j .LBB119_2
; RV64I-NEXT: .LBB119_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB119_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB119_4
; RV64I-NEXT: .LBB119_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
-; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB119_1
+; RV64I-NEXT: slli a2, a1, 48
+; RV64I-NEXT: srai a2, a2, 48
+; RV64I-NEXT: blt a2, s1, .LBB119_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB119_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB119_1
; RV64I-NEXT: .LBB119_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i16_seq_cst:
@@ -28553,34 +28373,32 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui s2, 16
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, s2
+; RV32I-NEXT: and s1, s1, s2
; RV32I-NEXT: j .LBB120_2
; RV32I-NEXT: .LBB120_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB120_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: addi a1, sp, 10
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sh a1, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a1, 14(sp)
; RV32I-NEXT: bnez a0, .LBB120_4
; RV32I-NEXT: .LBB120_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: and a0, a1, s2
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu s3, a0, .LBB120_1
+; RV32I-NEXT: and a2, a1, s2
+; RV32I-NEXT: bltu s1, a2, .LBB120_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB120_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB120_1
; RV32I-NEXT: .LBB120_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
@@ -28588,7 +28406,6 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
@@ -28649,34 +28466,32 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: and s3, s0, s2
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: j .LBB120_2
; RV64I-NEXT: .LBB120_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB120_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: addi a1, sp, 6
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: bnez a0, .LBB120_4
; RV64I-NEXT: .LBB120_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: and a0, a1, s2
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s3, a0, .LBB120_1
+; RV64I-NEXT: and a2, a1, s2
+; RV64I-NEXT: bltu s1, a2, .LBB120_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB120_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB120_1
; RV64I-NEXT: .LBB120_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
@@ -28684,7 +28499,6 @@ define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
@@ -28819,34 +28633,32 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui s2, 16
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, s2
+; RV32I-NEXT: and s1, s1, s2
; RV32I-NEXT: j .LBB121_2
; RV32I-NEXT: .LBB121_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB121_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: addi a1, sp, 10
+; RV32I-NEXT: sh a1, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a1, 14(sp)
; RV32I-NEXT: bnez a0, .LBB121_4
; RV32I-NEXT: .LBB121_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: and a0, a1, s2
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu s3, a0, .LBB121_1
+; RV32I-NEXT: and a2, a1, s2
+; RV32I-NEXT: bltu s1, a2, .LBB121_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB121_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB121_1
; RV32I-NEXT: .LBB121_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
@@ -28854,7 +28666,6 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
@@ -28940,34 +28751,32 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: and s3, s0, s2
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: j .LBB121_2
; RV64I-NEXT: .LBB121_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB121_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: bnez a0, .LBB121_4
; RV64I-NEXT: .LBB121_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: and a0, a1, s2
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s3, a0, .LBB121_1
+; RV64I-NEXT: and a2, a1, s2
+; RV64I-NEXT: bltu s1, a2, .LBB121_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB121_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB121_1
; RV64I-NEXT: .LBB121_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
@@ -28975,7 +28784,6 @@ define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
@@ -29185,34 +28993,32 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui s2, 16
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, s2
+; RV32I-NEXT: and s1, s1, s2
; RV32I-NEXT: j .LBB122_2
; RV32I-NEXT: .LBB122_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB122_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: addi a1, sp, 10
+; RV32I-NEXT: sh a1, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 3
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a1, 14(sp)
; RV32I-NEXT: bnez a0, .LBB122_4
; RV32I-NEXT: .LBB122_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: and a0, a1, s2
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu s3, a0, .LBB122_1
+; RV32I-NEXT: and a2, a1, s2
+; RV32I-NEXT: bltu s1, a2, .LBB122_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB122_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB122_1
; RV32I-NEXT: .LBB122_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
@@ -29220,7 +29026,6 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
@@ -29306,34 +29111,32 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: and s3, s0, s2
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: j .LBB122_2
; RV64I-NEXT: .LBB122_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB122_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 3
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: bnez a0, .LBB122_4
; RV64I-NEXT: .LBB122_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: and a0, a1, s2
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s3, a0, .LBB122_1
+; RV64I-NEXT: and a2, a1, s2
+; RV64I-NEXT: bltu s1, a2, .LBB122_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB122_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB122_1
; RV64I-NEXT: .LBB122_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
@@ -29341,7 +29144,6 @@ define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
@@ -29551,34 +29353,32 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui s2, 16
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, s2
+; RV32I-NEXT: and s1, s1, s2
; RV32I-NEXT: j .LBB123_2
; RV32I-NEXT: .LBB123_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB123_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: addi a1, sp, 10
+; RV32I-NEXT: sh a1, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a1, 14(sp)
; RV32I-NEXT: bnez a0, .LBB123_4
; RV32I-NEXT: .LBB123_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: and a0, a1, s2
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu s3, a0, .LBB123_1
+; RV32I-NEXT: and a2, a1, s2
+; RV32I-NEXT: bltu s1, a2, .LBB123_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB123_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB123_1
; RV32I-NEXT: .LBB123_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
@@ -29586,7 +29386,6 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
@@ -29672,34 +29471,32 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: and s3, s0, s2
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: j .LBB123_2
; RV64I-NEXT: .LBB123_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB123_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: bnez a0, .LBB123_4
; RV64I-NEXT: .LBB123_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: and a0, a1, s2
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s3, a0, .LBB123_1
+; RV64I-NEXT: and a2, a1, s2
+; RV64I-NEXT: bltu s1, a2, .LBB123_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB123_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB123_1
; RV64I-NEXT: .LBB123_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
@@ -29707,7 +29504,6 @@ define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
@@ -29917,34 +29713,32 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui s2, 16
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, s2
+; RV32I-NEXT: and s1, s1, s2
; RV32I-NEXT: j .LBB124_2
; RV32I-NEXT: .LBB124_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB124_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: addi a1, sp, 10
+; RV32I-NEXT: sh a1, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a1, 14(sp)
; RV32I-NEXT: bnez a0, .LBB124_4
; RV32I-NEXT: .LBB124_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: and a0, a1, s2
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu s3, a0, .LBB124_1
+; RV32I-NEXT: and a2, a1, s2
+; RV32I-NEXT: bltu s1, a2, .LBB124_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB124_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB124_1
; RV32I-NEXT: .LBB124_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
@@ -29952,7 +29746,6 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
@@ -30013,34 +29806,32 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: and s3, s0, s2
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: j .LBB124_2
; RV64I-NEXT: .LBB124_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB124_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: bnez a0, .LBB124_4
; RV64I-NEXT: .LBB124_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: and a0, a1, s2
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s3, a0, .LBB124_1
+; RV64I-NEXT: and a2, a1, s2
+; RV64I-NEXT: bltu s1, a2, .LBB124_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB124_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB124_1
; RV64I-NEXT: .LBB124_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
@@ -30048,7 +29839,6 @@ define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
@@ -30183,34 +29973,32 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui s2, 16
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, s2
+; RV32I-NEXT: and s1, s1, s2
; RV32I-NEXT: j .LBB125_2
; RV32I-NEXT: .LBB125_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB125_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: addi a1, sp, 10
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sh a1, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a1, 14(sp)
; RV32I-NEXT: bnez a0, .LBB125_4
; RV32I-NEXT: .LBB125_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: and a0, a1, s2
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s3, a0, .LBB125_1
+; RV32I-NEXT: and a2, a1, s2
+; RV32I-NEXT: bltu a2, s1, .LBB125_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB125_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB125_1
; RV32I-NEXT: .LBB125_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
@@ -30218,7 +30006,6 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
@@ -30279,34 +30066,32 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: and s3, s0, s2
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: j .LBB125_2
; RV64I-NEXT: .LBB125_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB125_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: addi a1, sp, 6
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: bnez a0, .LBB125_4
; RV64I-NEXT: .LBB125_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: and a0, a1, s2
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s3, a0, .LBB125_1
+; RV64I-NEXT: and a2, a1, s2
+; RV64I-NEXT: bltu a2, s1, .LBB125_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB125_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB125_1
; RV64I-NEXT: .LBB125_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
@@ -30314,7 +30099,6 @@ define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
@@ -30449,34 +30233,32 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui s2, 16
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, s2
+; RV32I-NEXT: and s1, s1, s2
; RV32I-NEXT: j .LBB126_2
; RV32I-NEXT: .LBB126_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB126_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: addi a1, sp, 10
+; RV32I-NEXT: sh a1, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 2
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a1, 14(sp)
; RV32I-NEXT: bnez a0, .LBB126_4
; RV32I-NEXT: .LBB126_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: and a0, a1, s2
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s3, a0, .LBB126_1
+; RV32I-NEXT: and a2, a1, s2
+; RV32I-NEXT: bltu a2, s1, .LBB126_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB126_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB126_1
; RV32I-NEXT: .LBB126_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
@@ -30484,7 +30266,6 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
@@ -30570,34 +30351,32 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: and s3, s0, s2
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: j .LBB126_2
; RV64I-NEXT: .LBB126_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB126_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: bnez a0, .LBB126_4
; RV64I-NEXT: .LBB126_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: and a0, a1, s2
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s3, a0, .LBB126_1
+; RV64I-NEXT: and a2, a1, s2
+; RV64I-NEXT: bltu a2, s1, .LBB126_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB126_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB126_1
; RV64I-NEXT: .LBB126_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
@@ -30605,7 +30384,6 @@ define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
@@ -30815,34 +30593,32 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui s2, 16
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, s2
+; RV32I-NEXT: and s1, s1, s2
; RV32I-NEXT: j .LBB127_2
; RV32I-NEXT: .LBB127_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB127_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: addi a1, sp, 10
+; RV32I-NEXT: sh a1, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 3
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a1, 14(sp)
; RV32I-NEXT: bnez a0, .LBB127_4
; RV32I-NEXT: .LBB127_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: and a0, a1, s2
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s3, a0, .LBB127_1
+; RV32I-NEXT: and a2, a1, s2
+; RV32I-NEXT: bltu a2, s1, .LBB127_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB127_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB127_1
; RV32I-NEXT: .LBB127_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
@@ -30850,7 +30626,6 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
@@ -30936,34 +30711,32 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: and s3, s0, s2
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: j .LBB127_2
; RV64I-NEXT: .LBB127_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB127_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 3
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: bnez a0, .LBB127_4
; RV64I-NEXT: .LBB127_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: and a0, a1, s2
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s3, a0, .LBB127_1
+; RV64I-NEXT: and a2, a1, s2
+; RV64I-NEXT: bltu a2, s1, .LBB127_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB127_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB127_1
; RV64I-NEXT: .LBB127_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
@@ -30971,7 +30744,6 @@ define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
@@ -31181,34 +30953,32 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui s2, 16
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, s2
+; RV32I-NEXT: and s1, s1, s2
; RV32I-NEXT: j .LBB128_2
; RV32I-NEXT: .LBB128_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB128_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: addi a1, sp, 10
+; RV32I-NEXT: sh a1, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 2
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a1, 14(sp)
; RV32I-NEXT: bnez a0, .LBB128_4
; RV32I-NEXT: .LBB128_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: and a0, a1, s2
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s3, a0, .LBB128_1
+; RV32I-NEXT: and a2, a1, s2
+; RV32I-NEXT: bltu a2, s1, .LBB128_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB128_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB128_1
; RV32I-NEXT: .LBB128_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
@@ -31216,7 +30986,6 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
@@ -31302,34 +31071,32 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: and s3, s0, s2
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: j .LBB128_2
; RV64I-NEXT: .LBB128_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB128_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: bnez a0, .LBB128_4
; RV64I-NEXT: .LBB128_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: and a0, a1, s2
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s3, a0, .LBB128_1
+; RV64I-NEXT: and a2, a1, s2
+; RV64I-NEXT: bltu a2, s1, .LBB128_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB128_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB128_1
; RV64I-NEXT: .LBB128_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
@@ -31337,7 +31104,6 @@ define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
@@ -31547,34 +31313,32 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui s2, 16
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, s2
+; RV32I-NEXT: and s1, s1, s2
; RV32I-NEXT: j .LBB129_2
; RV32I-NEXT: .LBB129_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB129_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: addi a1, sp, 10
+; RV32I-NEXT: sh a1, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
; RV32I-NEXT: li a3, 5
; RV32I-NEXT: li a4, 5
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a1, 14(sp)
; RV32I-NEXT: bnez a0, .LBB129_4
; RV32I-NEXT: .LBB129_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: and a0, a1, s2
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s3, a0, .LBB129_1
+; RV32I-NEXT: and a2, a1, s2
+; RV32I-NEXT: bltu a2, s1, .LBB129_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB129_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB129_1
; RV32I-NEXT: .LBB129_4: # %atomicrmw.end
; RV32I-NEXT: mv a0, a1
@@ -31582,7 +31346,6 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
@@ -31643,34 +31406,32 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: and s3, s0, s2
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: j .LBB129_2
; RV64I-NEXT: .LBB129_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB129_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: bnez a0, .LBB129_4
; RV64I-NEXT: .LBB129_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: and a0, a1, s2
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s3, a0, .LBB129_1
+; RV64I-NEXT: and a2, a1, s2
+; RV64I-NEXT: bltu a2, s1, .LBB129_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB129_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB129_1
; RV64I-NEXT: .LBB129_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
@@ -31678,7 +31439,6 @@ define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
@@ -35016,44 +34776,41 @@ define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i32_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB165_2
; RV64I-NEXT: .LBB165_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB165_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB165_4
; RV64I-NEXT: .LBB165_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB165_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: blt s1, a2, .LBB165_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB165_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB165_1
; RV64I-NEXT: .LBB165_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_monotonic:
@@ -35146,44 +34903,41 @@ define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i32_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB166_2
; RV64I-NEXT: .LBB166_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB166_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB166_4
; RV64I-NEXT: .LBB166_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB166_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: blt s1, a2, .LBB166_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB166_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB166_1
; RV64I-NEXT: .LBB166_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_acquire:
@@ -35281,44 +35035,41 @@ define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i32_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB167_2
; RV64I-NEXT: .LBB167_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB167_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 3
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB167_4
; RV64I-NEXT: .LBB167_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB167_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: blt s1, a2, .LBB167_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB167_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB167_1
; RV64I-NEXT: .LBB167_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_release:
@@ -35416,44 +35167,41 @@ define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i32_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB168_2
; RV64I-NEXT: .LBB168_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB168_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB168_4
; RV64I-NEXT: .LBB168_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB168_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: blt s1, a2, .LBB168_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB168_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB168_1
; RV64I-NEXT: .LBB168_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_acq_rel:
@@ -35551,44 +35299,41 @@ define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i32_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB169_2
; RV64I-NEXT: .LBB169_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB169_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB169_4
; RV64I-NEXT: .LBB169_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB169_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: blt s1, a2, .LBB169_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB169_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB169_1
; RV64I-NEXT: .LBB169_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_max_i32_seq_cst:
@@ -35646,7 +35391,7 @@ define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: .LBB170_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a1, .LBB170_1
+; RV32I-NEXT: blt a1, s0, .LBB170_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB170_2 Depth=1
; RV32I-NEXT: mv a2, s0
@@ -35681,44 +35426,41 @@ define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i32_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB170_2
; RV64I-NEXT: .LBB170_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB170_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB170_4
; RV64I-NEXT: .LBB170_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB170_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: blt a2, s1, .LBB170_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB170_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB170_1
; RV64I-NEXT: .LBB170_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_monotonic:
@@ -35771,7 +35513,7 @@ define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: .LBB171_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a1, .LBB171_1
+; RV32I-NEXT: blt a1, s0, .LBB171_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB171_2 Depth=1
; RV32I-NEXT: mv a2, s0
@@ -35811,44 +35553,41 @@ define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i32_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB171_2
; RV64I-NEXT: .LBB171_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB171_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB171_4
; RV64I-NEXT: .LBB171_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB171_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: blt a2, s1, .LBB171_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB171_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB171_1
; RV64I-NEXT: .LBB171_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_acquire:
@@ -35906,7 +35645,7 @@ define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: .LBB172_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a1, .LBB172_1
+; RV32I-NEXT: blt a1, s0, .LBB172_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB172_2 Depth=1
; RV32I-NEXT: mv a2, s0
@@ -35946,44 +35685,41 @@ define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i32_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB172_2
; RV64I-NEXT: .LBB172_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB172_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 3
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB172_4
; RV64I-NEXT: .LBB172_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB172_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: blt a2, s1, .LBB172_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB172_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB172_1
; RV64I-NEXT: .LBB172_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_release:
@@ -36041,7 +35777,7 @@ define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: .LBB173_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a1, .LBB173_1
+; RV32I-NEXT: blt a1, s0, .LBB173_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB173_2 Depth=1
; RV32I-NEXT: mv a2, s0
@@ -36081,44 +35817,41 @@ define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i32_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB173_2
; RV64I-NEXT: .LBB173_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB173_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB173_4
; RV64I-NEXT: .LBB173_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB173_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: blt a2, s1, .LBB173_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB173_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB173_1
; RV64I-NEXT: .LBB173_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_acq_rel:
@@ -36176,7 +35909,7 @@ define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: .LBB174_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a1, .LBB174_1
+; RV32I-NEXT: blt a1, s0, .LBB174_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB174_2 Depth=1
; RV32I-NEXT: mv a2, s0
@@ -36216,44 +35949,41 @@ define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i32_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB174_2
; RV64I-NEXT: .LBB174_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB174_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB174_4
; RV64I-NEXT: .LBB174_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB174_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: blt a2, s1, .LBB174_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB174_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB174_1
; RV64I-NEXT: .LBB174_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_min_i32_seq_cst:
@@ -36346,44 +36076,41 @@ define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i32_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB175_2
; RV64I-NEXT: .LBB175_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB175_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB175_4
; RV64I-NEXT: .LBB175_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s2, a0, .LBB175_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: bltu s1, a2, .LBB175_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB175_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB175_1
; RV64I-NEXT: .LBB175_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_monotonic:
@@ -36476,44 +36203,41 @@ define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i32_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB176_2
; RV64I-NEXT: .LBB176_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB176_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB176_4
; RV64I-NEXT: .LBB176_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s2, a0, .LBB176_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: bltu s1, a2, .LBB176_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB176_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB176_1
; RV64I-NEXT: .LBB176_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_acquire:
@@ -36611,44 +36335,41 @@ define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i32_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB177_2
; RV64I-NEXT: .LBB177_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB177_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 3
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB177_4
; RV64I-NEXT: .LBB177_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s2, a0, .LBB177_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: bltu s1, a2, .LBB177_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB177_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB177_1
; RV64I-NEXT: .LBB177_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_release:
@@ -36746,44 +36467,41 @@ define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i32_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB178_2
; RV64I-NEXT: .LBB178_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB178_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB178_4
; RV64I-NEXT: .LBB178_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s2, a0, .LBB178_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: bltu s1, a2, .LBB178_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB178_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB178_1
; RV64I-NEXT: .LBB178_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_acq_rel:
@@ -36881,44 +36599,41 @@ define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i32_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB179_2
; RV64I-NEXT: .LBB179_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB179_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB179_4
; RV64I-NEXT: .LBB179_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s2, a0, .LBB179_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: bltu s1, a2, .LBB179_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB179_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB179_1
; RV64I-NEXT: .LBB179_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umax_i32_seq_cst:
@@ -36976,7 +36691,7 @@ define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: .LBB180_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s0, a1, .LBB180_1
+; RV32I-NEXT: bltu a1, s0, .LBB180_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB180_2 Depth=1
; RV32I-NEXT: mv a2, s0
@@ -37011,44 +36726,41 @@ define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i32_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB180_2
; RV64I-NEXT: .LBB180_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB180_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB180_4
; RV64I-NEXT: .LBB180_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s2, a0, .LBB180_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: bltu a2, s1, .LBB180_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB180_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB180_1
; RV64I-NEXT: .LBB180_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_monotonic:
@@ -37101,7 +36813,7 @@ define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: .LBB181_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s0, a1, .LBB181_1
+; RV32I-NEXT: bltu a1, s0, .LBB181_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB181_2 Depth=1
; RV32I-NEXT: mv a2, s0
@@ -37141,44 +36853,41 @@ define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i32_acquire:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB181_2
; RV64I-NEXT: .LBB181_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB181_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 2
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB181_4
; RV64I-NEXT: .LBB181_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s2, a0, .LBB181_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: bltu a2, s1, .LBB181_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB181_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB181_1
; RV64I-NEXT: .LBB181_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_acquire:
@@ -37236,7 +36945,7 @@ define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: .LBB182_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s0, a1, .LBB182_1
+; RV32I-NEXT: bltu a1, s0, .LBB182_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB182_2 Depth=1
; RV32I-NEXT: mv a2, s0
@@ -37276,44 +36985,41 @@ define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i32_release:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB182_2
; RV64I-NEXT: .LBB182_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB182_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 3
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB182_4
; RV64I-NEXT: .LBB182_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s2, a0, .LBB182_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: bltu a2, s1, .LBB182_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB182_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB182_1
; RV64I-NEXT: .LBB182_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_release:
@@ -37371,7 +37077,7 @@ define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: .LBB183_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s0, a1, .LBB183_1
+; RV32I-NEXT: bltu a1, s0, .LBB183_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB183_2 Depth=1
; RV32I-NEXT: mv a2, s0
@@ -37411,44 +37117,41 @@ define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i32_acq_rel:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB183_2
; RV64I-NEXT: .LBB183_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB183_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 2
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB183_4
; RV64I-NEXT: .LBB183_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s2, a0, .LBB183_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: bltu a2, s1, .LBB183_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB183_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB183_1
; RV64I-NEXT: .LBB183_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_acq_rel:
@@ -37506,7 +37209,7 @@ define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: .LBB184_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s0, a1, .LBB184_1
+; RV32I-NEXT: bltu a1, s0, .LBB184_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB184_2 Depth=1
; RV32I-NEXT: mv a2, s0
@@ -37546,44 +37249,41 @@ define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i32_seq_cst:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB184_2
; RV64I-NEXT: .LBB184_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB184_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
; RV64I-NEXT: li a3, 5
; RV64I-NEXT: li a4, 5
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB184_4
; RV64I-NEXT: .LBB184_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s2, a0, .LBB184_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: bltu a2, s1, .LBB184_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB184_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB184_1
; RV64I-NEXT: .LBB184_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64I-ZALRSC-LABEL: atomicrmw_umin_i32_seq_cst:
@@ -41482,15 +41182,15 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: beq a1, s0, .LBB225_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB225_2 Depth=1
-; RV32I-NEXT: slt a0, s0, a1
+; RV32I-NEXT: slt a0, a1, s0
; RV32I-NEXT: j .LBB225_5
; RV32I-NEXT: .LBB225_4: # in Loop: Header=BB225_2 Depth=1
-; RV32I-NEXT: sltu a0, s1, a4
+; RV32I-NEXT: sltu a0, a4, s1
; RV32I-NEXT: .LBB225_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: beqz a0, .LBB225_1
+; RV32I-NEXT: bnez a0, .LBB225_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32I-NEXT: mv a2, s1
@@ -41536,15 +41236,15 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-ZALRSC-NEXT: beq a1, s0, .LBB225_4
; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB225_2 Depth=1
-; RV32I-ZALRSC-NEXT: slt a0, s0, a1
+; RV32I-ZALRSC-NEXT: slt a0, a1, s0
; RV32I-ZALRSC-NEXT: j .LBB225_5
; RV32I-ZALRSC-NEXT: .LBB225_4: # in Loop: Header=BB225_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s1, a4
+; RV32I-ZALRSC-NEXT: sltu a0, a4, s1
; RV32I-ZALRSC-NEXT: .LBB225_5: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, a4
; RV32I-ZALRSC-NEXT: mv a3, a1
-; RV32I-ZALRSC-NEXT: beqz a0, .LBB225_1
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB225_1
; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, s1
@@ -41590,15 +41290,15 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: beq a1, s0, .LBB225_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB225_2 Depth=1
-; RV32IA-NEXT: slt a0, s0, a1
+; RV32IA-NEXT: slt a0, a1, s0
; RV32IA-NEXT: j .LBB225_5
; RV32IA-NEXT: .LBB225_4: # in Loop: Header=BB225_2 Depth=1
-; RV32IA-NEXT: sltu a0, s1, a4
+; RV32IA-NEXT: sltu a0, a4, s1
; RV32IA-NEXT: .LBB225_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1
-; RV32IA-NEXT: beqz a0, .LBB225_1
+; RV32IA-NEXT: bnez a0, .LBB225_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV32IA-NEXT: mv a2, s1
@@ -41638,7 +41338,7 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: .LBB225_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a1, .LBB225_1
+; RV64I-NEXT: blt a1, s0, .LBB225_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB225_2 Depth=1
; RV64I-NEXT: mv a2, s0
@@ -41706,15 +41406,15 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: beq a1, s0, .LBB226_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB226_2 Depth=1
-; RV32I-NEXT: slt a0, s0, a1
+; RV32I-NEXT: slt a0, a1, s0
; RV32I-NEXT: j .LBB226_5
; RV32I-NEXT: .LBB226_4: # in Loop: Header=BB226_2 Depth=1
-; RV32I-NEXT: sltu a0, s1, a4
+; RV32I-NEXT: sltu a0, a4, s1
; RV32I-NEXT: .LBB226_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: beqz a0, .LBB226_1
+; RV32I-NEXT: bnez a0, .LBB226_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32I-NEXT: mv a2, s1
@@ -41760,15 +41460,15 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-ZALRSC-NEXT: beq a1, s0, .LBB226_4
; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB226_2 Depth=1
-; RV32I-ZALRSC-NEXT: slt a0, s0, a1
+; RV32I-ZALRSC-NEXT: slt a0, a1, s0
; RV32I-ZALRSC-NEXT: j .LBB226_5
; RV32I-ZALRSC-NEXT: .LBB226_4: # in Loop: Header=BB226_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s1, a4
+; RV32I-ZALRSC-NEXT: sltu a0, a4, s1
; RV32I-ZALRSC-NEXT: .LBB226_5: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, a4
; RV32I-ZALRSC-NEXT: mv a3, a1
-; RV32I-ZALRSC-NEXT: beqz a0, .LBB226_1
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB226_1
; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, s1
@@ -41814,15 +41514,15 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: beq a1, s0, .LBB226_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB226_2 Depth=1
-; RV32IA-NEXT: slt a0, s0, a1
+; RV32IA-NEXT: slt a0, a1, s0
; RV32IA-NEXT: j .LBB226_5
; RV32IA-NEXT: .LBB226_4: # in Loop: Header=BB226_2 Depth=1
-; RV32IA-NEXT: sltu a0, s1, a4
+; RV32IA-NEXT: sltu a0, a4, s1
; RV32IA-NEXT: .LBB226_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1
-; RV32IA-NEXT: beqz a0, .LBB226_1
+; RV32IA-NEXT: bnez a0, .LBB226_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV32IA-NEXT: mv a2, s1
@@ -41862,7 +41562,7 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: .LBB226_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a1, .LBB226_1
+; RV64I-NEXT: blt a1, s0, .LBB226_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB226_2 Depth=1
; RV64I-NEXT: mv a2, s0
@@ -41935,15 +41635,15 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: beq a1, s0, .LBB227_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB227_2 Depth=1
-; RV32I-NEXT: slt a0, s0, a1
+; RV32I-NEXT: slt a0, a1, s0
; RV32I-NEXT: j .LBB227_5
; RV32I-NEXT: .LBB227_4: # in Loop: Header=BB227_2 Depth=1
-; RV32I-NEXT: sltu a0, s1, a4
+; RV32I-NEXT: sltu a0, a4, s1
; RV32I-NEXT: .LBB227_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: beqz a0, .LBB227_1
+; RV32I-NEXT: bnez a0, .LBB227_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32I-NEXT: mv a2, s1
@@ -41989,15 +41689,15 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-ZALRSC-NEXT: beq a1, s0, .LBB227_4
; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB227_2 Depth=1
-; RV32I-ZALRSC-NEXT: slt a0, s0, a1
+; RV32I-ZALRSC-NEXT: slt a0, a1, s0
; RV32I-ZALRSC-NEXT: j .LBB227_5
; RV32I-ZALRSC-NEXT: .LBB227_4: # in Loop: Header=BB227_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s1, a4
+; RV32I-ZALRSC-NEXT: sltu a0, a4, s1
; RV32I-ZALRSC-NEXT: .LBB227_5: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, a4
; RV32I-ZALRSC-NEXT: mv a3, a1
-; RV32I-ZALRSC-NEXT: beqz a0, .LBB227_1
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB227_1
; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, s1
@@ -42043,15 +41743,15 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: beq a1, s0, .LBB227_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB227_2 Depth=1
-; RV32IA-NEXT: slt a0, s0, a1
+; RV32IA-NEXT: slt a0, a1, s0
; RV32IA-NEXT: j .LBB227_5
; RV32IA-NEXT: .LBB227_4: # in Loop: Header=BB227_2 Depth=1
-; RV32IA-NEXT: sltu a0, s1, a4
+; RV32IA-NEXT: sltu a0, a4, s1
; RV32IA-NEXT: .LBB227_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1
-; RV32IA-NEXT: beqz a0, .LBB227_1
+; RV32IA-NEXT: bnez a0, .LBB227_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV32IA-NEXT: mv a2, s1
@@ -42091,7 +41791,7 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: .LBB227_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a1, .LBB227_1
+; RV64I-NEXT: blt a1, s0, .LBB227_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB227_2 Depth=1
; RV64I-NEXT: mv a2, s0
@@ -42164,15 +41864,15 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: beq a1, s0, .LBB228_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB228_2 Depth=1
-; RV32I-NEXT: slt a0, s0, a1
+; RV32I-NEXT: slt a0, a1, s0
; RV32I-NEXT: j .LBB228_5
; RV32I-NEXT: .LBB228_4: # in Loop: Header=BB228_2 Depth=1
-; RV32I-NEXT: sltu a0, s1, a4
+; RV32I-NEXT: sltu a0, a4, s1
; RV32I-NEXT: .LBB228_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: beqz a0, .LBB228_1
+; RV32I-NEXT: bnez a0, .LBB228_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32I-NEXT: mv a2, s1
@@ -42218,15 +41918,15 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-ZALRSC-NEXT: beq a1, s0, .LBB228_4
; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB228_2 Depth=1
-; RV32I-ZALRSC-NEXT: slt a0, s0, a1
+; RV32I-ZALRSC-NEXT: slt a0, a1, s0
; RV32I-ZALRSC-NEXT: j .LBB228_5
; RV32I-ZALRSC-NEXT: .LBB228_4: # in Loop: Header=BB228_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s1, a4
+; RV32I-ZALRSC-NEXT: sltu a0, a4, s1
; RV32I-ZALRSC-NEXT: .LBB228_5: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, a4
; RV32I-ZALRSC-NEXT: mv a3, a1
-; RV32I-ZALRSC-NEXT: beqz a0, .LBB228_1
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB228_1
; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, s1
@@ -42272,15 +41972,15 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: beq a1, s0, .LBB228_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB228_2 Depth=1
-; RV32IA-NEXT: slt a0, s0, a1
+; RV32IA-NEXT: slt a0, a1, s0
; RV32IA-NEXT: j .LBB228_5
; RV32IA-NEXT: .LBB228_4: # in Loop: Header=BB228_2 Depth=1
-; RV32IA-NEXT: sltu a0, s1, a4
+; RV32IA-NEXT: sltu a0, a4, s1
; RV32IA-NEXT: .LBB228_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1
-; RV32IA-NEXT: beqz a0, .LBB228_1
+; RV32IA-NEXT: bnez a0, .LBB228_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV32IA-NEXT: mv a2, s1
@@ -42320,7 +42020,7 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: .LBB228_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a1, .LBB228_1
+; RV64I-NEXT: blt a1, s0, .LBB228_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB228_2 Depth=1
; RV64I-NEXT: mv a2, s0
@@ -42393,15 +42093,15 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: beq a1, s0, .LBB229_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB229_2 Depth=1
-; RV32I-NEXT: slt a0, s0, a1
+; RV32I-NEXT: slt a0, a1, s0
; RV32I-NEXT: j .LBB229_5
; RV32I-NEXT: .LBB229_4: # in Loop: Header=BB229_2 Depth=1
-; RV32I-NEXT: sltu a0, s1, a4
+; RV32I-NEXT: sltu a0, a4, s1
; RV32I-NEXT: .LBB229_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: beqz a0, .LBB229_1
+; RV32I-NEXT: bnez a0, .LBB229_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32I-NEXT: mv a2, s1
@@ -42447,15 +42147,15 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-ZALRSC-NEXT: beq a1, s0, .LBB229_4
; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB229_2 Depth=1
-; RV32I-ZALRSC-NEXT: slt a0, s0, a1
+; RV32I-ZALRSC-NEXT: slt a0, a1, s0
; RV32I-ZALRSC-NEXT: j .LBB229_5
; RV32I-ZALRSC-NEXT: .LBB229_4: # in Loop: Header=BB229_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s1, a4
+; RV32I-ZALRSC-NEXT: sltu a0, a4, s1
; RV32I-ZALRSC-NEXT: .LBB229_5: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, a4
; RV32I-ZALRSC-NEXT: mv a3, a1
-; RV32I-ZALRSC-NEXT: beqz a0, .LBB229_1
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB229_1
; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, s1
@@ -42501,15 +42201,15 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: beq a1, s0, .LBB229_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB229_2 Depth=1
-; RV32IA-NEXT: slt a0, s0, a1
+; RV32IA-NEXT: slt a0, a1, s0
; RV32IA-NEXT: j .LBB229_5
; RV32IA-NEXT: .LBB229_4: # in Loop: Header=BB229_2 Depth=1
-; RV32IA-NEXT: sltu a0, s1, a4
+; RV32IA-NEXT: sltu a0, a4, s1
; RV32IA-NEXT: .LBB229_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1
-; RV32IA-NEXT: beqz a0, .LBB229_1
+; RV32IA-NEXT: bnez a0, .LBB229_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV32IA-NEXT: mv a2, s1
@@ -42549,7 +42249,7 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: .LBB229_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a1, .LBB229_1
+; RV64I-NEXT: blt a1, s0, .LBB229_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB229_2 Depth=1
; RV64I-NEXT: mv a2, s0
@@ -43762,15 +43462,15 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: beq a1, s0, .LBB235_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB235_2 Depth=1
-; RV32I-NEXT: sltu a0, s0, a1
+; RV32I-NEXT: sltu a0, a1, s0
; RV32I-NEXT: j .LBB235_5
; RV32I-NEXT: .LBB235_4: # in Loop: Header=BB235_2 Depth=1
-; RV32I-NEXT: sltu a0, s1, a4
+; RV32I-NEXT: sltu a0, a4, s1
; RV32I-NEXT: .LBB235_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: beqz a0, .LBB235_1
+; RV32I-NEXT: bnez a0, .LBB235_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32I-NEXT: mv a2, s1
@@ -43816,15 +43516,15 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-ZALRSC-NEXT: beq a1, s0, .LBB235_4
; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB235_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s0, a1
+; RV32I-ZALRSC-NEXT: sltu a0, a1, s0
; RV32I-ZALRSC-NEXT: j .LBB235_5
; RV32I-ZALRSC-NEXT: .LBB235_4: # in Loop: Header=BB235_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s1, a4
+; RV32I-ZALRSC-NEXT: sltu a0, a4, s1
; RV32I-ZALRSC-NEXT: .LBB235_5: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, a4
; RV32I-ZALRSC-NEXT: mv a3, a1
-; RV32I-ZALRSC-NEXT: beqz a0, .LBB235_1
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB235_1
; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, s1
@@ -43870,15 +43570,15 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: beq a1, s0, .LBB235_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB235_2 Depth=1
-; RV32IA-NEXT: sltu a0, s0, a1
+; RV32IA-NEXT: sltu a0, a1, s0
; RV32IA-NEXT: j .LBB235_5
; RV32IA-NEXT: .LBB235_4: # in Loop: Header=BB235_2 Depth=1
-; RV32IA-NEXT: sltu a0, s1, a4
+; RV32IA-NEXT: sltu a0, a4, s1
; RV32IA-NEXT: .LBB235_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1
-; RV32IA-NEXT: beqz a0, .LBB235_1
+; RV32IA-NEXT: bnez a0, .LBB235_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV32IA-NEXT: mv a2, s1
@@ -43918,7 +43618,7 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: .LBB235_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s0, a1, .LBB235_1
+; RV64I-NEXT: bltu a1, s0, .LBB235_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB235_2 Depth=1
; RV64I-NEXT: mv a2, s0
@@ -43986,15 +43686,15 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: beq a1, s0, .LBB236_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB236_2 Depth=1
-; RV32I-NEXT: sltu a0, s0, a1
+; RV32I-NEXT: sltu a0, a1, s0
; RV32I-NEXT: j .LBB236_5
; RV32I-NEXT: .LBB236_4: # in Loop: Header=BB236_2 Depth=1
-; RV32I-NEXT: sltu a0, s1, a4
+; RV32I-NEXT: sltu a0, a4, s1
; RV32I-NEXT: .LBB236_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: beqz a0, .LBB236_1
+; RV32I-NEXT: bnez a0, .LBB236_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32I-NEXT: mv a2, s1
@@ -44040,15 +43740,15 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-ZALRSC-NEXT: beq a1, s0, .LBB236_4
; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB236_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s0, a1
+; RV32I-ZALRSC-NEXT: sltu a0, a1, s0
; RV32I-ZALRSC-NEXT: j .LBB236_5
; RV32I-ZALRSC-NEXT: .LBB236_4: # in Loop: Header=BB236_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s1, a4
+; RV32I-ZALRSC-NEXT: sltu a0, a4, s1
; RV32I-ZALRSC-NEXT: .LBB236_5: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, a4
; RV32I-ZALRSC-NEXT: mv a3, a1
-; RV32I-ZALRSC-NEXT: beqz a0, .LBB236_1
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB236_1
; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, s1
@@ -44094,15 +43794,15 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: beq a1, s0, .LBB236_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB236_2 Depth=1
-; RV32IA-NEXT: sltu a0, s0, a1
+; RV32IA-NEXT: sltu a0, a1, s0
; RV32IA-NEXT: j .LBB236_5
; RV32IA-NEXT: .LBB236_4: # in Loop: Header=BB236_2 Depth=1
-; RV32IA-NEXT: sltu a0, s1, a4
+; RV32IA-NEXT: sltu a0, a4, s1
; RV32IA-NEXT: .LBB236_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1
-; RV32IA-NEXT: beqz a0, .LBB236_1
+; RV32IA-NEXT: bnez a0, .LBB236_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV32IA-NEXT: mv a2, s1
@@ -44142,7 +43842,7 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: .LBB236_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s0, a1, .LBB236_1
+; RV64I-NEXT: bltu a1, s0, .LBB236_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB236_2 Depth=1
; RV64I-NEXT: mv a2, s0
@@ -44215,15 +43915,15 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: beq a1, s0, .LBB237_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB237_2 Depth=1
-; RV32I-NEXT: sltu a0, s0, a1
+; RV32I-NEXT: sltu a0, a1, s0
; RV32I-NEXT: j .LBB237_5
; RV32I-NEXT: .LBB237_4: # in Loop: Header=BB237_2 Depth=1
-; RV32I-NEXT: sltu a0, s1, a4
+; RV32I-NEXT: sltu a0, a4, s1
; RV32I-NEXT: .LBB237_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: beqz a0, .LBB237_1
+; RV32I-NEXT: bnez a0, .LBB237_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32I-NEXT: mv a2, s1
@@ -44269,15 +43969,15 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-ZALRSC-NEXT: beq a1, s0, .LBB237_4
; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB237_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s0, a1
+; RV32I-ZALRSC-NEXT: sltu a0, a1, s0
; RV32I-ZALRSC-NEXT: j .LBB237_5
; RV32I-ZALRSC-NEXT: .LBB237_4: # in Loop: Header=BB237_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s1, a4
+; RV32I-ZALRSC-NEXT: sltu a0, a4, s1
; RV32I-ZALRSC-NEXT: .LBB237_5: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, a4
; RV32I-ZALRSC-NEXT: mv a3, a1
-; RV32I-ZALRSC-NEXT: beqz a0, .LBB237_1
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB237_1
; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, s1
@@ -44323,15 +44023,15 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: beq a1, s0, .LBB237_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB237_2 Depth=1
-; RV32IA-NEXT: sltu a0, s0, a1
+; RV32IA-NEXT: sltu a0, a1, s0
; RV32IA-NEXT: j .LBB237_5
; RV32IA-NEXT: .LBB237_4: # in Loop: Header=BB237_2 Depth=1
-; RV32IA-NEXT: sltu a0, s1, a4
+; RV32IA-NEXT: sltu a0, a4, s1
; RV32IA-NEXT: .LBB237_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1
-; RV32IA-NEXT: beqz a0, .LBB237_1
+; RV32IA-NEXT: bnez a0, .LBB237_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV32IA-NEXT: mv a2, s1
@@ -44371,7 +44071,7 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: .LBB237_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s0, a1, .LBB237_1
+; RV64I-NEXT: bltu a1, s0, .LBB237_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB237_2 Depth=1
; RV64I-NEXT: mv a2, s0
@@ -44444,15 +44144,15 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: beq a1, s0, .LBB238_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB238_2 Depth=1
-; RV32I-NEXT: sltu a0, s0, a1
+; RV32I-NEXT: sltu a0, a1, s0
; RV32I-NEXT: j .LBB238_5
; RV32I-NEXT: .LBB238_4: # in Loop: Header=BB238_2 Depth=1
-; RV32I-NEXT: sltu a0, s1, a4
+; RV32I-NEXT: sltu a0, a4, s1
; RV32I-NEXT: .LBB238_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: beqz a0, .LBB238_1
+; RV32I-NEXT: bnez a0, .LBB238_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32I-NEXT: mv a2, s1
@@ -44498,15 +44198,15 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-ZALRSC-NEXT: beq a1, s0, .LBB238_4
; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB238_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s0, a1
+; RV32I-ZALRSC-NEXT: sltu a0, a1, s0
; RV32I-ZALRSC-NEXT: j .LBB238_5
; RV32I-ZALRSC-NEXT: .LBB238_4: # in Loop: Header=BB238_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s1, a4
+; RV32I-ZALRSC-NEXT: sltu a0, a4, s1
; RV32I-ZALRSC-NEXT: .LBB238_5: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, a4
; RV32I-ZALRSC-NEXT: mv a3, a1
-; RV32I-ZALRSC-NEXT: beqz a0, .LBB238_1
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB238_1
; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, s1
@@ -44552,15 +44252,15 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: beq a1, s0, .LBB238_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB238_2 Depth=1
-; RV32IA-NEXT: sltu a0, s0, a1
+; RV32IA-NEXT: sltu a0, a1, s0
; RV32IA-NEXT: j .LBB238_5
; RV32IA-NEXT: .LBB238_4: # in Loop: Header=BB238_2 Depth=1
-; RV32IA-NEXT: sltu a0, s1, a4
+; RV32IA-NEXT: sltu a0, a4, s1
; RV32IA-NEXT: .LBB238_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1
-; RV32IA-NEXT: beqz a0, .LBB238_1
+; RV32IA-NEXT: bnez a0, .LBB238_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV32IA-NEXT: mv a2, s1
@@ -44600,7 +44300,7 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: .LBB238_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s0, a1, .LBB238_1
+; RV64I-NEXT: bltu a1, s0, .LBB238_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB238_2 Depth=1
; RV64I-NEXT: mv a2, s0
@@ -44673,15 +44373,15 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: beq a1, s0, .LBB239_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB239_2 Depth=1
-; RV32I-NEXT: sltu a0, s0, a1
+; RV32I-NEXT: sltu a0, a1, s0
; RV32I-NEXT: j .LBB239_5
; RV32I-NEXT: .LBB239_4: # in Loop: Header=BB239_2 Depth=1
-; RV32I-NEXT: sltu a0, s1, a4
+; RV32I-NEXT: sltu a0, a4, s1
; RV32I-NEXT: .LBB239_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: beqz a0, .LBB239_1
+; RV32I-NEXT: bnez a0, .LBB239_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32I-NEXT: mv a2, s1
@@ -44727,15 +44427,15 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-ZALRSC-NEXT: beq a1, s0, .LBB239_4
; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB239_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s0, a1
+; RV32I-ZALRSC-NEXT: sltu a0, a1, s0
; RV32I-ZALRSC-NEXT: j .LBB239_5
; RV32I-ZALRSC-NEXT: .LBB239_4: # in Loop: Header=BB239_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s1, a4
+; RV32I-ZALRSC-NEXT: sltu a0, a4, s1
; RV32I-ZALRSC-NEXT: .LBB239_5: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, a4
; RV32I-ZALRSC-NEXT: mv a3, a1
-; RV32I-ZALRSC-NEXT: beqz a0, .LBB239_1
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB239_1
; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, s1
@@ -44781,15 +44481,15 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: beq a1, s0, .LBB239_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB239_2 Depth=1
-; RV32IA-NEXT: sltu a0, s0, a1
+; RV32IA-NEXT: sltu a0, a1, s0
; RV32IA-NEXT: j .LBB239_5
; RV32IA-NEXT: .LBB239_4: # in Loop: Header=BB239_2 Depth=1
-; RV32IA-NEXT: sltu a0, s1, a4
+; RV32IA-NEXT: sltu a0, a4, s1
; RV32IA-NEXT: .LBB239_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1
-; RV32IA-NEXT: beqz a0, .LBB239_1
+; RV32IA-NEXT: bnez a0, .LBB239_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV32IA-NEXT: mv a2, s1
@@ -44829,7 +44529,7 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: .LBB239_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s0, a1, .LBB239_1
+; RV64I-NEXT: bltu a1, s0, .LBB239_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB239_2 Depth=1
; RV64I-NEXT: mv a2, s0
diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll
index 3b5044113a0ef..e50ce815d2fac 100644
--- a/llvm/test/CodeGen/RISCV/atomic-signext.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll
@@ -902,47 +902,44 @@ define signext i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind {
define signext i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i8_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 24
-; RV32I-NEXT: srai s2, a0, 24
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: srai s1, s1, 24
; RV32I-NEXT: j .LBB10_2
; RV32I-NEXT: .LBB10_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB10_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB10_4
; RV32I-NEXT: .LBB10_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
-; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s2, a0, .LBB10_1
+; RV32I-NEXT: slli a2, a1, 24
+; RV32I-NEXT: srai a2, a2, 24
+; RV32I-NEXT: blt s1, a2, .LBB10_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB10_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB10_1
; RV32I-NEXT: .LBB10_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_max_i8_monotonic:
@@ -1009,47 +1006,44 @@ define signext i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i8_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 56
-; RV64I-NEXT: srai s2, a0, 56
+; RV64I-NEXT: slli s1, s1, 56
+; RV64I-NEXT: srai s1, s1, 56
; RV64I-NEXT: j .LBB10_2
; RV64I-NEXT: .LBB10_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB10_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB10_4
; RV64I-NEXT: .LBB10_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
-; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB10_1
+; RV64I-NEXT: slli a2, a1, 56
+; RV64I-NEXT: srai a2, a2, 56
+; RV64I-NEXT: blt s1, a2, .LBB10_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB10_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB10_1
; RV64I-NEXT: .LBB10_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_max_i8_monotonic:
@@ -1120,47 +1114,44 @@ define signext i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind {
define signext i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i8_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 24
-; RV32I-NEXT: srai s2, a0, 24
+; RV32I-NEXT: slli s1, s1, 24
+; RV32I-NEXT: srai s1, s1, 24
; RV32I-NEXT: j .LBB11_2
; RV32I-NEXT: .LBB11_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB11_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB11_4
; RV32I-NEXT: .LBB11_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 24
-; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s2, a0, .LBB11_1
+; RV32I-NEXT: slli a2, a1, 24
+; RV32I-NEXT: srai a2, a2, 24
+; RV32I-NEXT: blt a2, s1, .LBB11_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB11_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB11_1
; RV32I-NEXT: .LBB11_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_min_i8_monotonic:
@@ -1227,47 +1218,44 @@ define signext i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i8_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 56
-; RV64I-NEXT: srai s2, a0, 56
+; RV64I-NEXT: slli s1, s1, 56
+; RV64I-NEXT: srai s1, s1, 56
; RV64I-NEXT: j .LBB11_2
; RV64I-NEXT: .LBB11_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB11_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB11_4
; RV64I-NEXT: .LBB11_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 56
-; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB11_1
+; RV64I-NEXT: slli a2, a1, 56
+; RV64I-NEXT: srai a2, a2, 56
+; RV64I-NEXT: blt a2, s1, .LBB11_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB11_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB11_1
; RV64I-NEXT: .LBB11_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_min_i8_monotonic:
@@ -1338,45 +1326,42 @@ define signext i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind {
define signext i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umax_i8_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: zext.b s2, s0
+; RV32I-NEXT: zext.b s1, s1
; RV32I-NEXT: j .LBB12_2
; RV32I-NEXT: .LBB12_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB12_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB12_4
; RV32I-NEXT: .LBB12_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: zext.b a0, a1
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu s2, a0, .LBB12_1
+; RV32I-NEXT: zext.b a2, a1
+; RV32I-NEXT: bltu s1, a2, .LBB12_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB12_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB12_1
; RV32I-NEXT: .LBB12_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_umax_i8_monotonic:
@@ -1433,45 +1418,42 @@ define signext i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i8_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: zext.b s2, s0
+; RV64I-NEXT: zext.b s1, s1
; RV64I-NEXT: j .LBB12_2
; RV64I-NEXT: .LBB12_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB12_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB12_4
; RV64I-NEXT: .LBB12_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: zext.b a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s2, a0, .LBB12_1
+; RV64I-NEXT: zext.b a2, a1
+; RV64I-NEXT: bltu s1, a2, .LBB12_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB12_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB12_1
; RV64I-NEXT: .LBB12_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umax_i8_monotonic:
@@ -1532,45 +1514,42 @@ define signext i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind {
define signext i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
; RV32I-LABEL: atomicrmw_umin_i8_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_1
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: zext.b s2, s0
+; RV32I-NEXT: zext.b s1, s1
; RV32I-NEXT: j .LBB13_2
; RV32I-NEXT: .LBB13_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB13_2 Depth=1
-; RV32I-NEXT: sb a1, 15(sp)
-; RV32I-NEXT: addi a1, sp, 15
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sb a1, 3(sp)
+; RV32I-NEXT: addi a1, sp, 3
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_1
-; RV32I-NEXT: lbu a1, 15(sp)
+; RV32I-NEXT: lbu a1, 3(sp)
; RV32I-NEXT: bnez a0, .LBB13_4
; RV32I-NEXT: .LBB13_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: zext.b a0, a1
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s2, a0, .LBB13_1
+; RV32I-NEXT: zext.b a2, a1
+; RV32I-NEXT: bltu a2, s1, .LBB13_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB13_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB13_1
; RV32I-NEXT: .LBB13_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a1, 24
; RV32I-NEXT: srai a0, a0, 24
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_umin_i8_monotonic:
@@ -1627,45 +1606,42 @@ define signext i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i8_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_1
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: zext.b s2, s0
+; RV64I-NEXT: zext.b s1, s1
; RV64I-NEXT: j .LBB13_2
; RV64I-NEXT: .LBB13_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB13_2 Depth=1
-; RV64I-NEXT: sb a1, 15(sp)
-; RV64I-NEXT: addi a1, sp, 15
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sb a1, 7(sp)
+; RV64I-NEXT: addi a1, sp, 7
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_1
-; RV64I-NEXT: lbu a1, 15(sp)
+; RV64I-NEXT: lbu a1, 7(sp)
; RV64I-NEXT: bnez a0, .LBB13_4
; RV64I-NEXT: .LBB13_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: zext.b a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s2, a0, .LBB13_1
+; RV64I-NEXT: zext.b a2, a1
+; RV64I-NEXT: bltu a2, s1, .LBB13_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB13_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB13_1
; RV64I-NEXT: .LBB13_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a1, 56
; RV64I-NEXT: srai a0, a0, 56
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umin_i8_monotonic:
@@ -2496,47 +2472,44 @@ define signext i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind {
define signext i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_max_i16_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 16
-; RV32I-NEXT: srai s2, a0, 16
+; RV32I-NEXT: slli s1, s1, 16
+; RV32I-NEXT: srai s1, s1, 16
; RV32I-NEXT: j .LBB21_2
; RV32I-NEXT: .LBB21_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB21_2 Depth=1
-; RV32I-NEXT: sh a1, 14(sp)
-; RV32I-NEXT: addi a1, sp, 14
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sh a1, 2(sp)
+; RV32I-NEXT: addi a1, sp, 2
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 14(sp)
+; RV32I-NEXT: lh a1, 2(sp)
; RV32I-NEXT: bnez a0, .LBB21_4
; RV32I-NEXT: .LBB21_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
-; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt s2, a0, .LBB21_1
+; RV32I-NEXT: slli a2, a1, 16
+; RV32I-NEXT: srai a2, a2, 16
+; RV32I-NEXT: blt s1, a2, .LBB21_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB21_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB21_1
; RV32I-NEXT: .LBB21_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_max_i16_monotonic:
@@ -2607,47 +2580,44 @@ define signext i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i16_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 48
-; RV64I-NEXT: srai s2, a0, 48
+; RV64I-NEXT: slli s1, s1, 48
+; RV64I-NEXT: srai s1, s1, 48
; RV64I-NEXT: j .LBB21_2
; RV64I-NEXT: .LBB21_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB21_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: addi a1, sp, 14
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB21_4
; RV64I-NEXT: .LBB21_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
-; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB21_1
+; RV64I-NEXT: slli a2, a1, 48
+; RV64I-NEXT: srai a2, a2, 48
+; RV64I-NEXT: blt s1, a2, .LBB21_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB21_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB21_1
; RV64I-NEXT: .LBB21_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_max_i16_monotonic:
@@ -2722,47 +2692,44 @@ define signext i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind {
define signext i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-LABEL: atomicrmw_min_i16_monotonic:
; RV32I: # %bb.0:
-; RV32I-NEXT: addi sp, sp, -32
-; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: slli a0, s0, 16
-; RV32I-NEXT: srai s2, a0, 16
+; RV32I-NEXT: slli s1, s1, 16
+; RV32I-NEXT: srai s1, s1, 16
; RV32I-NEXT: j .LBB22_2
; RV32I-NEXT: .LBB22_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB22_2 Depth=1
-; RV32I-NEXT: sh a1, 14(sp)
-; RV32I-NEXT: addi a1, sp, 14
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sh a1, 2(sp)
+; RV32I-NEXT: addi a1, sp, 2
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 14(sp)
+; RV32I-NEXT: lh a1, 2(sp)
; RV32I-NEXT: bnez a0, .LBB22_4
; RV32I-NEXT: .LBB22_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: slli a0, a1, 16
-; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s2, a0, .LBB22_1
+; RV32I-NEXT: slli a2, a1, 16
+; RV32I-NEXT: srai a2, a2, 16
+; RV32I-NEXT: blt a2, s1, .LBB22_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB22_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB22_1
; RV32I-NEXT: .LBB22_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: srai a0, a0, 16
-; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: addi sp, sp, 32
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IA-LABEL: atomicrmw_min_i16_monotonic:
@@ -2833,47 +2800,44 @@ define signext i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i16_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: slli a0, s0, 48
-; RV64I-NEXT: srai s2, a0, 48
+; RV64I-NEXT: slli s1, s1, 48
+; RV64I-NEXT: srai s1, s1, 48
; RV64I-NEXT: j .LBB22_2
; RV64I-NEXT: .LBB22_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB22_2 Depth=1
-; RV64I-NEXT: sh a1, 14(sp)
-; RV64I-NEXT: addi a1, sp, 14
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sh a1, 6(sp)
+; RV64I-NEXT: addi a1, sp, 6
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 14(sp)
+; RV64I-NEXT: lh a1, 6(sp)
; RV64I-NEXT: bnez a0, .LBB22_4
; RV64I-NEXT: .LBB22_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: slli a0, a1, 48
-; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB22_1
+; RV64I-NEXT: slli a2, a1, 48
+; RV64I-NEXT: srai a2, a2, 48
+; RV64I-NEXT: blt a2, s1, .LBB22_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB22_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB22_1
; RV64I-NEXT: .LBB22_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a1, 48
; RV64I-NEXT: srai a0, a0, 48
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_min_i16_monotonic:
@@ -2953,34 +2917,32 @@ define signext i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui s2, 16
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, s2
+; RV32I-NEXT: and s1, s1, s2
; RV32I-NEXT: j .LBB23_2
; RV32I-NEXT: .LBB23_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB23_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: addi a1, sp, 10
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sh a1, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a1, 14(sp)
; RV32I-NEXT: bnez a0, .LBB23_4
; RV32I-NEXT: .LBB23_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: and a0, a1, s2
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu s3, a0, .LBB23_1
+; RV32I-NEXT: and a2, a1, s2
+; RV32I-NEXT: bltu s1, a2, .LBB23_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB23_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB23_1
; RV32I-NEXT: .LBB23_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a1, 16
@@ -2989,7 +2951,6 @@ define signext i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
@@ -3054,34 +3015,32 @@ define signext i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: and s3, s0, s2
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: j .LBB23_2
; RV64I-NEXT: .LBB23_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB23_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: addi a1, sp, 6
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: bnez a0, .LBB23_4
; RV64I-NEXT: .LBB23_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: and a0, a1, s2
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s3, a0, .LBB23_1
+; RV64I-NEXT: and a2, a1, s2
+; RV64I-NEXT: bltu s1, a2, .LBB23_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB23_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB23_1
; RV64I-NEXT: .LBB23_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a1, 48
@@ -3090,7 +3049,6 @@ define signext i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
@@ -3159,34 +3117,32 @@ define signext i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
-; RV32I-NEXT: mv s0, a1
-; RV32I-NEXT: mv s1, a0
+; RV32I-NEXT: mv s1, a1
+; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_2
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: lui s2, 16
; RV32I-NEXT: addi s2, s2, -1
-; RV32I-NEXT: and s3, s0, s2
+; RV32I-NEXT: and s1, s1, s2
; RV32I-NEXT: j .LBB24_2
; RV32I-NEXT: .LBB24_1: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB24_2 Depth=1
-; RV32I-NEXT: sh a1, 10(sp)
-; RV32I-NEXT: addi a1, sp, 10
-; RV32I-NEXT: mv a0, s1
+; RV32I-NEXT: sh a1, 14(sp)
+; RV32I-NEXT: addi a1, sp, 14
+; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_2
-; RV32I-NEXT: lh a1, 10(sp)
+; RV32I-NEXT: lh a1, 14(sp)
; RV32I-NEXT: bnez a0, .LBB24_4
; RV32I-NEXT: .LBB24_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32I-NEXT: and a0, a1, s2
-; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s3, a0, .LBB24_1
+; RV32I-NEXT: and a2, a1, s2
+; RV32I-NEXT: bltu a2, s1, .LBB24_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB24_2 Depth=1
-; RV32I-NEXT: mv a2, s0
+; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: j .LBB24_1
; RV32I-NEXT: .LBB24_4: # %atomicrmw.end
; RV32I-NEXT: slli a0, a1, 16
@@ -3195,7 +3151,6 @@ define signext i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
@@ -3260,34 +3215,32 @@ define signext i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_2
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: lui s2, 16
; RV64I-NEXT: addi s2, s2, -1
-; RV64I-NEXT: and s3, s0, s2
+; RV64I-NEXT: and s1, s1, s2
; RV64I-NEXT: j .LBB24_2
; RV64I-NEXT: .LBB24_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB24_2 Depth=1
-; RV64I-NEXT: sh a1, 6(sp)
-; RV64I-NEXT: addi a1, sp, 6
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sh a1, 14(sp)
+; RV64I-NEXT: addi a1, sp, 14
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_2
-; RV64I-NEXT: lh a1, 6(sp)
+; RV64I-NEXT: lh a1, 14(sp)
; RV64I-NEXT: bnez a0, .LBB24_4
; RV64I-NEXT: .LBB24_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: and a0, a1, s2
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s3, a0, .LBB24_1
+; RV64I-NEXT: and a2, a1, s2
+; RV64I-NEXT: bltu a2, s1, .LBB24_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB24_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB24_1
; RV64I-NEXT: .LBB24_4: # %atomicrmw.end
; RV64I-NEXT: slli a0, a1, 48
@@ -3296,7 +3249,6 @@ define signext i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind {
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
@@ -3863,44 +3815,41 @@ define signext i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_max_i32_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB32_2
; RV64I-NEXT: .LBB32_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB32_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB32_4
; RV64I-NEXT: .LBB32_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt s2, a0, .LBB32_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: blt s1, a2, .LBB32_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB32_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB32_1
; RV64I-NEXT: .LBB32_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_max_i32_monotonic:
@@ -3953,7 +3902,7 @@ define signext i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: .LBB33_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bge s0, a1, .LBB33_1
+; RV32I-NEXT: blt a1, s0, .LBB33_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB33_2 Depth=1
; RV32I-NEXT: mv a2, s0
@@ -3988,44 +3937,41 @@ define signext i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_min_i32_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB33_2
; RV64I-NEXT: .LBB33_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB33_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB33_4
; RV64I-NEXT: .LBB33_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s2, a0, .LBB33_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: blt a2, s1, .LBB33_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB33_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB33_1
; RV64I-NEXT: .LBB33_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_min_i32_monotonic:
@@ -4113,44 +4059,41 @@ define signext i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umax_i32_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB34_2
; RV64I-NEXT: .LBB34_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB34_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB34_4
; RV64I-NEXT: .LBB34_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu s2, a0, .LBB34_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: bltu s1, a2, .LBB34_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB34_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB34_1
; RV64I-NEXT: .LBB34_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umax_i32_monotonic:
@@ -4203,7 +4146,7 @@ define signext i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind {
; RV32I-NEXT: .LBB35_2: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bgeu s0, a1, .LBB35_1
+; RV32I-NEXT: bltu a1, s0, .LBB35_1
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB35_2 Depth=1
; RV32I-NEXT: mv a2, s0
@@ -4238,44 +4181,41 @@ define signext i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind {
;
; RV64I-LABEL: atomicrmw_umin_i32_monotonic:
; RV64I: # %bb.0:
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: mv s0, a1
-; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s1, a1
+; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: sext.w s2, s0
+; RV64I-NEXT: sext.w s1, s1
; RV64I-NEXT: j .LBB35_2
; RV64I-NEXT: .LBB35_1: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
-; RV64I-NEXT: sw a1, 12(sp)
-; RV64I-NEXT: addi a1, sp, 12
-; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: sw a1, 4(sp)
+; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 12(sp)
+; RV64I-NEXT: lw a1, 4(sp)
; RV64I-NEXT: bnez a0, .LBB35_4
; RV64I-NEXT: .LBB35_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s2, a0, .LBB35_1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: bltu a2, s1, .LBB35_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB35_2 Depth=1
-; RV64I-NEXT: mv a2, s0
+; RV64I-NEXT: mv a2, s1
; RV64I-NEXT: j .LBB35_1
; RV64I-NEXT: .LBB35_4: # %atomicrmw.end
; RV64I-NEXT: mv a0, a1
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64IA-LABEL: atomicrmw_umin_i32_monotonic:
@@ -5001,15 +4941,15 @@ define signext i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: beq a1, s0, .LBB44_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
-; RV32I-NEXT: slt a0, s0, a1
+; RV32I-NEXT: slt a0, a1, s0
; RV32I-NEXT: j .LBB44_5
; RV32I-NEXT: .LBB44_4: # in Loop: Header=BB44_2 Depth=1
-; RV32I-NEXT: sltu a0, s1, a4
+; RV32I-NEXT: sltu a0, a4, s1
; RV32I-NEXT: .LBB44_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: beqz a0, .LBB44_1
+; RV32I-NEXT: bnez a0, .LBB44_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: mv a2, s1
@@ -5055,15 +4995,15 @@ define signext i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: beq a1, s0, .LBB44_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1
-; RV32IA-NEXT: slt a0, s0, a1
+; RV32IA-NEXT: slt a0, a1, s0
; RV32IA-NEXT: j .LBB44_5
; RV32IA-NEXT: .LBB44_4: # in Loop: Header=BB44_2 Depth=1
-; RV32IA-NEXT: sltu a0, s1, a4
+; RV32IA-NEXT: sltu a0, a4, s1
; RV32IA-NEXT: .LBB44_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1
-; RV32IA-NEXT: beqz a0, .LBB44_1
+; RV32IA-NEXT: bnez a0, .LBB44_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32IA-NEXT: mv a2, s1
@@ -5109,15 +5049,15 @@ define signext i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-ZALRSC-NEXT: beq a1, s0, .LBB44_4
; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB44_2 Depth=1
-; RV32I-ZALRSC-NEXT: slt a0, s0, a1
+; RV32I-ZALRSC-NEXT: slt a0, a1, s0
; RV32I-ZALRSC-NEXT: j .LBB44_5
; RV32I-ZALRSC-NEXT: .LBB44_4: # in Loop: Header=BB44_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s1, a4
+; RV32I-ZALRSC-NEXT: sltu a0, a4, s1
; RV32I-ZALRSC-NEXT: .LBB44_5: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, a4
; RV32I-ZALRSC-NEXT: mv a3, a1
-; RV32I-ZALRSC-NEXT: beqz a0, .LBB44_1
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB44_1
; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, s1
@@ -5157,7 +5097,7 @@ define signext i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: .LBB44_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bge s0, a1, .LBB44_1
+; RV64I-NEXT: blt a1, s0, .LBB44_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV64I-NEXT: mv a2, s0
@@ -5449,15 +5389,15 @@ define signext i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: beq a1, s0, .LBB46_4
; RV32I-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
-; RV32I-NEXT: sltu a0, s0, a1
+; RV32I-NEXT: sltu a0, a1, s0
; RV32I-NEXT: j .LBB46_5
; RV32I-NEXT: .LBB46_4: # in Loop: Header=BB46_2 Depth=1
-; RV32I-NEXT: sltu a0, s1, a4
+; RV32I-NEXT: sltu a0, a4, s1
; RV32I-NEXT: .LBB46_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a1
-; RV32I-NEXT: beqz a0, .LBB46_1
+; RV32I-NEXT: bnez a0, .LBB46_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: mv a2, s1
@@ -5503,15 +5443,15 @@ define signext i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: beq a1, s0, .LBB46_4
; RV32IA-NEXT: # %bb.3: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1
-; RV32IA-NEXT: sltu a0, s0, a1
+; RV32IA-NEXT: sltu a0, a1, s0
; RV32IA-NEXT: j .LBB46_5
; RV32IA-NEXT: .LBB46_4: # in Loop: Header=BB46_2 Depth=1
-; RV32IA-NEXT: sltu a0, s1, a4
+; RV32IA-NEXT: sltu a0, a4, s1
; RV32IA-NEXT: .LBB46_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a1
-; RV32IA-NEXT: beqz a0, .LBB46_1
+; RV32IA-NEXT: bnez a0, .LBB46_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32IA-NEXT: mv a2, s1
@@ -5557,15 +5497,15 @@ define signext i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-ZALRSC-NEXT: beq a1, s0, .LBB46_4
; RV32I-ZALRSC-NEXT: # %bb.3: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB46_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s0, a1
+; RV32I-ZALRSC-NEXT: sltu a0, a1, s0
; RV32I-ZALRSC-NEXT: j .LBB46_5
; RV32I-ZALRSC-NEXT: .LBB46_4: # in Loop: Header=BB46_2 Depth=1
-; RV32I-ZALRSC-NEXT: sltu a0, s1, a4
+; RV32I-ZALRSC-NEXT: sltu a0, a4, s1
; RV32I-ZALRSC-NEXT: .LBB46_5: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, a4
; RV32I-ZALRSC-NEXT: mv a3, a1
-; RV32I-ZALRSC-NEXT: beqz a0, .LBB46_1
+; RV32I-ZALRSC-NEXT: bnez a0, .LBB46_1
; RV32I-ZALRSC-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-ZALRSC-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-ZALRSC-NEXT: mv a2, s1
@@ -5605,7 +5545,7 @@ define signext i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV64I-NEXT: .LBB46_2: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bgeu s0, a1, .LBB46_1
+; RV64I-NEXT: bltu a1, s0, .LBB46_1
; RV64I-NEXT: # %bb.3: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV64I-NEXT: mv a2, s0
@@ -7486,10 +7426,8 @@ define signext i32 @atomicrmw_max_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: bnez a0, .LBB60_8
; RV64I-NEXT: .LBB60_3: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: li a3, 1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt a3, a0, .LBB60_2
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: bgtz a2, .LBB60_2
; RV64I-NEXT: # %bb.4: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB60_3 Depth=1
; RV64I-NEXT: li a2, 1
@@ -7581,7 +7519,6 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a1, a1, 1
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: beqz a1, .LBB61_5
@@ -7590,22 +7527,21 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_4
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: li s1, 2
; RV32I-NEXT: j .LBB61_3
; RV32I-NEXT: .LBB61_2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB61_3 Depth=1
-; RV32I-NEXT: sw a1, 0(sp)
-; RV32I-NEXT: mv a1, sp
+; RV32I-NEXT: sw a1, 4(sp)
+; RV32I-NEXT: addi a1, sp, 4
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a1, 0(sp)
+; RV32I-NEXT: lw a1, 4(sp)
; RV32I-NEXT: bnez a0, .LBB61_8
; RV32I-NEXT: .LBB61_3: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: blt a1, s1, .LBB61_2
+; RV32I-NEXT: blez a1, .LBB61_2
; RV32I-NEXT: # %bb.4: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB61_3 Depth=1
; RV32I-NEXT: li a2, 1
@@ -7622,7 +7558,6 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
@@ -7681,7 +7616,6 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: andi a1, a1, 1
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: beqz a1, .LBB61_5
@@ -7690,23 +7624,21 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: li s1, 2
; RV64I-NEXT: j .LBB61_3
; RV64I-NEXT: .LBB61_2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB61_3 Depth=1
-; RV64I-NEXT: sw a1, 4(sp)
-; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: sw a1, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 4(sp)
+; RV64I-NEXT: lw a1, 12(sp)
; RV64I-NEXT: bnez a0, .LBB61_8
; RV64I-NEXT: .LBB61_3: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: blt a0, s1, .LBB61_2
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: blez a2, .LBB61_2
; RV64I-NEXT: # %bb.4: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB61_3 Depth=1
; RV64I-NEXT: li a2, 1
@@ -7723,7 +7655,6 @@ define signext i32 @atomicrmw_min_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
@@ -7883,15 +7814,17 @@ define signext i32 @atomicrmw_umax_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: andi a1, a1, 1
; RV64I-NEXT: mv s0, a0
-; RV64I-NEXT: beqz a1, .LBB62_5
+; RV64I-NEXT: beqz a1, .LBB62_3
; RV64I-NEXT: # %bb.1: # %then
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: j .LBB62_3
; RV64I-NEXT: .LBB62_2: # %atomicrmw.start
-; RV64I-NEXT: # in Loop: Header=BB62_3 Depth=1
+; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: seqz a0, a2
+; RV64I-NEXT: add a2, a2, a0
; RV64I-NEXT: sw a1, 12(sp)
; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0
@@ -7899,23 +7832,14 @@ define signext i32 @atomicrmw_umax_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
; RV64I-NEXT: lw a1, 12(sp)
-; RV64I-NEXT: bnez a0, .LBB62_6
-; RV64I-NEXT: .LBB62_3: # %atomicrmw.start
-; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: li a3, 1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu a3, a0, .LBB62_2
-; RV64I-NEXT: # %bb.4: # %atomicrmw.start
-; RV64I-NEXT: # in Loop: Header=BB62_3 Depth=1
-; RV64I-NEXT: li a2, 1
-; RV64I-NEXT: j .LBB62_2
-; RV64I-NEXT: .LBB62_5: # %else
+; RV64I-NEXT: beqz a0, .LBB62_2
+; RV64I-NEXT: j .LBB62_4
+; RV64I-NEXT: .LBB62_3: # %else
; RV64I-NEXT: lw a1, 0(s0)
; RV64I-NEXT: seqz a0, a1
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: sw a0, 0(s0)
-; RV64I-NEXT: .LBB62_6: # %merge
+; RV64I-NEXT: .LBB62_4: # %merge
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@@ -7989,7 +7913,6 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a1, a1, 1
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: beqz a1, .LBB63_5
@@ -7998,22 +7921,22 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __atomic_load_4
; RV32I-NEXT: mv a1, a0
-; RV32I-NEXT: li s1, 2
; RV32I-NEXT: j .LBB63_3
; RV32I-NEXT: .LBB63_2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB63_3 Depth=1
-; RV32I-NEXT: sw a1, 0(sp)
-; RV32I-NEXT: mv a1, sp
+; RV32I-NEXT: sw a1, 4(sp)
+; RV32I-NEXT: addi a1, sp, 4
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: li a4, 0
; RV32I-NEXT: call __atomic_compare_exchange_4
-; RV32I-NEXT: lw a1, 0(sp)
+; RV32I-NEXT: lw a1, 4(sp)
; RV32I-NEXT: bnez a0, .LBB63_8
; RV32I-NEXT: .LBB63_3: # %atomicrmw.start
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32I-NEXT: li a0, 1
; RV32I-NEXT: mv a2, a1
-; RV32I-NEXT: bltu a1, s1, .LBB63_2
+; RV32I-NEXT: bltu a1, a0, .LBB63_2
; RV32I-NEXT: # %bb.4: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB63_3 Depth=1
; RV32I-NEXT: li a2, 1
@@ -8031,7 +7954,6 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
@@ -8092,7 +8014,6 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: andi a1, a1, 1
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: beqz a1, .LBB63_5
@@ -8101,23 +8022,22 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __atomic_load_4
; RV64I-NEXT: mv a1, a0
-; RV64I-NEXT: li s1, 2
; RV64I-NEXT: j .LBB63_3
; RV64I-NEXT: .LBB63_2: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB63_3 Depth=1
-; RV64I-NEXT: sw a1, 4(sp)
-; RV64I-NEXT: addi a1, sp, 4
+; RV64I-NEXT: sw a1, 12(sp)
+; RV64I-NEXT: addi a1, sp, 12
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: li a3, 0
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call __atomic_compare_exchange_4
-; RV64I-NEXT: lw a1, 4(sp)
+; RV64I-NEXT: lw a1, 12(sp)
; RV64I-NEXT: bnez a0, .LBB63_8
; RV64I-NEXT: .LBB63_3: # %atomicrmw.start
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64I-NEXT: sext.w a0, a1
-; RV64I-NEXT: mv a2, a1
-; RV64I-NEXT: bltu a0, s1, .LBB63_2
+; RV64I-NEXT: sext.w a2, a1
+; RV64I-NEXT: li a0, 1
+; RV64I-NEXT: bltu a2, a0, .LBB63_2
; RV64I-NEXT: # %bb.4: # %atomicrmw.start
; RV64I-NEXT: # in Loop: Header=BB63_3 Depth=1
; RV64I-NEXT: li a2, 1
@@ -8135,7 +8055,6 @@ define signext i32 @atomicrmw_umin_i32_monotonic_crossbb(ptr %a, i1 %c) nounwind
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/compress.ll b/llvm/test/CodeGen/RISCV/compress.ll
index c8803773d7630..9dcc5b2f79f90 100644
--- a/llvm/test/CodeGen/RISCV/compress.ll
+++ b/llvm/test/CodeGen/RISCV/compress.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; This test is designed to run twice, once with function attributes and once
; with target attributes added on the command line.
;
@@ -59,25 +60,25 @@ define i32 @select(i32 %a, ptr %b) #0 {
; RV32IC-NEXT: bltu a2, a0, 0x26
; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a2, 0x0(a1)
-; RV32IC-NEXT: bgeu a0, a2, 0x2e
+; RV32IC-NEXT: bltu a2, a0, 0x2e
; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a2, 0x0(a1)
; RV32IC-NEXT: bltu a0, a2, 0x36
; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a2, 0x0(a1)
-; RV32IC-NEXT: bgeu a2, a0, 0x3e
+; RV32IC-NEXT: bltu a0, a2, 0x3e
; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a2, 0x0(a1)
; RV32IC-NEXT: blt a2, a0, 0x46
; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a2, 0x0(a1)
-; RV32IC-NEXT: bge a0, a2, 0x4e
+; RV32IC-NEXT: blt a2, a0, 0x4e
; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a2, 0x0(a1)
; RV32IC-NEXT: blt a0, a2, 0x56
; RV32IC-NEXT: c.mv a0, a2
; RV32IC-NEXT: c.lw a1, 0x0(a1)
-; RV32IC-NEXT: bge a1, a0, 0x5e
+; RV32IC-NEXT: blt a0, a1, 0x5e
; RV32IC-NEXT: c.mv a0, a1
; RV32IC-NEXT: c.jr ra
%val1 = load volatile i32, ptr %b
diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll
index 7821728aae46a..74edd1ec97982 100644
--- a/llvm/test/CodeGen/RISCV/forced-atomics.ll
+++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll
@@ -1428,10 +1428,8 @@ define i32 @rmw32_max_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB23_4
; RV64-NO-ATOMIC-NEXT: .LBB23_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64-NO-ATOMIC-NEXT: sext.w a0, a1
-; RV64-NO-ATOMIC-NEXT: li a3, 1
-; RV64-NO-ATOMIC-NEXT: mv a2, a1
-; RV64-NO-ATOMIC-NEXT: blt a3, a0, .LBB23_1
+; RV64-NO-ATOMIC-NEXT: sext.w a2, a1
+; RV64-NO-ATOMIC-NEXT: bgtz a2, .LBB23_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB23_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1
@@ -1472,27 +1470,25 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind {
; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16
; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32-NO-ATOMIC-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: mv s0, a0
; RV32-NO-ATOMIC-NEXT: li a1, 0
; RV32-NO-ATOMIC-NEXT: call __atomic_load_4
; RV32-NO-ATOMIC-NEXT: mv a1, a0
-; RV32-NO-ATOMIC-NEXT: li s1, 2
; RV32-NO-ATOMIC-NEXT: j .LBB24_2
; RV32-NO-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1
-; RV32-NO-ATOMIC-NEXT: sw a1, 0(sp)
-; RV32-NO-ATOMIC-NEXT: mv a1, sp
+; RV32-NO-ATOMIC-NEXT: sw a1, 4(sp)
+; RV32-NO-ATOMIC-NEXT: addi a1, sp, 4
; RV32-NO-ATOMIC-NEXT: li a3, 5
; RV32-NO-ATOMIC-NEXT: li a4, 5
; RV32-NO-ATOMIC-NEXT: mv a0, s0
; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4
-; RV32-NO-ATOMIC-NEXT: lw a1, 0(sp)
+; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp)
; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB24_4
; RV32-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV32-NO-ATOMIC-NEXT: mv a2, a1
-; RV32-NO-ATOMIC-NEXT: blt a1, s1, .LBB24_1
+; RV32-NO-ATOMIC-NEXT: blez a1, .LBB24_1
; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV32-NO-ATOMIC-NEXT: li a2, 1
@@ -1501,7 +1497,6 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind {
; RV32-NO-ATOMIC-NEXT: mv a0, a1
; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32-NO-ATOMIC-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16
; RV32-NO-ATOMIC-NEXT: ret
;
@@ -1530,28 +1525,25 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32
; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: mv s0, a0
; RV64-NO-ATOMIC-NEXT: li a1, 0
; RV64-NO-ATOMIC-NEXT: call __atomic_load_4
; RV64-NO-ATOMIC-NEXT: mv a1, a0
-; RV64-NO-ATOMIC-NEXT: li s1, 2
; RV64-NO-ATOMIC-NEXT: j .LBB24_2
; RV64-NO-ATOMIC-NEXT: .LBB24_1: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1
-; RV64-NO-ATOMIC-NEXT: sw a1, 4(sp)
-; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4
+; RV64-NO-ATOMIC-NEXT: sw a1, 12(sp)
+; RV64-NO-ATOMIC-NEXT: addi a1, sp, 12
; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4
-; RV64-NO-ATOMIC-NEXT: lw a1, 4(sp)
+; RV64-NO-ATOMIC-NEXT: lw a1, 12(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB24_4
; RV64-NO-ATOMIC-NEXT: .LBB24_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64-NO-ATOMIC-NEXT: sext.w a0, a1
-; RV64-NO-ATOMIC-NEXT: mv a2, a1
-; RV64-NO-ATOMIC-NEXT: blt a0, s1, .LBB24_1
+; RV64-NO-ATOMIC-NEXT: sext.w a2, a1
+; RV64-NO-ATOMIC-NEXT: blez a2, .LBB24_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB24_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1
@@ -1560,7 +1552,6 @@ define i32 @rmw32_min_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32
; RV64-NO-ATOMIC-NEXT: ret
;
@@ -1645,9 +1636,11 @@ define i32 @rmw32_umax_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: li a1, 0
; RV64-NO-ATOMIC-NEXT: call __atomic_load_4
; RV64-NO-ATOMIC-NEXT: mv a1, a0
-; RV64-NO-ATOMIC-NEXT: j .LBB25_2
; RV64-NO-ATOMIC-NEXT: .LBB25_1: # %atomicrmw.start
-; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB25_2 Depth=1
+; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64-NO-ATOMIC-NEXT: sext.w a2, a1
+; RV64-NO-ATOMIC-NEXT: seqz a0, a2
+; RV64-NO-ATOMIC-NEXT: add a2, a2, a0
; RV64-NO-ATOMIC-NEXT: sw a1, 12(sp)
; RV64-NO-ATOMIC-NEXT: addi a1, sp, 12
; RV64-NO-ATOMIC-NEXT: li a3, 5
@@ -1655,18 +1648,8 @@ define i32 @rmw32_umax_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4
; RV64-NO-ATOMIC-NEXT: lw a1, 12(sp)
-; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB25_4
-; RV64-NO-ATOMIC-NEXT: .LBB25_2: # %atomicrmw.start
-; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64-NO-ATOMIC-NEXT: sext.w a0, a1
-; RV64-NO-ATOMIC-NEXT: li a3, 1
-; RV64-NO-ATOMIC-NEXT: mv a2, a1
-; RV64-NO-ATOMIC-NEXT: bltu a3, a0, .LBB25_1
-; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
-; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB25_2 Depth=1
-; RV64-NO-ATOMIC-NEXT: li a2, 1
-; RV64-NO-ATOMIC-NEXT: j .LBB25_1
-; RV64-NO-ATOMIC-NEXT: .LBB25_4: # %atomicrmw.end
+; RV64-NO-ATOMIC-NEXT: beqz a0, .LBB25_1
+; RV64-NO-ATOMIC-NEXT: # %bb.2: # %atomicrmw.end
; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
@@ -1702,27 +1685,26 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind {
; RV32-NO-ATOMIC-NEXT: addi sp, sp, -16
; RV32-NO-ATOMIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
-; RV32-NO-ATOMIC-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32-NO-ATOMIC-NEXT: mv s0, a0
; RV32-NO-ATOMIC-NEXT: li a1, 0
; RV32-NO-ATOMIC-NEXT: call __atomic_load_4
; RV32-NO-ATOMIC-NEXT: mv a1, a0
-; RV32-NO-ATOMIC-NEXT: li s1, 2
; RV32-NO-ATOMIC-NEXT: j .LBB26_2
; RV32-NO-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1
-; RV32-NO-ATOMIC-NEXT: sw a1, 0(sp)
-; RV32-NO-ATOMIC-NEXT: mv a1, sp
+; RV32-NO-ATOMIC-NEXT: sw a1, 4(sp)
+; RV32-NO-ATOMIC-NEXT: addi a1, sp, 4
; RV32-NO-ATOMIC-NEXT: li a3, 5
; RV32-NO-ATOMIC-NEXT: li a4, 5
; RV32-NO-ATOMIC-NEXT: mv a0, s0
; RV32-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4
-; RV32-NO-ATOMIC-NEXT: lw a1, 0(sp)
+; RV32-NO-ATOMIC-NEXT: lw a1, 4(sp)
; RV32-NO-ATOMIC-NEXT: bnez a0, .LBB26_4
; RV32-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV32-NO-ATOMIC-NEXT: li a0, 1
; RV32-NO-ATOMIC-NEXT: mv a2, a1
-; RV32-NO-ATOMIC-NEXT: bltu a1, s1, .LBB26_1
+; RV32-NO-ATOMIC-NEXT: bltu a1, a0, .LBB26_1
; RV32-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1
; RV32-NO-ATOMIC-NEXT: li a2, 1
@@ -1731,7 +1713,6 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind {
; RV32-NO-ATOMIC-NEXT: mv a0, a1
; RV32-NO-ATOMIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
-; RV32-NO-ATOMIC-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32-NO-ATOMIC-NEXT: addi sp, sp, 16
; RV32-NO-ATOMIC-NEXT: ret
;
@@ -1760,28 +1741,26 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32
; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: mv s0, a0
; RV64-NO-ATOMIC-NEXT: li a1, 0
; RV64-NO-ATOMIC-NEXT: call __atomic_load_4
; RV64-NO-ATOMIC-NEXT: mv a1, a0
-; RV64-NO-ATOMIC-NEXT: li s1, 2
; RV64-NO-ATOMIC-NEXT: j .LBB26_2
; RV64-NO-ATOMIC-NEXT: .LBB26_1: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1
-; RV64-NO-ATOMIC-NEXT: sw a1, 4(sp)
-; RV64-NO-ATOMIC-NEXT: addi a1, sp, 4
+; RV64-NO-ATOMIC-NEXT: sw a1, 12(sp)
+; RV64-NO-ATOMIC-NEXT: addi a1, sp, 12
; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_4
-; RV64-NO-ATOMIC-NEXT: lw a1, 4(sp)
+; RV64-NO-ATOMIC-NEXT: lw a1, 12(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB26_4
; RV64-NO-ATOMIC-NEXT: .LBB26_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
-; RV64-NO-ATOMIC-NEXT: sext.w a0, a1
-; RV64-NO-ATOMIC-NEXT: mv a2, a1
-; RV64-NO-ATOMIC-NEXT: bltu a0, s1, .LBB26_1
+; RV64-NO-ATOMIC-NEXT: sext.w a2, a1
+; RV64-NO-ATOMIC-NEXT: li a0, 1
+; RV64-NO-ATOMIC-NEXT: bltu a2, a0, .LBB26_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB26_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1
@@ -1790,7 +1769,6 @@ define i32 @rmw32_umin_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32
; RV64-NO-ATOMIC-NEXT: ret
;
@@ -3520,7 +3498,7 @@ define i64 @rmw64_min_seq_cst(ptr %p) nounwind {
; RV32-NEXT: bnez a0, .LBB50_1
; RV32-NEXT: j .LBB50_5
; RV32-NEXT: .LBB50_4: # in Loop: Header=BB50_2 Depth=1
-; RV32-NEXT: sltiu a0, a4, 2
+; RV32-NEXT: seqz a0, a4
; RV32-NEXT: mv a2, a4
; RV32-NEXT: bnez a0, .LBB50_1
; RV32-NEXT: .LBB50_5: # %atomicrmw.start
@@ -3539,27 +3517,25 @@ define i64 @rmw64_min_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32
; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: mv s0, a0
; RV64-NO-ATOMIC-NEXT: li a1, 0
; RV64-NO-ATOMIC-NEXT: call __atomic_load_8
; RV64-NO-ATOMIC-NEXT: mv a1, a0
-; RV64-NO-ATOMIC-NEXT: li s1, 2
; RV64-NO-ATOMIC-NEXT: j .LBB50_2
; RV64-NO-ATOMIC-NEXT: .LBB50_1: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1
-; RV64-NO-ATOMIC-NEXT: sd a1, 0(sp)
-; RV64-NO-ATOMIC-NEXT: mv a1, sp
+; RV64-NO-ATOMIC-NEXT: sd a1, 8(sp)
+; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8
; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8
-; RV64-NO-ATOMIC-NEXT: ld a1, 0(sp)
+; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB50_4
; RV64-NO-ATOMIC-NEXT: .LBB50_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
; RV64-NO-ATOMIC-NEXT: mv a2, a1
-; RV64-NO-ATOMIC-NEXT: blt a1, s1, .LBB50_1
+; RV64-NO-ATOMIC-NEXT: blez a1, .LBB50_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB50_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1
@@ -3568,7 +3544,6 @@ define i64 @rmw64_min_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32
; RV64-NO-ATOMIC-NEXT: ret
;
@@ -3605,35 +3580,37 @@ define i64 @rmw64_umax_seq_cst(ptr %p) nounwind {
; RV32-NEXT: li a1, 0
; RV32-NEXT: call __atomic_load_8
; RV32-NEXT: mv a4, a0
+; RV32-NEXT: mv a3, a1
; RV32-NEXT: j .LBB51_2
; RV32-NEXT: .LBB51_1: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB51_2 Depth=1
-; RV32-NEXT: neg a3, a0
-; RV32-NEXT: and a3, a3, a1
; RV32-NEXT: sw a4, 0(sp)
-; RV32-NEXT: sw a1, 4(sp)
+; RV32-NEXT: sw a3, 4(sp)
; RV32-NEXT: mv a1, sp
; RV32-NEXT: li a4, 5
; RV32-NEXT: li a5, 5
; RV32-NEXT: mv a0, s0
; RV32-NEXT: call __atomic_compare_exchange_8
; RV32-NEXT: lw a4, 0(sp)
-; RV32-NEXT: lw a1, 4(sp)
-; RV32-NEXT: bnez a0, .LBB51_4
+; RV32-NEXT: lw a3, 4(sp)
+; RV32-NEXT: bnez a0, .LBB51_6
; RV32-NEXT: .LBB51_2: # %atomicrmw.start
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32-NEXT: snez a0, a1
-; RV32-NEXT: sltiu a2, a4, 2
-; RV32-NEXT: xori a2, a2, 1
-; RV32-NEXT: or a0, a2, a0
; RV32-NEXT: mv a2, a4
-; RV32-NEXT: bnez a0, .LBB51_1
+; RV32-NEXT: bnez a3, .LBB51_4
; RV32-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB51_2 Depth=1
; RV32-NEXT: li a2, 1
+; RV32-NEXT: .LBB51_4: # %atomicrmw.start
+; RV32-NEXT: # in Loop: Header=BB51_2 Depth=1
+; RV32-NEXT: bnez a3, .LBB51_1
+; RV32-NEXT: # %bb.5: # in Loop: Header=BB51_2 Depth=1
+; RV32-NEXT: seqz a2, a4
+; RV32-NEXT: add a2, a4, a2
; RV32-NEXT: j .LBB51_1
-; RV32-NEXT: .LBB51_4: # %atomicrmw.end
+; RV32-NEXT: .LBB51_6: # %atomicrmw.end
; RV32-NEXT: mv a0, a4
+; RV32-NEXT: mv a1, a3
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
@@ -3699,35 +3676,34 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind {
; RV32-NEXT: mv s0, a0
; RV32-NEXT: li a1, 0
; RV32-NEXT: call __atomic_load_8
-; RV32-NEXT: mv a4, a0
+; RV32-NEXT: mv a3, a0
; RV32-NEXT: j .LBB52_2
; RV32-NEXT: .LBB52_1: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1
-; RV32-NEXT: neg a3, a0
-; RV32-NEXT: and a3, a3, a1
-; RV32-NEXT: sw a4, 0(sp)
+; RV32-NEXT: sw a3, 0(sp)
; RV32-NEXT: sw a1, 4(sp)
; RV32-NEXT: mv a1, sp
; RV32-NEXT: li a4, 5
; RV32-NEXT: li a5, 5
; RV32-NEXT: mv a0, s0
+; RV32-NEXT: li a3, 0
; RV32-NEXT: call __atomic_compare_exchange_8
-; RV32-NEXT: lw a4, 0(sp)
+; RV32-NEXT: lw a3, 0(sp)
; RV32-NEXT: lw a1, 4(sp)
; RV32-NEXT: bnez a0, .LBB52_4
; RV32-NEXT: .LBB52_2: # %atomicrmw.start
; RV32-NEXT: # =>This Inner Loop Header: Depth=1
-; RV32-NEXT: sltiu a0, a4, 2
-; RV32-NEXT: seqz a2, a1
-; RV32-NEXT: and a0, a2, a0
-; RV32-NEXT: mv a2, a4
-; RV32-NEXT: bnez a0, .LBB52_1
+; RV32-NEXT: seqz a0, a1
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: or a2, a0, a3
+; RV32-NEXT: li a0, 1
+; RV32-NEXT: bltu a2, a0, .LBB52_1
; RV32-NEXT: # %bb.3: # %atomicrmw.start
; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV32-NEXT: li a2, 1
; RV32-NEXT: j .LBB52_1
; RV32-NEXT: .LBB52_4: # %atomicrmw.end
-; RV32-NEXT: mv a0, a4
+; RV32-NEXT: mv a0, a3
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
@@ -3738,27 +3714,26 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: addi sp, sp, -32
; RV64-NO-ATOMIC-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
-; RV64-NO-ATOMIC-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64-NO-ATOMIC-NEXT: mv s0, a0
; RV64-NO-ATOMIC-NEXT: li a1, 0
; RV64-NO-ATOMIC-NEXT: call __atomic_load_8
; RV64-NO-ATOMIC-NEXT: mv a1, a0
-; RV64-NO-ATOMIC-NEXT: li s1, 2
; RV64-NO-ATOMIC-NEXT: j .LBB52_2
; RV64-NO-ATOMIC-NEXT: .LBB52_1: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1
-; RV64-NO-ATOMIC-NEXT: sd a1, 0(sp)
-; RV64-NO-ATOMIC-NEXT: mv a1, sp
+; RV64-NO-ATOMIC-NEXT: sd a1, 8(sp)
+; RV64-NO-ATOMIC-NEXT: addi a1, sp, 8
; RV64-NO-ATOMIC-NEXT: li a3, 5
; RV64-NO-ATOMIC-NEXT: li a4, 5
; RV64-NO-ATOMIC-NEXT: mv a0, s0
; RV64-NO-ATOMIC-NEXT: call __atomic_compare_exchange_8
-; RV64-NO-ATOMIC-NEXT: ld a1, 0(sp)
+; RV64-NO-ATOMIC-NEXT: ld a1, 8(sp)
; RV64-NO-ATOMIC-NEXT: bnez a0, .LBB52_4
; RV64-NO-ATOMIC-NEXT: .LBB52_2: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64-NO-ATOMIC-NEXT: li a0, 1
; RV64-NO-ATOMIC-NEXT: mv a2, a1
-; RV64-NO-ATOMIC-NEXT: bltu a1, s1, .LBB52_1
+; RV64-NO-ATOMIC-NEXT: bltu a1, a0, .LBB52_1
; RV64-NO-ATOMIC-NEXT: # %bb.3: # %atomicrmw.start
; RV64-NO-ATOMIC-NEXT: # in Loop: Header=BB52_2 Depth=1
; RV64-NO-ATOMIC-NEXT: li a2, 1
@@ -3767,7 +3742,6 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind {
; RV64-NO-ATOMIC-NEXT: mv a0, a1
; RV64-NO-ATOMIC-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
-; RV64-NO-ATOMIC-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NO-ATOMIC-NEXT: addi sp, sp, 32
; RV64-NO-ATOMIC-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/fpclamptosat.ll b/llvm/test/CodeGen/RISCV/fpclamptosat.ll
index 13c11c5785898..2d6345e1952f9 100644
--- a/llvm/test/CodeGen/RISCV/fpclamptosat.ll
+++ b/llvm/test/CodeGen/RISCV/fpclamptosat.ll
@@ -183,12 +183,12 @@ define i32 @ustest_f64i32(double %x) {
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: .cfi_offset ra, -4
; RV32IF-NEXT: call __fixdfdi
-; RV32IF-NEXT: beqz a1, .LBB2_2
+; RV32IF-NEXT: bnez a1, .LBB2_2
; RV32IF-NEXT: # %bb.1: # %entry
-; RV32IF-NEXT: srli a2, a1, 31
+; RV32IF-NEXT: li a2, 1
; RV32IF-NEXT: j .LBB2_3
; RV32IF-NEXT: .LBB2_2:
-; RV32IF-NEXT: sltiu a2, a0, -1
+; RV32IF-NEXT: slti a2, a1, 1
; RV32IF-NEXT: .LBB2_3: # %entry
; RV32IF-NEXT: addi a3, a2, -1
; RV32IF-NEXT: neg a2, a2
@@ -492,12 +492,12 @@ define i32 @ustest_f16i32(half %x) {
; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: call __extendhfsf2
; RV32-NEXT: call __fixsfdi
-; RV32-NEXT: beqz a1, .LBB8_2
+; RV32-NEXT: bnez a1, .LBB8_2
; RV32-NEXT: # %bb.1: # %entry
-; RV32-NEXT: srli a2, a1, 31
+; RV32-NEXT: li a2, 1
; RV32-NEXT: j .LBB8_3
; RV32-NEXT: .LBB8_2:
-; RV32-NEXT: sltiu a2, a0, -1
+; RV32-NEXT: slti a2, a1, 1
; RV32-NEXT: .LBB8_3: # %entry
; RV32-NEXT: addi a3, a2, -1
; RV32-NEXT: neg a2, a2
@@ -1944,7 +1944,7 @@ define i64 @ustest_f64i64(double %x) {
; RV32IF-NEXT: li a3, 1023
; RV32IF-NEXT: bgeu a2, a3, .LBB20_2
; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: li s1, 0
+; RV32IF-NEXT: li s2, 0
; RV32IF-NEXT: li s6, 0
; RV32IF-NEXT: li a0, 0
; RV32IF-NEXT: li a1, 0
@@ -1954,7 +1954,7 @@ define i64 @ustest_f64i64(double %x) {
; RV32IF-NEXT: lui a3, 256
; RV32IF-NEXT: snez a4, a0
; RV32IF-NEXT: addi a0, a0, -1
-; RV32IF-NEXT: ori s2, s0, 1
+; RV32IF-NEXT: ori s1, s0, 1
; RV32IF-NEXT: addi a5, a3, -1
; RV32IF-NEXT: addi a3, a0, 1
; RV32IF-NEXT: and a1, a1, a5
@@ -2009,10 +2009,10 @@ define i64 @ustest_f64i64(double %x) {
; RV32IF-NEXT: or a2, a5, a7
; RV32IF-NEXT: or a3, a1, a3
; RV32IF-NEXT: sll s4, a4, a0
-; RV32IF-NEXT: mv a0, s2
+; RV32IF-NEXT: mv a0, s1
; RV32IF-NEXT: mv a1, s0
; RV32IF-NEXT: call __muldi3
-; RV32IF-NEXT: mv s1, a0
+; RV32IF-NEXT: mv s2, a0
; RV32IF-NEXT: mv s5, a1
; RV32IF-NEXT: mv a0, s0
; RV32IF-NEXT: mv a1, s0
@@ -2020,47 +2020,47 @@ define i64 @ustest_f64i64(double %x) {
; RV32IF-NEXT: mv a3, s3
; RV32IF-NEXT: call __muldi3
; RV32IF-NEXT: add a1, a1, s5
-; RV32IF-NEXT: add s7, a0, s1
+; RV32IF-NEXT: add s7, a0, s2
; RV32IF-NEXT: sltu a0, s7, a0
; RV32IF-NEXT: add s8, a1, a0
; RV32IF-NEXT: mv a0, s3
; RV32IF-NEXT: li a1, 0
-; RV32IF-NEXT: mv a2, s2
+; RV32IF-NEXT: mv a2, s1
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: call __muldi3
; RV32IF-NEXT: mv s5, a0
; RV32IF-NEXT: mv s6, a1
; RV32IF-NEXT: mv a0, s4
; RV32IF-NEXT: li a1, 0
-; RV32IF-NEXT: mv a2, s2
+; RV32IF-NEXT: mv a2, s1
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: call __muldi3
-; RV32IF-NEXT: mv s1, a0
-; RV32IF-NEXT: add s2, s5, a1
-; RV32IF-NEXT: sltu a0, s2, s5
+; RV32IF-NEXT: mv s2, a0
+; RV32IF-NEXT: add s1, s5, a1
+; RV32IF-NEXT: sltu a0, s1, s5
; RV32IF-NEXT: add s5, s6, a0
; RV32IF-NEXT: mv a0, s4
; RV32IF-NEXT: li a1, 0
; RV32IF-NEXT: mv a2, s0
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: call __muldi3
-; RV32IF-NEXT: add s6, a0, s2
+; RV32IF-NEXT: add s6, a0, s1
; RV32IF-NEXT: sltu a0, s6, a0
; RV32IF-NEXT: add a0, a1, a0
-; RV32IF-NEXT: add s2, s5, a0
-; RV32IF-NEXT: sltu s4, s2, s5
+; RV32IF-NEXT: add s1, s5, a0
+; RV32IF-NEXT: sltu s4, s1, s5
; RV32IF-NEXT: mv a0, s3
; RV32IF-NEXT: li a1, 0
; RV32IF-NEXT: mv a2, s0
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: call __muldi3
; RV32IF-NEXT: add a1, a1, s4
-; RV32IF-NEXT: add s2, a0, s2
-; RV32IF-NEXT: sltu a2, s2, a0
-; RV32IF-NEXT: add a0, s2, s7
+; RV32IF-NEXT: add s1, a0, s1
+; RV32IF-NEXT: sltu a2, s1, a0
+; RV32IF-NEXT: add a0, s1, s7
; RV32IF-NEXT: add a1, a1, a2
; RV32IF-NEXT: add a1, a1, s8
-; RV32IF-NEXT: sltu a2, a0, s2
+; RV32IF-NEXT: sltu a2, a0, s1
; RV32IF-NEXT: add a1, a1, a2
; RV32IF-NEXT: bnez a1, .LBB20_9
; RV32IF-NEXT: .LBB20_6:
@@ -2075,14 +2075,14 @@ define i64 @ustest_f64i64(double %x) {
; RV32IF-NEXT: .LBB20_8: # %fp-to-i-if-exp.small
; RV32IF-NEXT: mv a0, s4
; RV32IF-NEXT: li a1, 0
-; RV32IF-NEXT: mv a2, s2
+; RV32IF-NEXT: mv a2, s1
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: call __muldi3
-; RV32IF-NEXT: mv s1, a0
+; RV32IF-NEXT: mv s2, a0
; RV32IF-NEXT: mv s5, a1
; RV32IF-NEXT: mv a0, s3
; RV32IF-NEXT: li a1, 0
-; RV32IF-NEXT: mv a2, s2
+; RV32IF-NEXT: mv a2, s1
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: call __muldi3
; RV32IF-NEXT: add s5, a0, s5
@@ -2102,7 +2102,7 @@ define i64 @ustest_f64i64(double %x) {
; RV32IF-NEXT: mv a2, s0
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: call __muldi3
-; RV32IF-NEXT: mv s2, a0
+; RV32IF-NEXT: mv s1, a0
; RV32IF-NEXT: mv s5, a1
; RV32IF-NEXT: add s9, a0, s8
; RV32IF-NEXT: mv a0, s0
@@ -2111,7 +2111,7 @@ define i64 @ustest_f64i64(double %x) {
; RV32IF-NEXT: mv a3, s3
; RV32IF-NEXT: call __muldi3
; RV32IF-NEXT: add a0, s9, a0
-; RV32IF-NEXT: sltu a2, s9, s2
+; RV32IF-NEXT: sltu a2, s9, s1
; RV32IF-NEXT: sltu a3, s8, s7
; RV32IF-NEXT: sltu a4, a0, s9
; RV32IF-NEXT: add a3, s5, a3
@@ -2122,35 +2122,19 @@ define i64 @ustest_f64i64(double %x) {
; RV32IF-NEXT: .LBB20_9: # %fp-to-i-cleanup
; RV32IF-NEXT: srli a2, a1, 31
; RV32IF-NEXT: .LBB20_10: # %fp-to-i-cleanup
-; RV32IF-NEXT: xori a3, a0, 1
-; RV32IF-NEXT: or a3, a3, a1
-; RV32IF-NEXT: seqz a3, a3
-; RV32IF-NEXT: addi a3, a3, -1
-; RV32IF-NEXT: and a3, a3, a2
-; RV32IF-NEXT: neg a2, a3
-; RV32IF-NEXT: bnez a3, .LBB20_12
-; RV32IF-NEXT: # %bb.11: # %fp-to-i-cleanup
-; RV32IF-NEXT: li a0, 1
-; RV32IF-NEXT: .LBB20_12: # %fp-to-i-cleanup
-; RV32IF-NEXT: and a4, a2, a1
-; RV32IF-NEXT: beqz a4, .LBB20_14
-; RV32IF-NEXT: # %bb.13: # %fp-to-i-cleanup
-; RV32IF-NEXT: sgtz a1, a4
-; RV32IF-NEXT: j .LBB20_15
-; RV32IF-NEXT: .LBB20_14:
-; RV32IF-NEXT: snez a1, a0
-; RV32IF-NEXT: .LBB20_15: # %fp-to-i-cleanup
-; RV32IF-NEXT: and a3, a2, s6
-; RV32IF-NEXT: or a0, a0, a4
-; RV32IF-NEXT: and a2, a2, s1
-; RV32IF-NEXT: bnez a0, .LBB20_17
-; RV32IF-NEXT: # %bb.16:
-; RV32IF-NEXT: or a0, a2, a3
-; RV32IF-NEXT: snez a1, a0
-; RV32IF-NEXT: .LBB20_17: # %fp-to-i-cleanup
-; RV32IF-NEXT: neg a1, a1
-; RV32IF-NEXT: and a0, a1, a2
-; RV32IF-NEXT: and a1, a1, a3
+; RV32IF-NEXT: xori a0, a0, 1
+; RV32IF-NEXT: or a0, a0, a1
+; RV32IF-NEXT: seqz a0, a0
+; RV32IF-NEXT: addi a0, a0, -1
+; RV32IF-NEXT: and a0, a0, a2
+; RV32IF-NEXT: neg a0, a0
+; RV32IF-NEXT: and a2, a0, s6
+; RV32IF-NEXT: and a3, a0, s2
+; RV32IF-NEXT: and a0, a0, a1
+; RV32IF-NEXT: srli a0, a0, 31
+; RV32IF-NEXT: addi a1, a0, -1
+; RV32IF-NEXT: and a0, a1, a3
+; RV32IF-NEXT: and a1, a1, a2
; RV32IF-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s1, 68(sp) # 4-byte Folded Reload
@@ -2184,22 +2168,17 @@ define i64 @ustest_f64i64(double %x) {
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: call __fixdfti
-; RV64-NEXT: slti a2, a1, 1
+; RV64-NEXT: mv a2, a1
; RV64-NEXT: blez a1, .LBB20_2
; RV64-NEXT: # %bb.1: # %entry
-; RV64-NEXT: li a1, 1
+; RV64-NEXT: li a2, 1
; RV64-NEXT: .LBB20_2: # %entry
-; RV64-NEXT: neg a2, a2
-; RV64-NEXT: and a0, a2, a0
-; RV64-NEXT: beqz a1, .LBB20_4
-; RV64-NEXT: # %bb.3: # %entry
-; RV64-NEXT: sgtz a1, a1
-; RV64-NEXT: j .LBB20_5
-; RV64-NEXT: .LBB20_4:
-; RV64-NEXT: snez a1, a0
-; RV64-NEXT: .LBB20_5: # %entry
+; RV64-NEXT: slti a1, a1, 1
+; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: neg a1, a1
; RV64-NEXT: and a0, a1, a0
+; RV64-NEXT: addi a2, a2, -1
+; RV64-NEXT: and a0, a2, a0
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: .cfi_restore ra
; RV64-NEXT: addi sp, sp, 16
@@ -2239,7 +2218,7 @@ define i64 @ustest_f64i64(double %x) {
; RV32IFD-NEXT: li a2, 1023
; RV32IFD-NEXT: bgeu a0, a2, .LBB20_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: li s1, 0
+; RV32IFD-NEXT: li s2, 0
; RV32IFD-NEXT: li s6, 0
; RV32IFD-NEXT: li a0, 0
; RV32IFD-NEXT: li a1, 0
@@ -2248,7 +2227,7 @@ define i64 @ustest_f64i64(double %x) {
; RV32IFD-NEXT: lw a2, 8(sp)
; RV32IFD-NEXT: srai s0, a1, 31
; RV32IFD-NEXT: lui a3, 256
-; RV32IFD-NEXT: ori s2, s0, 1
+; RV32IFD-NEXT: ori s1, s0, 1
; RV32IFD-NEXT: addi a3, a3, -1
; RV32IFD-NEXT: and a1, a1, a3
; RV32IFD-NEXT: snez a4, a2
@@ -2305,10 +2284,10 @@ define i64 @ustest_f64i64(double %x) {
; RV32IFD-NEXT: or a2, a5, a7
; RV32IFD-NEXT: or a3, a1, a3
; RV32IFD-NEXT: sll s4, a4, a0
-; RV32IFD-NEXT: mv a0, s2
+; RV32IFD-NEXT: mv a0, s1
; RV32IFD-NEXT: mv a1, s0
; RV32IFD-NEXT: call __muldi3
-; RV32IFD-NEXT: mv s1, a0
+; RV32IFD-NEXT: mv s2, a0
; RV32IFD-NEXT: mv s5, a1
; RV32IFD-NEXT: mv a0, s0
; RV32IFD-NEXT: mv a1, s0
@@ -2316,47 +2295,47 @@ define i64 @ustest_f64i64(double %x) {
; RV32IFD-NEXT: mv a3, s3
; RV32IFD-NEXT: call __muldi3
; RV32IFD-NEXT: add a1, a1, s5
-; RV32IFD-NEXT: add s7, a0, s1
+; RV32IFD-NEXT: add s7, a0, s2
; RV32IFD-NEXT: sltu a0, s7, a0
; RV32IFD-NEXT: add s8, a1, a0
; RV32IFD-NEXT: mv a0, s3
; RV32IFD-NEXT: li a1, 0
-; RV32IFD-NEXT: mv a2, s2
+; RV32IFD-NEXT: mv a2, s1
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: call __muldi3
; RV32IFD-NEXT: mv s5, a0
; RV32IFD-NEXT: mv s6, a1
; RV32IFD-NEXT: mv a0, s4
; RV32IFD-NEXT: li a1, 0
-; RV32IFD-NEXT: mv a2, s2
+; RV32IFD-NEXT: mv a2, s1
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: call __muldi3
-; RV32IFD-NEXT: mv s1, a0
-; RV32IFD-NEXT: add s2, s5, a1
-; RV32IFD-NEXT: sltu a0, s2, s5
+; RV32IFD-NEXT: mv s2, a0
+; RV32IFD-NEXT: add s1, s5, a1
+; RV32IFD-NEXT: sltu a0, s1, s5
; RV32IFD-NEXT: add s5, s6, a0
; RV32IFD-NEXT: mv a0, s4
; RV32IFD-NEXT: li a1, 0
; RV32IFD-NEXT: mv a2, s0
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: call __muldi3
-; RV32IFD-NEXT: add s6, a0, s2
+; RV32IFD-NEXT: add s6, a0, s1
; RV32IFD-NEXT: sltu a0, s6, a0
; RV32IFD-NEXT: add a0, a1, a0
-; RV32IFD-NEXT: add s2, s5, a0
-; RV32IFD-NEXT: sltu s4, s2, s5
+; RV32IFD-NEXT: add s1, s5, a0
+; RV32IFD-NEXT: sltu s4, s1, s5
; RV32IFD-NEXT: mv a0, s3
; RV32IFD-NEXT: li a1, 0
; RV32IFD-NEXT: mv a2, s0
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: call __muldi3
; RV32IFD-NEXT: add a1, a1, s4
-; RV32IFD-NEXT: add s2, a0, s2
-; RV32IFD-NEXT: sltu a2, s2, a0
-; RV32IFD-NEXT: add a0, s2, s7
+; RV32IFD-NEXT: add s1, a0, s1
+; RV32IFD-NEXT: sltu a2, s1, a0
+; RV32IFD-NEXT: add a0, s1, s7
; RV32IFD-NEXT: add a1, a1, a2
; RV32IFD-NEXT: add a1, a1, s8
-; RV32IFD-NEXT: sltu a2, a0, s2
+; RV32IFD-NEXT: sltu a2, a0, s1
; RV32IFD-NEXT: add a1, a1, a2
; RV32IFD-NEXT: bnez a1, .LBB20_9
; RV32IFD-NEXT: .LBB20_6:
@@ -2371,14 +2350,14 @@ define i64 @ustest_f64i64(double %x) {
; RV32IFD-NEXT: .LBB20_8: # %fp-to-i-if-exp.small
; RV32IFD-NEXT: mv a0, s4
; RV32IFD-NEXT: li a1, 0
-; RV32IFD-NEXT: mv a2, s2
+; RV32IFD-NEXT: mv a2, s1
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: call __muldi3
-; RV32IFD-NEXT: mv s1, a0
+; RV32IFD-NEXT: mv s2, a0
; RV32IFD-NEXT: mv s5, a1
; RV32IFD-NEXT: mv a0, s3
; RV32IFD-NEXT: li a1, 0
-; RV32IFD-NEXT: mv a2, s2
+; RV32IFD-NEXT: mv a2, s1
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: call __muldi3
; RV32IFD-NEXT: add s5, a0, s5
@@ -2398,7 +2377,7 @@ define i64 @ustest_f64i64(double %x) {
; RV32IFD-NEXT: mv a2, s0
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: call __muldi3
-; RV32IFD-NEXT: mv s2, a0
+; RV32IFD-NEXT: mv s1, a0
; RV32IFD-NEXT: mv s5, a1
; RV32IFD-NEXT: add s9, a0, s8
; RV32IFD-NEXT: mv a0, s0
@@ -2407,7 +2386,7 @@ define i64 @ustest_f64i64(double %x) {
; RV32IFD-NEXT: mv a3, s3
; RV32IFD-NEXT: call __muldi3
; RV32IFD-NEXT: add a0, s9, a0
-; RV32IFD-NEXT: sltu a2, s9, s2
+; RV32IFD-NEXT: sltu a2, s9, s1
; RV32IFD-NEXT: sltu a3, s8, s7
; RV32IFD-NEXT: sltu a4, a0, s9
; RV32IFD-NEXT: add a3, s5, a3
@@ -2418,35 +2397,19 @@ define i64 @ustest_f64i64(double %x) {
; RV32IFD-NEXT: .LBB20_9: # %fp-to-i-cleanup
; RV32IFD-NEXT: srli a2, a1, 31
; RV32IFD-NEXT: .LBB20_10: # %fp-to-i-cleanup
-; RV32IFD-NEXT: xori a3, a0, 1
-; RV32IFD-NEXT: or a3, a3, a1
-; RV32IFD-NEXT: seqz a3, a3
-; RV32IFD-NEXT: addi a3, a3, -1
-; RV32IFD-NEXT: and a3, a3, a2
-; RV32IFD-NEXT: neg a2, a3
-; RV32IFD-NEXT: bnez a3, .LBB20_12
-; RV32IFD-NEXT: # %bb.11: # %fp-to-i-cleanup
-; RV32IFD-NEXT: li a0, 1
-; RV32IFD-NEXT: .LBB20_12: # %fp-to-i-cleanup
-; RV32IFD-NEXT: and a4, a2, a1
-; RV32IFD-NEXT: beqz a4, .LBB20_14
-; RV32IFD-NEXT: # %bb.13: # %fp-to-i-cleanup
-; RV32IFD-NEXT: sgtz a1, a4
-; RV32IFD-NEXT: j .LBB20_15
-; RV32IFD-NEXT: .LBB20_14:
-; RV32IFD-NEXT: snez a1, a0
-; RV32IFD-NEXT: .LBB20_15: # %fp-to-i-cleanup
-; RV32IFD-NEXT: and a3, a2, s6
-; RV32IFD-NEXT: or a0, a0, a4
-; RV32IFD-NEXT: and a2, a2, s1
-; RV32IFD-NEXT: bnez a0, .LBB20_17
-; RV32IFD-NEXT: # %bb.16:
-; RV32IFD-NEXT: or a0, a2, a3
-; RV32IFD-NEXT: snez a1, a0
-; RV32IFD-NEXT: .LBB20_17: # %fp-to-i-cleanup
-; RV32IFD-NEXT: neg a1, a1
-; RV32IFD-NEXT: and a0, a1, a2
-; RV32IFD-NEXT: and a1, a1, a3
+; RV32IFD-NEXT: xori a0, a0, 1
+; RV32IFD-NEXT: or a0, a0, a1
+; RV32IFD-NEXT: seqz a0, a0
+; RV32IFD-NEXT: addi a0, a0, -1
+; RV32IFD-NEXT: and a0, a0, a2
+; RV32IFD-NEXT: neg a0, a0
+; RV32IFD-NEXT: and a2, a0, s6
+; RV32IFD-NEXT: and a3, a0, s2
+; RV32IFD-NEXT: and a0, a0, a1
+; RV32IFD-NEXT: srli a0, a0, 31
+; RV32IFD-NEXT: addi a1, a0, -1
+; RV32IFD-NEXT: and a0, a1, a3
+; RV32IFD-NEXT: and a1, a1, a2
; RV32IFD-NEXT: lw ra, 92(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s0, 88(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: lw s1, 84(sp) # 4-byte Folded Reload
@@ -3041,35 +3004,19 @@ define i64 @ustest_f32i64(float %x) {
; RV32-NEXT: .LBB23_6: # %fp-to-i-cleanup
; RV32-NEXT: srli a2, a1, 31
; RV32-NEXT: .LBB23_7: # %fp-to-i-cleanup
-; RV32-NEXT: xori a3, a0, 1
-; RV32-NEXT: or a3, a3, a1
-; RV32-NEXT: seqz a3, a3
-; RV32-NEXT: addi a3, a3, -1
-; RV32-NEXT: and a3, a3, a2
-; RV32-NEXT: neg a2, a3
-; RV32-NEXT: bnez a3, .LBB23_9
-; RV32-NEXT: # %bb.8: # %fp-to-i-cleanup
-; RV32-NEXT: li a0, 1
-; RV32-NEXT: .LBB23_9: # %fp-to-i-cleanup
-; RV32-NEXT: and a4, a2, a1
-; RV32-NEXT: beqz a4, .LBB23_11
-; RV32-NEXT: # %bb.10: # %fp-to-i-cleanup
-; RV32-NEXT: sgtz a1, a4
-; RV32-NEXT: j .LBB23_12
-; RV32-NEXT: .LBB23_11:
-; RV32-NEXT: snez a1, a0
-; RV32-NEXT: .LBB23_12: # %fp-to-i-cleanup
-; RV32-NEXT: and a3, a2, s5
-; RV32-NEXT: or a0, a0, a4
-; RV32-NEXT: and a2, a2, s1
-; RV32-NEXT: bnez a0, .LBB23_14
-; RV32-NEXT: # %bb.13:
-; RV32-NEXT: or a0, a2, a3
-; RV32-NEXT: snez a1, a0
-; RV32-NEXT: .LBB23_14: # %fp-to-i-cleanup
-; RV32-NEXT: neg a1, a1
-; RV32-NEXT: and a0, a1, a2
-; RV32-NEXT: and a1, a1, a3
+; RV32-NEXT: xori a0, a0, 1
+; RV32-NEXT: or a0, a0, a1
+; RV32-NEXT: seqz a0, a0
+; RV32-NEXT: addi a0, a0, -1
+; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: neg a0, a0
+; RV32-NEXT: and a2, a0, s5
+; RV32-NEXT: and s1, a0, s1
+; RV32-NEXT: and a0, a0, a1
+; RV32-NEXT: srli a0, a0, 31
+; RV32-NEXT: addi a1, a0, -1
+; RV32-NEXT: and a0, a1, s1
+; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 68(sp) # 4-byte Folded Reload
@@ -3101,22 +3048,17 @@ define i64 @ustest_f32i64(float %x) {
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: call __fixsfti
-; RV64-NEXT: slti a2, a1, 1
+; RV64-NEXT: mv a2, a1
; RV64-NEXT: blez a1, .LBB23_2
; RV64-NEXT: # %bb.1: # %entry
-; RV64-NEXT: li a1, 1
+; RV64-NEXT: li a2, 1
; RV64-NEXT: .LBB23_2: # %entry
-; RV64-NEXT: neg a2, a2
-; RV64-NEXT: and a0, a2, a0
-; RV64-NEXT: beqz a1, .LBB23_4
-; RV64-NEXT: # %bb.3: # %entry
-; RV64-NEXT: sgtz a1, a1
-; RV64-NEXT: j .LBB23_5
-; RV64-NEXT: .LBB23_4:
-; RV64-NEXT: snez a1, a0
-; RV64-NEXT: .LBB23_5: # %entry
+; RV64-NEXT: slti a1, a1, 1
+; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: neg a1, a1
; RV64-NEXT: and a0, a1, a0
+; RV64-NEXT: addi a2, a2, -1
+; RV64-NEXT: and a0, a2, a0
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: .cfi_restore ra
; RV64-NEXT: addi sp, sp, 16
@@ -3140,50 +3082,8 @@ define i64 @stest_f16i64(half %x) {
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: call __extendhfsf2
-; RV32-NEXT: fcvt.w.s a2, fa0, rtz
-; RV32-NEXT: lui a0, 524288
-; RV32-NEXT: srai a3, a2, 31
-; RV32-NEXT: addi a4, a0, -1
-; RV32-NEXT: beq a3, a4, .LBB24_2
-; RV32-NEXT: # %bb.1: # %entry
-; RV32-NEXT: sltu a5, a3, a4
-; RV32-NEXT: bnez a3, .LBB24_3
-; RV32-NEXT: j .LBB24_4
-; RV32-NEXT: .LBB24_2:
-; RV32-NEXT: sltiu a5, a2, -1
-; RV32-NEXT: beqz a3, .LBB24_4
-; RV32-NEXT: .LBB24_3: # %entry
-; RV32-NEXT: srli a5, a3, 31
-; RV32-NEXT: .LBB24_4: # %entry
-; RV32-NEXT: neg a6, a5
-; RV32-NEXT: addi a7, a5, -1
-; RV32-NEXT: mv a1, a3
-; RV32-NEXT: bnez a5, .LBB24_6
-; RV32-NEXT: # %bb.5: # %entry
-; RV32-NEXT: mv a1, a4
-; RV32-NEXT: .LBB24_6: # %entry
-; RV32-NEXT: or a2, a7, a2
-; RV32-NEXT: and a3, a6, a3
-; RV32-NEXT: beq a1, a0, .LBB24_8
-; RV32-NEXT: # %bb.7: # %entry
-; RV32-NEXT: sltu a0, a0, a1
-; RV32-NEXT: li a4, -1
-; RV32-NEXT: bne a3, a4, .LBB24_9
-; RV32-NEXT: j .LBB24_10
-; RV32-NEXT: .LBB24_8:
-; RV32-NEXT: snez a0, a2
-; RV32-NEXT: li a4, -1
-; RV32-NEXT: beq a3, a4, .LBB24_10
-; RV32-NEXT: .LBB24_9: # %entry
-; RV32-NEXT: srli a3, a3, 31
-; RV32-NEXT: xori a0, a3, 1
-; RV32-NEXT: .LBB24_10: # %entry
-; RV32-NEXT: bnez a0, .LBB24_12
-; RV32-NEXT: # %bb.11: # %entry
-; RV32-NEXT: lui a1, 524288
-; RV32-NEXT: .LBB24_12: # %entry
-; RV32-NEXT: neg a0, a0
-; RV32-NEXT: and a0, a0, a2
+; RV32-NEXT: fcvt.w.s a0, fa0, rtz
+; RV32-NEXT: srai a1, a0, 31
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: .cfi_restore ra
; RV32-NEXT: addi sp, sp, 16
@@ -3293,33 +3193,16 @@ define i64 @ustest_f16i64(half %x) {
; RV32-NEXT: srai a1, a0, 31
; RV32-NEXT: srli a2, a1, 31
; RV32-NEXT: seqz a3, a1
-; RV32-NEXT: ori a4, a1, 1
; RV32-NEXT: or a2, a3, a2
-; RV32-NEXT: seqz a3, a4
+; RV32-NEXT: ori a3, a1, 1
+; RV32-NEXT: seqz a3, a3
; RV32-NEXT: addi a3, a3, -1
-; RV32-NEXT: and a4, a3, a2
-; RV32-NEXT: neg a2, a4
-; RV32-NEXT: mv a3, a1
-; RV32-NEXT: bnez a4, .LBB26_2
-; RV32-NEXT: # %bb.1: # %entry
-; RV32-NEXT: li a3, 1
-; RV32-NEXT: .LBB26_2: # %entry
-; RV32-NEXT: and a1, a2, a1
-; RV32-NEXT: beqz a1, .LBB26_4
-; RV32-NEXT: # %bb.3: # %entry
-; RV32-NEXT: sgtz a4, a1
-; RV32-NEXT: j .LBB26_5
-; RV32-NEXT: .LBB26_4:
-; RV32-NEXT: snez a4, a3
-; RV32-NEXT: .LBB26_5: # %entry
-; RV32-NEXT: or a3, a3, a1
+; RV32-NEXT: and a2, a3, a2
+; RV32-NEXT: neg a2, a2
; RV32-NEXT: and a0, a2, a0
-; RV32-NEXT: bnez a3, .LBB26_7
-; RV32-NEXT: # %bb.6:
-; RV32-NEXT: or a2, a0, a1
-; RV32-NEXT: snez a4, a2
-; RV32-NEXT: .LBB26_7: # %entry
-; RV32-NEXT: neg a2, a4
+; RV32-NEXT: and a1, a2, a1
+; RV32-NEXT: srli a2, a1, 31
+; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a0, a2, a0
; RV32-NEXT: and a1, a2, a1
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
@@ -3336,22 +3219,17 @@ define i64 @ustest_f16i64(half %x) {
; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: call __extendhfsf2
; RV64-NEXT: call __fixsfti
-; RV64-NEXT: slti a2, a1, 1
+; RV64-NEXT: mv a2, a1
; RV64-NEXT: blez a1, .LBB26_2
; RV64-NEXT: # %bb.1: # %entry
-; RV64-NEXT: li a1, 1
+; RV64-NEXT: li a2, 1
; RV64-NEXT: .LBB26_2: # %entry
-; RV64-NEXT: neg a2, a2
-; RV64-NEXT: and a0, a2, a0
-; RV64-NEXT: beqz a1, .LBB26_4
-; RV64-NEXT: # %bb.3: # %entry
-; RV64-NEXT: sgtz a1, a1
-; RV64-NEXT: j .LBB26_5
-; RV64-NEXT: .LBB26_4:
-; RV64-NEXT: snez a1, a0
-; RV64-NEXT: .LBB26_5: # %entry
+; RV64-NEXT: slti a1, a1, 1
+; RV64-NEXT: srli a2, a2, 63
; RV64-NEXT: neg a1, a1
; RV64-NEXT: and a0, a1, a0
+; RV64-NEXT: addi a2, a2, -1
+; RV64-NEXT: and a0, a2, a0
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: .cfi_restore ra
; RV64-NEXT: addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/pr148084.ll b/llvm/test/CodeGen/RISCV/pr148084.ll
index dcae5d6810eec..06aabfc1f3670 100644
--- a/llvm/test/CodeGen/RISCV/pr148084.ll
+++ b/llvm/test/CodeGen/RISCV/pr148084.ll
@@ -138,26 +138,18 @@ define fastcc void @search_tx_type() #0 {
; CHECK-NEXT: slli a4, a1, 51
; CHECK-NEXT: sext.w a3, a2
; CHECK-NEXT: mv a1, a2
-; CHECK-NEXT: bltz a4, .LBB0_49
+; CHECK-NEXT: bgez a4, .LBB0_45
; CHECK-NEXT: # %bb.44: # %bb
-; CHECK-NEXT: bge a3, a0, .LBB0_50
+; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: .LBB0_45: # %bb
-; CHECK-NEXT: sext.w a2, a1
-; CHECK-NEXT: blt a2, a0, .LBB0_47
-; CHECK-NEXT: .LBB0_46: # %bb
-; CHECK-NEXT: mv a0, a1
+; CHECK-NEXT: blt a3, a0, .LBB0_47
+; CHECK-NEXT: # %bb.46: # %bb
+; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB0_47: # %bb
-; CHECK-NEXT: sext.w a0, a0
+; CHECK-NEXT: sext.w a1, a1
+; CHECK-NEXT: max a0, a0, a1
; CHECK-NEXT: # %bb.48: # %get_tx_mask.exit
; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB0_49: # %bb
-; CHECK-NEXT: mv a1, a0
-; CHECK-NEXT: blt a3, a0, .LBB0_45
-; CHECK-NEXT: .LBB0_50: # %bb
-; CHECK-NEXT: mv a1, a2
-; CHECK-NEXT: sext.w a2, a2
-; CHECK-NEXT: bge a2, a0, .LBB0_46
-; CHECK-NEXT: j .LBB0_47
._crit_edge.i:
%.in196.i = load i16, ptr null, align 2
%i2 = load i16, ptr null, align 2
diff --git a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
index 2add54fa35539..1b2ecdfa325ac 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
@@ -89,23 +89,23 @@ entry:
define <2 x i32> @ustest_f64i32(<2 x double> %x) {
; CHECK-NOV-LABEL: ustest_f64i32:
; CHECK-NOV: # %bb.0: # %entry
-; CHECK-NOV-NEXT: fcvt.l.d a0, fa0, rtz
+; CHECK-NOV-NEXT: fcvt.l.d a1, fa1, rtz
; CHECK-NOV-NEXT: li a2, -1
; CHECK-NOV-NEXT: srli a2, a2, 32
-; CHECK-NOV-NEXT: fcvt.l.d a1, fa1, rtz
-; CHECK-NOV-NEXT: blt a0, a2, .LBB2_2
+; CHECK-NOV-NEXT: fcvt.l.d a0, fa0, rtz
+; CHECK-NOV-NEXT: blt a1, a2, .LBB2_2
; CHECK-NOV-NEXT: # %bb.1: # %entry
-; CHECK-NOV-NEXT: mv a0, a2
+; CHECK-NOV-NEXT: mv a1, a2
; CHECK-NOV-NEXT: .LBB2_2: # %entry
-; CHECK-NOV-NEXT: blt a1, a2, .LBB2_4
+; CHECK-NOV-NEXT: blt a0, a2, .LBB2_4
; CHECK-NOV-NEXT: # %bb.3: # %entry
-; CHECK-NOV-NEXT: mv a1, a2
+; CHECK-NOV-NEXT: mv a0, a2
; CHECK-NOV-NEXT: .LBB2_4: # %entry
+; CHECK-NOV-NEXT: sgtz a2, a0
+; CHECK-NOV-NEXT: neg a2, a2
+; CHECK-NOV-NEXT: and a0, a2, a0
; CHECK-NOV-NEXT: sgtz a2, a1
-; CHECK-NOV-NEXT: sgtz a3, a0
-; CHECK-NOV-NEXT: neg a3, a3
; CHECK-NOV-NEXT: neg a2, a2
-; CHECK-NOV-NEXT: and a0, a3, a0
; CHECK-NOV-NEXT: and a1, a2, a1
; CHECK-NOV-NEXT: ret
;
@@ -254,50 +254,50 @@ entry:
define <4 x i32> @ustest_f32i32(<4 x float> %x) {
; CHECK-NOV-LABEL: ustest_f32i32:
; CHECK-NOV: # %bb.0: # %entry
-; CHECK-NOV-NEXT: fcvt.l.s a1, fa0, rtz
-; CHECK-NOV-NEXT: li a5, -1
-; CHECK-NOV-NEXT: srli a5, a5, 32
-; CHECK-NOV-NEXT: fcvt.l.s a2, fa1, rtz
-; CHECK-NOV-NEXT: bge a1, a5, .LBB5_6
+; CHECK-NOV-NEXT: fcvt.l.s a1, fa3, rtz
+; CHECK-NOV-NEXT: li a3, -1
+; CHECK-NOV-NEXT: srli a3, a3, 32
+; CHECK-NOV-NEXT: fcvt.l.s a2, fa2, rtz
+; CHECK-NOV-NEXT: bge a1, a3, .LBB5_6
; CHECK-NOV-NEXT: # %bb.1: # %entry
-; CHECK-NOV-NEXT: fcvt.l.s a3, fa2, rtz
-; CHECK-NOV-NEXT: bge a2, a5, .LBB5_7
+; CHECK-NOV-NEXT: fcvt.l.s a4, fa1, rtz
+; CHECK-NOV-NEXT: bge a2, a3, .LBB5_7
; CHECK-NOV-NEXT: .LBB5_2: # %entry
-; CHECK-NOV-NEXT: fcvt.l.s a4, fa3, rtz
-; CHECK-NOV-NEXT: bge a3, a5, .LBB5_8
+; CHECK-NOV-NEXT: fcvt.l.s a5, fa0, rtz
+; CHECK-NOV-NEXT: bge a4, a3, .LBB5_8
; CHECK-NOV-NEXT: .LBB5_3: # %entry
-; CHECK-NOV-NEXT: blt a4, a5, .LBB5_5
+; CHECK-NOV-NEXT: blt a5, a3, .LBB5_5
; CHECK-NOV-NEXT: .LBB5_4: # %entry
-; CHECK-NOV-NEXT: mv a4, a5
+; CHECK-NOV-NEXT: mv a5, a3
; CHECK-NOV-NEXT: .LBB5_5: # %entry
+; CHECK-NOV-NEXT: sgtz a3, a5
+; CHECK-NOV-NEXT: neg a3, a3
+; CHECK-NOV-NEXT: and a3, a3, a5
; CHECK-NOV-NEXT: sgtz a5, a4
-; CHECK-NOV-NEXT: sgtz a6, a3
-; CHECK-NOV-NEXT: sgtz a7, a2
-; CHECK-NOV-NEXT: sgtz t0, a1
-; CHECK-NOV-NEXT: neg t0, t0
-; CHECK-NOV-NEXT: neg a7, a7
-; CHECK-NOV-NEXT: neg a6, a6
; CHECK-NOV-NEXT: neg a5, a5
-; CHECK-NOV-NEXT: and a1, t0, a1
-; CHECK-NOV-NEXT: and a2, a7, a2
-; CHECK-NOV-NEXT: and a3, a6, a3
; CHECK-NOV-NEXT: and a4, a5, a4
-; CHECK-NOV-NEXT: sw a1, 0(a0)
-; CHECK-NOV-NEXT: sw a2, 4(a0)
-; CHECK-NOV-NEXT: sw a3, 8(a0)
-; CHECK-NOV-NEXT: sw a4, 12(a0)
+; CHECK-NOV-NEXT: sgtz a5, a2
+; CHECK-NOV-NEXT: neg a5, a5
+; CHECK-NOV-NEXT: and a2, a5, a2
+; CHECK-NOV-NEXT: sgtz a5, a1
+; CHECK-NOV-NEXT: neg a5, a5
+; CHECK-NOV-NEXT: and a1, a5, a1
+; CHECK-NOV-NEXT: sw a3, 0(a0)
+; CHECK-NOV-NEXT: sw a4, 4(a0)
+; CHECK-NOV-NEXT: sw a2, 8(a0)
+; CHECK-NOV-NEXT: sw a1, 12(a0)
; CHECK-NOV-NEXT: ret
; CHECK-NOV-NEXT: .LBB5_6: # %entry
-; CHECK-NOV-NEXT: mv a1, a5
-; CHECK-NOV-NEXT: fcvt.l.s a3, fa2, rtz
-; CHECK-NOV-NEXT: blt a2, a5, .LBB5_2
+; CHECK-NOV-NEXT: mv a1, a3
+; CHECK-NOV-NEXT: fcvt.l.s a4, fa1, rtz
+; CHECK-NOV-NEXT: blt a2, a3, .LBB5_2
; CHECK-NOV-NEXT: .LBB5_7: # %entry
-; CHECK-NOV-NEXT: mv a2, a5
-; CHECK-NOV-NEXT: fcvt.l.s a4, fa3, rtz
-; CHECK-NOV-NEXT: blt a3, a5, .LBB5_3
+; CHECK-NOV-NEXT: mv a2, a3
+; CHECK-NOV-NEXT: fcvt.l.s a5, fa0, rtz
+; CHECK-NOV-NEXT: blt a4, a3, .LBB5_3
; CHECK-NOV-NEXT: .LBB5_8: # %entry
-; CHECK-NOV-NEXT: mv a3, a5
-; CHECK-NOV-NEXT: bge a4, a5, .LBB5_4
+; CHECK-NOV-NEXT: mv a4, a3
+; CHECK-NOV-NEXT: bge a5, a3, .LBB5_4
; CHECK-NOV-NEXT: j .LBB5_5
;
; CHECK-V-LABEL: ustest_f32i32:
@@ -720,8 +720,8 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
; CHECK-NOV-NEXT: .cfi_offset fs2, -64
; CHECK-NOV-NEXT: .cfi_remember_state
; CHECK-NOV-NEXT: lhu s1, 0(a1)
-; CHECK-NOV-NEXT: lhu a2, 8(a1)
-; CHECK-NOV-NEXT: lhu s2, 16(a1)
+; CHECK-NOV-NEXT: lhu s2, 8(a1)
+; CHECK-NOV-NEXT: lhu a2, 16(a1)
; CHECK-NOV-NEXT: lhu s3, 24(a1)
; CHECK-NOV-NEXT: mv s0, a0
; CHECK-NOV-NEXT: fmv.w.x fa0, a2
@@ -730,43 +730,43 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
; CHECK-NOV-NEXT: fmv.w.x fa0, s2
; CHECK-NOV-NEXT: call __extendhfsf2
; CHECK-NOV-NEXT: fmv.s fs1, fa0
-; CHECK-NOV-NEXT: fmv.w.x fa0, s3
+; CHECK-NOV-NEXT: fmv.w.x fa0, s1
; CHECK-NOV-NEXT: call __extendhfsf2
; CHECK-NOV-NEXT: fmv.s fs0, fa0
-; CHECK-NOV-NEXT: fmv.w.x fa0, s1
+; CHECK-NOV-NEXT: fmv.w.x fa0, s3
; CHECK-NOV-NEXT: fcvt.l.s s1, fs2, rtz
; CHECK-NOV-NEXT: call __extendhfsf2
; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz
-; CHECK-NOV-NEXT: li a3, -1
-; CHECK-NOV-NEXT: srli a3, a3, 32
-; CHECK-NOV-NEXT: bge a0, a3, .LBB8_6
+; CHECK-NOV-NEXT: li a2, -1
+; CHECK-NOV-NEXT: srli a2, a2, 32
+; CHECK-NOV-NEXT: bge a0, a2, .LBB8_6
; CHECK-NOV-NEXT: # %bb.1: # %entry
; CHECK-NOV-NEXT: fcvt.l.s a1, fs1, rtz
-; CHECK-NOV-NEXT: bge s1, a3, .LBB8_7
+; CHECK-NOV-NEXT: bge s1, a2, .LBB8_7
; CHECK-NOV-NEXT: .LBB8_2: # %entry
-; CHECK-NOV-NEXT: fcvt.l.s a2, fs0, rtz
-; CHECK-NOV-NEXT: bge a1, a3, .LBB8_8
+; CHECK-NOV-NEXT: fcvt.l.s a3, fs0, rtz
+; CHECK-NOV-NEXT: bge a1, a2, .LBB8_8
; CHECK-NOV-NEXT: .LBB8_3: # %entry
-; CHECK-NOV-NEXT: blt a2, a3, .LBB8_5
+; CHECK-NOV-NEXT: blt a3, a2, .LBB8_5
; CHECK-NOV-NEXT: .LBB8_4: # %entry
-; CHECK-NOV-NEXT: mv a2, a3
+; CHECK-NOV-NEXT: mv a3, a2
; CHECK-NOV-NEXT: .LBB8_5: # %entry
-; CHECK-NOV-NEXT: sgtz a3, a2
-; CHECK-NOV-NEXT: sgtz a4, a1
-; CHECK-NOV-NEXT: sgtz a5, s1
-; CHECK-NOV-NEXT: sgtz a6, a0
-; CHECK-NOV-NEXT: neg a6, a6
-; CHECK-NOV-NEXT: neg a5, a5
-; CHECK-NOV-NEXT: neg a4, a4
+; CHECK-NOV-NEXT: sgtz a2, a3
+; CHECK-NOV-NEXT: neg a2, a2
+; CHECK-NOV-NEXT: and a2, a2, a3
+; CHECK-NOV-NEXT: sgtz a3, a1
; CHECK-NOV-NEXT: neg a3, a3
-; CHECK-NOV-NEXT: and a0, a6, a0
-; CHECK-NOV-NEXT: and a5, a5, s1
-; CHECK-NOV-NEXT: and a1, a4, a1
-; CHECK-NOV-NEXT: and a2, a3, a2
-; CHECK-NOV-NEXT: sw a0, 0(s0)
-; CHECK-NOV-NEXT: sw a5, 4(s0)
-; CHECK-NOV-NEXT: sw a1, 8(s0)
-; CHECK-NOV-NEXT: sw a2, 12(s0)
+; CHECK-NOV-NEXT: and a1, a3, a1
+; CHECK-NOV-NEXT: sgtz a3, s1
+; CHECK-NOV-NEXT: neg a3, a3
+; CHECK-NOV-NEXT: and a3, a3, s1
+; CHECK-NOV-NEXT: sgtz a4, a0
+; CHECK-NOV-NEXT: neg a4, a4
+; CHECK-NOV-NEXT: and a0, a4, a0
+; CHECK-NOV-NEXT: sw a2, 0(s0)
+; CHECK-NOV-NEXT: sw a1, 4(s0)
+; CHECK-NOV-NEXT: sw a3, 8(s0)
+; CHECK-NOV-NEXT: sw a0, 12(s0)
; CHECK-NOV-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-NOV-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NOV-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
@@ -788,16 +788,16 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) {
; CHECK-NOV-NEXT: ret
; CHECK-NOV-NEXT: .LBB8_6: # %entry
; CHECK-NOV-NEXT: .cfi_restore_state
-; CHECK-NOV-NEXT: mv a0, a3
+; CHECK-NOV-NEXT: mv a0, a2
; CHECK-NOV-NEXT: fcvt.l.s a1, fs1, rtz
-; CHECK-NOV-NEXT: blt s1, a3, .LBB8_2
+; CHECK-NOV-NEXT: blt s1, a2, .LBB8_2
; CHECK-NOV-NEXT: .LBB8_7: # %entry
-; CHECK-NOV-NEXT: mv s1, a3
-; CHECK-NOV-NEXT: fcvt.l.s a2, fs0, rtz
-; CHECK-NOV-NEXT: blt a1, a3, .LBB8_3
+; CHECK-NOV-NEXT: mv s1, a2
+; CHECK-NOV-NEXT: fcvt.l.s a3, fs0, rtz
+; CHECK-NOV-NEXT: blt a1, a2, .LBB8_3
; CHECK-NOV-NEXT: .LBB8_8: # %entry
-; CHECK-NOV-NEXT: mv a1, a3
-; CHECK-NOV-NEXT: bge a2, a3, .LBB8_4
+; CHECK-NOV-NEXT: mv a1, a2
+; CHECK-NOV-NEXT: bge a3, a2, .LBB8_4
; CHECK-NOV-NEXT: j .LBB8_5
;
; CHECK-V-LABEL: ustest_f16i32:
@@ -977,23 +977,23 @@ entry:
define <2 x i16> @ustest_f64i16(<2 x double> %x) {
; CHECK-NOV-LABEL: ustest_f64i16:
; CHECK-NOV: # %bb.0: # %entry
-; CHECK-NOV-NEXT: fcvt.w.d a0, fa0, rtz
+; CHECK-NOV-NEXT: fcvt.w.d a1, fa1, rtz
; CHECK-NOV-NEXT: lui a2, 16
; CHECK-NOV-NEXT: addi a2, a2, -1
-; CHECK-NOV-NEXT: fcvt.w.d a1, fa1, rtz
-; CHECK-NOV-NEXT: blt a0, a2, .LBB11_2
+; CHECK-NOV-NEXT: fcvt.w.d a0, fa0, rtz
+; CHECK-NOV-NEXT: blt a1, a2, .LBB11_2
; CHECK-NOV-NEXT: # %bb.1: # %entry
-; CHECK-NOV-NEXT: mv a0, a2
+; CHECK-NOV-NEXT: mv a1, a2
; CHECK-NOV-NEXT: .LBB11_2: # %entry
-; CHECK-NOV-NEXT: blt a1, a2, .LBB11_4
+; CHECK-NOV-NEXT: blt a0, a2, .LBB11_4
; CHECK-NOV-NEXT: # %bb.3: # %entry
-; CHECK-NOV-NEXT: mv a1, a2
+; CHECK-NOV-NEXT: mv a0, a2
; CHECK-NOV-NEXT: .LBB11_4: # %entry
+; CHECK-NOV-NEXT: sgtz a2, a0
+; CHECK-NOV-NEXT: neg a2, a2
+; CHECK-NOV-NEXT: and a0, a2, a0
; CHECK-NOV-NEXT: sgtz a2, a1
-; CHECK-NOV-NEXT: sgtz a3, a0
-; CHECK-NOV-NEXT: neg a3, a3
; CHECK-NOV-NEXT: neg a2, a2
-; CHECK-NOV-NEXT: and a0, a3, a0
; CHECK-NOV-NEXT: and a1, a2, a1
; CHECK-NOV-NEXT: ret
;
@@ -1146,50 +1146,50 @@ entry:
define <4 x i16> @ustest_f32i16(<4 x float> %x) {
; CHECK-NOV-LABEL: ustest_f32i16:
; CHECK-NOV: # %bb.0: # %entry
-; CHECK-NOV-NEXT: fcvt.w.s a1, fa0, rtz
-; CHECK-NOV-NEXT: lui a5, 16
-; CHECK-NOV-NEXT: addi a5, a5, -1
-; CHECK-NOV-NEXT: fcvt.w.s a2, fa1, rtz
-; CHECK-NOV-NEXT: bge a1, a5, .LBB14_6
+; CHECK-NOV-NEXT: fcvt.w.s a1, fa3, rtz
+; CHECK-NOV-NEXT: lui a3, 16
+; CHECK-NOV-NEXT: addi a3, a3, -1
+; CHECK-NOV-NEXT: fcvt.w.s a2, fa2, rtz
+; CHECK-NOV-NEXT: bge a1, a3, .LBB14_6
; CHECK-NOV-NEXT: # %bb.1: # %entry
-; CHECK-NOV-NEXT: fcvt.w.s a3, fa2, rtz
-; CHECK-NOV-NEXT: bge a2, a5, .LBB14_7
+; CHECK-NOV-NEXT: fcvt.w.s a4, fa1, rtz
+; CHECK-NOV-NEXT: bge a2, a3, .LBB14_7
; CHECK-NOV-NEXT: .LBB14_2: # %entry
-; CHECK-NOV-NEXT: fcvt.w.s a4, fa3, rtz
-; CHECK-NOV-NEXT: bge a3, a5, .LBB14_8
+; CHECK-NOV-NEXT: fcvt.w.s a5, fa0, rtz
+; CHECK-NOV-NEXT: bge a4, a3, .LBB14_8
; CHECK-NOV-NEXT: .LBB14_3: # %entry
-; CHECK-NOV-NEXT: blt a4, a5, .LBB14_5
+; CHECK-NOV-NEXT: blt a5, a3, .LBB14_5
; CHECK-NOV-NEXT: .LBB14_4: # %entry
-; CHECK-NOV-NEXT: mv a4, a5
+; CHECK-NOV-NEXT: mv a5, a3
; CHECK-NOV-NEXT: .LBB14_5: # %entry
+; CHECK-NOV-NEXT: sgtz a3, a5
+; CHECK-NOV-NEXT: neg a3, a3
+; CHECK-NOV-NEXT: and a3, a3, a5
; CHECK-NOV-NEXT: sgtz a5, a4
-; CHECK-NOV-NEXT: sgtz a6, a3
-; CHECK-NOV-NEXT: sgtz a7, a2
-; CHECK-NOV-NEXT: sgtz t0, a1
-; CHECK-NOV-NEXT: neg t0, t0
-; CHECK-NOV-NEXT: neg a7, a7
-; CHECK-NOV-NEXT: neg a6, a6
; CHECK-NOV-NEXT: neg a5, a5
-; CHECK-NOV-NEXT: and a1, t0, a1
-; CHECK-NOV-NEXT: and a2, a7, a2
-; CHECK-NOV-NEXT: and a3, a6, a3
; CHECK-NOV-NEXT: and a4, a5, a4
-; CHECK-NOV-NEXT: sh a1, 0(a0)
-; CHECK-NOV-NEXT: sh a2, 2(a0)
-; CHECK-NOV-NEXT: sh a3, 4(a0)
-; CHECK-NOV-NEXT: sh a4, 6(a0)
+; CHECK-NOV-NEXT: sgtz a5, a2
+; CHECK-NOV-NEXT: neg a5, a5
+; CHECK-NOV-NEXT: and a2, a5, a2
+; CHECK-NOV-NEXT: sgtz a5, a1
+; CHECK-NOV-NEXT: neg a5, a5
+; CHECK-NOV-NEXT: and a1, a5, a1
+; CHECK-NOV-NEXT: sh a3, 0(a0)
+; CHECK-NOV-NEXT: sh a4, 2(a0)
+; CHECK-NOV-NEXT: sh a2, 4(a0)
+; CHECK-NOV-NEXT: sh a1, 6(a0)
; CHECK-NOV-NEXT: ret
; CHECK-NOV-NEXT: .LBB14_6: # %entry
-; CHECK-NOV-NEXT: mv a1, a5
-; CHECK-NOV-NEXT: fcvt.w.s a3, fa2, rtz
-; CHECK-NOV-NEXT: blt a2, a5, .LBB14_2
+; CHECK-NOV-NEXT: mv a1, a3
+; CHECK-NOV-NEXT: fcvt.w.s a4, fa1, rtz
+; CHECK-NOV-NEXT: blt a2, a3, .LBB14_2
; CHECK-NOV-NEXT: .LBB14_7: # %entry
-; CHECK-NOV-NEXT: mv a2, a5
-; CHECK-NOV-NEXT: fcvt.w.s a4, fa3, rtz
-; CHECK-NOV-NEXT: blt a3, a5, .LBB14_3
+; CHECK-NOV-NEXT: mv a2, a3
+; CHECK-NOV-NEXT: fcvt.w.s a5, fa0, rtz
+; CHECK-NOV-NEXT: blt a4, a3, .LBB14_3
; CHECK-NOV-NEXT: .LBB14_8: # %entry
-; CHECK-NOV-NEXT: mv a3, a5
-; CHECK-NOV-NEXT: bge a4, a5, .LBB14_4
+; CHECK-NOV-NEXT: mv a4, a3
+; CHECK-NOV-NEXT: bge a5, a3, .LBB14_4
; CHECK-NOV-NEXT: j .LBB14_5
;
; CHECK-V-LABEL: ustest_f32i16:
@@ -1974,96 +1974,96 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) {
; CHECK-NOV-NEXT: .cfi_remember_state
; CHECK-NOV-NEXT: lhu s1, 32(a1)
; CHECK-NOV-NEXT: lhu s2, 40(a1)
-; CHECK-NOV-NEXT: lhu s3, 48(a1)
-; CHECK-NOV-NEXT: lhu s4, 56(a1)
-; CHECK-NOV-NEXT: lhu s5, 0(a1)
-; CHECK-NOV-NEXT: lhu a2, 8(a1)
+; CHECK-NOV-NEXT: lhu a2, 48(a1)
+; CHECK-NOV-NEXT: lhu s3, 56(a1)
+; CHECK-NOV-NEXT: lhu s4, 0(a1)
+; CHECK-NOV-NEXT: lhu s5, 8(a1)
; CHECK-NOV-NEXT: lhu s6, 16(a1)
; CHECK-NOV-NEXT: lhu s7, 24(a1)
; CHECK-NOV-NEXT: mv s0, a0
; CHECK-NOV-NEXT: fmv.w.x fa0, a2
; CHECK-NOV-NEXT: call __extendhfsf2
; CHECK-NOV-NEXT: fmv.s fs6, fa0
-; CHECK-NOV-NEXT: fmv.w.x fa0, s6
+; CHECK-NOV-NEXT: fmv.w.x fa0, s2
; CHECK-NOV-NEXT: call __extendhfsf2
; CHECK-NOV-NEXT: fmv.s fs5, fa0
-; CHECK-NOV-NEXT: fmv.w.x fa0, s7
+; CHECK-NOV-NEXT: fmv.w.x fa0, s1
; CHECK-NOV-NEXT: call __extendhfsf2
; CHECK-NOV-NEXT: fmv.s fs4, fa0
-; CHECK-NOV-NEXT: fmv.w.x fa0, s1
+; CHECK-NOV-NEXT: fmv.w.x fa0, s7
; CHECK-NOV-NEXT: call __extendhfsf2
; CHECK-NOV-NEXT: fmv.s fs3, fa0
-; CHECK-NOV-NEXT: fmv.w.x fa0, s2
+; CHECK-NOV-NEXT: fmv.w.x fa0, s6
; CHECK-NOV-NEXT: call __extendhfsf2
; CHECK-NOV-NEXT: fmv.s fs2, fa0
-; CHECK-NOV-NEXT: fmv.w.x fa0, s3
+; CHECK-NOV-NEXT: fmv.w.x fa0, s5
; CHECK-NOV-NEXT: call __extendhfsf2
; CHECK-NOV-NEXT: fmv.s fs1, fa0
; CHECK-NOV-NEXT: fmv.w.x fa0, s4
; CHECK-NOV-NEXT: call __extendhfsf2
; CHECK-NOV-NEXT: fmv.s fs0, fa0
-; CHECK-NOV-NEXT: fmv.w.x fa0, s5
+; CHECK-NOV-NEXT: fmv.w.x fa0, s3
; CHECK-NOV-NEXT: fcvt.l.s s1, fs6, rtz
; CHECK-NOV-NEXT: call __extendhfsf2
; CHECK-NOV-NEXT: fcvt.l.s a0, fa0, rtz
-; CHECK-NOV-NEXT: lui a5, 16
-; CHECK-NOV-NEXT: addi a5, a5, -1
-; CHECK-NOV-NEXT: bge a0, a5, .LBB17_10
+; CHECK-NOV-NEXT: lui a3, 16
+; CHECK-NOV-NEXT: addi a3, a3, -1
+; CHECK-NOV-NEXT: bge a0, a3, .LBB17_10
; CHECK-NOV-NEXT: # %bb.1: # %entry
; CHECK-NOV-NEXT: fcvt.l.s a1, fs5, rtz
-; CHECK-NOV-NEXT: bge s1, a5, .LBB17_11
+; CHECK-NOV-NEXT: bge s1, a3, .LBB17_11
; CHECK-NOV-NEXT: .LBB17_2: # %entry
; CHECK-NOV-NEXT: fcvt.l.s a2, fs4, rtz
-; CHECK-NOV-NEXT: bge a1, a5, .LBB17_12
+; CHECK-NOV-NEXT: bge a1, a3, .LBB17_12
; CHECK-NOV-NEXT: .LBB17_3: # %entry
-; CHECK-NOV-NEXT: fcvt.l.s a3, fs3, rtz
-; CHECK-NOV-NEXT: bge a2, a5, .LBB17_13
+; CHECK-NOV-NEXT: fcvt.l.s a4, fs3, rtz
+; CHECK-NOV-NEXT: bge a2, a3, .LBB17_13
; CHECK-NOV-NEXT: .LBB17_4: # %entry
-; CHECK-NOV-NEXT: fcvt.l.s a4, fs2, rtz
-; CHECK-NOV-NEXT: bge a3, a5, .LBB17_14
+; CHECK-NOV-NEXT: fcvt.l.s a5, fs2, rtz
+; CHECK-NOV-NEXT: bge a4, a3, .LBB17_14
; CHECK-NOV-NEXT: .LBB17_5: # %entry
; CHECK-NOV-NEXT: fcvt.l.s a6, fs1, rtz
-; CHECK-NOV-NEXT: bge a4, a5, .LBB17_15
+; CHECK-NOV-NEXT: bge a5, a3, .LBB17_15
; CHECK-NOV-NEXT: .LBB17_6: # %entry
; CHECK-NOV-NEXT: fcvt.l.s a7, fs0, rtz
-; CHECK-NOV-NEXT: bge a6, a5, .LBB17_16
+; CHECK-NOV-NEXT: bge a6, a3, .LBB17_16
; CHECK-NOV-NEXT: .LBB17_7: # %entry
-; CHECK-NOV-NEXT: blt a7, a5, .LBB17_9
+; CHECK-NOV-NEXT: blt a7, a3, .LBB17_9
; CHECK-NOV-NEXT: .LBB17_8: # %entry
-; CHECK-NOV-NEXT: mv a7, a5
+; CHECK-NOV-NEXT: mv a7, a3
; CHECK-NOV-NEXT: .LBB17_9: # %entry
-; CHECK-NOV-NEXT: sgtz a5, a7
-; CHECK-NOV-NEXT: sgtz t0, a6
-; CHECK-NOV-NEXT: sgtz t1, a4
-; CHECK-NOV-NEXT: sgtz t2, a3
-; CHECK-NOV-NEXT: sgtz t3, a2
-; CHECK-NOV-NEXT: sgtz t4, a1
-; CHECK-NOV-NEXT: sgtz t5, s1
-; CHECK-NOV-NEXT: sgtz t6, a0
-; CHECK-NOV-NEXT: neg t6, t6
-; CHECK-NOV-NEXT: neg t5, t5
-; CHECK-NOV-NEXT: neg t4, t4
-; CHECK-NOV-NEXT: neg t3, t3
-; CHECK-NOV-NEXT: neg t2, t2
-; CHECK-NOV-NEXT: neg t1, t1
+; CHECK-NOV-NEXT: sgtz a3, a7
+; CHECK-NOV-NEXT: neg a3, a3
+; CHECK-NOV-NEXT: and a3, a3, a7
+; CHECK-NOV-NEXT: sgtz a7, a6
+; CHECK-NOV-NEXT: neg a7, a7
+; CHECK-NOV-NEXT: and a6, a7, a6
+; CHECK-NOV-NEXT: sgtz a7, a5
+; CHECK-NOV-NEXT: neg a7, a7
+; CHECK-NOV-NEXT: and a5, a7, a5
+; CHECK-NOV-NEXT: sgtz a7, a4
+; CHECK-NOV-NEXT: neg a7, a7
+; CHECK-NOV-NEXT: and a4, a7, a4
+; CHECK-NOV-NEXT: sgtz a7, a2
+; CHECK-NOV-NEXT: neg a7, a7
+; CHECK-NOV-NEXT: and a2, a7, a2
+; CHECK-NOV-NEXT: sgtz a7, a1
+; CHECK-NOV-NEXT: neg a7, a7
+; CHECK-NOV-NEXT: and a1, a7, a1
+; CHECK-NOV-NEXT: sgtz a7, s1
+; CHECK-NOV-NEXT: neg a7, a7
+; CHECK-NOV-NEXT: and a7, a7, s1
+; CHECK-NOV-NEXT: sgtz t0, a0
; CHECK-NOV-NEXT: neg t0, t0
-; CHECK-NOV-NEXT: neg a5, a5
-; CHECK-NOV-NEXT: and a0, t6, a0
-; CHECK-NOV-NEXT: and t5, t5, s1
-; CHECK-NOV-NEXT: and a1, t4, a1
-; CHECK-NOV-NEXT: and a2, t3, a2
-; CHECK-NOV-NEXT: and a3, t2, a3
-; CHECK-NOV-NEXT: and a4, t1, a4
-; CHECK-NOV-NEXT: and a6, t0, a6
-; CHECK-NOV-NEXT: and a5, a5, a7
-; CHECK-NOV-NEXT: sh a3, 8(s0)
-; CHECK-NOV-NEXT: sh a4, 10(s0)
-; CHECK-NOV-NEXT: sh a6, 12(s0)
-; CHECK-NOV-NEXT: sh a5, 14(s0)
-; CHECK-NOV-NEXT: sh a0, 0(s0)
-; CHECK-NOV-NEXT: sh t5, 2(s0)
-; CHECK-NOV-NEXT: sh a1, 4(s0)
-; CHECK-NOV-NEXT: sh a2, 6(s0)
+; CHECK-NOV-NEXT: and a0, t0, a0
+; CHECK-NOV-NEXT: sh a2, 8(s0)
+; CHECK-NOV-NEXT: sh a1, 10(s0)
+; CHECK-NOV-NEXT: sh a7, 12(s0)
+; CHECK-NOV-NEXT: sh a0, 14(s0)
+; CHECK-NOV-NEXT: sh a3, 0(s0)
+; CHECK-NOV-NEXT: sh a6, 2(s0)
+; CHECK-NOV-NEXT: sh a5, 4(s0)
+; CHECK-NOV-NEXT: sh a4, 6(s0)
; CHECK-NOV-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; CHECK-NOV-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; CHECK-NOV-NEXT: ld s1, 104(sp) # 8-byte Folded Reload
@@ -2101,32 +2101,32 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) {
; CHECK-NOV-NEXT: ret
; CHECK-NOV-NEXT: .LBB17_10: # %entry
; CHECK-NOV-NEXT: .cfi_restore_state
-; CHECK-NOV-NEXT: mv a0, a5
+; CHECK-NOV-NEXT: mv a0, a3
; CHECK-NOV-NEXT: fcvt.l.s a1, fs5, rtz
-; CHECK-NOV-NEXT: blt s1, a5, .LBB17_2
+; CHECK-NOV-NEXT: blt s1, a3, .LBB17_2
; CHECK-NOV-NEXT: .LBB17_11: # %entry
-; CHECK-NOV-NEXT: mv s1, a5
+; CHECK-NOV-NEXT: mv s1, a3
; CHECK-NOV-NEXT: fcvt.l.s a2, fs4, rtz
-; CHECK-NOV-NEXT: blt a1, a5, .LBB17_3
+; CHECK-NOV-NEXT: blt a1, a3, .LBB17_3
; CHECK-NOV-NEXT: .LBB17_12: # %entry
-; CHECK-NOV-NEXT: mv a1, a5
-; CHECK-NOV-NEXT: fcvt.l.s a3, fs3, rtz
-; CHECK-NOV-NEXT: blt a2, a5, .LBB17_4
+; CHECK-NOV-NEXT: mv a1, a3
+; CHECK-NOV-NEXT: fcvt.l.s a4, fs3, rtz
+; CHECK-NOV-NEXT: blt a2, a3, .LBB17_4
; CHECK-NOV-NEXT: .LBB17_13: # %entry
-; CHECK-NOV-NEXT: mv a2, a5
-; CHECK-NOV-NEXT: fcvt.l.s a4, fs2, rtz
-; CHECK-NOV-NEXT: blt a3, a5, .LBB17_5
+; CHECK-NOV-NEXT: mv a2, a3
+; CHECK-NOV-NEXT: fcvt.l.s a5, fs2, rtz
+; CHECK-NOV-NEXT: blt a4, a3, .LBB17_5
; CHECK-NOV-NEXT: .LBB17_14: # %entry
-; CHECK-NOV-NEXT: mv a3, a5
+; CHECK-NOV-NEXT: mv a4, a3
; CHECK-NOV-NEXT: fcvt.l.s a6, fs1, rtz
-; CHECK-NOV-NEXT: blt a4, a5, .LBB17_6
+; CHECK-NOV-NEXT: blt a5, a3, .LBB17_6
; CHECK-NOV-NEXT: .LBB17_15: # %entry
-; CHECK-NOV-NEXT: mv a4, a5
+; CHECK-NOV-NEXT: mv a5, a3
; CHECK-NOV-NEXT: fcvt.l.s a7, fs0, rtz
-; CHECK-NOV-NEXT: blt a6, a5, .LBB17_7
+; CHECK-NOV-NEXT: blt a6, a3, .LBB17_7
; CHECK-NOV-NEXT: .LBB17_16: # %entry
-; CHECK-NOV-NEXT: mv a6, a5
-; CHECK-NOV-NEXT: bge a7, a5, .LBB17_8
+; CHECK-NOV-NEXT: mv a6, a3
+; CHECK-NOV-NEXT: bge a7, a3, .LBB17_8
; CHECK-NOV-NEXT: j .LBB17_9
;
; CHECK-V-LABEL: ustest_f16i16:
diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll
index 299fe89a05328..ddd5247d9077a 100644
--- a/llvm/test/CodeGen/RISCV/select-cc.ll
+++ b/llvm/test/CodeGen/RISCV/select-cc.ll
@@ -27,7 +27,7 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_6:
; RV32I-NEXT: lw a2, 0(a1)
-; RV32I-NEXT: bgeu a0, a2, .LBB0_8
+; RV32I-NEXT: bltu a2, a0, .LBB0_8
; RV32I-NEXT: # %bb.7:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_8:
@@ -37,7 +37,7 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_10:
; RV32I-NEXT: lw a2, 0(a1)
-; RV32I-NEXT: bgeu a2, a0, .LBB0_12
+; RV32I-NEXT: bltu a0, a2, .LBB0_12
; RV32I-NEXT: # %bb.11:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_12:
@@ -47,7 +47,7 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_14:
; RV32I-NEXT: lw a2, 0(a1)
-; RV32I-NEXT: bge a0, a2, .LBB0_16
+; RV32I-NEXT: blt a2, a0, .LBB0_16
; RV32I-NEXT: # %bb.15:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_16:
@@ -57,7 +57,7 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_18:
; RV32I-NEXT: lw a2, 0(a1)
-; RV32I-NEXT: bge a2, a0, .LBB0_20
+; RV32I-NEXT: blt a0, a2, .LBB0_20
; RV32I-NEXT: # %bb.19:
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_20:
@@ -96,19 +96,19 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
; RV32IXQCI-NEXT: lw a2, 0(a1)
; RV32IXQCI-NEXT: qc.mvgeu a0, a4, a0, a4
; RV32IXQCI-NEXT: lw a3, 0(a1)
-; RV32IXQCI-NEXT: qc.mvltu a0, a0, a5, a5
+; RV32IXQCI-NEXT: qc.mvgeu a0, a5, a0, a5
; RV32IXQCI-NEXT: lw a4, 0(a1)
; RV32IXQCI-NEXT: qc.mvgeu a0, a0, a2, a2
; RV32IXQCI-NEXT: lw a2, 0(a1)
-; RV32IXQCI-NEXT: qc.mvltu a0, a3, a0, a3
+; RV32IXQCI-NEXT: qc.mvgeu a0, a0, a3, a3
; RV32IXQCI-NEXT: lw a3, 0(a1)
; RV32IXQCI-NEXT: qc.mvge a0, a4, a0, a4
; RV32IXQCI-NEXT: lw a4, 0(a1)
-; RV32IXQCI-NEXT: qc.mvlt a0, a0, a2, a2
+; RV32IXQCI-NEXT: qc.mvge a0, a2, a0, a2
; RV32IXQCI-NEXT: lw a2, 0(a1)
; RV32IXQCI-NEXT: qc.mvge a0, a0, a3, a3
; RV32IXQCI-NEXT: lw a3, 0(a1)
-; RV32IXQCI-NEXT: qc.mvlt a0, a4, a0, a4
+; RV32IXQCI-NEXT: qc.mvge a0, a0, a4, a4
; RV32IXQCI-NEXT: lw a4, 0(a1)
; RV32IXQCI-NEXT: lw a1, 0(a1)
; RV32IXQCI-NEXT: blez a2, .LBB0_2
@@ -140,7 +140,7 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_6:
; RV64I-NEXT: lw a2, 0(a1)
-; RV64I-NEXT: bgeu a0, a2, .LBB0_8
+; RV64I-NEXT: bltu a2, a0, .LBB0_8
; RV64I-NEXT: # %bb.7:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_8:
@@ -150,7 +150,7 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_10:
; RV64I-NEXT: lw a2, 0(a1)
-; RV64I-NEXT: bgeu a2, a0, .LBB0_12
+; RV64I-NEXT: bltu a0, a2, .LBB0_12
; RV64I-NEXT: # %bb.11:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_12:
@@ -160,7 +160,7 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_14:
; RV64I-NEXT: lw a2, 0(a1)
-; RV64I-NEXT: bge a0, a2, .LBB0_16
+; RV64I-NEXT: blt a2, a0, .LBB0_16
; RV64I-NEXT: # %bb.15:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_16:
@@ -170,7 +170,7 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_18:
; RV64I-NEXT: lw a2, 0(a1)
-; RV64I-NEXT: bge a2, a0, .LBB0_20
+; RV64I-NEXT: blt a0, a2, .LBB0_20
; RV64I-NEXT: # %bb.19:
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: .LBB0_20:
@@ -212,30 +212,26 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
; RV64I-CCMOV-NEXT: sltu a3, a4, a0
; RV64I-CCMOV-NEXT: mips.ccmov a0, a3, a0, a4
; RV64I-CCMOV-NEXT: lw a3, 0(a1)
-; RV64I-CCMOV-NEXT: sltu a4, a0, a5
-; RV64I-CCMOV-NEXT: mips.ccmov a0, a4, a5, a0
+; RV64I-CCMOV-NEXT: sltu a4, a5, a0
+; RV64I-CCMOV-NEXT: mips.ccmov a0, a4, a0, a5
; RV64I-CCMOV-NEXT: lw a4, 0(a1)
; RV64I-CCMOV-NEXT: sltu a5, a0, a2
; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a0, a2
; RV64I-CCMOV-NEXT: lw a2, 0(a1)
-; RV64I-CCMOV-NEXT: sltu a5, a3, a0
-; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a3, a0
+; RV64I-CCMOV-NEXT: sltu a5, a0, a3
+; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a0, a3
; RV64I-CCMOV-NEXT: lw a3, 0(a1)
-; RV64I-CCMOV-NEXT: sext.w a5, a0
-; RV64I-CCMOV-NEXT: slt a5, a4, a5
+; RV64I-CCMOV-NEXT: slt a5, a4, a0
; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a0, a4
; RV64I-CCMOV-NEXT: lw a4, 0(a1)
-; RV64I-CCMOV-NEXT: sext.w a5, a0
-; RV64I-CCMOV-NEXT: slt a5, a5, a2
-; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a2, a0
+; RV64I-CCMOV-NEXT: slt a5, a2, a0
+; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a0, a2
; RV64I-CCMOV-NEXT: lw a2, 0(a1)
-; RV64I-CCMOV-NEXT: sext.w a5, a0
-; RV64I-CCMOV-NEXT: slt a5, a5, a3
+; RV64I-CCMOV-NEXT: slt a5, a0, a3
; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a0, a3
; RV64I-CCMOV-NEXT: lw a3, 0(a1)
-; RV64I-CCMOV-NEXT: sext.w a5, a0
-; RV64I-CCMOV-NEXT: slt a5, a4, a5
-; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a4, a0
+; RV64I-CCMOV-NEXT: slt a5, a0, a4
+; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a0, a4
; RV64I-CCMOV-NEXT: lw a4, 0(a1)
; RV64I-CCMOV-NEXT: slti a5, a2, 1
; RV64I-CCMOV-NEXT: mips.ccmov a0, a5, a0, a2
@@ -246,7 +242,6 @@ define signext i32 @foo(i32 signext %a, ptr %b) nounwind {
; RV64I-CCMOV-NEXT: mips.ccmov a0, a3, a4, a0
; RV64I-CCMOV-NEXT: sltiu a2, a2, 2047
; RV64I-CCMOV-NEXT: mips.ccmov a0, a2, a1, a0
-; RV64I-CCMOV-NEXT: sext.w a0, a0
; RV64I-CCMOV-NEXT: ret
%val1 = load volatile i32, ptr %b
%tst1 = icmp eq i32 %a, %val1
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
index d107e5d1dc2e5..bd05b47942992 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-03.ll
@@ -19,7 +19,7 @@ define i32 @f1(i32 %dummy, ptr %src, i32 %b) {
; CHECK-NEXT: .LBB0_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lr %r0, %r2
-; CHECK-NEXT: crjle %r2, %r4, .LBB0_1
+; CHECK-NEXT: crjl %r2, %r4, .LBB0_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: lr %r0, %r4
@@ -67,7 +67,7 @@ define i32 @f3(i32 %dummy, ptr %src, i32 %b) {
; CHECK-NEXT: .LBB2_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lr %r0, %r2
-; CHECK-NEXT: clrjle %r2, %r4, .LBB2_1
+; CHECK-NEXT: clrjl %r2, %r4, .LBB2_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1
; CHECK-NEXT: lr %r0, %r4
@@ -115,7 +115,7 @@ define i32 @f5(i32 %dummy, ptr %src, i32 %b) {
; CHECK-NEXT: .LBB4_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lr %r0, %r2
-; CHECK-NEXT: crjle %r2, %r4, .LBB4_1
+; CHECK-NEXT: crjl %r2, %r4, .LBB4_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1
; CHECK-NEXT: lr %r0, %r4
@@ -140,7 +140,7 @@ define i32 @f6(i32 %dummy, ptr %src, i32 %b) {
; CHECK-NEXT: .LBB5_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lr %r0, %r2
-; CHECK-NEXT: crjle %r2, %r4, .LBB5_1
+; CHECK-NEXT: crjl %r2, %r4, .LBB5_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1
; CHECK-NEXT: lr %r0, %r4
@@ -165,7 +165,7 @@ define i32 @f7(i32 %dummy, ptr %src, i32 %b) {
; CHECK-NEXT: .LBB6_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lr %r0, %r2
-; CHECK-NEXT: crjle %r2, %r4, .LBB6_1
+; CHECK-NEXT: crjl %r2, %r4, .LBB6_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB6_2 Depth=1
; CHECK-NEXT: lr %r0, %r4
@@ -191,7 +191,7 @@ define i32 @f8(i32 %dummy, ptr %src, i32 %b) {
; CHECK-NEXT: .LBB7_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lr %r0, %r2
-; CHECK-NEXT: crjle %r2, %r4, .LBB7_1
+; CHECK-NEXT: crjl %r2, %r4, .LBB7_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB7_2 Depth=1
; CHECK-NEXT: lr %r0, %r4
@@ -216,7 +216,7 @@ define i32 @f9(i32 %dummy, ptr %src, i32 %b) {
; CHECK-NEXT: .LBB8_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lr %r0, %r2
-; CHECK-NEXT: crjle %r2, %r4, .LBB8_1
+; CHECK-NEXT: crjl %r2, %r4, .LBB8_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB8_2 Depth=1
; CHECK-NEXT: lr %r0, %r4
@@ -241,7 +241,7 @@ define i32 @f10(i32 %dummy, ptr %src, i32 %b) {
; CHECK-NEXT: .LBB9_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lr %r0, %r2
-; CHECK-NEXT: crjle %r2, %r4, .LBB9_1
+; CHECK-NEXT: crjl %r2, %r4, .LBB9_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB9_2 Depth=1
; CHECK-NEXT: lr %r0, %r4
@@ -267,7 +267,7 @@ define i32 @f11(i32 %dummy, ptr %src, i32 %b) {
; CHECK-NEXT: .LBB10_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lr %r0, %r2
-; CHECK-NEXT: crjle %r2, %r4, .LBB10_1
+; CHECK-NEXT: crjl %r2, %r4, .LBB10_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB10_2 Depth=1
; CHECK-NEXT: lr %r0, %r4
@@ -293,7 +293,7 @@ define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) {
; CHECK-NEXT: .LBB11_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lr %r0, %r2
-; CHECK-NEXT: crjle %r2, %r5, .LBB11_1
+; CHECK-NEXT: crjl %r2, %r5, .LBB11_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB11_2 Depth=1
; CHECK-NEXT: lr %r0, %r5
@@ -319,7 +319,7 @@ define i32 @f13(i32 %dummy, ptr %ptr) {
; CHECK-NEXT: .LBB12_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lr %r0, %r2
-; CHECK-NEXT: cijl %r2, 43, .LBB12_1
+; CHECK-NEXT: cijl %r2, 42, .LBB12_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB12_2 Depth=1
; CHECK-NEXT: lhi %r0, 42
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
index 9352118a32f8a..63ad30b2e0435 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-minmax-04.ll
@@ -19,7 +19,7 @@ define i64 @f1(i64 %dummy, ptr %src, i64 %b) {
; CHECK-NEXT: .LBB0_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lgr %r0, %r2
-; CHECK-NEXT: cgrjle %r2, %r4, .LBB0_1
+; CHECK-NEXT: cgrjl %r2, %r4, .LBB0_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB0_2 Depth=1
; CHECK-NEXT: lgr %r0, %r4
@@ -67,7 +67,7 @@ define i64 @f3(i64 %dummy, ptr %src, i64 %b) {
; CHECK-NEXT: .LBB2_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lgr %r0, %r2
-; CHECK-NEXT: clgrjle %r2, %r4, .LBB2_1
+; CHECK-NEXT: clgrjl %r2, %r4, .LBB2_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1
; CHECK-NEXT: lgr %r0, %r4
@@ -115,7 +115,7 @@ define i64 @f5(i64 %dummy, ptr %src, i64 %b) {
; CHECK-NEXT: .LBB4_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lgr %r0, %r2
-; CHECK-NEXT: cgrjle %r2, %r4, .LBB4_1
+; CHECK-NEXT: cgrjl %r2, %r4, .LBB4_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB4_2 Depth=1
; CHECK-NEXT: lgr %r0, %r4
@@ -141,7 +141,7 @@ define i64 @f6(i64 %dummy, ptr %src, i64 %b) {
; CHECK-NEXT: .LBB5_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lgr %r0, %r2
-; CHECK-NEXT: cgrjle %r2, %r4, .LBB5_1
+; CHECK-NEXT: cgrjl %r2, %r4, .LBB5_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB5_2 Depth=1
; CHECK-NEXT: lgr %r0, %r4
@@ -166,7 +166,7 @@ define i64 @f7(i64 %dummy, ptr %src, i64 %b) {
; CHECK-NEXT: .LBB6_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lgr %r0, %r2
-; CHECK-NEXT: cgrjle %r2, %r4, .LBB6_1
+; CHECK-NEXT: cgrjl %r2, %r4, .LBB6_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB6_2 Depth=1
; CHECK-NEXT: lgr %r0, %r4
@@ -192,7 +192,7 @@ define i64 @f8(i64 %dummy, ptr %src, i64 %b) {
; CHECK-NEXT: .LBB7_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lgr %r0, %r2
-; CHECK-NEXT: cgrjle %r2, %r4, .LBB7_1
+; CHECK-NEXT: cgrjl %r2, %r4, .LBB7_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB7_2 Depth=1
; CHECK-NEXT: lgr %r0, %r4
@@ -218,7 +218,7 @@ define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) {
; CHECK-NEXT: .LBB8_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lgr %r0, %r2
-; CHECK-NEXT: cgrjle %r2, %r5, .LBB8_1
+; CHECK-NEXT: cgrjl %r2, %r5, .LBB8_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB8_2 Depth=1
; CHECK-NEXT: lgr %r0, %r5
@@ -244,7 +244,7 @@ define i64 @f10(i64 %dummy, ptr %ptr) {
; CHECK-NEXT: .LBB9_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lgr %r0, %r2
-; CHECK-NEXT: cgijl %r2, 43, .LBB9_1
+; CHECK-NEXT: cgijl %r2, 42, .LBB9_1
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB9_2 Depth=1
; CHECK-NEXT: lghi %r0, 42
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
index 09edd6eb227af..ceefb787d58f6 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-ops-i128.ll
@@ -193,15 +193,15 @@ define i128 @atomicrmw_min(ptr %src, i128 %b) {
; CHECK-NEXT: je .LBB7_6
; CHECK-NEXT: .LBB7_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: vecg %v0, %v1
+; CHECK-NEXT: vecg %v1, %v0
; CHECK-NEXT: jlh .LBB7_4
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB7_2 Depth=1
-; CHECK-NEXT: vchlgs %v2, %v1, %v0
+; CHECK-NEXT: vchlgs %v2, %v0, %v1
; CHECK-NEXT: .LBB7_4: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB7_2 Depth=1
; CHECK-NEXT: vlr %v2, %v1
-; CHECK-NEXT: jnl .LBB7_1
+; CHECK-NEXT: jl .LBB7_1
; CHECK-NEXT: # %bb.5: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB7_2 Depth=1
; CHECK-NEXT: vlr %v2, %v0
@@ -271,15 +271,15 @@ define i128 @atomicrmw_umin(ptr %src, i128 %b) {
; CHECK-NEXT: je .LBB9_6
; CHECK-NEXT: .LBB9_2: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: veclg %v0, %v1
+; CHECK-NEXT: veclg %v1, %v0
; CHECK-NEXT: jlh .LBB9_4
; CHECK-NEXT: # %bb.3: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB9_2 Depth=1
-; CHECK-NEXT: vchlgs %v2, %v1, %v0
+; CHECK-NEXT: vchlgs %v2, %v0, %v1
; CHECK-NEXT: .LBB9_4: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB9_2 Depth=1
; CHECK-NEXT: vlr %v2, %v1
-; CHECK-NEXT: jnl .LBB9_1
+; CHECK-NEXT: jl .LBB9_1
; CHECK-NEXT: # %bb.5: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB9_2 Depth=1
; CHECK-NEXT: vlr %v2, %v0
diff --git a/llvm/test/CodeGen/SystemZ/int-max-01.ll b/llvm/test/CodeGen/SystemZ/int-max-01.ll
index 404a9a159304f..2e1c9136a09f6 100644
--- a/llvm/test/CodeGen/SystemZ/int-max-01.ll
+++ b/llvm/test/CodeGen/SystemZ/int-max-01.ll
@@ -32,18 +32,18 @@ define i128 @f1(i128 %val1, i128 %val2) {
define i128 @f2(i128 %val1, i128 %val2) {
; CHECK-LABEL: f2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: vecg %v0, %v1
+; CHECK-NEXT: vl %v0, 0(%r4), 3
+; CHECK-NEXT: vecg %v1, %v0
; CHECK-NEXT: je .LBB1_3
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: jl .LBB1_4
+; CHECK-NEXT: jnl .LBB1_4
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
; CHECK-NEXT: .LBB1_3:
-; CHECK-NEXT: vchlgs %v2, %v1, %v0
-; CHECK-NEXT: jnl .LBB1_2
+; CHECK-NEXT: vchlgs %v2, %v0, %v1
+; CHECK-NEXT: jl .LBB1_2
; CHECK-NEXT: .LBB1_4:
; CHECK-NEXT: vlr %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
@@ -82,18 +82,18 @@ define i128 @f3(i128 %val1, i128 %val2) {
define i128 @f4(i128 %val1, i128 %val2) {
; CHECK-LABEL: f4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r3), 3
; CHECK-NEXT: vl %v1, 0(%r4), 3
-; CHECK-NEXT: vecg %v0, %v1
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: vecg %v1, %v0
; CHECK-NEXT: je .LBB3_3
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: jl .LBB3_4
+; CHECK-NEXT: jnl .LBB3_4
; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
; CHECK-NEXT: .LBB3_3:
-; CHECK-NEXT: vchlgs %v2, %v1, %v0
-; CHECK-NEXT: jnl .LBB3_2
+; CHECK-NEXT: vchlgs %v2, %v0, %v1
+; CHECK-NEXT: jl .LBB3_2
; CHECK-NEXT: .LBB3_4:
; CHECK-NEXT: vlr %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
@@ -132,18 +132,18 @@ define i128 @f5(i128 %val1, i128 %val2) {
define i128 @f6(i128 %val1, i128 %val2) {
; CHECK-LABEL: f6:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r4), 3
; CHECK-NEXT: vl %v1, 0(%r3), 3
-; CHECK-NEXT: veclg %v0, %v1
+; CHECK-NEXT: vl %v0, 0(%r4), 3
+; CHECK-NEXT: veclg %v1, %v0
; CHECK-NEXT: je .LBB5_3
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: jl .LBB5_4
+; CHECK-NEXT: jnl .LBB5_4
; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
; CHECK-NEXT: .LBB5_3:
-; CHECK-NEXT: vchlgs %v2, %v1, %v0
-; CHECK-NEXT: jnl .LBB5_2
+; CHECK-NEXT: vchlgs %v2, %v0, %v1
+; CHECK-NEXT: jl .LBB5_2
; CHECK-NEXT: .LBB5_4:
; CHECK-NEXT: vlr %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
@@ -182,18 +182,18 @@ define i128 @f7(i128 %val1, i128 %val2) {
define i128 @f8(i128 %val1, i128 %val2) {
; CHECK-LABEL: f8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v0, 0(%r3), 3
; CHECK-NEXT: vl %v1, 0(%r4), 3
-; CHECK-NEXT: veclg %v0, %v1
+; CHECK-NEXT: vl %v0, 0(%r3), 3
+; CHECK-NEXT: veclg %v1, %v0
; CHECK-NEXT: je .LBB7_3
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: jl .LBB7_4
+; CHECK-NEXT: jnl .LBB7_4
; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
; CHECK-NEXT: .LBB7_3:
-; CHECK-NEXT: vchlgs %v2, %v1, %v0
-; CHECK-NEXT: jnl .LBB7_2
+; CHECK-NEXT: vchlgs %v2, %v0, %v1
+; CHECK-NEXT: jl .LBB7_2
; CHECK-NEXT: .LBB7_4:
; CHECK-NEXT: vlr %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
diff --git a/llvm/test/CodeGen/SystemZ/int-min-01.ll b/llvm/test/CodeGen/SystemZ/int-min-01.ll
index 8280be9c61339..008fc4e0bf9c3 100644
--- a/llvm/test/CodeGen/SystemZ/int-min-01.ll
+++ b/llvm/test/CodeGen/SystemZ/int-min-01.ll
@@ -32,18 +32,18 @@ define i128 @f1(i128 %val1, i128 %val2) {
define i128 @f2(i128 %val1, i128 %val2) {
; CHECK-LABEL: f2:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v1, 0(%r3), 3
; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: vecg %v1, %v0
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: vecg %v0, %v1
; CHECK-NEXT: je .LBB1_3
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: jl .LBB1_4
+; CHECK-NEXT: jnl .LBB1_4
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
; CHECK-NEXT: .LBB1_3:
-; CHECK-NEXT: vchlgs %v2, %v0, %v1
-; CHECK-NEXT: jnl .LBB1_2
+; CHECK-NEXT: vchlgs %v2, %v1, %v0
+; CHECK-NEXT: jl .LBB1_2
; CHECK-NEXT: .LBB1_4:
; CHECK-NEXT: vlr %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
@@ -82,18 +82,18 @@ define i128 @f3(i128 %val1, i128 %val2) {
define i128 @f4(i128 %val1, i128 %val2) {
; CHECK-LABEL: f4:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v1, 0(%r4), 3
; CHECK-NEXT: vl %v0, 0(%r3), 3
-; CHECK-NEXT: vecg %v1, %v0
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: vecg %v0, %v1
; CHECK-NEXT: je .LBB3_3
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: jl .LBB3_4
+; CHECK-NEXT: jnl .LBB3_4
; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
; CHECK-NEXT: .LBB3_3:
-; CHECK-NEXT: vchlgs %v2, %v0, %v1
-; CHECK-NEXT: jnl .LBB3_2
+; CHECK-NEXT: vchlgs %v2, %v1, %v0
+; CHECK-NEXT: jl .LBB3_2
; CHECK-NEXT: .LBB3_4:
; CHECK-NEXT: vlr %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
@@ -132,18 +132,18 @@ define i128 @f5(i128 %val1, i128 %val2) {
define i128 @f6(i128 %val1, i128 %val2) {
; CHECK-LABEL: f6:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v1, 0(%r3), 3
; CHECK-NEXT: vl %v0, 0(%r4), 3
-; CHECK-NEXT: veclg %v1, %v0
+; CHECK-NEXT: vl %v1, 0(%r3), 3
+; CHECK-NEXT: veclg %v0, %v1
; CHECK-NEXT: je .LBB5_3
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: jl .LBB5_4
+; CHECK-NEXT: jnl .LBB5_4
; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
; CHECK-NEXT: .LBB5_3:
-; CHECK-NEXT: vchlgs %v2, %v0, %v1
-; CHECK-NEXT: jnl .LBB5_2
+; CHECK-NEXT: vchlgs %v2, %v1, %v0
+; CHECK-NEXT: jl .LBB5_2
; CHECK-NEXT: .LBB5_4:
; CHECK-NEXT: vlr %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
@@ -182,18 +182,18 @@ define i128 @f7(i128 %val1, i128 %val2) {
define i128 @f8(i128 %val1, i128 %val2) {
; CHECK-LABEL: f8:
; CHECK: # %bb.0:
-; CHECK-NEXT: vl %v1, 0(%r4), 3
; CHECK-NEXT: vl %v0, 0(%r3), 3
-; CHECK-NEXT: veclg %v1, %v0
+; CHECK-NEXT: vl %v1, 0(%r4), 3
+; CHECK-NEXT: veclg %v0, %v1
; CHECK-NEXT: je .LBB7_3
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: jl .LBB7_4
+; CHECK-NEXT: jnl .LBB7_4
; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
; CHECK-NEXT: .LBB7_3:
-; CHECK-NEXT: vchlgs %v2, %v0, %v1
-; CHECK-NEXT: jnl .LBB7_2
+; CHECK-NEXT: vchlgs %v2, %v1, %v0
+; CHECK-NEXT: jl .LBB7_2
; CHECK-NEXT: .LBB7_4:
; CHECK-NEXT: vlr %v0, %v1
; CHECK-NEXT: vst %v0, 0(%r2), 3
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/minloop.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/minloop.ll
index bcedcd40ba112..14118976ab627 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/minloop.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/minloop.ll
@@ -37,20 +37,24 @@ define void @arm_min_q31(ptr nocapture readonly %pSrc, i32 %blockSize, ptr nocap
; CHECK-NEXT: ldrd r5, r6, [r0, #-12]
; CHECK-NEXT: ldr r4, [r0, #-4]
; CHECK-NEXT: cmp r12, r5
-; CHECK-NEXT: csel r5, r5, r12, gt
; CHECK-NEXT: csinc r7, r10, r8, le
+; CHECK-NEXT: cmp r5, r12
+; CHECK-NEXT: csel r5, r5, r12, lt
; CHECK-NEXT: cmp r5, r6
; CHECK-NEXT: it gt
; CHECK-NEXT: addgt.w r7, r8, #2
-; CHECK-NEXT: csel r6, r6, r5, gt
+; CHECK-NEXT: cmp r6, r5
+; CHECK-NEXT: csel r6, r6, r5, lt
; CHECK-NEXT: cmp r6, r4
; CHECK-NEXT: it gt
; CHECK-NEXT: addgt.w r7, r8, #3
-; CHECK-NEXT: csel r6, r4, r6, gt
+; CHECK-NEXT: cmp r4, r6
; CHECK-NEXT: add.w r8, r8, #4
+; CHECK-NEXT: csel r6, r4, r6, lt
; CHECK-NEXT: cmp r6, r11
; CHECK-NEXT: csel r10, r8, r7, gt
-; CHECK-NEXT: csel r12, r11, r6, gt
+; CHECK-NEXT: cmp r11, r6
+; CHECK-NEXT: csel r12, r11, r6, lt
; CHECK-NEXT: le lr, .LBB0_5
; CHECK-NEXT: @ %bb.6: @ %while.end.loopexit.unr-lcssa.loopexit
; CHECK-NEXT: ldr r6, [sp] @ 4-byte Reload
@@ -61,14 +65,16 @@ define void @arm_min_q31(ptr nocapture readonly %pSrc, i32 %blockSize, ptr nocap
; CHECK-NEXT: sub.w r1, r1, r9
; CHECK-NEXT: cmp r12, r7
; CHECK-NEXT: csel r10, r1, r10, gt
-; CHECK-NEXT: csel r12, r7, r12, gt
+; CHECK-NEXT: cmp r7, r12
+; CHECK-NEXT: csel r12, r7, r12, lt
; CHECK-NEXT: cmp r6, #1
; CHECK-NEXT: beq .LBB0_10
; CHECK-NEXT: @ %bb.8: @ %while.body.epil.1
; CHECK-NEXT: ldr r7, [r0, #8]
; CHECK-NEXT: cmp r12, r7
; CHECK-NEXT: csinc r10, r10, r1, le
-; CHECK-NEXT: csel r12, r7, r12, gt
+; CHECK-NEXT: cmp r7, r12
+; CHECK-NEXT: csel r12, r7, r12, lt
; CHECK-NEXT: cmp r6, #2
; CHECK-NEXT: beq .LBB0_10
; CHECK-NEXT: @ %bb.9: @ %while.body.epil.2
@@ -76,7 +82,8 @@ define void @arm_min_q31(ptr nocapture readonly %pSrc, i32 %blockSize, ptr nocap
; CHECK-NEXT: cmp r12, r0
; CHECK-NEXT: it gt
; CHECK-NEXT: addgt.w r10, r1, #2
-; CHECK-NEXT: csel r12, r0, r12, gt
+; CHECK-NEXT: cmp r0, r12
+; CHECK-NEXT: csel r12, r0, r12, lt
; CHECK-NEXT: .LBB0_10: @ %while.end
; CHECK-NEXT: str.w r12, [r2]
; CHECK-NEXT: str.w r10, [r3]
diff --git a/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll b/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
index 706a7c34c3df5..153e1fcf755d6 100644
--- a/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
@@ -362,25 +362,25 @@ define i32 @d(i64 %e, i32 %f, i64 %g, i32 %h) {
; CHECK-NEXT: movs r0, #1
; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: csel r7, r2, r0, lt
-; CHECK-NEXT: mov r12, r1
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: cmp r7, #3
-; CHECK-NEXT: it ls
-; CHECK-NEXT: movls r1, #3
; CHECK-NEXT: mov r4, r2
-; CHECK-NEXT: subs r1, r1, r7
+; CHECK-NEXT: mov r12, r1
+; CHECK-NEXT: movs r3, #3
+; CHECK-NEXT: rsb.w r1, r7, #3
+; CHECK-NEXT: movs r2, #0
+; CHECK-NEXT: cmp r3, r7
+; CHECK-NEXT: ldr r5, [sp, #128]
+; CHECK-NEXT: csel r1, r1, r2, hs
; CHECK-NEXT: movw r2, #43691
; CHECK-NEXT: adds r1, #2
; CHECK-NEXT: movt r2, #43690
-; CHECK-NEXT: ldr r6, [sp, #128]
; CHECK-NEXT: movw r8, :lower16:c
+; CHECK-NEXT: mov.w r9, #12
; CHECK-NEXT: umull r1, r2, r1, r2
; CHECK-NEXT: movt r8, :upper16:c
; CHECK-NEXT: movs r1, #4
; CHECK-NEXT: @ implicit-def: $r10
-; CHECK-NEXT: @ implicit-def: $r5
+; CHECK-NEXT: @ implicit-def: $r6
; CHECK-NEXT: @ implicit-def: $r11
-; CHECK-NEXT: mov.w r9, #12
; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: add.w r1, r1, r2, lsr #1
; CHECK-NEXT: add.w r0, r0, r2, lsr #1
@@ -422,9 +422,9 @@ define i32 @d(i64 %e, i32 %f, i64 %g, i32 %h) {
; CHECK-NEXT: mov.w r10, #0
; CHECK-NEXT: .LBB1_5: @ %for.cond.cleanup5
; CHECK-NEXT: @ in Loop: Header=BB1_6 Depth=1
-; CHECK-NEXT: adds r5, #2
-; CHECK-NEXT: subs.w r1, r5, lr
-; CHECK-NEXT: asr.w r0, r5, #31
+; CHECK-NEXT: adds r6, #2
+; CHECK-NEXT: subs.w r1, r6, lr
+; CHECK-NEXT: asr.w r0, r6, #31
; CHECK-NEXT: sbcs.w r0, r0, r12
; CHECK-NEXT: bge.w .LBB1_28
; CHECK-NEXT: .LBB1_6: @ %for.cond2.preheader
@@ -444,12 +444,12 @@ define i32 @d(i64 %e, i32 %f, i64 %g, i32 %h) {
; CHECK-NEXT: ldrd r2, r3, [sp, #120]
; CHECK-NEXT: movs r0, #32
; CHECK-NEXT: movs r1, #0
-; CHECK-NEXT: mov r4, r6
+; CHECK-NEXT: mov r4, r5
; CHECK-NEXT: mov r7, r12
-; CHECK-NEXT: mov r6, lr
+; CHECK-NEXT: mov r5, lr
; CHECK-NEXT: bl __aeabi_ldivmod
-; CHECK-NEXT: mov lr, r6
-; CHECK-NEXT: mov r6, r4
+; CHECK-NEXT: mov lr, r5
+; CHECK-NEXT: mov r5, r4
; CHECK-NEXT: mov r12, r7
; CHECK-NEXT: ldr r3, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: ldr r4, [sp, #12] @ 4-byte Reload
@@ -516,7 +516,7 @@ define i32 @d(i64 %e, i32 %f, i64 %g, i32 %h) {
; CHECK-NEXT: bne .LBB1_14
; CHECK-NEXT: .LBB1_15: @ %for.cond9.for.cond15.preheader_crit_edge.us
; CHECK-NEXT: @ in Loop: Header=BB1_10 Depth=2
-; CHECK-NEXT: cmp r6, #0
+; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: beq .LBB1_9
; CHECK-NEXT: @ %bb.16: @ %for.cond9.for.cond15.preheader_crit_edge.us
; CHECK-NEXT: @ in Loop: Header=BB1_10 Depth=2
@@ -526,7 +526,7 @@ define i32 @d(i64 %e, i32 %f, i64 %g, i32 %h) {
; CHECK-NEXT: b .LBB1_26
; CHECK-NEXT: .LBB1_17: @ %for.body6.lr.ph.split
; CHECK-NEXT: @ in Loop: Header=BB1_6 Depth=1
-; CHECK-NEXT: cmp r6, #0
+; CHECK-NEXT: cmp r5, #0
; CHECK-NEXT: beq.w .LBB1_2
; CHECK-NEXT: @ %bb.18: @ in Loop: Header=BB1_6 Depth=1
; CHECK-NEXT: mov r0, r11
diff --git a/llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll b/llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
index c7661a1f430c6..c112958474545 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
@@ -770,37 +770,39 @@ for.cond.cleanup: ; preds = %for.body, %middle.b
define i32 @smin_i32_inloop(ptr nocapture readonly %x, i32 %n) {
; CHECK-LABEL: smin_i32_inloop:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r7, lr}
-; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: .save {r4, lr}
+; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: cmp r1, #1
; CHECK-NEXT: blt .LBB8_3
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
; CHECK-NEXT: mov r12, r0
+; CHECK-NEXT: mvn r0, #-2147483648
; CHECK-NEXT: cmp r1, #4
; CHECK-NEXT: bhs .LBB8_4
; CHECK-NEXT: @ %bb.2:
-; CHECK-NEXT: mvn r0, #-2147483648
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: b .LBB8_7
; CHECK-NEXT: .LBB8_3:
; CHECK-NEXT: mvn r0, #-2147483648
-; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: pop {r4, pc}
; CHECK-NEXT: .LBB8_4: @ %vector.ph
; CHECK-NEXT: bic r3, r1, #3
; CHECK-NEXT: movs r2, #1
-; CHECK-NEXT: subs r0, r3, #4
-; CHECK-NEXT: add.w lr, r2, r0, lsr #2
-; CHECK-NEXT: mvn r0, #-2147483648
+; CHECK-NEXT: sub.w lr, r3, #4
+; CHECK-NEXT: add.w lr, r2, lr, lsr #2
; CHECK-NEXT: mov r2, r12
; CHECK-NEXT: .LBB8_5: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [r2], #16
-; CHECK-NEXT: vminv.s32 r0, q0
+; CHECK-NEXT: mvn r4, #-2147483648
+; CHECK-NEXT: vminv.s32 r4, q0
+; CHECK-NEXT: cmp r0, r4
+; CHECK-NEXT: csel r0, r0, r4, lt
; CHECK-NEXT: le lr, .LBB8_5
; CHECK-NEXT: @ %bb.6: @ %middle.block
; CHECK-NEXT: cmp r3, r1
; CHECK-NEXT: it eq
-; CHECK-NEXT: popeq {r7, pc}
+; CHECK-NEXT: popeq {r4, pc}
; CHECK-NEXT: .LBB8_7: @ %for.body.preheader1
; CHECK-NEXT: sub.w lr, r1, r3
; CHECK-NEXT: add.w r2, r12, r3, lsl #2
@@ -811,7 +813,7 @@ define i32 @smin_i32_inloop(ptr nocapture readonly %x, i32 %n) {
; CHECK-NEXT: csel r0, r0, r1, lt
; CHECK-NEXT: le lr, .LBB8_8
; CHECK-NEXT: @ %bb.9: @ %for.cond.cleanup
-; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: pop {r4, pc}
entry:
%cmp6 = icmp sgt i32 %n, 0
br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
@@ -963,37 +965,39 @@ for.cond.cleanup: ; preds = %for.body, %middle.b
define i32 @smax_i32_inloop(ptr nocapture readonly %x, i32 %n) {
; CHECK-LABEL: smax_i32_inloop:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r7, lr}
-; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: .save {r4, lr}
+; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: cmp r1, #1
; CHECK-NEXT: blt .LBB10_3
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
; CHECK-NEXT: mov r12, r0
+; CHECK-NEXT: mov.w r0, #-2147483648
; CHECK-NEXT: cmp r1, #4
; CHECK-NEXT: bhs .LBB10_4
; CHECK-NEXT: @ %bb.2:
-; CHECK-NEXT: mov.w r0, #-2147483648
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: b .LBB10_7
; CHECK-NEXT: .LBB10_3:
; CHECK-NEXT: mov.w r0, #-2147483648
-; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: pop {r4, pc}
; CHECK-NEXT: .LBB10_4: @ %vector.ph
; CHECK-NEXT: bic r3, r1, #3
; CHECK-NEXT: movs r2, #1
-; CHECK-NEXT: subs r0, r3, #4
-; CHECK-NEXT: add.w lr, r2, r0, lsr #2
-; CHECK-NEXT: mov.w r0, #-2147483648
+; CHECK-NEXT: sub.w lr, r3, #4
+; CHECK-NEXT: add.w lr, r2, lr, lsr #2
; CHECK-NEXT: mov r2, r12
; CHECK-NEXT: .LBB10_5: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [r2], #16
-; CHECK-NEXT: vmaxv.s32 r0, q0
+; CHECK-NEXT: mov.w r4, #-2147483648
+; CHECK-NEXT: vmaxv.s32 r4, q0
+; CHECK-NEXT: cmp r0, r4
+; CHECK-NEXT: csel r0, r0, r4, gt
; CHECK-NEXT: le lr, .LBB10_5
; CHECK-NEXT: @ %bb.6: @ %middle.block
; CHECK-NEXT: cmp r3, r1
; CHECK-NEXT: it eq
-; CHECK-NEXT: popeq {r7, pc}
+; CHECK-NEXT: popeq {r4, pc}
; CHECK-NEXT: .LBB10_7: @ %for.body.preheader1
; CHECK-NEXT: sub.w lr, r1, r3
; CHECK-NEXT: add.w r2, r12, r3, lsl #2
@@ -1004,7 +1008,7 @@ define i32 @smax_i32_inloop(ptr nocapture readonly %x, i32 %n) {
; CHECK-NEXT: csel r0, r0, r1, gt
; CHECK-NEXT: le lr, .LBB10_8
; CHECK-NEXT: @ %bb.9: @ %for.cond.cleanup
-; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: pop {r4, pc}
entry:
%cmp6 = icmp sgt i32 %n, 0
br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
@@ -1156,37 +1160,39 @@ for.cond.cleanup: ; preds = %for.body, %middle.b
define i32 @umin_i32_inloop(ptr nocapture readonly %x, i32 %n) {
; CHECK-LABEL: umin_i32_inloop:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r7, lr}
-; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: .save {r4, lr}
+; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: cmp r1, #1
; CHECK-NEXT: blt .LBB12_3
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
; CHECK-NEXT: mov r12, r0
+; CHECK-NEXT: mov.w r0, #-1
; CHECK-NEXT: cmp r1, #4
; CHECK-NEXT: bhs .LBB12_4
; CHECK-NEXT: @ %bb.2:
-; CHECK-NEXT: mov.w r0, #-1
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: b .LBB12_7
; CHECK-NEXT: .LBB12_3:
; CHECK-NEXT: mov.w r0, #-1
-; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: pop {r4, pc}
; CHECK-NEXT: .LBB12_4: @ %vector.ph
; CHECK-NEXT: bic r3, r1, #3
; CHECK-NEXT: movs r2, #1
-; CHECK-NEXT: subs r0, r3, #4
-; CHECK-NEXT: add.w lr, r2, r0, lsr #2
-; CHECK-NEXT: mov.w r0, #-1
+; CHECK-NEXT: sub.w lr, r3, #4
+; CHECK-NEXT: add.w lr, r2, lr, lsr #2
; CHECK-NEXT: mov r2, r12
; CHECK-NEXT: .LBB12_5: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [r2], #16
-; CHECK-NEXT: vminv.u32 r0, q0
+; CHECK-NEXT: mov.w r4, #-1
+; CHECK-NEXT: vminv.u32 r4, q0
+; CHECK-NEXT: cmp r0, r4
+; CHECK-NEXT: csel r0, r0, r4, lo
; CHECK-NEXT: le lr, .LBB12_5
; CHECK-NEXT: @ %bb.6: @ %middle.block
; CHECK-NEXT: cmp r3, r1
; CHECK-NEXT: it eq
-; CHECK-NEXT: popeq {r7, pc}
+; CHECK-NEXT: popeq {r4, pc}
; CHECK-NEXT: .LBB12_7: @ %for.body.preheader1
; CHECK-NEXT: sub.w lr, r1, r3
; CHECK-NEXT: add.w r2, r12, r3, lsl #2
@@ -1197,7 +1203,7 @@ define i32 @umin_i32_inloop(ptr nocapture readonly %x, i32 %n) {
; CHECK-NEXT: csel r0, r0, r1, hi
; CHECK-NEXT: le lr, .LBB12_8
; CHECK-NEXT: @ %bb.9: @ %for.cond.cleanup
-; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: pop {r4, pc}
entry:
%cmp6 = icmp sgt i32 %n, 0
br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
@@ -1349,48 +1355,49 @@ for.cond.cleanup: ; preds = %for.body, %middle.b
define i32 @umax_i32_inloop(ptr nocapture readonly %x, i32 %n) {
; CHECK-LABEL: umax_i32_inloop:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r7, lr}
-; CHECK-NEXT: push {r7, lr}
+; CHECK-NEXT: .save {r4, lr}
+; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: cmp r1, #1
-; CHECK-NEXT: blt .LBB14_3
+; CHECK-NEXT: blt .LBB14_8
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
; CHECK-NEXT: mov r12, r0
-; CHECK-NEXT: cmp r1, #4
-; CHECK-NEXT: bhs .LBB14_4
-; CHECK-NEXT: @ %bb.2:
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: movs r0, #0
-; CHECK-NEXT: b .LBB14_7
-; CHECK-NEXT: .LBB14_3:
-; CHECK-NEXT: movs r0, #0
-; CHECK-NEXT: pop {r7, pc}
-; CHECK-NEXT: .LBB14_4: @ %vector.ph
+; CHECK-NEXT: cmp r1, #4
+; CHECK-NEXT: blo .LBB14_5
+; CHECK-NEXT: @ %bb.2: @ %vector.ph
; CHECK-NEXT: bic r3, r1, #3
; CHECK-NEXT: movs r2, #1
; CHECK-NEXT: subs r0, r3, #4
; CHECK-NEXT: add.w lr, r2, r0, lsr #2
; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: mov r2, r12
-; CHECK-NEXT: .LBB14_5: @ %vector.body
+; CHECK-NEXT: .LBB14_3: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [r2], #16
-; CHECK-NEXT: vmaxv.u32 r0, q0
-; CHECK-NEXT: le lr, .LBB14_5
-; CHECK-NEXT: @ %bb.6: @ %middle.block
+; CHECK-NEXT: movs r4, #0
+; CHECK-NEXT: vmaxv.u32 r4, q0
+; CHECK-NEXT: cmp r0, r4
+; CHECK-NEXT: csel r0, r0, r4, hi
+; CHECK-NEXT: le lr, .LBB14_3
+; CHECK-NEXT: @ %bb.4: @ %middle.block
; CHECK-NEXT: cmp r3, r1
; CHECK-NEXT: it eq
-; CHECK-NEXT: popeq {r7, pc}
-; CHECK-NEXT: .LBB14_7: @ %for.body.preheader1
+; CHECK-NEXT: popeq {r4, pc}
+; CHECK-NEXT: .LBB14_5: @ %for.body.preheader1
; CHECK-NEXT: sub.w lr, r1, r3
; CHECK-NEXT: add.w r2, r12, r3, lsl #2
-; CHECK-NEXT: .LBB14_8: @ %for.body
+; CHECK-NEXT: .LBB14_6: @ %for.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldr r1, [r2], #4
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csel r0, r0, r1, hi
-; CHECK-NEXT: le lr, .LBB14_8
-; CHECK-NEXT: @ %bb.9: @ %for.cond.cleanup
-; CHECK-NEXT: pop {r7, pc}
+; CHECK-NEXT: le lr, .LBB14_6
+; CHECK-NEXT: @ %bb.7: @ %for.cond.cleanup
+; CHECK-NEXT: pop {r4, pc}
+; CHECK-NEXT: .LBB14_8:
+; CHECK-NEXT: movs r0, #0
+; CHECK-NEXT: pop {r4, pc}
entry:
%cmp6 = icmp sgt i32 %n, 0
br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
diff --git a/llvm/test/CodeGen/Thumb2/mve-vmaxv-vminv-scalar.ll b/llvm/test/CodeGen/Thumb2/mve-vmaxv-vminv-scalar.ll
index 35e578e425e74..ef77c89dd124c 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vmaxv-vminv-scalar.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vmaxv-vminv-scalar.ll
@@ -4,8 +4,11 @@
define arm_aapcs_vfpcc zeroext i8 @uminv16i8(<16 x i8> %vec, i8 zeroext %min) {
; CHECK-LABEL: uminv16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.u8 r0, q0
-; CHECK-NEXT: uxtb r0, r0
+; CHECK-NEXT: movs r1, #255
+; CHECK-NEXT: vminv.u8 r1, q0
+; CHECK-NEXT: uxtb r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, lo
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %vec)
%cmp = icmp ult i8 %x, %min
@@ -16,8 +19,11 @@ define arm_aapcs_vfpcc zeroext i8 @uminv16i8(<16 x i8> %vec, i8 zeroext %min) {
define arm_aapcs_vfpcc zeroext i16 @uminv8i16(<8 x i16> %vec, i16 zeroext %min) {
; CHECK-LABEL: uminv8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.u16 r0, q0
-; CHECK-NEXT: uxth r0, r0
+; CHECK-NEXT: movw r1, #65535
+; CHECK-NEXT: vminv.u16 r1, q0
+; CHECK-NEXT: uxth r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, lo
; CHECK-NEXT: bx lr
%x = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %vec)
%cmp = icmp ult i16 %x, %min
@@ -28,7 +34,10 @@ define arm_aapcs_vfpcc zeroext i16 @uminv8i16(<8 x i16> %vec, i16 zeroext %min)
define arm_aapcs_vfpcc i32 @uminv4i32(<4 x i32> %vec, i32 %min) {
; CHECK-LABEL: uminv4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.u32 r0, q0
+; CHECK-NEXT: mov.w r1, #-1
+; CHECK-NEXT: vminv.u32 r1, q0
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, lo
; CHECK-NEXT: bx lr
%x = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %vec)
%cmp = icmp ult i32 %x, %min
@@ -39,8 +48,11 @@ define arm_aapcs_vfpcc i32 @uminv4i32(<4 x i32> %vec, i32 %min) {
define arm_aapcs_vfpcc signext i8 @sminv16i8(<16 x i8> %vec, i8 signext %min) {
; CHECK-LABEL: sminv16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.s8 r0, q0
-; CHECK-NEXT: sxtb r0, r0
+; CHECK-NEXT: movs r1, #127
+; CHECK-NEXT: vminv.s8 r1, q0
+; CHECK-NEXT: sxtb r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, lt
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %vec)
%cmp = icmp slt i8 %x, %min
@@ -51,8 +63,11 @@ define arm_aapcs_vfpcc signext i8 @sminv16i8(<16 x i8> %vec, i8 signext %min) {
define arm_aapcs_vfpcc signext i16 @sminv8i16(<8 x i16> %vec, i16 signext %min) {
; CHECK-LABEL: sminv8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.s16 r0, q0
-; CHECK-NEXT: sxth r0, r0
+; CHECK-NEXT: movw r1, #32767
+; CHECK-NEXT: vminv.s16 r1, q0
+; CHECK-NEXT: sxth r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, lt
; CHECK-NEXT: bx lr
%x = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %vec)
%cmp = icmp slt i16 %x, %min
@@ -63,7 +78,10 @@ define arm_aapcs_vfpcc signext i16 @sminv8i16(<8 x i16> %vec, i16 signext %min)
define arm_aapcs_vfpcc i32 @sminv4i32(<4 x i32> %vec, i32 %min) {
; CHECK-LABEL: sminv4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.s32 r0, q0
+; CHECK-NEXT: mvn r1, #-2147483648
+; CHECK-NEXT: vminv.s32 r1, q0
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, lt
; CHECK-NEXT: bx lr
%x = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %vec)
%cmp = icmp slt i32 %x, %min
@@ -74,8 +92,11 @@ define arm_aapcs_vfpcc i32 @sminv4i32(<4 x i32> %vec, i32 %min) {
define arm_aapcs_vfpcc zeroext i8 @umaxv16i8(<16 x i8> %vec, i8 zeroext %max) {
; CHECK-LABEL: umaxv16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.u8 r0, q0
-; CHECK-NEXT: uxtb r0, r0
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: vmaxv.u8 r1, q0
+; CHECK-NEXT: uxtb r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, hi
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %vec)
%cmp = icmp ugt i8 %x, %max
@@ -86,8 +107,11 @@ define arm_aapcs_vfpcc zeroext i8 @umaxv16i8(<16 x i8> %vec, i8 zeroext %max) {
define arm_aapcs_vfpcc zeroext i16 @umaxv8i16(<8 x i16> %vec, i16 zeroext %max) {
; CHECK-LABEL: umaxv8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.u16 r0, q0
-; CHECK-NEXT: uxth r0, r0
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: vmaxv.u16 r1, q0
+; CHECK-NEXT: uxth r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, hi
; CHECK-NEXT: bx lr
%x = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %vec)
%cmp = icmp ugt i16 %x, %max
@@ -98,7 +122,10 @@ define arm_aapcs_vfpcc zeroext i16 @umaxv8i16(<8 x i16> %vec, i16 zeroext %max)
define arm_aapcs_vfpcc i32 @umaxv4i32(<4 x i32> %vec, i32 %max) {
; CHECK-LABEL: umaxv4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.u32 r0, q0
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: vmaxv.u32 r1, q0
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, hi
; CHECK-NEXT: bx lr
%x = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %vec)
%cmp = icmp ugt i32 %x, %max
@@ -109,8 +136,11 @@ define arm_aapcs_vfpcc i32 @umaxv4i32(<4 x i32> %vec, i32 %max) {
define arm_aapcs_vfpcc signext i8 @smaxv16i8(<16 x i8> %vec, i8 signext %max) {
; CHECK-LABEL: smaxv16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.s8 r0, q0
-; CHECK-NEXT: sxtb r0, r0
+; CHECK-NEXT: mvn r1, #127
+; CHECK-NEXT: vmaxv.s8 r1, q0
+; CHECK-NEXT: sxtb r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, gt
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %vec)
%cmp = icmp sgt i8 %x, %max
@@ -121,8 +151,12 @@ define arm_aapcs_vfpcc signext i8 @smaxv16i8(<16 x i8> %vec, i8 signext %max) {
define arm_aapcs_vfpcc signext i16 @smaxv8i16(<8 x i16> %vec, i16 signext %max) {
; CHECK-LABEL: smaxv8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.s16 r0, q0
-; CHECK-NEXT: sxth r0, r0
+; CHECK-NEXT: movw r1, #32768
+; CHECK-NEXT: movt r1, #65535
+; CHECK-NEXT: vmaxv.s16 r1, q0
+; CHECK-NEXT: sxth r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, gt
; CHECK-NEXT: bx lr
%x = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %vec)
%cmp = icmp sgt i16 %x, %max
@@ -133,7 +167,10 @@ define arm_aapcs_vfpcc signext i16 @smaxv8i16(<8 x i16> %vec, i16 signext %max)
define arm_aapcs_vfpcc i32 @smaxv4i32(<4 x i32> %vec, i32 %max) {
; CHECK-LABEL: smaxv4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.s32 r0, q0
+; CHECK-NEXT: mov.w r1, #-2147483648
+; CHECK-NEXT: vmaxv.s32 r1, q0
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, gt
; CHECK-NEXT: bx lr
%x = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %vec)
%cmp = icmp sgt i32 %x, %max
@@ -144,8 +181,11 @@ define arm_aapcs_vfpcc i32 @smaxv4i32(<4 x i32> %vec, i32 %max) {
define arm_aapcs_vfpcc zeroext i8 @commute_uminv16i8(<16 x i8> %vec, i8 zeroext %min) {
; CHECK-LABEL: commute_uminv16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.u8 r0, q0
-; CHECK-NEXT: uxtb r0, r0
+; CHECK-NEXT: movs r1, #255
+; CHECK-NEXT: vminv.u8 r1, q0
+; CHECK-NEXT: uxtb r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, lo
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %vec)
%cmp = icmp ult i8 %min, %x
@@ -156,8 +196,11 @@ define arm_aapcs_vfpcc zeroext i8 @commute_uminv16i8(<16 x i8> %vec, i8 zeroext
define arm_aapcs_vfpcc zeroext i16 @commute_uminv8i16(<8 x i16> %vec, i16 zeroext %min) {
; CHECK-LABEL: commute_uminv8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.u16 r0, q0
-; CHECK-NEXT: uxth r0, r0
+; CHECK-NEXT: movw r1, #65535
+; CHECK-NEXT: vminv.u16 r1, q0
+; CHECK-NEXT: uxth r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, lo
; CHECK-NEXT: bx lr
%x = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %vec)
%cmp = icmp ult i16 %min, %x
@@ -168,7 +211,10 @@ define arm_aapcs_vfpcc zeroext i16 @commute_uminv8i16(<8 x i16> %vec, i16 zeroex
define arm_aapcs_vfpcc i32 @commute_uminv4i32(<4 x i32> %vec, i32 %min) {
; CHECK-LABEL: commute_uminv4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.u32 r0, q0
+; CHECK-NEXT: mov.w r1, #-1
+; CHECK-NEXT: vminv.u32 r1, q0
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, lo
; CHECK-NEXT: bx lr
%x = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %vec)
%cmp = icmp ult i32 %min, %x
@@ -179,8 +225,11 @@ define arm_aapcs_vfpcc i32 @commute_uminv4i32(<4 x i32> %vec, i32 %min) {
define arm_aapcs_vfpcc signext i8 @commute_sminv16i8(<16 x i8> %vec, i8 signext %min) {
; CHECK-LABEL: commute_sminv16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.s8 r0, q0
-; CHECK-NEXT: sxtb r0, r0
+; CHECK-NEXT: movs r1, #127
+; CHECK-NEXT: vminv.s8 r1, q0
+; CHECK-NEXT: sxtb r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, lt
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %vec)
%cmp = icmp slt i8 %min, %x
@@ -191,8 +240,11 @@ define arm_aapcs_vfpcc signext i8 @commute_sminv16i8(<16 x i8> %vec, i8 signext
define arm_aapcs_vfpcc signext i16 @commute_sminv8i16(<8 x i16> %vec, i16 signext %min) {
; CHECK-LABEL: commute_sminv8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.s16 r0, q0
-; CHECK-NEXT: sxth r0, r0
+; CHECK-NEXT: movw r1, #32767
+; CHECK-NEXT: vminv.s16 r1, q0
+; CHECK-NEXT: sxth r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, lt
; CHECK-NEXT: bx lr
%x = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %vec)
%cmp = icmp slt i16 %min, %x
@@ -203,7 +255,10 @@ define arm_aapcs_vfpcc signext i16 @commute_sminv8i16(<8 x i16> %vec, i16 signex
define arm_aapcs_vfpcc i32 @commute_sminv4i32(<4 x i32> %vec, i32 %min) {
; CHECK-LABEL: commute_sminv4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.s32 r0, q0
+; CHECK-NEXT: mvn r1, #-2147483648
+; CHECK-NEXT: vminv.s32 r1, q0
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, lt
; CHECK-NEXT: bx lr
%x = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %vec)
%cmp = icmp slt i32 %min, %x
@@ -214,8 +269,11 @@ define arm_aapcs_vfpcc i32 @commute_sminv4i32(<4 x i32> %vec, i32 %min) {
define arm_aapcs_vfpcc zeroext i8 @commute_umaxv16i8(<16 x i8> %vec, i8 zeroext %max) {
; CHECK-LABEL: commute_umaxv16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.u8 r0, q0
-; CHECK-NEXT: uxtb r0, r0
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: vmaxv.u8 r1, q0
+; CHECK-NEXT: uxtb r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, hi
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %vec)
%cmp = icmp ugt i8 %max, %x
@@ -226,8 +284,11 @@ define arm_aapcs_vfpcc zeroext i8 @commute_umaxv16i8(<16 x i8> %vec, i8 zeroext
define arm_aapcs_vfpcc zeroext i16 @commute_umaxv8i16(<8 x i16> %vec, i16 zeroext %max) {
; CHECK-LABEL: commute_umaxv8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.u16 r0, q0
-; CHECK-NEXT: uxth r0, r0
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: vmaxv.u16 r1, q0
+; CHECK-NEXT: uxth r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, hi
; CHECK-NEXT: bx lr
%x = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %vec)
%cmp = icmp ugt i16 %max, %x
@@ -238,7 +299,10 @@ define arm_aapcs_vfpcc zeroext i16 @commute_umaxv8i16(<8 x i16> %vec, i16 zeroex
define arm_aapcs_vfpcc i32 @commute_umaxv4i32(<4 x i32> %vec, i32 %max) {
; CHECK-LABEL: commute_umaxv4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.u32 r0, q0
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: vmaxv.u32 r1, q0
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, hi
; CHECK-NEXT: bx lr
%x = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %vec)
%cmp = icmp ugt i32 %max, %x
@@ -249,8 +313,11 @@ define arm_aapcs_vfpcc i32 @commute_umaxv4i32(<4 x i32> %vec, i32 %max) {
define arm_aapcs_vfpcc signext i8 @commute_smaxv16i8(<16 x i8> %vec, i8 signext %max) {
; CHECK-LABEL: commute_smaxv16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.s8 r0, q0
-; CHECK-NEXT: sxtb r0, r0
+; CHECK-NEXT: mvn r1, #127
+; CHECK-NEXT: vmaxv.s8 r1, q0
+; CHECK-NEXT: sxtb r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, gt
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %vec)
%cmp = icmp sgt i8 %max, %x
@@ -261,8 +328,12 @@ define arm_aapcs_vfpcc signext i8 @commute_smaxv16i8(<16 x i8> %vec, i8 signext
define arm_aapcs_vfpcc signext i16 @commute_smaxv8i16(<8 x i16> %vec, i16 signext %max) {
; CHECK-LABEL: commute_smaxv8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.s16 r0, q0
-; CHECK-NEXT: sxth r0, r0
+; CHECK-NEXT: movw r1, #32768
+; CHECK-NEXT: movt r1, #65535
+; CHECK-NEXT: vmaxv.s16 r1, q0
+; CHECK-NEXT: sxth r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, gt
; CHECK-NEXT: bx lr
%x = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %vec)
%cmp = icmp sgt i16 %max, %x
@@ -273,7 +344,10 @@ define arm_aapcs_vfpcc signext i16 @commute_smaxv8i16(<8 x i16> %vec, i16 signex
define arm_aapcs_vfpcc i32 @commute_smaxv4i32(<4 x i32> %vec, i32 %max) {
; CHECK-LABEL: commute_smaxv4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.s32 r0, q0
+; CHECK-NEXT: mov.w r1, #-2147483648
+; CHECK-NEXT: vmaxv.s32 r1, q0
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, gt
; CHECK-NEXT: bx lr
%x = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %vec)
%cmp = icmp sgt i32 %max, %x
@@ -286,10 +360,9 @@ define arm_aapcs_vfpcc signext i8 @mismatch_smaxv16i8(<16 x i8> %vec, i8 signext
; CHECK: @ %bb.0:
; CHECK-NEXT: mvn r1, #127
; CHECK-NEXT: vmaxv.s8 r1, q0
-; CHECK-NEXT: sxtb r2, r1
-; CHECK-NEXT: cmp r2, r0
-; CHECK-NEXT: csel r0, r0, r1, gt
-; CHECK-NEXT: sxtb r0, r0
+; CHECK-NEXT: sxtb r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, lt
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %vec)
%cmp = icmp sgt i8 %x, %max
@@ -302,10 +375,9 @@ define arm_aapcs_vfpcc signext i8 @mismatch2_smaxv16i8(<16 x i8> %vec, i8 signex
; CHECK: @ %bb.0:
; CHECK-NEXT: mvn r1, #127
; CHECK-NEXT: vmaxv.s8 r1, q0
-; CHECK-NEXT: sxtb r2, r1
-; CHECK-NEXT: cmp r0, r2
-; CHECK-NEXT: csel r0, r1, r0, gt
-; CHECK-NEXT: sxtb r0, r0
+; CHECK-NEXT: sxtb r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, lt
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %vec)
%cmp = icmp sgt i8 %max, %x
@@ -316,8 +388,11 @@ define arm_aapcs_vfpcc signext i8 @mismatch2_smaxv16i8(<16 x i8> %vec, i8 signex
define arm_aapcs_vfpcc zeroext i8 @inverted_uminv16i8(<16 x i8> %vec, i8 zeroext %min) {
; CHECK-LABEL: inverted_uminv16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.u8 r0, q0
-; CHECK-NEXT: uxtb r0, r0
+; CHECK-NEXT: movs r1, #255
+; CHECK-NEXT: vminv.u8 r1, q0
+; CHECK-NEXT: uxtb r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, lo
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %vec)
%cmp = icmp ugt i8 %x, %min
@@ -328,8 +403,11 @@ define arm_aapcs_vfpcc zeroext i8 @inverted_uminv16i8(<16 x i8> %vec, i8 zeroext
define arm_aapcs_vfpcc zeroext i16 @inverted_uminv8i16(<8 x i16> %vec, i16 zeroext %min) {
; CHECK-LABEL: inverted_uminv8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.u16 r0, q0
-; CHECK-NEXT: uxth r0, r0
+; CHECK-NEXT: movw r1, #65535
+; CHECK-NEXT: vminv.u16 r1, q0
+; CHECK-NEXT: uxth r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, lo
; CHECK-NEXT: bx lr
%x = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %vec)
%cmp = icmp ugt i16 %x, %min
@@ -340,7 +418,10 @@ define arm_aapcs_vfpcc zeroext i16 @inverted_uminv8i16(<8 x i16> %vec, i16 zeroe
define arm_aapcs_vfpcc i32 @inverted_uminv4i32(<4 x i32> %vec, i32 %min) {
; CHECK-LABEL: inverted_uminv4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.u32 r0, q0
+; CHECK-NEXT: mov.w r1, #-1
+; CHECK-NEXT: vminv.u32 r1, q0
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, lo
; CHECK-NEXT: bx lr
%x = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %vec)
%cmp = icmp ugt i32 %x, %min
@@ -351,8 +432,11 @@ define arm_aapcs_vfpcc i32 @inverted_uminv4i32(<4 x i32> %vec, i32 %min) {
define arm_aapcs_vfpcc signext i8 @inverted_sminv16i8(<16 x i8> %vec, i8 signext %min) {
; CHECK-LABEL: inverted_sminv16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.s8 r0, q0
-; CHECK-NEXT: sxtb r0, r0
+; CHECK-NEXT: movs r1, #127
+; CHECK-NEXT: vminv.s8 r1, q0
+; CHECK-NEXT: sxtb r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, lt
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %vec)
%cmp = icmp sgt i8 %x, %min
@@ -363,8 +447,11 @@ define arm_aapcs_vfpcc signext i8 @inverted_sminv16i8(<16 x i8> %vec, i8 signext
define arm_aapcs_vfpcc signext i16 @inverted_sminv8i16(<8 x i16> %vec, i16 signext %min) {
; CHECK-LABEL: inverted_sminv8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.s16 r0, q0
-; CHECK-NEXT: sxth r0, r0
+; CHECK-NEXT: movw r1, #32767
+; CHECK-NEXT: vminv.s16 r1, q0
+; CHECK-NEXT: sxth r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, lt
; CHECK-NEXT: bx lr
%x = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %vec)
%cmp = icmp sgt i16 %x, %min
@@ -375,7 +462,10 @@ define arm_aapcs_vfpcc signext i16 @inverted_sminv8i16(<8 x i16> %vec, i16 signe
define arm_aapcs_vfpcc i32 @inverted_sminv4i32(<4 x i32> %vec, i32 %min) {
; CHECK-LABEL: inverted_sminv4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.s32 r0, q0
+; CHECK-NEXT: mvn r1, #-2147483648
+; CHECK-NEXT: vminv.s32 r1, q0
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, lt
; CHECK-NEXT: bx lr
%x = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %vec)
%cmp = icmp sgt i32 %x, %min
@@ -386,8 +476,11 @@ define arm_aapcs_vfpcc i32 @inverted_sminv4i32(<4 x i32> %vec, i32 %min) {
define arm_aapcs_vfpcc zeroext i8 @inverted_umaxv16i8(<16 x i8> %vec, i8 zeroext %max) {
; CHECK-LABEL: inverted_umaxv16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.u8 r0, q0
-; CHECK-NEXT: uxtb r0, r0
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: vmaxv.u8 r1, q0
+; CHECK-NEXT: uxtb r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, hi
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %vec)
%cmp = icmp ult i8 %x, %max
@@ -398,8 +491,11 @@ define arm_aapcs_vfpcc zeroext i8 @inverted_umaxv16i8(<16 x i8> %vec, i8 zeroext
define arm_aapcs_vfpcc zeroext i16 @inverted_umaxv8i16(<8 x i16> %vec, i16 zeroext %max) {
; CHECK-LABEL: inverted_umaxv8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.u16 r0, q0
-; CHECK-NEXT: uxth r0, r0
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: vmaxv.u16 r1, q0
+; CHECK-NEXT: uxth r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, hi
; CHECK-NEXT: bx lr
%x = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %vec)
%cmp = icmp ult i16 %x, %max
@@ -410,7 +506,10 @@ define arm_aapcs_vfpcc zeroext i16 @inverted_umaxv8i16(<8 x i16> %vec, i16 zeroe
define arm_aapcs_vfpcc i32 @inverted_umaxv4i32(<4 x i32> %vec, i32 %max) {
; CHECK-LABEL: inverted_umaxv4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.u32 r0, q0
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: vmaxv.u32 r1, q0
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, hi
; CHECK-NEXT: bx lr
%x = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %vec)
%cmp = icmp ult i32 %x, %max
@@ -421,8 +520,11 @@ define arm_aapcs_vfpcc i32 @inverted_umaxv4i32(<4 x i32> %vec, i32 %max) {
define arm_aapcs_vfpcc signext i8 @inverted_smaxv16i8(<16 x i8> %vec, i8 signext %max) {
; CHECK-LABEL: inverted_smaxv16i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.s8 r0, q0
-; CHECK-NEXT: sxtb r0, r0
+; CHECK-NEXT: mvn r1, #127
+; CHECK-NEXT: vmaxv.s8 r1, q0
+; CHECK-NEXT: sxtb r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, gt
; CHECK-NEXT: bx lr
%x = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %vec)
%cmp = icmp slt i8 %x, %max
@@ -433,8 +535,12 @@ define arm_aapcs_vfpcc signext i8 @inverted_smaxv16i8(<16 x i8> %vec, i8 signext
define arm_aapcs_vfpcc signext i16 @inverted_smaxv8i16(<8 x i16> %vec, i16 signext %max) {
; CHECK-LABEL: inverted_smaxv8i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.s16 r0, q0
-; CHECK-NEXT: sxth r0, r0
+; CHECK-NEXT: movw r1, #32768
+; CHECK-NEXT: movt r1, #65535
+; CHECK-NEXT: vmaxv.s16 r1, q0
+; CHECK-NEXT: sxth r1, r1
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, gt
; CHECK-NEXT: bx lr
%x = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %vec)
%cmp = icmp slt i16 %x, %max
@@ -445,7 +551,10 @@ define arm_aapcs_vfpcc signext i16 @inverted_smaxv8i16(<8 x i16> %vec, i16 signe
define arm_aapcs_vfpcc i32 @inverted_smaxv4i32(<4 x i32> %vec, i32 %max) {
; CHECK-LABEL: inverted_smaxv4i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.s32 r0, q0
+; CHECK-NEXT: mov.w r1, #-2147483648
+; CHECK-NEXT: vmaxv.s32 r1, q0
+; CHECK-NEXT: cmp r0, r1
+; CHECK-NEXT: csel r0, r0, r1, gt
; CHECK-NEXT: bx lr
%x = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %vec)
%cmp = icmp slt i32 %x, %max
diff --git a/llvm/test/CodeGen/Thumb2/mve-vmaxv.ll b/llvm/test/CodeGen/Thumb2/mve-vmaxv.ll
index 9502716bc98cf..2a3068f3a44b9 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vmaxv.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vmaxv.ll
@@ -140,7 +140,12 @@ define arm_aapcs_vfpcc i32 @vminv_u_v4i32(<4 x i32> %s1) {
define arm_aapcs_vfpcc i8 @vmaxv_s_v16i8_i8(<16 x i8> %s1, i8 %s2) {
; CHECK-LABEL: vmaxv_s_v16i8_i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.s8 r0, q0
+; CHECK-NEXT: mvn r1, #127
+; CHECK-NEXT: sxtb r0, r0
+; CHECK-NEXT: vmaxv.s8 r1, q0
+; CHECK-NEXT: sxtb r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, gt
; CHECK-NEXT: bx lr
%r = call i8 @llvm.vector.reduce.smax.v16i8(<16 x i8> %s1)
%c = icmp sgt i8 %r, %s2
@@ -167,7 +172,13 @@ define arm_aapcs_vfpcc i32 @vmaxv_s_v16i8_i32(<16 x i8> %s1, i32 %s2) {
define arm_aapcs_vfpcc i16 @vmaxv_s_v8i16_i16(<8 x i16> %s1, i16 %s2) {
; CHECK-LABEL: vmaxv_s_v8i16_i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.s16 r0, q0
+; CHECK-NEXT: movw r1, #32768
+; CHECK-NEXT: sxth r0, r0
+; CHECK-NEXT: movt r1, #65535
+; CHECK-NEXT: vmaxv.s16 r1, q0
+; CHECK-NEXT: sxth r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, gt
; CHECK-NEXT: bx lr
%r = call i16 @llvm.vector.reduce.smax.v8i16(<8 x i16> %s1)
%c = icmp sgt i16 %r, %s2
@@ -195,7 +206,10 @@ define arm_aapcs_vfpcc i32 @vmaxv_s_v8i16_i32(<8 x i16> %s1, i32 %s2) {
define arm_aapcs_vfpcc i32 @vmaxv_s_v4i32_i32(<4 x i32> %s1, i32 %s2) {
; CHECK-LABEL: vmaxv_s_v4i32_i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.s32 r0, q0
+; CHECK-NEXT: mov.w r1, #-2147483648
+; CHECK-NEXT: vmaxv.s32 r1, q0
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, gt
; CHECK-NEXT: bx lr
%r = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> %s1)
%c = icmp sgt i32 %r, %s2
@@ -206,7 +220,12 @@ define arm_aapcs_vfpcc i32 @vmaxv_s_v4i32_i32(<4 x i32> %s1, i32 %s2) {
define arm_aapcs_vfpcc i8 @vmaxv_u_v16i8_i8(<16 x i8> %s1, i8 %s2) {
; CHECK-LABEL: vmaxv_u_v16i8_i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.u8 r0, q0
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: uxtb r0, r0
+; CHECK-NEXT: vmaxv.u8 r1, q0
+; CHECK-NEXT: uxtb r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, hi
; CHECK-NEXT: bx lr
%r = call i8 @llvm.vector.reduce.umax.v16i8(<16 x i8> %s1)
%c = icmp ugt i8 %r, %s2
@@ -233,7 +252,12 @@ define arm_aapcs_vfpcc i32 @vmaxv_u_v16i8_i32(<16 x i8> %s1, i32 %s2) {
define arm_aapcs_vfpcc i16 @vmaxv_u_v8i16_i16(<8 x i16> %s1, i16 %s2) {
; CHECK-LABEL: vmaxv_u_v8i16_i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.u16 r0, q0
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: uxth r0, r0
+; CHECK-NEXT: vmaxv.u16 r1, q0
+; CHECK-NEXT: uxth r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, hi
; CHECK-NEXT: bx lr
%r = call i16 @llvm.vector.reduce.umax.v8i16(<8 x i16> %s1)
%c = icmp ugt i16 %r, %s2
@@ -260,7 +284,10 @@ define arm_aapcs_vfpcc i32 @vmaxv_u_v8i16_i32(<8 x i16> %s1, i32 %s2) {
define arm_aapcs_vfpcc i32 @vmaxv_u_v4i32_i32(<4 x i32> %s1, i32 %s2) {
; CHECK-LABEL: vmaxv_u_v4i32_i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vmaxv.u32 r0, q0
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: vmaxv.u32 r1, q0
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, hi
; CHECK-NEXT: bx lr
%r = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %s1)
%c = icmp ugt i32 %r, %s2
@@ -271,7 +298,12 @@ define arm_aapcs_vfpcc i32 @vmaxv_u_v4i32_i32(<4 x i32> %s1, i32 %s2) {
define arm_aapcs_vfpcc i8 @vminv_s_v16i8_i8(<16 x i8> %s1, i8 %s2) {
; CHECK-LABEL: vminv_s_v16i8_i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.s8 r0, q0
+; CHECK-NEXT: movs r1, #127
+; CHECK-NEXT: sxtb r0, r0
+; CHECK-NEXT: vminv.s8 r1, q0
+; CHECK-NEXT: sxtb r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, lt
; CHECK-NEXT: bx lr
%r = call i8 @llvm.vector.reduce.smin.v16i8(<16 x i8> %s1)
%c = icmp slt i8 %r, %s2
@@ -298,7 +330,12 @@ define arm_aapcs_vfpcc i32 @vminv_s_v16i8_i32(<16 x i8> %s1, i32 %s2) {
define arm_aapcs_vfpcc i16 @vminv_s_v8i16_i16(<8 x i16> %s1, i16 %s2) {
; CHECK-LABEL: vminv_s_v8i16_i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.s16 r0, q0
+; CHECK-NEXT: movw r1, #32767
+; CHECK-NEXT: sxth r0, r0
+; CHECK-NEXT: vminv.s16 r1, q0
+; CHECK-NEXT: sxth r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, lt
; CHECK-NEXT: bx lr
%r = call i16 @llvm.vector.reduce.smin.v8i16(<8 x i16> %s1)
%c = icmp slt i16 %r, %s2
@@ -325,7 +362,10 @@ define arm_aapcs_vfpcc i32 @vminv_s_v8i16_i32(<8 x i16> %s1, i32 %s2) {
define arm_aapcs_vfpcc i32 @vminv_s_v4i32_i32(<4 x i32> %s1, i32 %s2) {
; CHECK-LABEL: vminv_s_v4i32_i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.s32 r0, q0
+; CHECK-NEXT: mvn r1, #-2147483648
+; CHECK-NEXT: vminv.s32 r1, q0
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, lt
; CHECK-NEXT: bx lr
%r = call i32 @llvm.vector.reduce.smin.v4i32(<4 x i32> %s1)
%c = icmp slt i32 %r, %s2
@@ -336,7 +376,12 @@ define arm_aapcs_vfpcc i32 @vminv_s_v4i32_i32(<4 x i32> %s1, i32 %s2) {
define arm_aapcs_vfpcc i8 @vminv_u_v16i8_i8(<16 x i8> %s1, i8 %s2) {
; CHECK-LABEL: vminv_u_v16i8_i8:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.u8 r0, q0
+; CHECK-NEXT: movs r1, #255
+; CHECK-NEXT: uxtb r0, r0
+; CHECK-NEXT: vminv.u8 r1, q0
+; CHECK-NEXT: uxtb r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, lo
; CHECK-NEXT: bx lr
%r = call i8 @llvm.vector.reduce.umin.v16i8(<16 x i8> %s1)
%c = icmp ult i8 %r, %s2
@@ -363,7 +408,12 @@ define arm_aapcs_vfpcc i32 @vminv_u_v16i8_i32(<16 x i8> %s1, i32 %s2) {
define arm_aapcs_vfpcc i16 @vminv_u_v8i16_i16(<8 x i16> %s1, i16 %s2) {
; CHECK-LABEL: vminv_u_v8i16_i16:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.u16 r0, q0
+; CHECK-NEXT: movw r1, #65535
+; CHECK-NEXT: uxth r0, r0
+; CHECK-NEXT: vminv.u16 r1, q0
+; CHECK-NEXT: uxth r1, r1
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, lo
; CHECK-NEXT: bx lr
%r = call i16 @llvm.vector.reduce.umin.v8i16(<8 x i16> %s1)
%c = icmp ult i16 %r, %s2
@@ -390,7 +440,10 @@ define arm_aapcs_vfpcc i32 @vminv_u_v8i16_i32(<8 x i16> %s1, i32 %s2) {
define arm_aapcs_vfpcc i32 @vminv_u_v4i32_i32(<4 x i32> %s1, i32 %s2) {
; CHECK-LABEL: vminv_u_v4i32_i32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: vminv.u32 r0, q0
+; CHECK-NEXT: mov.w r1, #-1
+; CHECK-NEXT: vminv.u32 r1, q0
+; CHECK-NEXT: cmp r1, r0
+; CHECK-NEXT: csel r0, r1, r0, lo
; CHECK-NEXT: bx lr
%r = call i32 @llvm.vector.reduce.umin.v4i32(<4 x i32> %s1)
%c = icmp ult i32 %r, %s2
diff --git a/llvm/test/CodeGen/Thumb2/v8_IT_4.ll b/llvm/test/CodeGen/Thumb2/v8_IT_4.ll
index fb6c86ab9fda9..c636e92eef9f2 100644
--- a/llvm/test/CodeGen/Thumb2/v8_IT_4.ll
+++ b/llvm/test/CodeGen/Thumb2/v8_IT_4.ll
@@ -23,10 +23,10 @@ define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(ptr %this, ptr %__str) {
; P01-NEXT: mov r0, r8
; P01-NEXT: bl _ZNKSs4sizeEv
; P01-NEXT: mov r6, r4
-; P01-NEXT: cmp r4, r0
+; P01-NEXT: cmp r0, r4
; P01-NEXT: mov r7, r0
-; P01-NEXT: it hi
-; P01-NEXT: movhi r6, r0
+; P01-NEXT: it lo
+; P01-NEXT: movlo r6, r0
; P01-NEXT: mov r0, r5
; P01-NEXT: bl _ZNKSs7_M_dataEv
; P01-NEXT: mov r5, r0
@@ -53,10 +53,10 @@ define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(ptr %this, ptr %__str) {
; P23-NEXT: mov r0, r8
; P23-NEXT: bl _ZNKSs4sizeEv
; P23-NEXT: mov r4, r6
-; P23-NEXT: cmp r6, r0
+; P23-NEXT: cmp r0, r6
; P23-NEXT: mov r5, r0
-; P23-NEXT: it hi
-; P23-NEXT: movhi r4, r0
+; P23-NEXT: it lo
+; P23-NEXT: movlo r4, r0
; P23-NEXT: mov r0, r7
; P23-NEXT: bl _ZNKSs7_M_dataEv
; P23-NEXT: mov r7, r0
diff --git a/llvm/test/CodeGen/VE/Scalar/atomic.ll b/llvm/test/CodeGen/VE/Scalar/atomic.ll
index b6bbad18e4136..4eea6d3ab9c5c 100644
--- a/llvm/test/CodeGen/VE/Scalar/atomic.ll
+++ b/llvm/test/CodeGen/VE/Scalar/atomic.ll
@@ -261,9 +261,8 @@ define signext i32 @test_atomic_fetch_umin_4() {
; CHECK-NEXT: .LBB9_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: or %s2, 0, %s1
-; CHECK-NEXT: cmpu.w %s3, 2, %s1
; CHECK-NEXT: or %s1, 0, %s2
-; CHECK-NEXT: cmov.w.le %s1, (63)0, %s3
+; CHECK-NEXT: cmov.w.ne %s1, (63)0, %s2
; CHECK-NEXT: cas.w %s1, (%s0), %s2
; CHECK-NEXT: brne.w %s1, %s2, .LBB9_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
diff --git a/llvm/test/CodeGen/VE/Scalar/max.ll b/llvm/test/CodeGen/VE/Scalar/max.ll
index 7950842670afb..7a67db1e6cca8 100644
--- a/llvm/test/CodeGen/VE/Scalar/max.ll
+++ b/llvm/test/CodeGen/VE/Scalar/max.ll
@@ -215,7 +215,7 @@ define i64 @max2u64(i64, i64) {
; CHECK-LABEL: max2u64:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s2, %s0, %s1
-; CHECK-NEXT: cmov.l.ge %s1, %s0, %s2
+; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i64 %0, %1
@@ -259,7 +259,7 @@ define i32 @max2u32(i32, i32) {
; CHECK-LABEL: max2u32:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s2, %s0, %s1
-; CHECK-NEXT: cmov.w.ge %s1, %s0, %s2
+; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp uge i32 %0, %1
diff --git a/llvm/test/CodeGen/VE/Scalar/min.ll b/llvm/test/CodeGen/VE/Scalar/min.ll
index 36a2e06a2c9d4..8d0a9e21d6eb1 100644
--- a/llvm/test/CodeGen/VE/Scalar/min.ll
+++ b/llvm/test/CodeGen/VE/Scalar/min.ll
@@ -213,7 +213,7 @@ define i64 @min2u64(i64, i64) {
; CHECK-LABEL: min2u64:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.l %s2, %s0, %s1
-; CHECK-NEXT: cmov.l.le %s1, %s0, %s2
+; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i64 %0, %1
@@ -257,7 +257,7 @@ define i32 @min2u32(i32, i32) {
; CHECK-LABEL: min2u32:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpu.w %s2, %s0, %s1
-; CHECK-NEXT: cmov.w.le %s1, %s0, %s2
+; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
%3 = icmp ule i32 %0, %1
diff --git a/llvm/test/CodeGen/VE/Scalar/smin.ll b/llvm/test/CodeGen/VE/Scalar/smin.ll
index b58b8525db1af..ec975f53eae67 100644
--- a/llvm/test/CodeGen/VE/Scalar/smin.ll
+++ b/llvm/test/CodeGen/VE/Scalar/smin.ll
@@ -137,7 +137,7 @@ define i128 @func_smin_fore_zero_i128(i128 noundef %0) {
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s2, %s1, 63
; CHECK-NEXT: and %s0, %s2, %s0
-; CHECK-NEXT: and %s1, %s2, %s1
+; CHECK-NEXT: mins.l %s1, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i128 @llvm.smin.i128(i128 %0, i128 0)
ret i128 %2
@@ -192,7 +192,7 @@ define i128 @func_smin_back_zero_i128(i128 noundef %0) {
; CHECK: # %bb.0:
; CHECK-NEXT: sra.l %s2, %s1, 63
; CHECK-NEXT: and %s0, %s2, %s0
-; CHECK-NEXT: and %s1, %s2, %s1
+; CHECK-NEXT: mins.l %s1, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i128 @llvm.smin.i128(i128 %0, i128 0)
ret i128 %2
diff --git a/llvm/test/CodeGen/WebAssembly/fpclamptosat.ll b/llvm/test/CodeGen/WebAssembly/fpclamptosat.ll
index 267d94b601666..8d2e0146242dc 100644
--- a/llvm/test/CodeGen/WebAssembly/fpclamptosat.ll
+++ b/llvm/test/CodeGen/WebAssembly/fpclamptosat.ll
@@ -593,6 +593,7 @@ define i64 @ustest_f64i64(double %x) {
; CHECK-NEXT: i32.const 16
; CHECK-NEXT: i32.add
; CHECK-NEXT: global.set __stack_pointer
+; CHECK-NEXT: i64.const 0
; CHECK-NEXT: local.get 3
; CHECK-NEXT: i64.const 0
; CHECK-NEXT: local.get 2
@@ -600,21 +601,12 @@ define i64 @ustest_f64i64(double %x) {
; CHECK-NEXT: i64.lt_s
; CHECK-NEXT: local.tee 1
; CHECK-NEXT: i64.select
-; CHECK-NEXT: local.tee 3
-; CHECK-NEXT: i64.const 0
-; CHECK-NEXT: local.get 3
-; CHECK-NEXT: i64.const 0
-; CHECK-NEXT: i64.ne
; CHECK-NEXT: local.get 2
; CHECK-NEXT: i64.const 1
; CHECK-NEXT: local.get 1
; CHECK-NEXT: i64.select
-; CHECK-NEXT: local.tee 2
; CHECK-NEXT: i64.const 0
-; CHECK-NEXT: i64.gt_s
-; CHECK-NEXT: local.get 2
-; CHECK-NEXT: i64.eqz
-; CHECK-NEXT: i32.select
+; CHECK-NEXT: i64.lt_s
; CHECK-NEXT: i64.select
; CHECK-NEXT: # fallthrough-return
entry:
@@ -766,6 +758,7 @@ define i64 @ustest_f32i64(float %x) {
; CHECK-NEXT: i32.const 16
; CHECK-NEXT: i32.add
; CHECK-NEXT: global.set __stack_pointer
+; CHECK-NEXT: i64.const 0
; CHECK-NEXT: local.get 3
; CHECK-NEXT: i64.const 0
; CHECK-NEXT: local.get 2
@@ -773,21 +766,12 @@ define i64 @ustest_f32i64(float %x) {
; CHECK-NEXT: i64.lt_s
; CHECK-NEXT: local.tee 1
; CHECK-NEXT: i64.select
-; CHECK-NEXT: local.tee 3
-; CHECK-NEXT: i64.const 0
-; CHECK-NEXT: local.get 3
-; CHECK-NEXT: i64.const 0
-; CHECK-NEXT: i64.ne
; CHECK-NEXT: local.get 2
; CHECK-NEXT: i64.const 1
; CHECK-NEXT: local.get 1
; CHECK-NEXT: i64.select
-; CHECK-NEXT: local.tee 2
; CHECK-NEXT: i64.const 0
-; CHECK-NEXT: i64.gt_s
-; CHECK-NEXT: local.get 2
-; CHECK-NEXT: i64.eqz
-; CHECK-NEXT: i32.select
+; CHECK-NEXT: i64.lt_s
; CHECK-NEXT: i64.select
; CHECK-NEXT: # fallthrough-return
entry:
@@ -956,6 +940,7 @@ define i64 @ustest_f16i64(half %x) {
; CHECK-NEXT: i32.const 16
; CHECK-NEXT: i32.add
; CHECK-NEXT: global.set __stack_pointer
+; CHECK-NEXT: i64.const 0
; CHECK-NEXT: local.get 3
; CHECK-NEXT: i64.const 0
; CHECK-NEXT: local.get 2
@@ -963,21 +948,12 @@ define i64 @ustest_f16i64(half %x) {
; CHECK-NEXT: i64.lt_s
; CHECK-NEXT: local.tee 1
; CHECK-NEXT: i64.select
-; CHECK-NEXT: local.tee 3
-; CHECK-NEXT: i64.const 0
-; CHECK-NEXT: local.get 3
-; CHECK-NEXT: i64.const 0
-; CHECK-NEXT: i64.ne
; CHECK-NEXT: local.get 2
; CHECK-NEXT: i64.const 1
; CHECK-NEXT: local.get 1
; CHECK-NEXT: i64.select
-; CHECK-NEXT: local.tee 2
; CHECK-NEXT: i64.const 0
-; CHECK-NEXT: i64.gt_s
-; CHECK-NEXT: local.get 2
-; CHECK-NEXT: i64.eqz
-; CHECK-NEXT: i32.select
+; CHECK-NEXT: i64.lt_s
; CHECK-NEXT: i64.select
; CHECK-NEXT: # fallthrough-return
entry:
diff --git a/llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll b/llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll
index 1a8d33f5b3480..55c5ff2689e0e 100644
--- a/llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll
+++ b/llvm/test/CodeGen/X86/8bit_cmov_of_trunc_promotion.ll
@@ -98,12 +98,12 @@ define i8 @neg_only_one_truncation(i32 %a1_wide_orig, i8 %a2_orig, i32 %inc) nou
;
; I386-CMOV-LABEL: neg_only_one_truncation:
; I386-CMOV: # %bb.0:
-; I386-CMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
+; I386-CMOV-NEXT: movl {{[0-9]+}}(%esp), %edx
; I386-CMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; I386-CMOV-NEXT: addl %eax, %ecx
-; I386-CMOV-NEXT: addb {{[0-9]+}}(%esp), %al
-; I386-CMOV-NEXT: cmpb %al, %cl
-; I386-CMOV-NEXT: movzbl %al, %eax
+; I386-CMOV-NEXT: addl %edx, %ecx
+; I386-CMOV-NEXT: addb {{[0-9]+}}(%esp), %dl
+; I386-CMOV-NEXT: movzbl %dl, %eax
+; I386-CMOV-NEXT: cmpb %dl, %cl
; I386-CMOV-NEXT: cmovgl %ecx, %eax
; I386-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I386-CMOV-NEXT: retl
@@ -124,12 +124,12 @@ define i8 @neg_only_one_truncation(i32 %a1_wide_orig, i8 %a2_orig, i32 %inc) nou
;
; I686-CMOV-LABEL: neg_only_one_truncation:
; I686-CMOV: # %bb.0:
-; I686-CMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
+; I686-CMOV-NEXT: movl {{[0-9]+}}(%esp), %edx
; I686-CMOV-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; I686-CMOV-NEXT: addl %eax, %ecx
-; I686-CMOV-NEXT: addb {{[0-9]+}}(%esp), %al
-; I686-CMOV-NEXT: cmpb %al, %cl
-; I686-CMOV-NEXT: movzbl %al, %eax
+; I686-CMOV-NEXT: addl %edx, %ecx
+; I686-CMOV-NEXT: addb {{[0-9]+}}(%esp), %dl
+; I686-CMOV-NEXT: movzbl %dl, %eax
+; I686-CMOV-NEXT: cmpb %dl, %cl
; I686-CMOV-NEXT: cmovgl %ecx, %eax
; I686-CMOV-NEXT: # kill: def $al killed $al killed $eax
; I686-CMOV-NEXT: retl
@@ -140,8 +140,8 @@ define i8 @neg_only_one_truncation(i32 %a1_wide_orig, i8 %a2_orig, i32 %inc) nou
; X86_64-NEXT: # kill: def $edi killed $edi def $rdi
; X86_64-NEXT: leal (%rdi,%rdx), %ecx
; X86_64-NEXT: addb %sil, %dl
-; X86_64-NEXT: cmpb %dl, %cl
; X86_64-NEXT: movzbl %dl, %eax
+; X86_64-NEXT: cmpb %al, %cl
; X86_64-NEXT: cmovgl %ecx, %eax
; X86_64-NEXT: # kill: def $al killed $al killed $eax
; X86_64-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/apx/cfcmov.ll b/llvm/test/CodeGen/X86/apx/cfcmov.ll
index 37ba3d451c2b1..a4f56c401a4e3 100644
--- a/llvm/test/CodeGen/X86/apx/cfcmov.ll
+++ b/llvm/test/CodeGen/X86/apx/cfcmov.ll
@@ -98,8 +98,8 @@ define void @cfcmov16mr(ptr %p, i16 %0) {
; CHECK-LABEL: cfcmov16mr:
; CHECK: # %bb.0:
; CHECK-NEXT: movzwl (%rdi), %eax
-; CHECK-NEXT: cmpw %ax, %si
-; CHECK-NEXT: cfcmovlew %si, (%rdi)
+; CHECK-NEXT: cmpw %si, %ax
+; CHECK-NEXT: cfcmovgew %si, (%rdi)
; CHECK-NEXT: retq
%2 = load i16, ptr %p, align 2
%3 = icmp sgt i16 %0, %2
@@ -166,8 +166,8 @@ define void @loadstorediffptr(ptr %p, i32 %0) {
; CHECK-LABEL: loadstorediffptr:
; CHECK: # %bb.0:
; CHECK-NEXT: movl (%rdi), %eax
-; CHECK-NEXT: cmpl %eax, %esi
-; CHECK-NEXT: cmovbel %eax, %esi
+; CHECK-NEXT: cmpl %esi, %eax
+; CHECK-NEXT: cmoval %eax, %esi
; CHECK-NEXT: movl %esi, 4(%rdi)
; CHECK-NEXT: retq
%2 = getelementptr [2 x i32], ptr %p, i32 0, i32 0
diff --git a/llvm/test/CodeGen/X86/atomic-minmax-i6432.ll b/llvm/test/CodeGen/X86/atomic-minmax-i6432.ll
index 362135cb1808b..5fece25100842 100644
--- a/llvm/test/CodeGen/X86/atomic-minmax-i6432.ll
+++ b/llvm/test/CodeGen/X86/atomic-minmax-i6432.ll
@@ -72,7 +72,7 @@ define i64 @atomic_min_i64() nounwind {
; LINUX-NEXT: .p2align 4
; LINUX-NEXT: .LBB1_1: # %atomicrmw.start
; LINUX-NEXT: # =>This Inner Loop Header: Depth=1
-; LINUX-NEXT: cmpl $7, %eax
+; LINUX-NEXT: cmpl $6, %eax
; LINUX-NEXT: movl %edx, %ecx
; LINUX-NEXT: sbbl $0, %ecx
; LINUX-NEXT: movl $0, %ecx
@@ -98,7 +98,7 @@ define i64 @atomic_min_i64() nounwind {
; PIC-NEXT: .p2align 4
; PIC-NEXT: LBB1_1: ## %atomicrmw.start
; PIC-NEXT: ## =>This Inner Loop Header: Depth=1
-; PIC-NEXT: cmpl $7, %eax
+; PIC-NEXT: cmpl $6, %eax
; PIC-NEXT: movl %edx, %ecx
; PIC-NEXT: sbbl $0, %ecx
; PIC-NEXT: movl $0, %ecx
@@ -120,31 +120,28 @@ define i64 @atomic_umax_i64() nounwind {
; LINUX-LABEL: atomic_umax_i64:
; LINUX: # %bb.0: # %entry
; LINUX-NEXT: pushl %ebx
-; LINUX-NEXT: pushl %esi
; LINUX-NEXT: movl sc64+4, %edx
; LINUX-NEXT: movl sc64, %eax
-; LINUX-NEXT: movl $7, %esi
; LINUX-NEXT: .p2align 4
; LINUX-NEXT: .LBB2_1: # %atomicrmw.start
; LINUX-NEXT: # =>This Inner Loop Header: Depth=1
-; LINUX-NEXT: cmpl %eax, %esi
-; LINUX-NEXT: movl $0, %ecx
-; LINUX-NEXT: sbbl %edx, %ecx
-; LINUX-NEXT: movl $0, %ecx
-; LINUX-NEXT: cmovbl %edx, %ecx
+; LINUX-NEXT: cmpl $8, %eax
+; LINUX-NEXT: movl $7, %ecx
+; LINUX-NEXT: cmovael %eax, %ecx
+; LINUX-NEXT: testl %edx, %edx
; LINUX-NEXT: movl $7, %ebx
-; LINUX-NEXT: cmovbl %eax, %ebx
+; LINUX-NEXT: cmovnel %eax, %ebx
+; LINUX-NEXT: cmovel %ecx, %ebx
+; LINUX-NEXT: movl %edx, %ecx
; LINUX-NEXT: lock cmpxchg8b sc64
; LINUX-NEXT: jne .LBB2_1
; LINUX-NEXT: # %bb.2: # %atomicrmw.end
-; LINUX-NEXT: popl %esi
; LINUX-NEXT: popl %ebx
; LINUX-NEXT: retl
;
; PIC-LABEL: atomic_umax_i64:
; PIC: ## %bb.0: ## %entry
; PIC-NEXT: pushl %ebx
-; PIC-NEXT: pushl %edi
; PIC-NEXT: pushl %esi
; PIC-NEXT: calll L2$pb
; PIC-NEXT: L2$pb:
@@ -152,22 +149,21 @@ define i64 @atomic_umax_i64() nounwind {
; PIC-NEXT: movl L_sc64$non_lazy_ptr-L2$pb(%eax), %esi
; PIC-NEXT: movl (%esi), %eax
; PIC-NEXT: movl 4(%esi), %edx
-; PIC-NEXT: movl $7, %edi
; PIC-NEXT: .p2align 4
; PIC-NEXT: LBB2_1: ## %atomicrmw.start
; PIC-NEXT: ## =>This Inner Loop Header: Depth=1
-; PIC-NEXT: cmpl %eax, %edi
-; PIC-NEXT: movl $0, %ecx
-; PIC-NEXT: sbbl %edx, %ecx
-; PIC-NEXT: movl $0, %ecx
-; PIC-NEXT: cmovbl %edx, %ecx
+; PIC-NEXT: cmpl $8, %eax
+; PIC-NEXT: movl $7, %ecx
+; PIC-NEXT: cmovael %eax, %ecx
+; PIC-NEXT: testl %edx, %edx
; PIC-NEXT: movl $7, %ebx
-; PIC-NEXT: cmovbl %eax, %ebx
+; PIC-NEXT: cmovnel %eax, %ebx
+; PIC-NEXT: cmovel %ecx, %ebx
+; PIC-NEXT: movl %edx, %ecx
; PIC-NEXT: lock cmpxchg8b (%esi)
; PIC-NEXT: jne LBB2_1
; PIC-NEXT: ## %bb.2: ## %atomicrmw.end
; PIC-NEXT: popl %esi
-; PIC-NEXT: popl %edi
; PIC-NEXT: popl %ebx
; PIC-NEXT: retl
entry:
@@ -179,27 +175,30 @@ define i64 @atomic_umin_i64() nounwind {
; LINUX-LABEL: atomic_umin_i64:
; LINUX: # %bb.0: # %entry
; LINUX-NEXT: pushl %ebx
+; LINUX-NEXT: pushl %esi
; LINUX-NEXT: movl sc64+4, %edx
; LINUX-NEXT: movl sc64, %eax
+; LINUX-NEXT: movl $8, %esi
; LINUX-NEXT: .p2align 4
; LINUX-NEXT: .LBB3_1: # %atomicrmw.start
; LINUX-NEXT: # =>This Inner Loop Header: Depth=1
-; LINUX-NEXT: cmpl $9, %eax
-; LINUX-NEXT: movl %edx, %ecx
-; LINUX-NEXT: sbbl $0, %ecx
-; LINUX-NEXT: movl $0, %ecx
-; LINUX-NEXT: cmovbl %edx, %ecx
+; LINUX-NEXT: cmpl $8, %eax
; LINUX-NEXT: movl $8, %ebx
; LINUX-NEXT: cmovbl %eax, %ebx
+; LINUX-NEXT: testl %edx, %edx
+; LINUX-NEXT: cmovnel %esi, %ebx
+; LINUX-NEXT: xorl %ecx, %ecx
; LINUX-NEXT: lock cmpxchg8b sc64
; LINUX-NEXT: jne .LBB3_1
; LINUX-NEXT: # %bb.2: # %atomicrmw.end
+; LINUX-NEXT: popl %esi
; LINUX-NEXT: popl %ebx
; LINUX-NEXT: retl
;
; PIC-LABEL: atomic_umin_i64:
; PIC: ## %bb.0: ## %entry
; PIC-NEXT: pushl %ebx
+; PIC-NEXT: pushl %edi
; PIC-NEXT: pushl %esi
; PIC-NEXT: calll L3$pb
; PIC-NEXT: L3$pb:
@@ -207,20 +206,21 @@ define i64 @atomic_umin_i64() nounwind {
; PIC-NEXT: movl L_sc64$non_lazy_ptr-L3$pb(%eax), %esi
; PIC-NEXT: movl (%esi), %eax
; PIC-NEXT: movl 4(%esi), %edx
+; PIC-NEXT: movl $8, %edi
; PIC-NEXT: .p2align 4
; PIC-NEXT: LBB3_1: ## %atomicrmw.start
; PIC-NEXT: ## =>This Inner Loop Header: Depth=1
-; PIC-NEXT: cmpl $9, %eax
-; PIC-NEXT: movl %edx, %ecx
-; PIC-NEXT: sbbl $0, %ecx
-; PIC-NEXT: movl $0, %ecx
-; PIC-NEXT: cmovbl %edx, %ecx
+; PIC-NEXT: cmpl $8, %eax
; PIC-NEXT: movl $8, %ebx
; PIC-NEXT: cmovbl %eax, %ebx
+; PIC-NEXT: testl %edx, %edx
+; PIC-NEXT: cmovnel %edi, %ebx
+; PIC-NEXT: xorl %ecx, %ecx
; PIC-NEXT: lock cmpxchg8b (%esi)
; PIC-NEXT: jne LBB3_1
; PIC-NEXT: ## %bb.2: ## %atomicrmw.end
; PIC-NEXT: popl %esi
+; PIC-NEXT: popl %edi
; PIC-NEXT: popl %ebx
; PIC-NEXT: retl
entry:
diff --git a/llvm/test/CodeGen/X86/atomic128.ll b/llvm/test/CodeGen/X86/atomic128.ll
index 8d43c612aa07f..737cc3de559a7 100644
--- a/llvm/test/CodeGen/X86/atomic128.ll
+++ b/llvm/test/CodeGen/X86/atomic128.ll
@@ -178,13 +178,13 @@ define void @fetch_and_min(ptr %p, i128 %bits) {
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: LBB6_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpq %rax, %rsi
-; CHECK-NEXT: movq %r8, %rcx
-; CHECK-NEXT: sbbq %rdx, %rcx
+; CHECK-NEXT: cmpq %rsi, %rax
+; CHECK-NEXT: movq %rdx, %rcx
+; CHECK-NEXT: sbbq %r8, %rcx
; CHECK-NEXT: movq %r8, %rcx
-; CHECK-NEXT: cmovgeq %rdx, %rcx
+; CHECK-NEXT: cmovlq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx
-; CHECK-NEXT: cmovgeq %rax, %rbx
+; CHECK-NEXT: cmovlq %rax, %rbx
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB6_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
@@ -240,13 +240,13 @@ define void @fetch_and_umin(ptr %p, i128 %bits) {
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: LBB8_1: ## %atomicrmw.start
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpq %rax, %rsi
-; CHECK-NEXT: movq %r8, %rcx
-; CHECK-NEXT: sbbq %rdx, %rcx
+; CHECK-NEXT: cmpq %rsi, %rax
+; CHECK-NEXT: movq %rdx, %rcx
+; CHECK-NEXT: sbbq %r8, %rcx
; CHECK-NEXT: movq %r8, %rcx
-; CHECK-NEXT: cmovaeq %rdx, %rcx
+; CHECK-NEXT: cmovbq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx
-; CHECK-NEXT: cmovaeq %rax, %rbx
+; CHECK-NEXT: cmovbq %rax, %rbx
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: jne LBB8_1
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
diff --git a/llvm/test/CodeGen/X86/atomic32.ll b/llvm/test/CodeGen/X86/atomic32.ll
index f4666738db7d2..cbd4d98430e58 100644
--- a/llvm/test/CodeGen/X86/atomic32.ll
+++ b/llvm/test/CodeGen/X86/atomic32.ll
@@ -392,7 +392,7 @@ define void @atomic_fetch_min32(i32 %x) nounwind {
; X64-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload
; X64-NEXT: movl %eax, %edx
; X64-NEXT: subl %ecx, %edx
-; X64-NEXT: cmovlel %eax, %ecx
+; X64-NEXT: cmovll %eax, %ecx
; X64-NEXT: lock cmpxchgl %ecx, sc32(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
@@ -415,7 +415,7 @@ define void @atomic_fetch_min32(i32 %x) nounwind {
; X86-CMOV-NEXT: movl (%esp), %ecx # 4-byte Reload
; X86-CMOV-NEXT: movl %eax, %edx
; X86-CMOV-NEXT: subl %ecx, %edx
-; X86-CMOV-NEXT: cmovlel %eax, %ecx
+; X86-CMOV-NEXT: cmovll %eax, %ecx
; X86-CMOV-NEXT: lock cmpxchgl %ecx, sc32
; X86-CMOV-NEXT: sete %cl
; X86-CMOV-NEXT: testb $1, %cl
@@ -441,7 +441,7 @@ define void @atomic_fetch_min32(i32 %x) nounwind {
; X86-NOCMOV-NEXT: movl %eax, %ecx
; X86-NOCMOV-NEXT: subl %edx, %ecx
; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NOCMOV-NEXT: jle .LBB7_4
+; X86-NOCMOV-NEXT: jl .LBB7_4
; X86-NOCMOV-NEXT: # %bb.3: # %atomicrmw.start
; X86-NOCMOV-NEXT: # in Loop: Header=BB7_1 Depth=1
; X86-NOCMOV-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
@@ -475,7 +475,7 @@ define void @atomic_fetch_min32(i32 %x) nounwind {
; X86-NOX87-NEXT: movl %eax, %ecx
; X86-NOX87-NEXT: subl %edx, %ecx
; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NOX87-NEXT: jle .LBB7_4
+; X86-NOX87-NEXT: jl .LBB7_4
; X86-NOX87-NEXT: # %bb.3: # %atomicrmw.start
; X86-NOX87-NEXT: # in Loop: Header=BB7_1 Depth=1
; X86-NOX87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
@@ -626,7 +626,7 @@ define void @atomic_fetch_umin32(i32 %x) nounwind {
; X64-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %ecx # 4-byte Reload
; X64-NEXT: movl %eax, %edx
; X64-NEXT: subl %ecx, %edx
-; X64-NEXT: cmovbel %eax, %ecx
+; X64-NEXT: cmovbl %eax, %ecx
; X64-NEXT: lock cmpxchgl %ecx, sc32(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
@@ -649,7 +649,7 @@ define void @atomic_fetch_umin32(i32 %x) nounwind {
; X86-CMOV-NEXT: movl (%esp), %ecx # 4-byte Reload
; X86-CMOV-NEXT: movl %eax, %edx
; X86-CMOV-NEXT: subl %ecx, %edx
-; X86-CMOV-NEXT: cmovbel %eax, %ecx
+; X86-CMOV-NEXT: cmovbl %eax, %ecx
; X86-CMOV-NEXT: lock cmpxchgl %ecx, sc32
; X86-CMOV-NEXT: sete %cl
; X86-CMOV-NEXT: testb $1, %cl
@@ -675,7 +675,7 @@ define void @atomic_fetch_umin32(i32 %x) nounwind {
; X86-NOCMOV-NEXT: movl %eax, %ecx
; X86-NOCMOV-NEXT: subl %edx, %ecx
; X86-NOCMOV-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NOCMOV-NEXT: jbe .LBB9_4
+; X86-NOCMOV-NEXT: jb .LBB9_4
; X86-NOCMOV-NEXT: # %bb.3: # %atomicrmw.start
; X86-NOCMOV-NEXT: # in Loop: Header=BB9_1 Depth=1
; X86-NOCMOV-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
@@ -709,7 +709,7 @@ define void @atomic_fetch_umin32(i32 %x) nounwind {
; X86-NOX87-NEXT: movl %eax, %ecx
; X86-NOX87-NEXT: subl %edx, %ecx
; X86-NOX87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; X86-NOX87-NEXT: jbe .LBB9_4
+; X86-NOX87-NEXT: jb .LBB9_4
; X86-NOX87-NEXT: # %bb.3: # %atomicrmw.start
; X86-NOX87-NEXT: # in Loop: Header=BB9_1 Depth=1
; X86-NOX87-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
diff --git a/llvm/test/CodeGen/X86/atomic64.ll b/llvm/test/CodeGen/X86/atomic64.ll
index 8f4da356e06cb..823bb336ae61b 100644
--- a/llvm/test/CodeGen/X86/atomic64.ll
+++ b/llvm/test/CodeGen/X86/atomic64.ll
@@ -404,7 +404,7 @@ define void @atomic_fetch_min64(i64 %x) nounwind {
; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
; X64-NEXT: movq %rax, %rdx
; X64-NEXT: subq %rcx, %rdx
-; X64-NEXT: cmovleq %rax, %rcx
+; X64-NEXT: cmovlq %rax, %rcx
; X64-NEXT: lock cmpxchgq %rcx, sc64(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
@@ -418,9 +418,10 @@ define void @atomic_fetch_min64(i64 %x) nounwind {
; I486: # %bb.0:
; I486-NEXT: pushl %ebp
; I486-NEXT: movl %esp, %ebp
+; I486-NEXT: pushl %edi
; I486-NEXT: pushl %esi
; I486-NEXT: andl $-8, %esp
-; I486-NEXT: subl $72, %esp
+; I486-NEXT: subl $64, %esp
; I486-NEXT: movl 12(%ebp), %eax
; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: movl 8(%ebp), %eax
@@ -432,17 +433,19 @@ define void @atomic_fetch_min64(i64 %x) nounwind {
; I486-NEXT: jmp .LBB7_1
; I486-NEXT: .LBB7_1: # %atomicrmw.start
; I486-NEXT: # =>This Inner Loop Header: Depth=1
-; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; I486-NEXT: subl %ecx, %esi
-; I486-NEXT: sbbl %eax, %edx
+; I486-NEXT: movl %ecx, %edx
+; I486-NEXT: subl %edi, %edx
+; I486-NEXT: movl %eax, %edx
+; I486-NEXT: sbbl %esi, %edx
; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; I486-NEXT: jge .LBB7_4
+; I486-NEXT: jl .LBB7_4
; I486-NEXT: # %bb.3: # %atomicrmw.start
; I486-NEXT: # in Loop: Header=BB7_1 Depth=1
; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
@@ -475,8 +478,9 @@ define void @atomic_fetch_min64(i64 %x) nounwind {
; I486-NEXT: je .LBB7_1
; I486-NEXT: jmp .LBB7_2
; I486-NEXT: .LBB7_2: # %atomicrmw.end
-; I486-NEXT: leal -4(%ebp), %esp
+; I486-NEXT: leal -8(%ebp), %esp
; I486-NEXT: popl %esi
+; I486-NEXT: popl %edi
; I486-NEXT: popl %ebp
; I486-NEXT: retl
%t1 = atomicrmw min ptr @sc64, i64 %x acquire
@@ -588,7 +592,7 @@ define void @atomic_fetch_umin64(i64 %x) nounwind {
; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
; X64-NEXT: movq %rax, %rdx
; X64-NEXT: subq %rcx, %rdx
-; X64-NEXT: cmovbeq %rax, %rcx
+; X64-NEXT: cmovbq %rax, %rcx
; X64-NEXT: lock cmpxchgq %rcx, sc64(%rip)
; X64-NEXT: sete %cl
; X64-NEXT: testb $1, %cl
@@ -602,9 +606,10 @@ define void @atomic_fetch_umin64(i64 %x) nounwind {
; I486: # %bb.0:
; I486-NEXT: pushl %ebp
; I486-NEXT: movl %esp, %ebp
+; I486-NEXT: pushl %edi
; I486-NEXT: pushl %esi
; I486-NEXT: andl $-8, %esp
-; I486-NEXT: subl $72, %esp
+; I486-NEXT: subl $64, %esp
; I486-NEXT: movl 12(%ebp), %eax
; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: movl 8(%ebp), %eax
@@ -616,17 +621,19 @@ define void @atomic_fetch_umin64(i64 %x) nounwind {
; I486-NEXT: jmp .LBB9_1
; I486-NEXT: .LBB9_1: # %atomicrmw.start
; I486-NEXT: # =>This Inner Loop Header: Depth=1
-; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload
; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
+; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload
; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload
; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; I486-NEXT: subl %ecx, %esi
-; I486-NEXT: sbbl %eax, %edx
+; I486-NEXT: movl %ecx, %edx
+; I486-NEXT: subl %edi, %edx
+; I486-NEXT: movl %eax, %edx
+; I486-NEXT: sbbl %esi, %edx
; I486-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; I486-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
-; I486-NEXT: jae .LBB9_4
+; I486-NEXT: jb .LBB9_4
; I486-NEXT: # %bb.3: # %atomicrmw.start
; I486-NEXT: # in Loop: Header=BB9_1 Depth=1
; I486-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
@@ -659,8 +666,9 @@ define void @atomic_fetch_umin64(i64 %x) nounwind {
; I486-NEXT: je .LBB9_1
; I486-NEXT: jmp .LBB9_2
; I486-NEXT: .LBB9_2: # %atomicrmw.end
-; I486-NEXT: leal -4(%ebp), %esp
+; I486-NEXT: leal -8(%ebp), %esp
; I486-NEXT: popl %esi
+; I486-NEXT: popl %edi
; I486-NEXT: popl %ebp
; I486-NEXT: retl
%t1 = atomicrmw umin ptr @sc64, i64 %x acquire
diff --git a/llvm/test/CodeGen/X86/atomic6432.ll b/llvm/test/CodeGen/X86/atomic6432.ll
index 8ff5f338e1482..4ebc5aba525cd 100644
--- a/llvm/test/CodeGen/X86/atomic6432.ll
+++ b/llvm/test/CodeGen/X86/atomic6432.ll
@@ -531,12 +531,12 @@ define void @atomic_fetch_min64(i64 %x) nounwind {
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X32-NEXT: movl (%esp), %ecx # 4-byte Reload
-; X32-NEXT: movl %ebx, %esi
-; X32-NEXT: subl %eax, %esi
-; X32-NEXT: movl %ecx, %esi
-; X32-NEXT: sbbl %edx, %esi
-; X32-NEXT: cmovgel %edx, %ecx
-; X32-NEXT: cmovgel %eax, %ebx
+; X32-NEXT: movl %eax, %esi
+; X32-NEXT: subl %ebx, %esi
+; X32-NEXT: movl %edx, %esi
+; X32-NEXT: sbbl %ecx, %esi
+; X32-NEXT: cmovll %edx, %ecx
+; X32-NEXT: cmovll %eax, %ebx
; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
@@ -613,12 +613,12 @@ define void @atomic_fetch_umin64(i64 %x) nounwind {
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload
; X32-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload
; X32-NEXT: movl (%esp), %ecx # 4-byte Reload
-; X32-NEXT: movl %ebx, %esi
-; X32-NEXT: subl %eax, %esi
-; X32-NEXT: movl %ecx, %esi
-; X32-NEXT: sbbl %edx, %esi
-; X32-NEXT: cmovael %edx, %ecx
-; X32-NEXT: cmovael %eax, %ebx
+; X32-NEXT: movl %eax, %esi
+; X32-NEXT: subl %ebx, %esi
+; X32-NEXT: movl %edx, %esi
+; X32-NEXT: sbbl %ecx, %esi
+; X32-NEXT: cmovbl %edx, %ecx
+; X32-NEXT: cmovbl %eax, %ebx
; X32-NEXT: lock cmpxchg8b sc64
; X32-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X32-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
diff --git a/llvm/test/CodeGen/X86/cmov.ll b/llvm/test/CodeGen/X86/cmov.ll
index 374e75967d52f..55482c6ce05af 100644
--- a/llvm/test/CodeGen/X86/cmov.ll
+++ b/llvm/test/CodeGen/X86/cmov.ll
@@ -213,10 +213,10 @@ define i64 @test8(i64 %0, i64 %1, i64 %2) {
define i32 @smin(i32 %x) {
; CHECK-LABEL: smin:
; CHECK: # %bb.0:
-; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: notl %edi
+; CHECK-NEXT: cmpl $-1, %edi
; CHECK-NEXT: movl $-1, %eax
-; CHECK-NEXT: cmovnsl %edi, %eax
+; CHECK-NEXT: cmovll %edi, %eax
; CHECK-NEXT: retq
%not_x = xor i32 %x, -1
%1 = icmp slt i32 %not_x, -1
@@ -251,9 +251,9 @@ define i32 @pr47049_2(i32 %0) {
define i32 @pr47049_3(i32 %0) {
; CHECK-LABEL: pr47049_3:
; CHECK: # %bb.0:
-; CHECK-NEXT: testl %edi, %edi
+; CHECK-NEXT: cmpl $2, %edi
; CHECK-NEXT: movl $1, %eax
-; CHECK-NEXT: cmovgl %edi, %eax
+; CHECK-NEXT: cmovgel %edi, %eax
; CHECK-NEXT: retq
%2 = icmp sgt i32 %0, 1
%3 = select i1 %2, i32 %0, i32 1
@@ -263,9 +263,9 @@ define i32 @pr47049_3(i32 %0) {
define i32 @pr47049_4(i32 %0) {
; CHECK-LABEL: pr47049_4:
; CHECK: # %bb.0:
-; CHECK-NEXT: testl %edi, %edi
-; CHECK-NEXT: movl $1, %eax
-; CHECK-NEXT: cmovnel %edi, %eax
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: cmpl $1, %edi
+; CHECK-NEXT: adcl $0, %eax
; CHECK-NEXT: retq
%2 = icmp ugt i32 %0, 1
%3 = select i1 %2, i32 %0, i32 1
diff --git a/llvm/test/CodeGen/X86/fpclamptosat_vec.ll b/llvm/test/CodeGen/X86/fpclamptosat_vec.ll
index 991ce33e58b4c..6b760b3f9afeb 100644
--- a/llvm/test/CodeGen/X86/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/X86/fpclamptosat_vec.ll
@@ -18,30 +18,30 @@ define <2 x i32> @stest_f64i32(<2 x double> %x) nounwind {
; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pxor %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
-; SSE-NEXT: pxor %xmm4, %xmm4
+; SSE-NEXT: pcmpeqd %xmm4, %xmm4
; SSE-NEXT: pcmpeqd %xmm3, %xmm4
-; SSE-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
-; SSE-NEXT: pcmpgtd %xmm2, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,0,2,2]
-; SSE-NEXT: pand %xmm4, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
-; SSE-NEXT: por %xmm2, %xmm3
-; SSE-NEXT: pand %xmm3, %xmm1
-; SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
-; SSE-NEXT: por %xmm1, %xmm3
-; SSE-NEXT: pxor %xmm3, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm2, %xmm2
-; SSE-NEXT: pcmpeqd %xmm1, %xmm2
-; SSE-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,0,2,2]
+; SSE-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
+; SSE-NEXT: pand %xmm4, %xmm3
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: pand %xmm2, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; SSE-NEXT: por %xmm1, %xmm0
-; SSE-NEXT: pand %xmm0, %xmm3
-; SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: por %xmm3, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE-NEXT: por %xmm1, %xmm2
+; SSE-NEXT: pxor %xmm2, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; SSE-NEXT: pxor %xmm3, %xmm3
+; SSE-NEXT: pcmpeqd %xmm1, %xmm3
+; SSE-NEXT: movdqa {{.*#+}} xmm1 = [4294967295,4294967295]
+; SSE-NEXT: pcmpgtd %xmm0, %xmm1
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,2,2]
+; SSE-NEXT: pand %xmm3, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; SSE-NEXT: por %xmm0, %xmm1
+; SSE-NEXT: pand %xmm1, %xmm2
+; SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: por %xmm2, %xmm1
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; SSE-NEXT: retq
;
; AVX2-LABEL: stest_f64i32:
@@ -53,11 +53,11 @@ define <2 x i32> @stest_f64i32(<2 x double> %x) nounwind {
; AVX2-NEXT: vmovq %rcx, %xmm1
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm1 = [2147483647,2147483647]
+; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm2 = [18446744071562067968,18446744071562067968]
+; AVX2-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm3
+; AVX2-NEXT: vblendvpd %xmm3, %xmm0, %xmm2, %xmm0
; AVX2-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm1 = [18446744071562067968,18446744071562067968]
-; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2
-; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX2-NEXT: retq
;
@@ -165,28 +165,29 @@ define <2 x i32> @ustest_f64i32(<2 x double> %x) nounwind {
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pxor %xmm0, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
-; SSE-NEXT: pxor %xmm4, %xmm4
-; SSE-NEXT: pcmpeqd %xmm3, %xmm4
-; SSE-NEXT: movdqa {{.*#+}} xmm3 = [2147483647,2147483647]
-; SSE-NEXT: pcmpgtd %xmm2, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,0,2,2]
+; SSE-NEXT: movdqa %xmm2, %xmm3
+; SSE-NEXT: pcmpgtd %xmm0, %xmm3
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
+; SSE-NEXT: pcmpeqd %xmm0, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: por %xmm2, %xmm3
-; SSE-NEXT: pand %xmm3, %xmm1
-; SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
-; SSE-NEXT: por %xmm1, %xmm3
-; SSE-NEXT: movdqa %xmm3, %xmm1
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: pcmpgtd %xmm0, %xmm2
-; SSE-NEXT: pcmpeqd %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; SSE-NEXT: pand %xmm1, %xmm3
+; SSE-NEXT: pxor %xmm3, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; SSE-NEXT: pxor %xmm2, %xmm2
+; SSE-NEXT: pcmpeqd %xmm1, %xmm2
+; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483647,2147483647]
+; SSE-NEXT: pcmpgtd %xmm0, %xmm1
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,2,2]
; SSE-NEXT: pand %xmm2, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
+; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE-NEXT: por %xmm0, %xmm1
+; SSE-NEXT: pcmpeqd %xmm0, %xmm0
+; SSE-NEXT: pxor %xmm1, %xmm0
; SSE-NEXT: pand %xmm3, %xmm1
+; SSE-NEXT: por %xmm0, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; SSE-NEXT: retq
;
@@ -199,12 +200,12 @@ define <2 x i32> @ustest_f64i32(<2 x double> %x) nounwind {
; AVX2-NEXT: vmovq %rax, %xmm0
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm1 = [4294967295,4294967295]
+; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX2-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm2
+; AVX2-NEXT: vpand %xmm0, %xmm2, %xmm0
; AVX2-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm1
-; AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
-; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX2-NEXT: retq
;
; AVX512-LABEL: ustest_f64i32:
@@ -227,77 +228,77 @@ entry:
define <4 x i32> @stest_f32i32(<4 x float> %x) nounwind {
; SSE-LABEL: stest_f32i32:
; SSE: # %bb.0: # %entry
+; SSE-NEXT: cvttss2si %xmm0, %rax
+; SSE-NEXT: movq %rax, %xmm2
; SSE-NEXT: movaps %xmm0, %xmm1
-; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm1, %rax
; SSE-NEXT: movq %rax, %xmm1
-; SSE-NEXT: movaps %xmm0, %xmm2
-; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
-; SSE-NEXT: cvttss2si %xmm2, %rax
-; SSE-NEXT: movq %rax, %xmm2
; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
+; SSE-NEXT: cvttss2si %xmm1, %rax
+; SSE-NEXT: movq %rax, %xmm1
+; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm4
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm0[0]
-; SSE-NEXT: movdqa {{.*#+}} xmm3 = [2147483647,2147483647]
+; SSE-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm1[0]
+; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483647,2147483647]
+; SSE-NEXT: movdqa {{.*#+}} xmm3 = [18446744071562067968,18446744071562067968]
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
-; SSE-NEXT: movdqa %xmm4, %xmm1
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,1,3,3]
-; SSE-NEXT: pxor %xmm6, %xmm6
-; SSE-NEXT: pcmpeqd %xmm6, %xmm5
-; SSE-NEXT: movdqa {{.*#+}} xmm7 = [4294967295,4294967295]
-; SSE-NEXT: movdqa %xmm7, %xmm8
-; SSE-NEXT: pcmpgtd %xmm1, %xmm8
-; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm8[0,0,2,2]
-; SSE-NEXT: pand %xmm5, %xmm9
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm8[1,1,3,3]
-; SSE-NEXT: por %xmm9, %xmm1
-; SSE-NEXT: pand %xmm1, %xmm4
-; SSE-NEXT: pandn %xmm3, %xmm1
-; SSE-NEXT: por %xmm4, %xmm1
-; SSE-NEXT: movdqa %xmm2, %xmm4
-; SSE-NEXT: pxor %xmm0, %xmm4
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm6, %xmm5
-; SSE-NEXT: pcmpgtd %xmm4, %xmm7
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
-; SSE-NEXT: pand %xmm5, %xmm4
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
-; SSE-NEXT: por %xmm4, %xmm5
-; SSE-NEXT: pand %xmm5, %xmm2
-; SSE-NEXT: pandn %xmm3, %xmm5
-; SSE-NEXT: por %xmm2, %xmm5
-; SSE-NEXT: movdqa {{.*#+}} xmm2 = [18446744071562067968,18446744071562067968]
-; SSE-NEXT: movdqa %xmm5, %xmm3
-; SSE-NEXT: pxor %xmm0, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
+; SSE-NEXT: movdqa %xmm4, %xmm5
+; SSE-NEXT: pxor %xmm0, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm5[1,1,3,3]
; SSE-NEXT: pcmpeqd %xmm6, %xmm6
-; SSE-NEXT: pcmpeqd %xmm6, %xmm4
+; SSE-NEXT: pcmpeqd %xmm6, %xmm8
; SSE-NEXT: movdqa {{.*#+}} xmm7 = [18446744069414584320,18446744069414584320]
-; SSE-NEXT: pcmpgtd %xmm7, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm3[0,0,2,2]
-; SSE-NEXT: pand %xmm4, %xmm8
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
-; SSE-NEXT: por %xmm8, %xmm3
-; SSE-NEXT: pand %xmm3, %xmm5
-; SSE-NEXT: pandn %xmm2, %xmm3
-; SSE-NEXT: por %xmm5, %xmm3
-; SSE-NEXT: pxor %xmm1, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm6, %xmm4
-; SSE-NEXT: pcmpgtd %xmm7, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm0[0,0,2,2]
-; SSE-NEXT: pand %xmm4, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; SSE-NEXT: por %xmm5, %xmm0
-; SSE-NEXT: pand %xmm0, %xmm1
-; SSE-NEXT: pandn %xmm2, %xmm0
-; SSE-NEXT: por %xmm1, %xmm0
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
+; SSE-NEXT: pcmpgtd %xmm7, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2]
+; SSE-NEXT: pand %xmm8, %xmm9
+; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm5[1,1,3,3]
+; SSE-NEXT: por %xmm9, %xmm10
+; SSE-NEXT: pand %xmm10, %xmm4
+; SSE-NEXT: pandn %xmm3, %xmm10
+; SSE-NEXT: por %xmm4, %xmm10
+; SSE-NEXT: movdqa %xmm10, %xmm4
+; SSE-NEXT: pxor %xmm0, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm4[1,1,3,3]
+; SSE-NEXT: pxor %xmm8, %xmm8
+; SSE-NEXT: pcmpeqd %xmm8, %xmm9
+; SSE-NEXT: movdqa {{.*#+}} xmm5 = [4294967295,4294967295]
+; SSE-NEXT: movdqa %xmm5, %xmm11
+; SSE-NEXT: pcmpgtd %xmm4, %xmm11
+; SSE-NEXT: pshufd {{.*#+}} xmm12 = xmm11[0,0,2,2]
+; SSE-NEXT: pand %xmm9, %xmm12
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm11[1,1,3,3]
+; SSE-NEXT: por %xmm12, %xmm4
+; SSE-NEXT: pand %xmm4, %xmm10
+; SSE-NEXT: pandn %xmm1, %xmm4
+; SSE-NEXT: por %xmm10, %xmm4
+; SSE-NEXT: movdqa %xmm2, %xmm9
+; SSE-NEXT: pxor %xmm0, %xmm9
+; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm9[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm6, %xmm10
+; SSE-NEXT: pcmpgtd %xmm7, %xmm9
+; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm9[0,0,2,2]
+; SSE-NEXT: pand %xmm10, %xmm6
+; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm9[1,1,3,3]
+; SSE-NEXT: por %xmm6, %xmm7
+; SSE-NEXT: pand %xmm7, %xmm2
+; SSE-NEXT: pandn %xmm3, %xmm7
+; SSE-NEXT: por %xmm2, %xmm7
+; SSE-NEXT: pxor %xmm7, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm8, %xmm2
+; SSE-NEXT: pcmpgtd %xmm0, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm5[0,0,2,2]
+; SSE-NEXT: pand %xmm2, %xmm3
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3]
+; SSE-NEXT: por %xmm3, %xmm0
+; SSE-NEXT: pand %xmm0, %xmm7
+; SSE-NEXT: pandn %xmm1, %xmm0
+; SSE-NEXT: por %xmm7, %xmm0
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm4[0,2]
; SSE-NEXT: retq
;
; AVX2-LABEL: stest_f32i32:
@@ -317,11 +318,11 @@ define <4 x i32> @stest_f32i32(<4 x float> %x) nounwind {
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [2147483647,2147483647,2147483647,2147483647]
+; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [18446744071562067968,18446744071562067968,18446744071562067968,18446744071562067968]
+; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm3
+; AVX2-NEXT: vblendvpd %ymm3, %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [18446744071562067968,18446744071562067968,18446744071562067968,18446744071562067968]
-; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
; AVX2-NEXT: # ymm1 = mem[0,1,0,1]
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
@@ -487,71 +488,72 @@ entry:
define <4 x i32> @ustest_f32i32(<4 x float> %x) nounwind {
; SSE-LABEL: ustest_f32i32:
; SSE: # %bb.0: # %entry
-; SSE-NEXT: movaps %xmm0, %xmm1
-; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
-; SSE-NEXT: cvttss2si %xmm1, %rax
+; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: movaps %xmm0, %xmm2
-; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
+; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm2, %rax
; SSE-NEXT: movq %rax, %xmm2
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm4
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSE-NEXT: movaps %xmm0, %xmm2
+; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3],xmm0[3,3]
+; SSE-NEXT: cvttss2si %xmm2, %rax
+; SSE-NEXT: movq %rax, %xmm2
+; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm4 = xmm4[0],xmm0[0]
-; SSE-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
+; SSE-NEXT: movq %rax, %xmm3
+; SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0]
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
-; SSE-NEXT: movdqa %xmm4, %xmm1
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,1,3,3]
-; SSE-NEXT: pxor %xmm6, %xmm6
-; SSE-NEXT: pcmpeqd %xmm6, %xmm5
-; SSE-NEXT: movdqa {{.*#+}} xmm7 = [2147483647,2147483647]
-; SSE-NEXT: movdqa %xmm7, %xmm8
-; SSE-NEXT: pcmpgtd %xmm1, %xmm8
-; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm8[0,0,2,2]
-; SSE-NEXT: pand %xmm5, %xmm9
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm8[1,1,3,3]
-; SSE-NEXT: por %xmm9, %xmm1
-; SSE-NEXT: pand %xmm1, %xmm4
-; SSE-NEXT: pandn %xmm3, %xmm1
-; SSE-NEXT: por %xmm4, %xmm1
-; SSE-NEXT: movdqa %xmm2, %xmm4
-; SSE-NEXT: pxor %xmm0, %xmm4
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm6, %xmm5
-; SSE-NEXT: pcmpgtd %xmm4, %xmm7
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm7[0,0,2,2]
-; SSE-NEXT: pand %xmm5, %xmm4
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
-; SSE-NEXT: por %xmm4, %xmm5
-; SSE-NEXT: pand %xmm5, %xmm2
-; SSE-NEXT: pandn %xmm3, %xmm5
-; SSE-NEXT: por %xmm2, %xmm5
-; SSE-NEXT: movdqa %xmm5, %xmm2
-; SSE-NEXT: pxor %xmm0, %xmm2
-; SSE-NEXT: movdqa %xmm2, %xmm3
-; SSE-NEXT: pcmpgtd %xmm0, %xmm3
-; SSE-NEXT: pcmpeqd %xmm0, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE-NEXT: pand %xmm3, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
-; SSE-NEXT: por %xmm2, %xmm3
-; SSE-NEXT: pand %xmm5, %xmm3
-; SSE-NEXT: movdqa %xmm1, %xmm2
+; SSE-NEXT: movdqa %xmm3, %xmm2
; SSE-NEXT: pxor %xmm0, %xmm2
; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pcmpgtd %xmm0, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE-NEXT: pand %xmm4, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
-; SSE-NEXT: por %xmm2, %xmm0
-; SSE-NEXT: pand %xmm1, %xmm0
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
+; SSE-NEXT: pand %xmm5, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm4[1,1,3,3]
+; SSE-NEXT: por %xmm2, %xmm6
+; SSE-NEXT: pand %xmm3, %xmm6
+; SSE-NEXT: movdqa %xmm6, %xmm2
+; SSE-NEXT: pxor %xmm0, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3]
+; SSE-NEXT: pxor %xmm5, %xmm5
+; SSE-NEXT: pcmpeqd %xmm5, %xmm4
+; SSE-NEXT: movdqa {{.*#+}} xmm3 = [2147483647,2147483647]
+; SSE-NEXT: movdqa %xmm3, %xmm7
+; SSE-NEXT: pcmpgtd %xmm2, %xmm7
+; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
+; SSE-NEXT: pand %xmm4, %xmm8
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm7[1,1,3,3]
+; SSE-NEXT: por %xmm8, %xmm2
+; SSE-NEXT: pcmpeqd %xmm4, %xmm4
+; SSE-NEXT: pand %xmm2, %xmm6
+; SSE-NEXT: pxor %xmm4, %xmm2
+; SSE-NEXT: por %xmm6, %xmm2
+; SSE-NEXT: movdqa %xmm1, %xmm6
+; SSE-NEXT: pxor %xmm0, %xmm6
+; SSE-NEXT: movdqa %xmm6, %xmm7
+; SSE-NEXT: pcmpgtd %xmm0, %xmm7
+; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
+; SSE-NEXT: pcmpeqd %xmm0, %xmm6
+; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
+; SSE-NEXT: pand %xmm8, %xmm6
+; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm7[1,1,3,3]
+; SSE-NEXT: por %xmm6, %xmm7
+; SSE-NEXT: pand %xmm1, %xmm7
+; SSE-NEXT: pxor %xmm7, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm5, %xmm1
+; SSE-NEXT: pcmpgtd %xmm0, %xmm3
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm3[0,0,2,2]
+; SSE-NEXT: pand %xmm1, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3]
+; SSE-NEXT: por %xmm5, %xmm0
+; SSE-NEXT: pxor %xmm0, %xmm4
+; SSE-NEXT: pand %xmm7, %xmm0
+; SSE-NEXT: por %xmm4, %xmm0
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
; SSE-NEXT: retq
;
; AVX2-LABEL: ustest_f32i32:
@@ -571,14 +573,14 @@ define <4 x i32> @ustest_f32i32(<4 x float> %x) nounwind {
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4294967295,4294967295,4294967295,4294967295]
+; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm2
+; AVX2-NEXT: vpand %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm1
-; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
+; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
; AVX2-NEXT: # ymm1 = mem[0,1,0,1]
-; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
@@ -605,14 +607,15 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) nounwind {
; SSE-LABEL: stest_f16i32:
; SSE: # %bb.0: # %entry
; SSE-NEXT: subq $72, %rsp
-; SSE-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: movdqa %xmm0, %xmm1
-; SSE-NEXT: psrld $16, %xmm1
-; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: psrlq $48, %xmm0
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: psrlq $48, %xmm1
+; SSE-NEXT: movdqa %xmm1, (%rsp) # 16-byte Spill
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: psrld $16, %xmm1
+; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm0
@@ -621,9 +624,9 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) nounwind {
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: punpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
-; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
@@ -632,67 +635,66 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) nounwind {
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movdqa (%rsp), %xmm3 # 16-byte Reload
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
-; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483647,2147483647]
-; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
-; SSE-NEXT: movdqa %xmm3, %xmm1
-; SSE-NEXT: movdqa %xmm3, %xmm8
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
-; SSE-NEXT: pxor %xmm4, %xmm4
-; SSE-NEXT: pcmpeqd %xmm4, %xmm3
-; SSE-NEXT: movdqa {{.*#+}} xmm5 = [4294967295,4294967295]
-; SSE-NEXT: movdqa %xmm5, %xmm6
-; SSE-NEXT: pcmpgtd %xmm1, %xmm6
-; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
-; SSE-NEXT: pand %xmm3, %xmm7
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm6[1,1,3,3]
-; SSE-NEXT: por %xmm7, %xmm1
-; SSE-NEXT: pand %xmm1, %xmm8
-; SSE-NEXT: pandn %xmm2, %xmm1
-; SSE-NEXT: por %xmm8, %xmm1
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 16-byte Reload
-; SSE-NEXT: movdqa %xmm7, %xmm3
-; SSE-NEXT: pxor %xmm0, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm3[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm4, %xmm6
-; SSE-NEXT: pcmpgtd %xmm3, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm5[0,0,2,2]
-; SSE-NEXT: pand %xmm6, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
-; SSE-NEXT: por %xmm3, %xmm4
-; SSE-NEXT: movdqa %xmm7, %xmm3
-; SSE-NEXT: pand %xmm4, %xmm3
-; SSE-NEXT: pandn %xmm2, %xmm4
-; SSE-NEXT: por %xmm3, %xmm4
+; SSE-NEXT: movq %rax, %xmm3
+; SSE-NEXT: punpcklqdq (%rsp), %xmm3 # 16-byte Folded Reload
+; SSE-NEXT: # xmm3 = xmm3[0],mem[0]
+; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483647,2147483647]
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [18446744071562067968,18446744071562067968]
-; SSE-NEXT: movdqa %xmm4, %xmm3
+; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
+; SSE-NEXT: movdqa %xmm3, %xmm4
+; SSE-NEXT: pxor %xmm0, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm4[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm5, %xmm5
+; SSE-NEXT: pcmpeqd %xmm5, %xmm7
+; SSE-NEXT: movdqa {{.*#+}} xmm6 = [18446744069414584320,18446744069414584320]
+; SSE-NEXT: pcmpgtd %xmm6, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm4[0,0,2,2]
+; SSE-NEXT: pand %xmm7, %xmm8
+; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm4[1,1,3,3]
+; SSE-NEXT: por %xmm8, %xmm9
+; SSE-NEXT: pand %xmm9, %xmm3
+; SSE-NEXT: pandn %xmm2, %xmm9
+; SSE-NEXT: por %xmm3, %xmm9
+; SSE-NEXT: movdqa %xmm9, %xmm3
; SSE-NEXT: pxor %xmm0, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm3[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm6, %xmm6
-; SSE-NEXT: pcmpeqd %xmm6, %xmm5
-; SSE-NEXT: movdqa {{.*#+}} xmm7 = [18446744069414584320,18446744069414584320]
-; SSE-NEXT: pcmpgtd %xmm7, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm3[0,0,2,2]
-; SSE-NEXT: pand %xmm5, %xmm8
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
-; SSE-NEXT: por %xmm8, %xmm3
-; SSE-NEXT: pand %xmm3, %xmm4
-; SSE-NEXT: pandn %xmm2, %xmm3
-; SSE-NEXT: por %xmm4, %xmm3
-; SSE-NEXT: pxor %xmm1, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm6, %xmm4
-; SSE-NEXT: pcmpgtd %xmm7, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm0[0,0,2,2]
-; SSE-NEXT: pand %xmm4, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm3[1,1,3,3]
+; SSE-NEXT: pxor %xmm7, %xmm7
+; SSE-NEXT: pcmpeqd %xmm7, %xmm8
+; SSE-NEXT: movdqa {{.*#+}} xmm4 = [4294967295,4294967295]
+; SSE-NEXT: movdqa %xmm4, %xmm10
+; SSE-NEXT: pcmpgtd %xmm3, %xmm10
+; SSE-NEXT: pshufd {{.*#+}} xmm11 = xmm10[0,0,2,2]
+; SSE-NEXT: pand %xmm8, %xmm11
+; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm10[1,1,3,3]
+; SSE-NEXT: por %xmm11, %xmm3
+; SSE-NEXT: pand %xmm3, %xmm9
+; SSE-NEXT: pandn %xmm1, %xmm3
+; SSE-NEXT: por %xmm9, %xmm3
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload
+; SSE-NEXT: movdqa %xmm10, %xmm8
+; SSE-NEXT: pxor %xmm0, %xmm8
+; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm8[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm5, %xmm9
+; SSE-NEXT: pcmpgtd %xmm6, %xmm8
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm8[0,0,2,2]
+; SSE-NEXT: pand %xmm9, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm8[1,1,3,3]
+; SSE-NEXT: por %xmm5, %xmm6
+; SSE-NEXT: movdqa %xmm10, %xmm5
+; SSE-NEXT: pand %xmm6, %xmm5
+; SSE-NEXT: pandn %xmm2, %xmm6
+; SSE-NEXT: por %xmm5, %xmm6
+; SSE-NEXT: pxor %xmm6, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm7, %xmm2
+; SSE-NEXT: pcmpgtd %xmm0, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
+; SSE-NEXT: pand %xmm2, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
; SSE-NEXT: por %xmm5, %xmm0
-; SSE-NEXT: pand %xmm0, %xmm1
-; SSE-NEXT: pandn %xmm2, %xmm0
-; SSE-NEXT: por %xmm1, %xmm0
+; SSE-NEXT: pand %xmm0, %xmm6
+; SSE-NEXT: pandn %xmm1, %xmm0
+; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
; SSE-NEXT: addq $72, %rsp
; SSE-NEXT: retq
@@ -704,11 +706,11 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) nounwind {
; AVX2-NEXT: vcvttss2si %xmm1, %rax
; AVX2-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
-; AVX2-NEXT: vcvttss2si %xmm1, %rcx
-; AVX2-NEXT: vcvtph2ps %xmm0, %xmm1
; AVX2-NEXT: vmovq %rax, %xmm2
; AVX2-NEXT: vcvttss2si %xmm1, %rax
-; AVX2-NEXT: vmovq %rcx, %xmm1
+; AVX2-NEXT: vmovq %rax, %xmm1
+; AVX2-NEXT: vcvtph2ps %xmm0, %xmm3
+; AVX2-NEXT: vcvttss2si %xmm3, %rax
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX2-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm0
@@ -718,11 +720,11 @@ define <4 x i32> @stest_f16i32(<4 x half> %x) nounwind {
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [2147483647,2147483647,2147483647,2147483647]
+; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [18446744071562067968,18446744071562067968,18446744071562067968,18446744071562067968]
+; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm3
+; AVX2-NEXT: vblendvpd %ymm3, %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [18446744071562067968,18446744071562067968,18446744071562067968,18446744071562067968]
-; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
; AVX2-NEXT: # ymm1 = mem[0,1,0,1]
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
@@ -912,14 +914,15 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) nounwind {
; SSE-LABEL: ustest_f16i32:
; SSE: # %bb.0: # %entry
; SSE-NEXT: subq $72, %rsp
-; SSE-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: movdqa %xmm0, %xmm1
-; SSE-NEXT: psrld $16, %xmm1
-; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: psrlq $48, %xmm0
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: psrlq $48, %xmm1
+; SSE-NEXT: movdqa %xmm1, (%rsp) # 16-byte Spill
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: psrld $16, %xmm1
+; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm0
@@ -928,9 +931,9 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) nounwind {
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: punpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
-; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
@@ -939,62 +942,61 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) nounwind {
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movdqa (%rsp), %xmm3 # 16-byte Reload
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
-; SSE-NEXT: movdqa {{.*#+}} xmm2 = [4294967295,4294967295]
+; SSE-NEXT: movq %rax, %xmm1
+; SSE-NEXT: punpcklqdq (%rsp), %xmm1 # 16-byte Folded Reload
+; SSE-NEXT: # xmm1 = xmm1[0],mem[0]
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
-; SSE-NEXT: movdqa %xmm3, %xmm1
-; SSE-NEXT: movdqa %xmm3, %xmm8
+; SSE-NEXT: movdqa %xmm1, %xmm2
+; SSE-NEXT: pxor %xmm0, %xmm2
+; SSE-NEXT: movdqa %xmm2, %xmm3
+; SSE-NEXT: pcmpgtd %xmm0, %xmm3
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
+; SSE-NEXT: pcmpeqd %xmm0, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; SSE-NEXT: pand %xmm4, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm3[1,1,3,3]
+; SSE-NEXT: por %xmm2, %xmm5
+; SSE-NEXT: pand %xmm1, %xmm5
+; SSE-NEXT: movdqa %xmm5, %xmm1
; SSE-NEXT: pxor %xmm0, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
; SSE-NEXT: pxor %xmm4, %xmm4
; SSE-NEXT: pcmpeqd %xmm4, %xmm3
-; SSE-NEXT: movdqa {{.*#+}} xmm5 = [2147483647,2147483647]
-; SSE-NEXT: movdqa %xmm5, %xmm6
+; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483647,2147483647]
+; SSE-NEXT: movdqa %xmm2, %xmm6
; SSE-NEXT: pcmpgtd %xmm1, %xmm6
; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
; SSE-NEXT: pand %xmm3, %xmm7
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm6[1,1,3,3]
; SSE-NEXT: por %xmm7, %xmm1
-; SSE-NEXT: pand %xmm1, %xmm8
-; SSE-NEXT: pandn %xmm2, %xmm1
-; SSE-NEXT: por %xmm8, %xmm1
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 16-byte Reload
-; SSE-NEXT: movdqa %xmm7, %xmm3
-; SSE-NEXT: pxor %xmm0, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm3[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm4, %xmm6
-; SSE-NEXT: pcmpgtd %xmm3, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm5[0,0,2,2]
-; SSE-NEXT: pand %xmm6, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[1,1,3,3]
-; SSE-NEXT: por %xmm3, %xmm4
-; SSE-NEXT: movdqa %xmm7, %xmm3
-; SSE-NEXT: pand %xmm4, %xmm3
-; SSE-NEXT: pandn %xmm2, %xmm4
-; SSE-NEXT: por %xmm3, %xmm4
-; SSE-NEXT: movdqa %xmm4, %xmm2
-; SSE-NEXT: pxor %xmm0, %xmm2
-; SSE-NEXT: movdqa %xmm2, %xmm3
-; SSE-NEXT: pcmpgtd %xmm0, %xmm3
-; SSE-NEXT: pcmpeqd %xmm0, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE-NEXT: pand %xmm3, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
-; SSE-NEXT: por %xmm2, %xmm3
-; SSE-NEXT: pand %xmm4, %xmm3
-; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: pxor %xmm0, %xmm2
-; SSE-NEXT: movdqa %xmm2, %xmm4
-; SSE-NEXT: pcmpgtd %xmm0, %xmm4
-; SSE-NEXT: pcmpeqd %xmm0, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE-NEXT: pand %xmm4, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
-; SSE-NEXT: por %xmm2, %xmm0
-; SSE-NEXT: pand %xmm1, %xmm0
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
+; SSE-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE-NEXT: pand %xmm1, %xmm5
+; SSE-NEXT: pxor %xmm3, %xmm1
+; SSE-NEXT: por %xmm5, %xmm1
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm8 # 16-byte Reload
+; SSE-NEXT: movdqa %xmm8, %xmm5
+; SSE-NEXT: pxor %xmm0, %xmm5
+; SSE-NEXT: movdqa %xmm5, %xmm6
+; SSE-NEXT: pcmpgtd %xmm0, %xmm6
+; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
+; SSE-NEXT: pcmpeqd %xmm0, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
+; SSE-NEXT: pand %xmm7, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
+; SSE-NEXT: por %xmm5, %xmm6
+; SSE-NEXT: pand %xmm8, %xmm6
+; SSE-NEXT: pxor %xmm6, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm4, %xmm5
+; SSE-NEXT: pcmpgtd %xmm0, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
+; SSE-NEXT: pand %xmm5, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
+; SSE-NEXT: por %xmm4, %xmm0
+; SSE-NEXT: pxor %xmm0, %xmm3
+; SSE-NEXT: pand %xmm6, %xmm0
+; SSE-NEXT: por %xmm3, %xmm0
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSE-NEXT: addq $72, %rsp
; SSE-NEXT: retq
;
@@ -1019,14 +1021,14 @@ define <4 x i32> @ustest_f16i32(<4 x half> %x) nounwind {
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4294967295,4294967295,4294967295,4294967295]
+; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm2
+; AVX2-NEXT: vpand %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm1
-; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
+; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
; AVX2-NEXT: # ymm1 = mem[0,1,0,1]
-; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
@@ -1126,16 +1128,18 @@ define <2 x i16> @ustest_f64i16(<2 x double> %x) nounwind {
; SSE: # %bb.0: # %entry
; SSE-NEXT: cvttpd2dq %xmm0, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,u,u]
-; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: pcmpgtd %xmm0, %xmm2
-; SSE-NEXT: pand %xmm2, %xmm0
-; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: pxor %xmm2, %xmm2
+; SSE-NEXT: movapd %xmm0, %xmm3
+; SSE-NEXT: pcmpgtd %xmm2, %xmm3
+; SSE-NEXT: pand %xmm0, %xmm3
+; SSE-NEXT: movdqa %xmm3, %xmm0
+; SSE-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: pandn %xmm3, %xmm0
+; SSE-NEXT: pcmpgtd %xmm3, %xmm1
+; SSE-NEXT: pcmpeqd %xmm2, %xmm2
+; SSE-NEXT: pxor %xmm1, %xmm2
; SSE-NEXT: por %xmm0, %xmm2
-; SSE-NEXT: pxor %xmm0, %xmm0
-; SSE-NEXT: movdqa %xmm2, %xmm1
-; SSE-NEXT: pcmpgtd %xmm0, %xmm1
-; SSE-NEXT: pand %xmm2, %xmm1
-; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
+; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm2[0,2,2,3,4,5,6,7]
; SSE-NEXT: retq
;
; AVX-LABEL: ustest_f64i16:
@@ -1229,16 +1233,18 @@ define <4 x i16> @ustest_f32i16(<4 x float> %x) nounwind {
; SSE: # %bb.0: # %entry
; SSE-NEXT: cvttps2dq %xmm0, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
-; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: pcmpgtd %xmm0, %xmm2
-; SSE-NEXT: pand %xmm2, %xmm0
-; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: pxor %xmm2, %xmm2
+; SSE-NEXT: movdqa %xmm0, %xmm3
+; SSE-NEXT: pcmpgtd %xmm2, %xmm3
+; SSE-NEXT: pand %xmm0, %xmm3
+; SSE-NEXT: movdqa %xmm3, %xmm0
+; SSE-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: pandn %xmm3, %xmm0
+; SSE-NEXT: pcmpgtd %xmm3, %xmm1
+; SSE-NEXT: pcmpeqd %xmm2, %xmm2
+; SSE-NEXT: pxor %xmm1, %xmm2
; SSE-NEXT: por %xmm0, %xmm2
-; SSE-NEXT: pxor %xmm0, %xmm0
-; SSE-NEXT: movdqa %xmm2, %xmm1
-; SSE-NEXT: pcmpgtd %xmm0, %xmm1
-; SSE-NEXT: pand %xmm2, %xmm1
-; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
+; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm2[0,2,2,3,4,5,6,7]
; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE-NEXT: retq
@@ -1473,75 +1479,75 @@ define <8 x i16> @ustest_f16i16(<8 x half> %x) nounwind {
; SSE: # %bb.0: # %entry
; SSE-NEXT: subq $72, %rsp
; SSE-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: psrlq $48, %xmm0
+; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE-NEXT: cvttps2dq %xmm0, %xmm0
; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: callq __extendhfsf2 at PLT
-; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: psrld $16, %xmm0
-; SSE-NEXT: callq __extendhfsf2 at PLT
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; SSE-NEXT: cvttps2dq %xmm1, %xmm0
-; SSE-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
-; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE-NEXT: cvttps2dq %xmm0, %xmm0
+; SSE-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; SSE-NEXT: psrlq $48, %xmm0
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE-NEXT: cvttps2dq %xmm0, %xmm0
+; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; SSE-NEXT: callq __extendhfsf2 at PLT
+; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
+; SSE-NEXT: psrld $16, %xmm0
+; SSE-NEXT: callq __extendhfsf2 at PLT
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE-NEXT: cvttps2dq %xmm1, %xmm0
; SSE-NEXT: punpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
-; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: pcmpgtd %xmm0, %xmm2
-; SSE-NEXT: pand %xmm2, %xmm0
-; SSE-NEXT: pandn %xmm1, %xmm2
-; SSE-NEXT: por %xmm0, %xmm2
-; SSE-NEXT: movdqa %xmm1, %xmm3
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; SSE-NEXT: pcmpgtd %xmm0, %xmm3
-; SSE-NEXT: pand %xmm3, %xmm0
-; SSE-NEXT: pandn %xmm1, %xmm3
-; SSE-NEXT: por %xmm0, %xmm3
-; SSE-NEXT: pxor %xmm1, %xmm1
-; SSE-NEXT: movdqa %xmm3, %xmm0
-; SSE-NEXT: pcmpgtd %xmm1, %xmm0
-; SSE-NEXT: pand %xmm3, %xmm0
-; SSE-NEXT: movdqa %xmm2, %xmm3
-; SSE-NEXT: pcmpgtd %xmm1, %xmm3
-; SSE-NEXT: pand %xmm2, %xmm3
-; SSE-NEXT: pslld $16, %xmm3
-; SSE-NEXT: psrad $16, %xmm3
+; SSE-NEXT: pxor %xmm2, %xmm2
+; SSE-NEXT: movdqa %xmm0, %xmm3
+; SSE-NEXT: pcmpgtd %xmm2, %xmm3
+; SSE-NEXT: pand %xmm0, %xmm3
+; SSE-NEXT: movdqa %xmm1, %xmm0
+; SSE-NEXT: pcmpgtd %xmm3, %xmm0
+; SSE-NEXT: pand %xmm0, %xmm3
+; SSE-NEXT: pcmpeqd %xmm4, %xmm4
+; SSE-NEXT: pxor %xmm4, %xmm0
+; SSE-NEXT: por %xmm3, %xmm0
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Reload
+; SSE-NEXT: movdqa %xmm5, %xmm3
+; SSE-NEXT: pcmpgtd %xmm2, %xmm3
+; SSE-NEXT: pand %xmm5, %xmm3
+; SSE-NEXT: pcmpgtd %xmm3, %xmm1
+; SSE-NEXT: pand %xmm1, %xmm3
+; SSE-NEXT: pxor %xmm4, %xmm1
+; SSE-NEXT: por %xmm3, %xmm1
+; SSE-NEXT: pslld $16, %xmm1
+; SSE-NEXT: psrad $16, %xmm1
; SSE-NEXT: pslld $16, %xmm0
; SSE-NEXT: psrad $16, %xmm0
-; SSE-NEXT: packssdw %xmm3, %xmm0
+; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: addq $72, %rsp
; SSE-NEXT: retq
;
@@ -2642,30 +2648,30 @@ define <2 x i32> @stest_f64i32_mm(<2 x double> %x) nounwind {
; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pxor %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
-; SSE-NEXT: pxor %xmm4, %xmm4
+; SSE-NEXT: pcmpeqd %xmm4, %xmm4
; SSE-NEXT: pcmpeqd %xmm3, %xmm4
-; SSE-NEXT: movdqa {{.*#+}} xmm3 = [4294967295,4294967295]
-; SSE-NEXT: pcmpgtd %xmm2, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,0,2,2]
-; SSE-NEXT: pand %xmm4, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
-; SSE-NEXT: por %xmm2, %xmm3
-; SSE-NEXT: pand %xmm3, %xmm1
-; SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
-; SSE-NEXT: por %xmm1, %xmm3
-; SSE-NEXT: pxor %xmm3, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm2, %xmm2
-; SSE-NEXT: pcmpeqd %xmm1, %xmm2
-; SSE-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,0,2,2]
+; SSE-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
+; SSE-NEXT: pand %xmm4, %xmm3
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
+; SSE-NEXT: por %xmm3, %xmm2
; SSE-NEXT: pand %xmm2, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; SSE-NEXT: por %xmm1, %xmm0
-; SSE-NEXT: pand %xmm0, %xmm3
-; SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: por %xmm3, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE-NEXT: por %xmm1, %xmm2
+; SSE-NEXT: pxor %xmm2, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; SSE-NEXT: pxor %xmm3, %xmm3
+; SSE-NEXT: pcmpeqd %xmm1, %xmm3
+; SSE-NEXT: movdqa {{.*#+}} xmm1 = [4294967295,4294967295]
+; SSE-NEXT: pcmpgtd %xmm0, %xmm1
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,2,2]
+; SSE-NEXT: pand %xmm3, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
+; SSE-NEXT: por %xmm0, %xmm1
+; SSE-NEXT: pand %xmm1, %xmm2
+; SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE-NEXT: por %xmm2, %xmm1
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; SSE-NEXT: retq
;
; AVX2-LABEL: stest_f64i32_mm:
@@ -2677,11 +2683,11 @@ define <2 x i32> @stest_f64i32_mm(<2 x double> %x) nounwind {
; AVX2-NEXT: vmovq %rcx, %xmm1
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm1 = [2147483647,2147483647]
+; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm2 = [18446744071562067968,18446744071562067968]
+; AVX2-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm3
+; AVX2-NEXT: vblendvpd %xmm3, %xmm0, %xmm2, %xmm0
; AVX2-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm1 = [18446744071562067968,18446744071562067968]
-; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2
-; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX2-NEXT: retq
;
@@ -2786,28 +2792,29 @@ define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) nounwind {
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pxor %xmm0, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
-; SSE-NEXT: pxor %xmm4, %xmm4
-; SSE-NEXT: pcmpeqd %xmm3, %xmm4
-; SSE-NEXT: movdqa {{.*#+}} xmm3 = [2147483647,2147483647]
-; SSE-NEXT: pcmpgtd %xmm2, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,0,2,2]
+; SSE-NEXT: movdqa %xmm2, %xmm3
+; SSE-NEXT: pcmpgtd %xmm0, %xmm3
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
+; SSE-NEXT: pcmpeqd %xmm0, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
; SSE-NEXT: por %xmm2, %xmm3
-; SSE-NEXT: pand %xmm3, %xmm1
-; SSE-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3
-; SSE-NEXT: por %xmm1, %xmm3
-; SSE-NEXT: movdqa %xmm3, %xmm1
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: pcmpgtd %xmm0, %xmm2
-; SSE-NEXT: pcmpeqd %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
+; SSE-NEXT: pand %xmm1, %xmm3
+; SSE-NEXT: pxor %xmm3, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; SSE-NEXT: pxor %xmm2, %xmm2
+; SSE-NEXT: pcmpeqd %xmm1, %xmm2
+; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483647,2147483647]
+; SSE-NEXT: pcmpgtd %xmm0, %xmm1
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,0,2,2]
; SSE-NEXT: pand %xmm2, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
+; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; SSE-NEXT: por %xmm0, %xmm1
+; SSE-NEXT: pcmpeqd %xmm0, %xmm0
+; SSE-NEXT: pxor %xmm1, %xmm0
; SSE-NEXT: pand %xmm3, %xmm1
+; SSE-NEXT: por %xmm0, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; SSE-NEXT: retq
;
@@ -2820,12 +2827,12 @@ define <2 x i32> @ustest_f64i32_mm(<2 x double> %x) nounwind {
; AVX2-NEXT: vmovq %rax, %xmm0
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm1 = [4294967295,4294967295]
+; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX2-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm2
+; AVX2-NEXT: vpand %xmm0, %xmm2, %xmm0
; AVX2-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
; AVX2-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm1
-; AVX2-NEXT: vpand %xmm0, %xmm1, %xmm0
-; AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
+; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX2-NEXT: retq
;
; AVX512-LABEL: ustest_f64i32_mm:
@@ -2846,77 +2853,77 @@ entry:
define <4 x i32> @stest_f32i32_mm(<4 x float> %x) nounwind {
; SSE-LABEL: stest_f32i32_mm:
; SSE: # %bb.0: # %entry
+; SSE-NEXT: cvttss2si %xmm0, %rax
+; SSE-NEXT: movq %rax, %xmm2
; SSE-NEXT: movaps %xmm0, %xmm1
-; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm1, %rax
; SSE-NEXT: movq %rax, %xmm1
-; SSE-NEXT: movaps %xmm0, %xmm2
-; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
-; SSE-NEXT: cvttss2si %xmm2, %rax
-; SSE-NEXT: movq %rax, %xmm2
; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
+; SSE-NEXT: cvttss2si %xmm1, %rax
+; SSE-NEXT: movq %rax, %xmm1
+; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm3
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
+; SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm1[0]
+; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483647,2147483647]
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
-; SSE-NEXT: movdqa %xmm3, %xmm1
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
-; SSE-NEXT: pxor %xmm5, %xmm5
-; SSE-NEXT: pcmpeqd %xmm5, %xmm4
-; SSE-NEXT: movdqa {{.*#+}} xmm6 = [4294967295,4294967295]
-; SSE-NEXT: movdqa %xmm6, %xmm7
-; SSE-NEXT: pcmpgtd %xmm1, %xmm7
-; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
-; SSE-NEXT: pand %xmm4, %xmm8
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm7[1,1,3,3]
-; SSE-NEXT: por %xmm8, %xmm1
-; SSE-NEXT: movdqa {{.*#+}} xmm4 = [2147483647,2147483647]
-; SSE-NEXT: pand %xmm1, %xmm3
-; SSE-NEXT: pandn %xmm4, %xmm1
-; SSE-NEXT: por %xmm3, %xmm1
-; SSE-NEXT: movdqa %xmm2, %xmm3
-; SSE-NEXT: pxor %xmm0, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm3[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm5, %xmm7
-; SSE-NEXT: pcmpgtd %xmm3, %xmm6
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,0,2,2]
-; SSE-NEXT: pand %xmm7, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
-; SSE-NEXT: por %xmm3, %xmm5
-; SSE-NEXT: pand %xmm5, %xmm2
-; SSE-NEXT: pandn %xmm4, %xmm5
-; SSE-NEXT: por %xmm2, %xmm5
-; SSE-NEXT: movdqa %xmm5, %xmm2
-; SSE-NEXT: pxor %xmm0, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
+; SSE-NEXT: movdqa %xmm3, %xmm5
+; SSE-NEXT: pxor %xmm0, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm5[1,1,3,3]
; SSE-NEXT: pcmpeqd %xmm4, %xmm4
-; SSE-NEXT: pcmpeqd %xmm4, %xmm3
-; SSE-NEXT: movdqa {{.*#+}} xmm6 = [18446744069414584320,18446744069414584320]
-; SSE-NEXT: pcmpgtd %xmm6, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm2[0,0,2,2]
-; SSE-NEXT: pand %xmm3, %xmm7
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE-NEXT: por %xmm7, %xmm2
-; SSE-NEXT: movdqa {{.*#+}} xmm3 = [18446744071562067968,18446744071562067968]
-; SSE-NEXT: pand %xmm2, %xmm5
-; SSE-NEXT: pandn %xmm3, %xmm2
-; SSE-NEXT: por %xmm5, %xmm2
-; SSE-NEXT: pxor %xmm1, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm4, %xmm5
-; SSE-NEXT: pcmpgtd %xmm6, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,0,2,2]
-; SSE-NEXT: pand %xmm5, %xmm4
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm4, %xmm6
+; SSE-NEXT: movdqa {{.*#+}} xmm7 = [18446744069414584320,18446744069414584320]
+; SSE-NEXT: pcmpgtd %xmm7, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm5[0,0,2,2]
+; SSE-NEXT: pand %xmm6, %xmm8
+; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm5[1,1,3,3]
+; SSE-NEXT: por %xmm8, %xmm9
+; SSE-NEXT: movdqa {{.*#+}} xmm5 = [18446744071562067968,18446744071562067968]
+; SSE-NEXT: pand %xmm9, %xmm3
+; SSE-NEXT: pandn %xmm5, %xmm9
+; SSE-NEXT: por %xmm3, %xmm9
+; SSE-NEXT: movdqa %xmm9, %xmm3
+; SSE-NEXT: pxor %xmm0, %xmm3
+; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm3[1,1,3,3]
+; SSE-NEXT: pxor %xmm8, %xmm8
+; SSE-NEXT: pcmpeqd %xmm8, %xmm10
+; SSE-NEXT: movdqa {{.*#+}} xmm6 = [4294967295,4294967295]
+; SSE-NEXT: movdqa %xmm6, %xmm11
+; SSE-NEXT: pcmpgtd %xmm3, %xmm11
+; SSE-NEXT: pshufd {{.*#+}} xmm12 = xmm11[0,0,2,2]
+; SSE-NEXT: pand %xmm10, %xmm12
+; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm11[1,1,3,3]
+; SSE-NEXT: por %xmm12, %xmm3
+; SSE-NEXT: pand %xmm3, %xmm9
+; SSE-NEXT: pandn %xmm1, %xmm3
+; SSE-NEXT: por %xmm9, %xmm3
+; SSE-NEXT: movdqa %xmm2, %xmm9
+; SSE-NEXT: pxor %xmm0, %xmm9
+; SSE-NEXT: pshufd {{.*#+}} xmm10 = xmm9[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm4, %xmm10
+; SSE-NEXT: pcmpgtd %xmm7, %xmm9
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm9[0,0,2,2]
+; SSE-NEXT: pand %xmm10, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm9[1,1,3,3]
+; SSE-NEXT: por %xmm4, %xmm7
+; SSE-NEXT: pand %xmm7, %xmm2
+; SSE-NEXT: pandn %xmm5, %xmm7
+; SSE-NEXT: por %xmm2, %xmm7
+; SSE-NEXT: pxor %xmm7, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm8, %xmm2
+; SSE-NEXT: pcmpgtd %xmm0, %xmm6
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm6[0,0,2,2]
+; SSE-NEXT: pand %xmm2, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
; SSE-NEXT: por %xmm4, %xmm0
-; SSE-NEXT: pand %xmm0, %xmm1
-; SSE-NEXT: pandn %xmm3, %xmm0
-; SSE-NEXT: por %xmm1, %xmm0
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
+; SSE-NEXT: pand %xmm0, %xmm7
+; SSE-NEXT: pandn %xmm1, %xmm0
+; SSE-NEXT: por %xmm7, %xmm0
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
; SSE-NEXT: retq
;
; AVX2-LABEL: stest_f32i32_mm:
@@ -2936,11 +2943,11 @@ define <4 x i32> @stest_f32i32_mm(<4 x float> %x) nounwind {
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [2147483647,2147483647,2147483647,2147483647]
+; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [18446744071562067968,18446744071562067968,18446744071562067968,18446744071562067968]
+; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm3
+; AVX2-NEXT: vblendvpd %ymm3, %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [18446744071562067968,18446744071562067968,18446744071562067968,18446744071562067968]
-; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
; AVX2-NEXT: # ymm1 = mem[0,1,0,1]
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
@@ -3103,71 +3110,72 @@ entry:
define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) nounwind {
; SSE-LABEL: ustest_f32i32_mm:
; SSE: # %bb.0: # %entry
-; SSE-NEXT: movaps %xmm0, %xmm1
-; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,3],xmm0[3,3]
-; SSE-NEXT: cvttss2si %xmm1, %rax
+; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: movaps %xmm0, %xmm2
-; SSE-NEXT: unpckhpd {{.*#+}} xmm2 = xmm2[1],xmm0[1]
+; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm2, %rax
; SSE-NEXT: movq %rax, %xmm2
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
+; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
+; SSE-NEXT: movaps %xmm0, %xmm2
+; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,3],xmm0[3,3]
+; SSE-NEXT: cvttss2si %xmm2, %rax
+; SSE-NEXT: movq %rax, %xmm2
+; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm3
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm0[0]
+; SSE-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm2[0]
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
-; SSE-NEXT: movdqa %xmm3, %xmm1
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
-; SSE-NEXT: pxor %xmm5, %xmm5
-; SSE-NEXT: pcmpeqd %xmm5, %xmm4
-; SSE-NEXT: movdqa {{.*#+}} xmm6 = [2147483647,2147483647]
-; SSE-NEXT: movdqa %xmm6, %xmm7
-; SSE-NEXT: pcmpgtd %xmm1, %xmm7
-; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
-; SSE-NEXT: pand %xmm4, %xmm8
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm7[1,1,3,3]
-; SSE-NEXT: por %xmm8, %xmm1
-; SSE-NEXT: movdqa {{.*#+}} xmm4 = [4294967295,4294967295]
-; SSE-NEXT: pand %xmm1, %xmm3
-; SSE-NEXT: pandn %xmm4, %xmm1
-; SSE-NEXT: por %xmm3, %xmm1
-; SSE-NEXT: movdqa %xmm2, %xmm3
-; SSE-NEXT: pxor %xmm0, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm3[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm5, %xmm7
-; SSE-NEXT: pcmpgtd %xmm3, %xmm6
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm6[0,0,2,2]
-; SSE-NEXT: pand %xmm7, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
-; SSE-NEXT: por %xmm3, %xmm5
-; SSE-NEXT: pand %xmm5, %xmm2
-; SSE-NEXT: pandn %xmm4, %xmm5
-; SSE-NEXT: por %xmm2, %xmm5
-; SSE-NEXT: movdqa %xmm5, %xmm2
-; SSE-NEXT: pxor %xmm0, %xmm2
-; SSE-NEXT: movdqa %xmm2, %xmm3
-; SSE-NEXT: pcmpgtd %xmm0, %xmm3
-; SSE-NEXT: pcmpeqd %xmm0, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE-NEXT: pand %xmm3, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
-; SSE-NEXT: por %xmm2, %xmm3
-; SSE-NEXT: pand %xmm5, %xmm3
-; SSE-NEXT: movdqa %xmm1, %xmm2
+; SSE-NEXT: movdqa %xmm3, %xmm2
; SSE-NEXT: pxor %xmm0, %xmm2
; SSE-NEXT: movdqa %xmm2, %xmm4
; SSE-NEXT: pcmpgtd %xmm0, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE-NEXT: pand %xmm4, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
-; SSE-NEXT: por %xmm2, %xmm0
-; SSE-NEXT: pand %xmm1, %xmm0
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
+; SSE-NEXT: pand %xmm5, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm4[1,1,3,3]
+; SSE-NEXT: por %xmm2, %xmm6
+; SSE-NEXT: pand %xmm3, %xmm6
+; SSE-NEXT: movdqa %xmm6, %xmm2
+; SSE-NEXT: pxor %xmm0, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3]
+; SSE-NEXT: pxor %xmm5, %xmm5
+; SSE-NEXT: pcmpeqd %xmm5, %xmm4
+; SSE-NEXT: movdqa {{.*#+}} xmm3 = [2147483647,2147483647]
+; SSE-NEXT: movdqa %xmm3, %xmm7
+; SSE-NEXT: pcmpgtd %xmm2, %xmm7
+; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
+; SSE-NEXT: pand %xmm4, %xmm8
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm7[1,1,3,3]
+; SSE-NEXT: por %xmm8, %xmm2
+; SSE-NEXT: pcmpeqd %xmm4, %xmm4
+; SSE-NEXT: pand %xmm2, %xmm6
+; SSE-NEXT: pxor %xmm4, %xmm2
+; SSE-NEXT: por %xmm6, %xmm2
+; SSE-NEXT: movdqa %xmm1, %xmm6
+; SSE-NEXT: pxor %xmm0, %xmm6
+; SSE-NEXT: movdqa %xmm6, %xmm7
+; SSE-NEXT: pcmpgtd %xmm0, %xmm7
+; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm7[0,0,2,2]
+; SSE-NEXT: pcmpeqd %xmm0, %xmm6
+; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
+; SSE-NEXT: pand %xmm8, %xmm6
+; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm7[1,1,3,3]
+; SSE-NEXT: por %xmm6, %xmm7
+; SSE-NEXT: pand %xmm1, %xmm7
+; SSE-NEXT: pxor %xmm7, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm5, %xmm1
+; SSE-NEXT: pcmpgtd %xmm0, %xmm3
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm3[0,0,2,2]
+; SSE-NEXT: pand %xmm1, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3]
+; SSE-NEXT: por %xmm5, %xmm0
+; SSE-NEXT: pxor %xmm0, %xmm4
+; SSE-NEXT: pand %xmm7, %xmm0
+; SSE-NEXT: por %xmm4, %xmm0
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
; SSE-NEXT: retq
;
; AVX2-LABEL: ustest_f32i32_mm:
@@ -3187,14 +3195,14 @@ define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) nounwind {
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4294967295,4294967295,4294967295,4294967295]
+; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm2
+; AVX2-NEXT: vpand %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm1
-; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
+; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
; AVX2-NEXT: # ymm1 = mem[0,1,0,1]
-; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
@@ -3219,14 +3227,15 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) nounwind {
; SSE-LABEL: stest_f16i32_mm:
; SSE: # %bb.0: # %entry
; SSE-NEXT: subq $72, %rsp
-; SSE-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: movdqa %xmm0, %xmm1
-; SSE-NEXT: psrld $16, %xmm1
-; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: psrlq $48, %xmm0
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: psrlq $48, %xmm1
+; SSE-NEXT: movdqa %xmm1, (%rsp) # 16-byte Spill
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: psrld $16, %xmm1
+; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm0
@@ -3235,9 +3244,9 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) nounwind {
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: punpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
-; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
@@ -3246,67 +3255,66 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) nounwind {
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movdqa (%rsp), %xmm2 # 16-byte Reload
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; SSE-NEXT: movq %rax, %xmm2
+; SSE-NEXT: punpcklqdq (%rsp), %xmm2 # 16-byte Folded Reload
+; SSE-NEXT: # xmm2 = xmm2[0],mem[0]
+; SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483647,2147483647]
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
-; SSE-NEXT: movdqa %xmm2, %xmm1
-; SSE-NEXT: movdqa %xmm2, %xmm7
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; SSE-NEXT: pxor %xmm3, %xmm3
-; SSE-NEXT: pcmpeqd %xmm3, %xmm2
-; SSE-NEXT: movdqa {{.*#+}} xmm4 = [4294967295,4294967295]
-; SSE-NEXT: movdqa %xmm4, %xmm5
-; SSE-NEXT: pcmpgtd %xmm1, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
-; SSE-NEXT: pand %xmm2, %xmm6
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3]
-; SSE-NEXT: por %xmm6, %xmm1
-; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483647,2147483647]
-; SSE-NEXT: pand %xmm1, %xmm7
-; SSE-NEXT: pandn %xmm2, %xmm1
-; SSE-NEXT: por %xmm7, %xmm1
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 16-byte Reload
-; SSE-NEXT: movdqa %xmm7, %xmm5
-; SSE-NEXT: pxor %xmm0, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm5[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm3, %xmm6
-; SSE-NEXT: pcmpgtd %xmm5, %xmm4
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,0,2,2]
-; SSE-NEXT: pand %xmm6, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
-; SSE-NEXT: por %xmm3, %xmm4
-; SSE-NEXT: movdqa %xmm7, %xmm3
-; SSE-NEXT: pand %xmm4, %xmm3
-; SSE-NEXT: pandn %xmm2, %xmm4
-; SSE-NEXT: por %xmm3, %xmm4
-; SSE-NEXT: movdqa %xmm4, %xmm2
-; SSE-NEXT: pxor %xmm0, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm5, %xmm5
-; SSE-NEXT: pcmpeqd %xmm5, %xmm3
+; SSE-NEXT: movdqa %xmm2, %xmm4
+; SSE-NEXT: pxor %xmm0, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE-NEXT: pcmpeqd %xmm3, %xmm5
; SSE-NEXT: movdqa {{.*#+}} xmm6 = [18446744069414584320,18446744069414584320]
-; SSE-NEXT: pcmpgtd %xmm6, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm2[0,0,2,2]
-; SSE-NEXT: pand %xmm3, %xmm7
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE-NEXT: por %xmm7, %xmm2
-; SSE-NEXT: movdqa {{.*#+}} xmm3 = [18446744071562067968,18446744071562067968]
-; SSE-NEXT: pand %xmm2, %xmm4
-; SSE-NEXT: pandn %xmm3, %xmm2
-; SSE-NEXT: por %xmm4, %xmm2
-; SSE-NEXT: pxor %xmm1, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm5, %xmm4
-; SSE-NEXT: pcmpgtd %xmm6, %xmm0
-; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm0[0,0,2,2]
-; SSE-NEXT: pand %xmm4, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; SSE-NEXT: por %xmm5, %xmm0
-; SSE-NEXT: pand %xmm0, %xmm1
-; SSE-NEXT: pandn %xmm3, %xmm0
-; SSE-NEXT: por %xmm1, %xmm0
+; SSE-NEXT: pcmpgtd %xmm6, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm4[0,0,2,2]
+; SSE-NEXT: pand %xmm5, %xmm7
+; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm4[1,1,3,3]
+; SSE-NEXT: por %xmm7, %xmm8
+; SSE-NEXT: movdqa {{.*#+}} xmm4 = [18446744071562067968,18446744071562067968]
+; SSE-NEXT: pand %xmm8, %xmm2
+; SSE-NEXT: pandn %xmm4, %xmm8
+; SSE-NEXT: por %xmm2, %xmm8
+; SSE-NEXT: movdqa %xmm8, %xmm2
+; SSE-NEXT: pxor %xmm0, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm2[1,1,3,3]
+; SSE-NEXT: pxor %xmm7, %xmm7
+; SSE-NEXT: pcmpeqd %xmm7, %xmm9
+; SSE-NEXT: movdqa {{.*#+}} xmm5 = [4294967295,4294967295]
+; SSE-NEXT: movdqa %xmm5, %xmm10
+; SSE-NEXT: pcmpgtd %xmm2, %xmm10
+; SSE-NEXT: pshufd {{.*#+}} xmm11 = xmm10[0,0,2,2]
+; SSE-NEXT: pand %xmm9, %xmm11
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm10[1,1,3,3]
+; SSE-NEXT: por %xmm11, %xmm2
+; SSE-NEXT: pand %xmm2, %xmm8
+; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: por %xmm8, %xmm2
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 16-byte Reload
+; SSE-NEXT: movdqa %xmm10, %xmm8
+; SSE-NEXT: pxor %xmm0, %xmm8
+; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm8[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm3, %xmm9
+; SSE-NEXT: pcmpgtd %xmm6, %xmm8
+; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm8[0,0,2,2]
+; SSE-NEXT: pand %xmm9, %xmm3
+; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm8[1,1,3,3]
+; SSE-NEXT: por %xmm3, %xmm6
+; SSE-NEXT: movdqa %xmm10, %xmm3
+; SSE-NEXT: pand %xmm6, %xmm3
+; SSE-NEXT: pandn %xmm4, %xmm6
+; SSE-NEXT: por %xmm3, %xmm6
+; SSE-NEXT: pxor %xmm6, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm7, %xmm3
+; SSE-NEXT: pcmpgtd %xmm0, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[0,0,2,2]
+; SSE-NEXT: pand %xmm3, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm5[1,1,3,3]
+; SSE-NEXT: por %xmm4, %xmm0
+; SSE-NEXT: pand %xmm0, %xmm6
+; SSE-NEXT: pandn %xmm1, %xmm0
+; SSE-NEXT: por %xmm6, %xmm0
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
; SSE-NEXT: addq $72, %rsp
; SSE-NEXT: retq
@@ -3318,11 +3326,11 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) nounwind {
; AVX2-NEXT: vcvttss2si %xmm1, %rax
; AVX2-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX2-NEXT: vcvtph2ps %xmm1, %xmm1
-; AVX2-NEXT: vcvttss2si %xmm1, %rcx
-; AVX2-NEXT: vcvtph2ps %xmm0, %xmm1
; AVX2-NEXT: vmovq %rax, %xmm2
; AVX2-NEXT: vcvttss2si %xmm1, %rax
-; AVX2-NEXT: vmovq %rcx, %xmm1
+; AVX2-NEXT: vmovq %rax, %xmm1
+; AVX2-NEXT: vcvtph2ps %xmm0, %xmm3
+; AVX2-NEXT: vcvttss2si %xmm3, %rax
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX2-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX2-NEXT: vcvtph2ps %xmm0, %xmm0
@@ -3332,11 +3340,11 @@ define <4 x i32> @stest_f16i32_mm(<4 x half> %x) nounwind {
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [2147483647,2147483647,2147483647,2147483647]
+; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [18446744071562067968,18446744071562067968,18446744071562067968,18446744071562067968]
+; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm3
+; AVX2-NEXT: vblendvpd %ymm3, %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [18446744071562067968,18446744071562067968,18446744071562067968,18446744071562067968]
-; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm2
-; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
; AVX2-NEXT: # ymm1 = mem[0,1,0,1]
; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
@@ -3523,14 +3531,15 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) nounwind {
; SSE-LABEL: ustest_f16i32_mm:
; SSE: # %bb.0: # %entry
; SSE-NEXT: subq $72, %rsp
-; SSE-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: movdqa %xmm0, %xmm1
-; SSE-NEXT: psrld $16, %xmm1
-; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: movaps %xmm0, %xmm1
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]
; SSE-NEXT: movaps %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: psrlq $48, %xmm0
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: psrlq $48, %xmm1
+; SSE-NEXT: movdqa %xmm1, (%rsp) # 16-byte Spill
+; SSE-NEXT: movaps %xmm0, %xmm1
+; SSE-NEXT: psrld $16, %xmm1
+; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm0
@@ -3539,9 +3548,9 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) nounwind {
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: punpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
-; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
+; SSE-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
@@ -3550,62 +3559,61 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) nounwind {
; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: cvttss2si %xmm0, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movdqa (%rsp), %xmm2 # 16-byte Reload
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm0[0]
+; SSE-NEXT: movq %rax, %xmm1
+; SSE-NEXT: punpcklqdq (%rsp), %xmm1 # 16-byte Folded Reload
+; SSE-NEXT: # xmm1 = xmm1[0],mem[0]
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483648,2147483648]
-; SSE-NEXT: movdqa %xmm2, %xmm1
-; SSE-NEXT: movdqa %xmm2, %xmm7
-; SSE-NEXT: pxor %xmm0, %xmm1
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
-; SSE-NEXT: pxor %xmm3, %xmm3
-; SSE-NEXT: pcmpeqd %xmm3, %xmm2
-; SSE-NEXT: movdqa {{.*#+}} xmm4 = [2147483647,2147483647]
-; SSE-NEXT: movdqa %xmm4, %xmm5
-; SSE-NEXT: pcmpgtd %xmm1, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm5[0,0,2,2]
-; SSE-NEXT: pand %xmm2, %xmm6
-; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm5[1,1,3,3]
-; SSE-NEXT: por %xmm6, %xmm1
-; SSE-NEXT: movdqa {{.*#+}} xmm2 = [4294967295,4294967295]
-; SSE-NEXT: pand %xmm1, %xmm7
-; SSE-NEXT: pandn %xmm2, %xmm1
-; SSE-NEXT: por %xmm7, %xmm1
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm7 # 16-byte Reload
-; SSE-NEXT: movdqa %xmm7, %xmm5
-; SSE-NEXT: pxor %xmm0, %xmm5
-; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm5[1,1,3,3]
-; SSE-NEXT: pcmpeqd %xmm3, %xmm6
-; SSE-NEXT: pcmpgtd %xmm5, %xmm4
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[0,0,2,2]
-; SSE-NEXT: pand %xmm6, %xmm3
-; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
-; SSE-NEXT: por %xmm3, %xmm4
-; SSE-NEXT: movdqa %xmm7, %xmm3
-; SSE-NEXT: pand %xmm4, %xmm3
-; SSE-NEXT: pandn %xmm2, %xmm4
-; SSE-NEXT: por %xmm3, %xmm4
-; SSE-NEXT: movdqa %xmm4, %xmm2
+; SSE-NEXT: movdqa %xmm1, %xmm2
; SSE-NEXT: pxor %xmm0, %xmm2
; SSE-NEXT: movdqa %xmm2, %xmm3
; SSE-NEXT: pcmpgtd %xmm0, %xmm3
-; SSE-NEXT: pcmpeqd %xmm0, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
-; SSE-NEXT: pand %xmm3, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
-; SSE-NEXT: por %xmm2, %xmm3
-; SSE-NEXT: pand %xmm4, %xmm3
-; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: pxor %xmm0, %xmm2
-; SSE-NEXT: movdqa %xmm2, %xmm4
-; SSE-NEXT: pcmpgtd %xmm0, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
; SSE-NEXT: pcmpeqd %xmm0, %xmm2
; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; SSE-NEXT: pand %xmm4, %xmm2
-; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
-; SSE-NEXT: por %xmm2, %xmm0
-; SSE-NEXT: pand %xmm1, %xmm0
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm3[0,2]
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm3[1,1,3,3]
+; SSE-NEXT: por %xmm2, %xmm5
+; SSE-NEXT: pand %xmm1, %xmm5
+; SSE-NEXT: movdqa %xmm5, %xmm1
+; SSE-NEXT: pxor %xmm0, %xmm1
+; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
+; SSE-NEXT: pxor %xmm4, %xmm4
+; SSE-NEXT: pcmpeqd %xmm4, %xmm3
+; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2147483647,2147483647]
+; SSE-NEXT: movdqa %xmm2, %xmm6
+; SSE-NEXT: pcmpgtd %xmm1, %xmm6
+; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
+; SSE-NEXT: pand %xmm3, %xmm7
+; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm6[1,1,3,3]
+; SSE-NEXT: por %xmm7, %xmm1
+; SSE-NEXT: pcmpeqd %xmm3, %xmm3
+; SSE-NEXT: pand %xmm1, %xmm5
+; SSE-NEXT: pxor %xmm3, %xmm1
+; SSE-NEXT: por %xmm5, %xmm1
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm8 # 16-byte Reload
+; SSE-NEXT: movdqa %xmm8, %xmm5
+; SSE-NEXT: pxor %xmm0, %xmm5
+; SSE-NEXT: movdqa %xmm5, %xmm6
+; SSE-NEXT: pcmpgtd %xmm0, %xmm6
+; SSE-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
+; SSE-NEXT: pcmpeqd %xmm0, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
+; SSE-NEXT: pand %xmm7, %xmm5
+; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[1,1,3,3]
+; SSE-NEXT: por %xmm5, %xmm6
+; SSE-NEXT: pand %xmm8, %xmm6
+; SSE-NEXT: pxor %xmm6, %xmm0
+; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
+; SSE-NEXT: pcmpeqd %xmm4, %xmm5
+; SSE-NEXT: pcmpgtd %xmm0, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
+; SSE-NEXT: pand %xmm5, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[1,1,3,3]
+; SSE-NEXT: por %xmm4, %xmm0
+; SSE-NEXT: pxor %xmm0, %xmm3
+; SSE-NEXT: pand %xmm6, %xmm0
+; SSE-NEXT: por %xmm3, %xmm0
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; SSE-NEXT: addq $72, %rsp
; SSE-NEXT: retq
;
@@ -3630,14 +3638,14 @@ define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) nounwind {
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm2[0],xmm0[0]
; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4294967295,4294967295,4294967295,4294967295]
+; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
+; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm2
+; AVX2-NEXT: vpand %ymm0, %ymm2, %ymm0
; AVX2-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm2
; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
-; AVX2-NEXT: vpcmpgtq %ymm1, %ymm0, %ymm1
-; AVX2-NEXT: vpand %ymm0, %ymm1, %ymm0
-; AVX2-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
+; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [0,2,4,6,0,2,4,6]
; AVX2-NEXT: # ymm1 = mem[0,1,0,1]
-; AVX2-NEXT: vpermd %ymm0, %ymm1, %ymm0
+; AVX2-NEXT: vpermps %ymm0, %ymm1, %ymm0
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; AVX2-NEXT: vzeroupper
; AVX2-NEXT: retq
@@ -3732,16 +3740,18 @@ define <2 x i16> @ustest_f64i16_mm(<2 x double> %x) nounwind {
; SSE: # %bb.0: # %entry
; SSE-NEXT: cvttpd2dq %xmm0, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,u,u]
-; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: pcmpgtd %xmm0, %xmm2
-; SSE-NEXT: pand %xmm2, %xmm0
-; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: pxor %xmm2, %xmm2
+; SSE-NEXT: movapd %xmm0, %xmm3
+; SSE-NEXT: pcmpgtd %xmm2, %xmm3
+; SSE-NEXT: pand %xmm0, %xmm3
+; SSE-NEXT: movdqa %xmm3, %xmm0
+; SSE-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: pandn %xmm3, %xmm0
+; SSE-NEXT: pcmpgtd %xmm3, %xmm1
+; SSE-NEXT: pcmpeqd %xmm2, %xmm2
+; SSE-NEXT: pxor %xmm1, %xmm2
; SSE-NEXT: por %xmm0, %xmm2
-; SSE-NEXT: pxor %xmm0, %xmm0
-; SSE-NEXT: movdqa %xmm2, %xmm1
-; SSE-NEXT: pcmpgtd %xmm0, %xmm1
-; SSE-NEXT: pand %xmm2, %xmm1
-; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
+; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm2[0,2,2,3,4,5,6,7]
; SSE-NEXT: retq
;
; AVX-LABEL: ustest_f64i16_mm:
@@ -3830,16 +3840,18 @@ define <4 x i16> @ustest_f32i16_mm(<4 x float> %x) nounwind {
; SSE: # %bb.0: # %entry
; SSE-NEXT: cvttps2dq %xmm0, %xmm0
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
-; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: pcmpgtd %xmm0, %xmm2
-; SSE-NEXT: pand %xmm2, %xmm0
-; SSE-NEXT: pandn %xmm1, %xmm2
+; SSE-NEXT: pxor %xmm2, %xmm2
+; SSE-NEXT: movdqa %xmm0, %xmm3
+; SSE-NEXT: pcmpgtd %xmm2, %xmm3
+; SSE-NEXT: pand %xmm0, %xmm3
+; SSE-NEXT: movdqa %xmm3, %xmm0
+; SSE-NEXT: pcmpgtd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: pandn %xmm3, %xmm0
+; SSE-NEXT: pcmpgtd %xmm3, %xmm1
+; SSE-NEXT: pcmpeqd %xmm2, %xmm2
+; SSE-NEXT: pxor %xmm1, %xmm2
; SSE-NEXT: por %xmm0, %xmm2
-; SSE-NEXT: pxor %xmm0, %xmm0
-; SSE-NEXT: movdqa %xmm2, %xmm1
-; SSE-NEXT: pcmpgtd %xmm0, %xmm1
-; SSE-NEXT: pand %xmm2, %xmm1
-; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
+; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm2[0,2,2,3,4,5,6,7]
; SSE-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE-NEXT: retq
@@ -4069,75 +4081,75 @@ define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) nounwind {
; SSE: # %bb.0: # %entry
; SSE-NEXT: subq $72, %rsp
; SSE-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: psrlq $48, %xmm0
+; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE-NEXT: cvttps2dq %xmm0, %xmm0
; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: callq __extendhfsf2 at PLT
-; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
-; SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: psrld $16, %xmm0
-; SSE-NEXT: callq __extendhfsf2 at PLT
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
-; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
-; SSE-NEXT: cvttps2dq %xmm1, %xmm0
-; SSE-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
-; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
-; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE-NEXT: cvttps2dq %xmm0, %xmm0
+; SSE-NEXT: unpcklpd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
+; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: psrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
+; SSE-NEXT: psrlq $48, %xmm0
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE-NEXT: callq __extendhfsf2 at PLT
; SSE-NEXT: unpcklps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE-NEXT: cvttps2dq %xmm0, %xmm0
+; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; SSE-NEXT: callq __extendhfsf2 at PLT
+; SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
+; SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
+; SSE-NEXT: psrld $16, %xmm0
+; SSE-NEXT: callq __extendhfsf2 at PLT
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload
+; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; SSE-NEXT: cvttps2dq %xmm1, %xmm0
; SSE-NEXT: punpcklqdq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload
; SSE-NEXT: # xmm0 = xmm0[0],mem[0]
; SSE-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
-; SSE-NEXT: movdqa %xmm1, %xmm2
-; SSE-NEXT: pcmpgtd %xmm0, %xmm2
-; SSE-NEXT: pand %xmm2, %xmm0
-; SSE-NEXT: pandn %xmm1, %xmm2
-; SSE-NEXT: por %xmm0, %xmm2
-; SSE-NEXT: movdqa %xmm1, %xmm3
-; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload
-; SSE-NEXT: pcmpgtd %xmm0, %xmm3
-; SSE-NEXT: pand %xmm3, %xmm0
-; SSE-NEXT: pandn %xmm1, %xmm3
-; SSE-NEXT: por %xmm0, %xmm3
-; SSE-NEXT: pxor %xmm1, %xmm1
-; SSE-NEXT: movdqa %xmm3, %xmm0
-; SSE-NEXT: pcmpgtd %xmm1, %xmm0
-; SSE-NEXT: pand %xmm3, %xmm0
-; SSE-NEXT: movdqa %xmm2, %xmm3
-; SSE-NEXT: pcmpgtd %xmm1, %xmm3
-; SSE-NEXT: pand %xmm2, %xmm3
-; SSE-NEXT: pslld $16, %xmm3
-; SSE-NEXT: psrad $16, %xmm3
+; SSE-NEXT: pxor %xmm2, %xmm2
+; SSE-NEXT: movdqa %xmm0, %xmm3
+; SSE-NEXT: pcmpgtd %xmm2, %xmm3
+; SSE-NEXT: pand %xmm0, %xmm3
+; SSE-NEXT: movdqa %xmm1, %xmm0
+; SSE-NEXT: pcmpgtd %xmm3, %xmm0
+; SSE-NEXT: pand %xmm0, %xmm3
+; SSE-NEXT: pcmpeqd %xmm4, %xmm4
+; SSE-NEXT: pxor %xmm4, %xmm0
+; SSE-NEXT: por %xmm3, %xmm0
+; SSE-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm5 # 16-byte Reload
+; SSE-NEXT: movdqa %xmm5, %xmm3
+; SSE-NEXT: pcmpgtd %xmm2, %xmm3
+; SSE-NEXT: pand %xmm5, %xmm3
+; SSE-NEXT: pcmpgtd %xmm3, %xmm1
+; SSE-NEXT: pand %xmm1, %xmm3
+; SSE-NEXT: pxor %xmm4, %xmm1
+; SSE-NEXT: por %xmm3, %xmm1
+; SSE-NEXT: pslld $16, %xmm1
+; SSE-NEXT: psrad $16, %xmm1
; SSE-NEXT: pslld $16, %xmm0
; SSE-NEXT: psrad $16, %xmm0
-; SSE-NEXT: packssdw %xmm3, %xmm0
+; SSE-NEXT: packssdw %xmm1, %xmm0
; SSE-NEXT: addq $72, %rsp
; SSE-NEXT: retq
;
@@ -4176,122 +4188,77 @@ define <2 x i64> @stest_f64i64_mm(<2 x double> %x) nounwind {
; SSE-NEXT: pushq %rbx
; SSE-NEXT: subq $24, %rsp
; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: callq __fixdfti at PLT
; SSE-NEXT: movq %rax, %rbx
; SSE-NEXT: movq %rdx, %r14
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: callq __fixdfti at PLT
-; SSE-NEXT: xorl %ecx, %ecx
-; SSE-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
-; SSE-NEXT: cmpq %rsi, %rax
-; SSE-NEXT: movq %rdx, %rdi
-; SSE-NEXT: sbbq $0, %rdi
-; SSE-NEXT: cmovgeq %rcx, %rdx
-; SSE-NEXT: cmovgeq %rsi, %rax
-; SSE-NEXT: cmpq %rsi, %rbx
-; SSE-NEXT: movq %r14, %rdi
-; SSE-NEXT: sbbq $0, %rdi
-; SSE-NEXT: cmovlq %r14, %rcx
-; SSE-NEXT: cmovlq %rbx, %rsi
-; SSE-NEXT: movabsq $-9223372036854775808, %rdi # imm = 0x8000000000000000
-; SSE-NEXT: cmpq %rsi, %rdi
-; SSE-NEXT: movq $-1, %r8
-; SSE-NEXT: movq $-1, %r9
-; SSE-NEXT: sbbq %rcx, %r9
-; SSE-NEXT: cmovgeq %rdi, %rsi
-; SSE-NEXT: cmpq %rax, %rdi
-; SSE-NEXT: sbbq %rdx, %r8
+; SSE-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE-NEXT: cmpq %rax, %rcx
+; SSE-NEXT: movq $-1, %rsi
+; SSE-NEXT: movq $-1, %rdi
+; SSE-NEXT: sbbq %rdx, %rdi
+; SSE-NEXT: cmovgeq %rsi, %rdx
+; SSE-NEXT: cmovgeq %rcx, %rax
+; SSE-NEXT: movabsq $9223372036854775807, %rdi # imm = 0x7FFFFFFFFFFFFFFF
+; SSE-NEXT: cmpq %rdi, %rax
+; SSE-NEXT: sbbq $0, %rdx
; SSE-NEXT: cmovgeq %rdi, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movq %rsi, %xmm1
+; SSE-NEXT: cmpq %rbx, %rcx
+; SSE-NEXT: movq $-1, %rdx
+; SSE-NEXT: sbbq %r14, %rdx
+; SSE-NEXT: cmovlq %r14, %rsi
+; SSE-NEXT: cmovlq %rbx, %rcx
+; SSE-NEXT: cmpq %rdi, %rcx
+; SSE-NEXT: sbbq $0, %rsi
+; SSE-NEXT: cmovgeq %rdi, %rcx
+; SSE-NEXT: movq %rcx, %xmm0
+; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: addq $24, %rsp
; SSE-NEXT: popq %rbx
; SSE-NEXT: popq %r14
; SSE-NEXT: retq
;
-; AVX2-LABEL: stest_f64i64_mm:
-; AVX2: # %bb.0: # %entry
-; AVX2-NEXT: pushq %r14
-; AVX2-NEXT: pushq %rbx
-; AVX2-NEXT: subq $24, %rsp
-; AVX2-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
-; AVX2-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX2-NEXT: callq __fixdfti at PLT
-; AVX2-NEXT: movq %rax, %rbx
-; AVX2-NEXT: movq %rdx, %r14
-; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
-; AVX2-NEXT: callq __fixdfti at PLT
-; AVX2-NEXT: xorl %ecx, %ecx
-; AVX2-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
-; AVX2-NEXT: cmpq %rsi, %rax
-; AVX2-NEXT: movq %rdx, %rdi
-; AVX2-NEXT: sbbq $0, %rdi
-; AVX2-NEXT: cmovgeq %rcx, %rdx
-; AVX2-NEXT: cmovgeq %rsi, %rax
-; AVX2-NEXT: cmpq %rsi, %rbx
-; AVX2-NEXT: movq %r14, %rdi
-; AVX2-NEXT: sbbq $0, %rdi
-; AVX2-NEXT: cmovlq %r14, %rcx
-; AVX2-NEXT: cmovlq %rbx, %rsi
-; AVX2-NEXT: movabsq $-9223372036854775808, %rdi # imm = 0x8000000000000000
-; AVX2-NEXT: cmpq %rsi, %rdi
-; AVX2-NEXT: movq $-1, %r8
-; AVX2-NEXT: sbbq %rcx, %r8
-; AVX2-NEXT: movq $-1, %rcx
-; AVX2-NEXT: cmovgeq %rdi, %rsi
-; AVX2-NEXT: cmpq %rax, %rdi
-; AVX2-NEXT: sbbq %rdx, %rcx
-; AVX2-NEXT: cmovgeq %rdi, %rax
-; AVX2-NEXT: vmovq %rax, %xmm0
-; AVX2-NEXT: vmovq %rsi, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; AVX2-NEXT: addq $24, %rsp
-; AVX2-NEXT: popq %rbx
-; AVX2-NEXT: popq %r14
-; AVX2-NEXT: retq
-;
-; AVX512-LABEL: stest_f64i64_mm:
-; AVX512: # %bb.0: # %entry
-; AVX512-NEXT: pushq %r14
-; AVX512-NEXT: pushq %rbx
-; AVX512-NEXT: subq $24, %rsp
-; AVX512-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
-; AVX512-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
-; AVX512-NEXT: callq __fixdfti at PLT
-; AVX512-NEXT: movq %rax, %rbx
-; AVX512-NEXT: movq %rdx, %r14
-; AVX512-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
-; AVX512-NEXT: callq __fixdfti at PLT
-; AVX512-NEXT: xorl %ecx, %ecx
-; AVX512-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
-; AVX512-NEXT: cmpq %rsi, %rax
-; AVX512-NEXT: movq %rdx, %rdi
-; AVX512-NEXT: sbbq $0, %rdi
-; AVX512-NEXT: cmovgeq %rcx, %rdx
-; AVX512-NEXT: cmovgeq %rsi, %rax
-; AVX512-NEXT: cmpq %rsi, %rbx
-; AVX512-NEXT: movq %r14, %rdi
-; AVX512-NEXT: sbbq $0, %rdi
-; AVX512-NEXT: cmovlq %r14, %rcx
-; AVX512-NEXT: cmovlq %rbx, %rsi
-; AVX512-NEXT: movabsq $-9223372036854775808, %rdi # imm = 0x8000000000000000
-; AVX512-NEXT: cmpq %rsi, %rdi
-; AVX512-NEXT: movq $-1, %r8
-; AVX512-NEXT: movq $-1, %r9
-; AVX512-NEXT: sbbq %rcx, %r9
-; AVX512-NEXT: cmovgeq %rdi, %rsi
-; AVX512-NEXT: cmpq %rax, %rdi
-; AVX512-NEXT: sbbq %rdx, %r8
-; AVX512-NEXT: cmovgeq %rdi, %rax
-; AVX512-NEXT: vmovq %rax, %xmm0
-; AVX512-NEXT: vmovq %rsi, %xmm1
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; AVX512-NEXT: addq $24, %rsp
-; AVX512-NEXT: popq %rbx
-; AVX512-NEXT: popq %r14
-; AVX512-NEXT: retq
+; AVX-LABEL: stest_f64i64_mm:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: pushq %r14
+; AVX-NEXT: pushq %rbx
+; AVX-NEXT: subq $24, %rsp
+; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; AVX-NEXT: callq __fixdfti at PLT
+; AVX-NEXT: movq %rax, %rbx
+; AVX-NEXT: movq %rdx, %r14
+; AVX-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; AVX-NEXT: # xmm0 = mem[1,0]
+; AVX-NEXT: callq __fixdfti at PLT
+; AVX-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; AVX-NEXT: cmpq %rax, %rcx
+; AVX-NEXT: movq $-1, %rsi
+; AVX-NEXT: movq $-1, %rdi
+; AVX-NEXT: sbbq %rdx, %rdi
+; AVX-NEXT: cmovgeq %rsi, %rdx
+; AVX-NEXT: cmovgeq %rcx, %rax
+; AVX-NEXT: movabsq $9223372036854775807, %rdi # imm = 0x7FFFFFFFFFFFFFFF
+; AVX-NEXT: cmpq %rdi, %rax
+; AVX-NEXT: sbbq $0, %rdx
+; AVX-NEXT: cmovgeq %rdi, %rax
+; AVX-NEXT: cmpq %rbx, %rcx
+; AVX-NEXT: movq $-1, %rdx
+; AVX-NEXT: sbbq %r14, %rdx
+; AVX-NEXT: cmovlq %r14, %rsi
+; AVX-NEXT: cmovlq %rbx, %rcx
+; AVX-NEXT: cmpq %rdi, %rcx
+; AVX-NEXT: sbbq $0, %rsi
+; AVX-NEXT: cmovgeq %rdi, %rcx
+; AVX-NEXT: vmovq %rcx, %xmm0
+; AVX-NEXT: vmovq %rax, %xmm1
+; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-NEXT: addq $24, %rsp
+; AVX-NEXT: popq %rbx
+; AVX-NEXT: popq %r14
+; AVX-NEXT: retq
entry:
%conv = fptosi <2 x double> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
@@ -4364,26 +4331,25 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) nounwind {
; SSE-NEXT: pushq %rbx
; SSE-NEXT: subq $24, %rsp
; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: callq __fixdfti at PLT
; SSE-NEXT: movq %rax, %rbx
; SSE-NEXT: movq %rdx, %r14
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
; SSE-NEXT: callq __fixdfti at PLT
; SSE-NEXT: xorl %ecx, %ecx
; SSE-NEXT: testq %rdx, %rdx
+; SSE-NEXT: cmovsq %rcx, %rax
+; SSE-NEXT: cmovleq %rcx, %rdx
+; SSE-NEXT: testq %rdx, %rdx
; SSE-NEXT: cmovgq %rcx, %rax
-; SSE-NEXT: movl $1, %esi
-; SSE-NEXT: cmovgq %rsi, %rdx
; SSE-NEXT: testq %r14, %r14
-; SSE-NEXT: cmovgq %rcx, %rbx
-; SSE-NEXT: cmovleq %r14, %rsi
-; SSE-NEXT: testq %rsi, %rsi
; SSE-NEXT: cmovsq %rcx, %rbx
-; SSE-NEXT: testq %rdx, %rdx
-; SSE-NEXT: cmovsq %rcx, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movq %rbx, %xmm1
+; SSE-NEXT: cmovleq %rcx, %r14
+; SSE-NEXT: testq %r14, %r14
+; SSE-NEXT: cmovgq %rcx, %rbx
+; SSE-NEXT: movq %rbx, %xmm0
+; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: addq $24, %rsp
; SSE-NEXT: popq %rbx
@@ -4395,27 +4361,26 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) nounwind {
; AVX-NEXT: pushq %r14
; AVX-NEXT: pushq %rbx
; AVX-NEXT: subq $24, %rsp
-; AVX-NEXT: vmovapd %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]
+; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; AVX-NEXT: callq __fixdfti at PLT
; AVX-NEXT: movq %rax, %rbx
; AVX-NEXT: movq %rdx, %r14
-; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX-NEXT: vpermilpd $1, (%rsp), %xmm0 # 16-byte Folded Reload
+; AVX-NEXT: # xmm0 = mem[1,0]
; AVX-NEXT: callq __fixdfti at PLT
; AVX-NEXT: xorl %ecx, %ecx
; AVX-NEXT: testq %rdx, %rdx
+; AVX-NEXT: cmovsq %rcx, %rax
+; AVX-NEXT: cmovleq %rcx, %rdx
+; AVX-NEXT: testq %rdx, %rdx
; AVX-NEXT: cmovgq %rcx, %rax
-; AVX-NEXT: movl $1, %esi
-; AVX-NEXT: cmovgq %rsi, %rdx
; AVX-NEXT: testq %r14, %r14
-; AVX-NEXT: cmovgq %rcx, %rbx
-; AVX-NEXT: cmovleq %r14, %rsi
-; AVX-NEXT: testq %rsi, %rsi
; AVX-NEXT: cmovsq %rcx, %rbx
-; AVX-NEXT: testq %rdx, %rdx
-; AVX-NEXT: cmovsq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovq %rbx, %xmm1
+; AVX-NEXT: cmovleq %rcx, %r14
+; AVX-NEXT: testq %r14, %r14
+; AVX-NEXT: cmovgq %rcx, %rbx
+; AVX-NEXT: vmovq %rbx, %xmm0
+; AVX-NEXT: vmovq %rax, %xmm1
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-NEXT: addq $24, %rsp
; AVX-NEXT: popq %rbx
@@ -4427,131 +4392,86 @@ entry:
%spec.store.select7 = call <2 x i128> @llvm.smax.v2i128(<2 x i128> %spec.store.select, <2 x i128> zeroinitializer)
%conv6 = trunc <2 x i128> %spec.store.select7 to <2 x i64>
ret <2 x i64> %conv6
-}
-
-define <2 x i64> @stest_f32i64_mm(<2 x float> %x) nounwind {
-; SSE-LABEL: stest_f32i64_mm:
-; SSE: # %bb.0: # %entry
-; SSE-NEXT: pushq %r14
-; SSE-NEXT: pushq %rbx
-; SSE-NEXT: subq $24, %rsp
-; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
-; SSE-NEXT: callq __fixsfti at PLT
-; SSE-NEXT: movq %rax, %rbx
-; SSE-NEXT: movq %rdx, %r14
-; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
-; SSE-NEXT: callq __fixsfti at PLT
-; SSE-NEXT: xorl %ecx, %ecx
-; SSE-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
-; SSE-NEXT: cmpq %rsi, %rax
-; SSE-NEXT: movq %rdx, %rdi
-; SSE-NEXT: sbbq $0, %rdi
-; SSE-NEXT: cmovgeq %rcx, %rdx
-; SSE-NEXT: cmovgeq %rsi, %rax
-; SSE-NEXT: cmpq %rsi, %rbx
-; SSE-NEXT: movq %r14, %rdi
-; SSE-NEXT: sbbq $0, %rdi
-; SSE-NEXT: cmovlq %r14, %rcx
-; SSE-NEXT: cmovlq %rbx, %rsi
-; SSE-NEXT: movabsq $-9223372036854775808, %rdi # imm = 0x8000000000000000
-; SSE-NEXT: cmpq %rsi, %rdi
-; SSE-NEXT: movq $-1, %r8
-; SSE-NEXT: movq $-1, %r9
-; SSE-NEXT: sbbq %rcx, %r9
-; SSE-NEXT: cmovgeq %rdi, %rsi
-; SSE-NEXT: cmpq %rax, %rdi
-; SSE-NEXT: sbbq %rdx, %r8
-; SSE-NEXT: cmovgeq %rdi, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movq %rsi, %xmm1
-; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; SSE-NEXT: addq $24, %rsp
-; SSE-NEXT: popq %rbx
-; SSE-NEXT: popq %r14
-; SSE-NEXT: retq
-;
-; AVX2-LABEL: stest_f32i64_mm:
-; AVX2: # %bb.0: # %entry
-; AVX2-NEXT: pushq %r14
-; AVX2-NEXT: pushq %rbx
-; AVX2-NEXT: subq $24, %rsp
-; AVX2-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX2-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; AVX2-NEXT: callq __fixsfti at PLT
-; AVX2-NEXT: movq %rax, %rbx
-; AVX2-NEXT: movq %rdx, %r14
-; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
-; AVX2-NEXT: callq __fixsfti at PLT
-; AVX2-NEXT: xorl %ecx, %ecx
-; AVX2-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
-; AVX2-NEXT: cmpq %rsi, %rax
-; AVX2-NEXT: movq %rdx, %rdi
-; AVX2-NEXT: sbbq $0, %rdi
-; AVX2-NEXT: cmovgeq %rcx, %rdx
-; AVX2-NEXT: cmovgeq %rsi, %rax
-; AVX2-NEXT: cmpq %rsi, %rbx
-; AVX2-NEXT: movq %r14, %rdi
-; AVX2-NEXT: sbbq $0, %rdi
-; AVX2-NEXT: cmovlq %r14, %rcx
-; AVX2-NEXT: cmovlq %rbx, %rsi
-; AVX2-NEXT: movabsq $-9223372036854775808, %rdi # imm = 0x8000000000000000
-; AVX2-NEXT: cmpq %rsi, %rdi
-; AVX2-NEXT: movq $-1, %r8
-; AVX2-NEXT: sbbq %rcx, %r8
-; AVX2-NEXT: movq $-1, %rcx
-; AVX2-NEXT: cmovgeq %rdi, %rsi
-; AVX2-NEXT: cmpq %rax, %rdi
-; AVX2-NEXT: sbbq %rdx, %rcx
-; AVX2-NEXT: cmovgeq %rdi, %rax
-; AVX2-NEXT: vmovq %rax, %xmm0
-; AVX2-NEXT: vmovq %rsi, %xmm1
-; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; AVX2-NEXT: addq $24, %rsp
-; AVX2-NEXT: popq %rbx
-; AVX2-NEXT: popq %r14
-; AVX2-NEXT: retq
-;
-; AVX512-LABEL: stest_f32i64_mm:
-; AVX512: # %bb.0: # %entry
-; AVX512-NEXT: pushq %r14
-; AVX512-NEXT: pushq %rbx
-; AVX512-NEXT: subq $24, %rsp
-; AVX512-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX512-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
-; AVX512-NEXT: callq __fixsfti at PLT
-; AVX512-NEXT: movq %rax, %rbx
-; AVX512-NEXT: movq %rdx, %r14
-; AVX512-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
-; AVX512-NEXT: callq __fixsfti at PLT
-; AVX512-NEXT: xorl %ecx, %ecx
-; AVX512-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
-; AVX512-NEXT: cmpq %rsi, %rax
-; AVX512-NEXT: movq %rdx, %rdi
-; AVX512-NEXT: sbbq $0, %rdi
-; AVX512-NEXT: cmovgeq %rcx, %rdx
-; AVX512-NEXT: cmovgeq %rsi, %rax
-; AVX512-NEXT: cmpq %rsi, %rbx
-; AVX512-NEXT: movq %r14, %rdi
-; AVX512-NEXT: sbbq $0, %rdi
-; AVX512-NEXT: cmovlq %r14, %rcx
-; AVX512-NEXT: cmovlq %rbx, %rsi
-; AVX512-NEXT: movabsq $-9223372036854775808, %rdi # imm = 0x8000000000000000
-; AVX512-NEXT: cmpq %rsi, %rdi
-; AVX512-NEXT: movq $-1, %r8
-; AVX512-NEXT: movq $-1, %r9
-; AVX512-NEXT: sbbq %rcx, %r9
-; AVX512-NEXT: cmovgeq %rdi, %rsi
-; AVX512-NEXT: cmpq %rax, %rdi
-; AVX512-NEXT: sbbq %rdx, %r8
-; AVX512-NEXT: cmovgeq %rdi, %rax
-; AVX512-NEXT: vmovq %rax, %xmm0
-; AVX512-NEXT: vmovq %rsi, %xmm1
-; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; AVX512-NEXT: addq $24, %rsp
-; AVX512-NEXT: popq %rbx
-; AVX512-NEXT: popq %r14
-; AVX512-NEXT: retq
+}
+
+define <2 x i64> @stest_f32i64_mm(<2 x float> %x) nounwind {
+; SSE-LABEL: stest_f32i64_mm:
+; SSE: # %bb.0: # %entry
+; SSE-NEXT: pushq %r14
+; SSE-NEXT: pushq %rbx
+; SSE-NEXT: subq $24, %rsp
+; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
+; SSE-NEXT: callq __fixsfti at PLT
+; SSE-NEXT: movq %rax, %rbx
+; SSE-NEXT: movq %rdx, %r14
+; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; SSE-NEXT: callq __fixsfti at PLT
+; SSE-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE-NEXT: cmpq %rax, %rcx
+; SSE-NEXT: movq $-1, %rsi
+; SSE-NEXT: movq $-1, %rdi
+; SSE-NEXT: sbbq %rdx, %rdi
+; SSE-NEXT: cmovgeq %rsi, %rdx
+; SSE-NEXT: cmovgeq %rcx, %rax
+; SSE-NEXT: movabsq $9223372036854775807, %rdi # imm = 0x7FFFFFFFFFFFFFFF
+; SSE-NEXT: cmpq %rdi, %rax
+; SSE-NEXT: sbbq $0, %rdx
+; SSE-NEXT: cmovgeq %rdi, %rax
+; SSE-NEXT: cmpq %rbx, %rcx
+; SSE-NEXT: movq $-1, %rdx
+; SSE-NEXT: sbbq %r14, %rdx
+; SSE-NEXT: cmovlq %r14, %rsi
+; SSE-NEXT: cmovlq %rbx, %rcx
+; SSE-NEXT: cmpq %rdi, %rcx
+; SSE-NEXT: sbbq $0, %rsi
+; SSE-NEXT: cmovgeq %rdi, %rcx
+; SSE-NEXT: movq %rcx, %xmm0
+; SSE-NEXT: movq %rax, %xmm1
+; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; SSE-NEXT: addq $24, %rsp
+; SSE-NEXT: popq %rbx
+; SSE-NEXT: popq %r14
+; SSE-NEXT: retq
+;
+; AVX-LABEL: stest_f32i64_mm:
+; AVX: # %bb.0: # %entry
+; AVX-NEXT: pushq %r14
+; AVX-NEXT: pushq %rbx
+; AVX-NEXT: subq $24, %rsp
+; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; AVX-NEXT: callq __fixsfti at PLT
+; AVX-NEXT: movq %rax, %rbx
+; AVX-NEXT: movq %rdx, %r14
+; AVX-NEXT: vmovshdup (%rsp), %xmm0 # 16-byte Folded Reload
+; AVX-NEXT: # xmm0 = mem[1,1,3,3]
+; AVX-NEXT: callq __fixsfti at PLT
+; AVX-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; AVX-NEXT: cmpq %rax, %rcx
+; AVX-NEXT: movq $-1, %rsi
+; AVX-NEXT: movq $-1, %rdi
+; AVX-NEXT: sbbq %rdx, %rdi
+; AVX-NEXT: cmovgeq %rsi, %rdx
+; AVX-NEXT: cmovgeq %rcx, %rax
+; AVX-NEXT: movabsq $9223372036854775807, %rdi # imm = 0x7FFFFFFFFFFFFFFF
+; AVX-NEXT: cmpq %rdi, %rax
+; AVX-NEXT: sbbq $0, %rdx
+; AVX-NEXT: cmovgeq %rdi, %rax
+; AVX-NEXT: cmpq %rbx, %rcx
+; AVX-NEXT: movq $-1, %rdx
+; AVX-NEXT: sbbq %r14, %rdx
+; AVX-NEXT: cmovlq %r14, %rsi
+; AVX-NEXT: cmovlq %rbx, %rcx
+; AVX-NEXT: cmpq %rdi, %rcx
+; AVX-NEXT: sbbq $0, %rsi
+; AVX-NEXT: cmovgeq %rdi, %rcx
+; AVX-NEXT: vmovq %rcx, %xmm0
+; AVX-NEXT: vmovq %rax, %xmm1
+; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX-NEXT: addq $24, %rsp
+; AVX-NEXT: popq %rbx
+; AVX-NEXT: popq %r14
+; AVX-NEXT: retq
entry:
%conv = fptosi <2 x float> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
@@ -4624,26 +4544,25 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) nounwind {
; SSE-NEXT: pushq %rbx
; SSE-NEXT: subq $24, %rsp
; SSE-NEXT: movaps %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE-NEXT: callq __fixsfti at PLT
; SSE-NEXT: movq %rax, %rbx
; SSE-NEXT: movq %rdx, %r14
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
+; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE-NEXT: callq __fixsfti at PLT
; SSE-NEXT: xorl %ecx, %ecx
; SSE-NEXT: testq %rdx, %rdx
+; SSE-NEXT: cmovsq %rcx, %rax
+; SSE-NEXT: cmovleq %rcx, %rdx
+; SSE-NEXT: testq %rdx, %rdx
; SSE-NEXT: cmovgq %rcx, %rax
-; SSE-NEXT: movl $1, %esi
-; SSE-NEXT: cmovgq %rsi, %rdx
; SSE-NEXT: testq %r14, %r14
-; SSE-NEXT: cmovgq %rcx, %rbx
-; SSE-NEXT: cmovleq %r14, %rsi
-; SSE-NEXT: testq %rsi, %rsi
; SSE-NEXT: cmovsq %rcx, %rbx
-; SSE-NEXT: testq %rdx, %rdx
-; SSE-NEXT: cmovsq %rcx, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movq %rbx, %xmm1
+; SSE-NEXT: cmovleq %rcx, %r14
+; SSE-NEXT: testq %r14, %r14
+; SSE-NEXT: cmovgq %rcx, %rbx
+; SSE-NEXT: movq %rbx, %xmm0
+; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: addq $24, %rsp
; SSE-NEXT: popq %rbx
@@ -4656,26 +4575,25 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) nounwind {
; AVX-NEXT: pushq %rbx
; AVX-NEXT: subq $24, %rsp
; AVX-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3]
; AVX-NEXT: callq __fixsfti at PLT
; AVX-NEXT: movq %rax, %rbx
; AVX-NEXT: movq %rdx, %r14
-; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX-NEXT: vmovshdup (%rsp), %xmm0 # 16-byte Folded Reload
+; AVX-NEXT: # xmm0 = mem[1,1,3,3]
; AVX-NEXT: callq __fixsfti at PLT
; AVX-NEXT: xorl %ecx, %ecx
; AVX-NEXT: testq %rdx, %rdx
+; AVX-NEXT: cmovsq %rcx, %rax
+; AVX-NEXT: cmovleq %rcx, %rdx
+; AVX-NEXT: testq %rdx, %rdx
; AVX-NEXT: cmovgq %rcx, %rax
-; AVX-NEXT: movl $1, %esi
-; AVX-NEXT: cmovgq %rsi, %rdx
; AVX-NEXT: testq %r14, %r14
-; AVX-NEXT: cmovgq %rcx, %rbx
-; AVX-NEXT: cmovleq %r14, %rsi
-; AVX-NEXT: testq %rsi, %rsi
; AVX-NEXT: cmovsq %rcx, %rbx
-; AVX-NEXT: testq %rdx, %rdx
-; AVX-NEXT: cmovsq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovq %rbx, %xmm1
+; AVX-NEXT: cmovleq %rcx, %r14
+; AVX-NEXT: testq %r14, %r14
+; AVX-NEXT: cmovgq %rcx, %rbx
+; AVX-NEXT: vmovq %rbx, %xmm0
+; AVX-NEXT: vmovq %rax, %xmm1
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX-NEXT: addq $24, %rsp
; AVX-NEXT: popq %rbx
@@ -4695,36 +4613,35 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) nounwind {
; SSE-NEXT: pushq %r14
; SSE-NEXT: pushq %rbx
; SSE-NEXT: subq $24, %rsp
-; SSE-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: psrld $16, %xmm0
+; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: psrld $16, %xmm1
+; SSE-NEXT: movdqa %xmm1, (%rsp) # 16-byte Spill
; SSE-NEXT: callq __fixhfti at PLT
; SSE-NEXT: movq %rax, %rbx
; SSE-NEXT: movq %rdx, %r14
; SSE-NEXT: movaps (%rsp), %xmm0 # 16-byte Reload
; SSE-NEXT: callq __fixhfti at PLT
-; SSE-NEXT: xorl %ecx, %ecx
-; SSE-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
-; SSE-NEXT: cmpq %rsi, %rax
-; SSE-NEXT: movq %rdx, %rdi
-; SSE-NEXT: sbbq $0, %rdi
-; SSE-NEXT: cmovgeq %rcx, %rdx
-; SSE-NEXT: cmovgeq %rsi, %rax
-; SSE-NEXT: cmpq %rsi, %rbx
-; SSE-NEXT: movq %r14, %rdi
-; SSE-NEXT: sbbq $0, %rdi
-; SSE-NEXT: cmovlq %r14, %rcx
-; SSE-NEXT: cmovlq %rbx, %rsi
-; SSE-NEXT: movabsq $-9223372036854775808, %rdi # imm = 0x8000000000000000
-; SSE-NEXT: cmpq %rsi, %rdi
-; SSE-NEXT: movq $-1, %r8
-; SSE-NEXT: movq $-1, %r9
-; SSE-NEXT: sbbq %rcx, %r9
-; SSE-NEXT: cmovgeq %rdi, %rsi
-; SSE-NEXT: cmpq %rax, %rdi
-; SSE-NEXT: sbbq %rdx, %r8
+; SSE-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; SSE-NEXT: cmpq %rax, %rcx
+; SSE-NEXT: movq $-1, %rsi
+; SSE-NEXT: movq $-1, %rdi
+; SSE-NEXT: sbbq %rdx, %rdi
+; SSE-NEXT: cmovgeq %rsi, %rdx
+; SSE-NEXT: cmovgeq %rcx, %rax
+; SSE-NEXT: movabsq $9223372036854775807, %rdi # imm = 0x7FFFFFFFFFFFFFFF
+; SSE-NEXT: cmpq %rdi, %rax
+; SSE-NEXT: sbbq $0, %rdx
; SSE-NEXT: cmovgeq %rdi, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movq %rsi, %xmm1
+; SSE-NEXT: cmpq %rbx, %rcx
+; SSE-NEXT: movq $-1, %rdx
+; SSE-NEXT: sbbq %r14, %rdx
+; SSE-NEXT: cmovlq %r14, %rsi
+; SSE-NEXT: cmovlq %rbx, %rcx
+; SSE-NEXT: cmpq %rdi, %rcx
+; SSE-NEXT: sbbq $0, %rsi
+; SSE-NEXT: cmovgeq %rdi, %rcx
+; SSE-NEXT: movq %rcx, %xmm0
+; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: addq $24, %rsp
; SSE-NEXT: popq %rbx
@@ -4736,36 +4653,34 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) nounwind {
; AVX2-NEXT: pushq %r14
; AVX2-NEXT: pushq %rbx
; AVX2-NEXT: subq $24, %rsp
-; AVX2-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
-; AVX2-NEXT: vpsrld $16, %xmm0, %xmm0
+; AVX2-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; AVX2-NEXT: callq __fixhfti at PLT
; AVX2-NEXT: movq %rax, %rbx
; AVX2-NEXT: movq %rdx, %r14
-; AVX2-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX2-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; AVX2-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX2-NEXT: callq __fixhfti at PLT
-; AVX2-NEXT: xorl %ecx, %ecx
-; AVX2-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
-; AVX2-NEXT: cmpq %rsi, %rax
-; AVX2-NEXT: movq %rdx, %rdi
-; AVX2-NEXT: sbbq $0, %rdi
-; AVX2-NEXT: cmovgeq %rcx, %rdx
-; AVX2-NEXT: cmovgeq %rsi, %rax
-; AVX2-NEXT: cmpq %rsi, %rbx
-; AVX2-NEXT: movq %r14, %rdi
-; AVX2-NEXT: sbbq $0, %rdi
-; AVX2-NEXT: cmovlq %r14, %rcx
-; AVX2-NEXT: cmovlq %rbx, %rsi
-; AVX2-NEXT: movabsq $-9223372036854775808, %rdi # imm = 0x8000000000000000
-; AVX2-NEXT: cmpq %rsi, %rdi
-; AVX2-NEXT: movq $-1, %r8
-; AVX2-NEXT: sbbq %rcx, %r8
-; AVX2-NEXT: movq $-1, %rcx
-; AVX2-NEXT: cmovgeq %rdi, %rsi
-; AVX2-NEXT: cmpq %rax, %rdi
-; AVX2-NEXT: sbbq %rdx, %rcx
+; AVX2-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; AVX2-NEXT: cmpq %rax, %rcx
+; AVX2-NEXT: movq $-1, %rsi
+; AVX2-NEXT: movq $-1, %rdi
+; AVX2-NEXT: sbbq %rdx, %rdi
+; AVX2-NEXT: cmovgeq %rsi, %rdx
+; AVX2-NEXT: cmovgeq %rcx, %rax
+; AVX2-NEXT: movabsq $9223372036854775807, %rdi # imm = 0x7FFFFFFFFFFFFFFF
+; AVX2-NEXT: cmpq %rdi, %rax
+; AVX2-NEXT: sbbq $0, %rdx
; AVX2-NEXT: cmovgeq %rdi, %rax
-; AVX2-NEXT: vmovq %rax, %xmm0
-; AVX2-NEXT: vmovq %rsi, %xmm1
+; AVX2-NEXT: cmpq %rbx, %rcx
+; AVX2-NEXT: movq $-1, %rdx
+; AVX2-NEXT: sbbq %r14, %rdx
+; AVX2-NEXT: cmovlq %r14, %rsi
+; AVX2-NEXT: cmovlq %rbx, %rcx
+; AVX2-NEXT: cmpq %rdi, %rcx
+; AVX2-NEXT: sbbq $0, %rsi
+; AVX2-NEXT: cmovgeq %rdi, %rcx
+; AVX2-NEXT: vmovq %rcx, %xmm0
+; AVX2-NEXT: vmovq %rax, %xmm1
; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX2-NEXT: addq $24, %rsp
; AVX2-NEXT: popq %rbx
@@ -4777,36 +4692,33 @@ define <2 x i64> @stest_f16i64_mm(<2 x half> %x) nounwind {
; AVX512-NEXT: pushq %r14
; AVX512-NEXT: pushq %rbx
; AVX512-NEXT: subq $24, %rsp
-; AVX512-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
-; AVX512-NEXT: vpsrld $16, %xmm0, %xmm0
+; AVX512-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
; AVX512-NEXT: callq __fixhfti at PLT
; AVX512-NEXT: movq %rax, %rbx
; AVX512-NEXT: movq %rdx, %r14
-; AVX512-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
+; AVX512-NEXT: vpsrld $16, (%rsp), %xmm0 # 16-byte Folded Reload
; AVX512-NEXT: callq __fixhfti at PLT
-; AVX512-NEXT: xorl %ecx, %ecx
-; AVX512-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
-; AVX512-NEXT: cmpq %rsi, %rax
-; AVX512-NEXT: movq %rdx, %rdi
-; AVX512-NEXT: sbbq $0, %rdi
-; AVX512-NEXT: cmovgeq %rcx, %rdx
-; AVX512-NEXT: cmovgeq %rsi, %rax
-; AVX512-NEXT: cmpq %rsi, %rbx
-; AVX512-NEXT: movq %r14, %rdi
-; AVX512-NEXT: sbbq $0, %rdi
-; AVX512-NEXT: cmovlq %r14, %rcx
-; AVX512-NEXT: cmovlq %rbx, %rsi
-; AVX512-NEXT: movabsq $-9223372036854775808, %rdi # imm = 0x8000000000000000
-; AVX512-NEXT: cmpq %rsi, %rdi
-; AVX512-NEXT: movq $-1, %r8
-; AVX512-NEXT: movq $-1, %r9
-; AVX512-NEXT: sbbq %rcx, %r9
-; AVX512-NEXT: cmovgeq %rdi, %rsi
-; AVX512-NEXT: cmpq %rax, %rdi
-; AVX512-NEXT: sbbq %rdx, %r8
+; AVX512-NEXT: movabsq $-9223372036854775808, %rcx # imm = 0x8000000000000000
+; AVX512-NEXT: cmpq %rax, %rcx
+; AVX512-NEXT: movq $-1, %rsi
+; AVX512-NEXT: movq $-1, %rdi
+; AVX512-NEXT: sbbq %rdx, %rdi
+; AVX512-NEXT: cmovgeq %rsi, %rdx
+; AVX512-NEXT: cmovgeq %rcx, %rax
+; AVX512-NEXT: movabsq $9223372036854775807, %rdi # imm = 0x7FFFFFFFFFFFFFFF
+; AVX512-NEXT: cmpq %rdi, %rax
+; AVX512-NEXT: sbbq $0, %rdx
; AVX512-NEXT: cmovgeq %rdi, %rax
-; AVX512-NEXT: vmovq %rax, %xmm0
-; AVX512-NEXT: vmovq %rsi, %xmm1
+; AVX512-NEXT: cmpq %rbx, %rcx
+; AVX512-NEXT: movq $-1, %rdx
+; AVX512-NEXT: sbbq %r14, %rdx
+; AVX512-NEXT: cmovlq %r14, %rsi
+; AVX512-NEXT: cmovlq %rbx, %rcx
+; AVX512-NEXT: cmpq %rdi, %rcx
+; AVX512-NEXT: sbbq $0, %rsi
+; AVX512-NEXT: cmovgeq %rdi, %rcx
+; AVX512-NEXT: vmovq %rcx, %xmm0
+; AVX512-NEXT: vmovq %rax, %xmm1
; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; AVX512-NEXT: addq $24, %rsp
; AVX512-NEXT: popq %rbx
@@ -4908,8 +4820,9 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) nounwind {
; SSE-NEXT: pushq %r14
; SSE-NEXT: pushq %rbx
; SSE-NEXT: subq $24, %rsp
-; SSE-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
-; SSE-NEXT: psrld $16, %xmm0
+; SSE-NEXT: movdqa %xmm0, %xmm1
+; SSE-NEXT: psrld $16, %xmm1
+; SSE-NEXT: movdqa %xmm1, (%rsp) # 16-byte Spill
; SSE-NEXT: callq __fixhfti at PLT
; SSE-NEXT: movq %rax, %rbx
; SSE-NEXT: movq %rdx, %r14
@@ -4917,55 +4830,83 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) nounwind {
; SSE-NEXT: callq __fixhfti at PLT
; SSE-NEXT: xorl %ecx, %ecx
; SSE-NEXT: testq %rdx, %rdx
+; SSE-NEXT: cmovsq %rcx, %rax
+; SSE-NEXT: cmovleq %rcx, %rdx
+; SSE-NEXT: testq %rdx, %rdx
; SSE-NEXT: cmovgq %rcx, %rax
-; SSE-NEXT: movl $1, %esi
-; SSE-NEXT: cmovgq %rsi, %rdx
; SSE-NEXT: testq %r14, %r14
-; SSE-NEXT: cmovgq %rcx, %rbx
-; SSE-NEXT: cmovleq %r14, %rsi
-; SSE-NEXT: testq %rsi, %rsi
; SSE-NEXT: cmovsq %rcx, %rbx
-; SSE-NEXT: testq %rdx, %rdx
-; SSE-NEXT: cmovsq %rcx, %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: movq %rbx, %xmm1
+; SSE-NEXT: cmovleq %rcx, %r14
+; SSE-NEXT: testq %r14, %r14
+; SSE-NEXT: cmovgq %rcx, %rbx
+; SSE-NEXT: movq %rbx, %xmm0
+; SSE-NEXT: movq %rax, %xmm1
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; SSE-NEXT: addq $24, %rsp
; SSE-NEXT: popq %rbx
; SSE-NEXT: popq %r14
; SSE-NEXT: retq
;
-; AVX-LABEL: ustest_f16i64_mm:
-; AVX: # %bb.0: # %entry
-; AVX-NEXT: pushq %r14
-; AVX-NEXT: pushq %rbx
-; AVX-NEXT: subq $24, %rsp
-; AVX-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
-; AVX-NEXT: vpsrld $16, %xmm0, %xmm0
-; AVX-NEXT: callq __fixhfti at PLT
-; AVX-NEXT: movq %rax, %rbx
-; AVX-NEXT: movq %rdx, %r14
-; AVX-NEXT: vmovaps (%rsp), %xmm0 # 16-byte Reload
-; AVX-NEXT: callq __fixhfti at PLT
-; AVX-NEXT: xorl %ecx, %ecx
-; AVX-NEXT: testq %rdx, %rdx
-; AVX-NEXT: cmovgq %rcx, %rax
-; AVX-NEXT: movl $1, %esi
-; AVX-NEXT: cmovgq %rsi, %rdx
-; AVX-NEXT: testq %r14, %r14
-; AVX-NEXT: cmovgq %rcx, %rbx
-; AVX-NEXT: cmovleq %r14, %rsi
-; AVX-NEXT: testq %rsi, %rsi
-; AVX-NEXT: cmovsq %rcx, %rbx
-; AVX-NEXT: testq %rdx, %rdx
-; AVX-NEXT: cmovsq %rcx, %rax
-; AVX-NEXT: vmovq %rax, %xmm0
-; AVX-NEXT: vmovq %rbx, %xmm1
-; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
-; AVX-NEXT: addq $24, %rsp
-; AVX-NEXT: popq %rbx
-; AVX-NEXT: popq %r14
-; AVX-NEXT: retq
+; AVX2-LABEL: ustest_f16i64_mm:
+; AVX2: # %bb.0: # %entry
+; AVX2-NEXT: pushq %r14
+; AVX2-NEXT: pushq %rbx
+; AVX2-NEXT: subq $24, %rsp
+; AVX2-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; AVX2-NEXT: callq __fixhfti at PLT
+; AVX2-NEXT: movq %rax, %rbx
+; AVX2-NEXT: movq %rdx, %r14
+; AVX2-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
+; AVX2-NEXT: vpsrld $16, %xmm0, %xmm0
+; AVX2-NEXT: callq __fixhfti at PLT
+; AVX2-NEXT: xorl %ecx, %ecx
+; AVX2-NEXT: testq %rdx, %rdx
+; AVX2-NEXT: cmovsq %rcx, %rax
+; AVX2-NEXT: cmovleq %rcx, %rdx
+; AVX2-NEXT: testq %rdx, %rdx
+; AVX2-NEXT: cmovgq %rcx, %rax
+; AVX2-NEXT: testq %r14, %r14
+; AVX2-NEXT: cmovsq %rcx, %rbx
+; AVX2-NEXT: cmovleq %rcx, %r14
+; AVX2-NEXT: testq %r14, %r14
+; AVX2-NEXT: cmovgq %rcx, %rbx
+; AVX2-NEXT: vmovq %rbx, %xmm0
+; AVX2-NEXT: vmovq %rax, %xmm1
+; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX2-NEXT: addq $24, %rsp
+; AVX2-NEXT: popq %rbx
+; AVX2-NEXT: popq %r14
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: ustest_f16i64_mm:
+; AVX512: # %bb.0: # %entry
+; AVX512-NEXT: pushq %r14
+; AVX512-NEXT: pushq %rbx
+; AVX512-NEXT: subq $24, %rsp
+; AVX512-NEXT: vmovaps %xmm0, (%rsp) # 16-byte Spill
+; AVX512-NEXT: callq __fixhfti at PLT
+; AVX512-NEXT: movq %rax, %rbx
+; AVX512-NEXT: movq %rdx, %r14
+; AVX512-NEXT: vpsrld $16, (%rsp), %xmm0 # 16-byte Folded Reload
+; AVX512-NEXT: callq __fixhfti at PLT
+; AVX512-NEXT: xorl %ecx, %ecx
+; AVX512-NEXT: testq %rdx, %rdx
+; AVX512-NEXT: cmovsq %rcx, %rax
+; AVX512-NEXT: cmovleq %rcx, %rdx
+; AVX512-NEXT: testq %rdx, %rdx
+; AVX512-NEXT: cmovgq %rcx, %rax
+; AVX512-NEXT: testq %r14, %r14
+; AVX512-NEXT: cmovsq %rcx, %rbx
+; AVX512-NEXT: cmovleq %rcx, %r14
+; AVX512-NEXT: testq %r14, %r14
+; AVX512-NEXT: cmovgq %rcx, %rbx
+; AVX512-NEXT: vmovq %rbx, %xmm0
+; AVX512-NEXT: vmovq %rax, %xmm1
+; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; AVX512-NEXT: addq $24, %rsp
+; AVX512-NEXT: popq %rbx
+; AVX512-NEXT: popq %r14
+; AVX512-NEXT: retq
entry:
%conv = fptosi <2 x half> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
diff --git a/llvm/test/CodeGen/X86/jump_sign.ll b/llvm/test/CodeGen/X86/jump_sign.ll
index d28a93ec3d77c..2a6283273c526 100644
--- a/llvm/test/CodeGen/X86/jump_sign.ll
+++ b/llvm/test/CodeGen/X86/jump_sign.ll
@@ -32,10 +32,11 @@ declare i32 @baz(...)
define i32 @func_g(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: func_g:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: subl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: cmovsl %ecx, %eax
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: subl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: testl %ecx, %ecx
+; CHECK-NEXT: cmovgl %ecx, %eax
; CHECK-NEXT: retl
%sub = sub nsw i32 %a, %b
%cmp = icmp sgt i32 %sub, 0
@@ -285,10 +286,11 @@ if.else.i104: ; preds = %if.then44
define i32 @func_p(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: func_p:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: addl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: cmovsl %ecx, %eax
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: addl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: testl %ecx, %ecx
+; CHECK-NEXT: cmovgl %ecx, %eax
; CHECK-NEXT: retl
%add = add nsw i32 %b, %a
%cmp = icmp sgt i32 %add, 0
@@ -351,10 +353,11 @@ return:
define i32 @func_dec(i32 %a) nounwind {
; CHECK-LABEL: func_dec:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: decl %eax
-; CHECK-NEXT: cmovsl %ecx, %eax
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: decl %ecx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: testl %ecx, %ecx
+; CHECK-NEXT: cmovgl %ecx, %eax
; CHECK-NEXT: retl
%sub = sub nsw i32 %a, 1
%cmp = icmp sgt i32 %sub, 0
@@ -365,10 +368,11 @@ define i32 @func_dec(i32 %a) nounwind {
define i32 @func_inc(i32 %a) nounwind {
; CHECK-LABEL: func_inc:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT: xorl %ecx, %ecx
-; CHECK-NEXT: incl %eax
-; CHECK-NEXT: cmovsl %ecx, %eax
+; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT: incl %ecx
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: testl %ecx, %ecx
+; CHECK-NEXT: cmovgl %ecx, %eax
; CHECK-NEXT: retl
%add = add nsw i32 %a, 1
%cmp = icmp sgt i32 %add, 0
diff --git a/llvm/test/CodeGen/X86/mul-constant-result.ll b/llvm/test/CodeGen/X86/mul-constant-result.ll
index 1f9e7a93ad0b9..1a9bca8a1d64f 100644
--- a/llvm/test/CodeGen/X86/mul-constant-result.ll
+++ b/llvm/test/CodeGen/X86/mul-constant-result.ll
@@ -9,193 +9,161 @@
define i32 @mult(i32, i32) local_unnamed_addr #0 {
; X86-LABEL: mult:
; X86: # %bb.0:
-; X86-NEXT: pushl %esi
-; X86-NEXT: .cfi_def_cfa_offset 8
-; X86-NEXT: .cfi_offset %esi, -8
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT: cmpl $2, %edx
+; X86-NEXT: testl %edx, %edx
; X86-NEXT: movl $1, %eax
-; X86-NEXT: movl $1, %esi
-; X86-NEXT: jge .LBB0_2
+; X86-NEXT: jle .LBB0_2
; X86-NEXT: # %bb.1:
-; X86-NEXT: movl %edx, %esi
+; X86-NEXT: movl $1, %edx
; X86-NEXT: .LBB0_2:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: testl %edx, %edx
; X86-NEXT: je .LBB0_4
; X86-NEXT: # %bb.3:
-; X86-NEXT: movl %esi, %eax
+; X86-NEXT: movl %edx, %eax
; X86-NEXT: .LBB0_4:
; X86-NEXT: decl %ecx
; X86-NEXT: cmpl $31, %ecx
-; X86-NEXT: ja .LBB0_35
+; X86-NEXT: ja .LBB0_38
; X86-NEXT: # %bb.5:
; X86-NEXT: jmpl *.LJTI0_0(,%ecx,4)
; X86-NEXT: .LBB0_6:
; X86-NEXT: addl %eax, %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
-; X86-NEXT: .LBB0_7:
-; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .LBB0_33:
; X86-NEXT: leal (%eax,%eax,8), %ecx
; X86-NEXT: leal (%ecx,%ecx,2), %ecx
-; X86-NEXT: jmp .LBB0_9
-; X86-NEXT: .LBB0_8:
+; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_22:
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: shll $4, %ecx
-; X86-NEXT: jmp .LBB0_9
-; X86-NEXT: .LBB0_10:
+; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_20:
; X86-NEXT: leal (%eax,%eax,4), %eax
-; X86-NEXT: jmp .LBB0_18
-; X86-NEXT: .LBB0_11:
+; X86-NEXT: leal (%eax,%eax,2), %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_17:
; X86-NEXT: shll $2, %eax
-; X86-NEXT: jmp .LBB0_18
-; X86-NEXT: .LBB0_13:
+; X86-NEXT: leal (%eax,%eax,2), %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_9:
+; X86-NEXT: leal (%eax,%eax,4), %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_18:
; X86-NEXT: leal (%eax,%eax,2), %ecx
-; X86-NEXT: jmp .LBB0_14
+; X86-NEXT: leal (%eax,%ecx,4), %eax
+; X86-NEXT: retl
; X86-NEXT: .LBB0_15:
; X86-NEXT: addl %eax, %eax
-; X86-NEXT: jmp .LBB0_12
-; X86-NEXT: .LBB0_16:
+; X86-NEXT: leal (%eax,%eax,4), %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_31:
; X86-NEXT: leal (%eax,%eax,4), %ecx
; X86-NEXT: leal (%ecx,%ecx,4), %ecx
-; X86-NEXT: jmp .LBB0_9
-; X86-NEXT: .LBB0_17:
+; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_30:
; X86-NEXT: leal (%eax,%eax,4), %eax
-; X86-NEXT: jmp .LBB0_12
-; X86-NEXT: .LBB0_19:
+; X86-NEXT: leal (%eax,%eax,4), %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_7:
+; X86-NEXT: leal (%eax,%eax,2), %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_21:
; X86-NEXT: shll $4, %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
-; X86-NEXT: .LBB0_20:
-; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .LBB0_8:
; X86-NEXT: shll $2, %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
-; X86-NEXT: .LBB0_21:
-; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .LBB0_13:
; X86-NEXT: shll $3, %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
-; X86-NEXT: .LBB0_22:
-; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .LBB0_37:
; X86-NEXT: shll $5, %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
; X86-NEXT: .LBB0_23:
-; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: addl %eax, %eax
-; X86-NEXT: .LBB0_33:
; X86-NEXT: leal (%eax,%eax,8), %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
-; X86-NEXT: .LBB0_24:
-; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .LBB0_26:
; X86-NEXT: leal (%eax,%eax,4), %ecx
-; X86-NEXT: .LBB0_14:
; X86-NEXT: leal (%eax,%ecx,4), %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
-; X86-NEXT: .LBB0_25:
-; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .LBB0_10:
; X86-NEXT: addl %eax, %eax
-; X86-NEXT: jmp .LBB0_18
-; X86-NEXT: .LBB0_26:
+; X86-NEXT: leal (%eax,%eax,2), %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_27:
; X86-NEXT: leal (%eax,%eax,4), %ecx
; X86-NEXT: leal (%eax,%ecx,4), %ecx
-; X86-NEXT: jmp .LBB0_9
-; X86-NEXT: .LBB0_27:
+; X86-NEXT: addl %ecx, %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_19:
; X86-NEXT: leal (%eax,%eax), %ecx
; X86-NEXT: shll $4, %eax
-; X86-NEXT: jmp .LBB0_28
-; X86-NEXT: .LBB0_29:
+; X86-NEXT: subl %ecx, %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_11:
; X86-NEXT: leal (,%eax,8), %ecx
-; X86-NEXT: jmp .LBB0_38
-; X86-NEXT: .LBB0_30:
+; X86-NEXT: jmp .LBB0_12
+; X86-NEXT: .LBB0_24:
; X86-NEXT: leal (%eax,%eax,8), %ecx
-; X86-NEXT: jmp .LBB0_32
-; X86-NEXT: .LBB0_31:
+; X86-NEXT: leal (%eax,%ecx,2), %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_16:
; X86-NEXT: leal (%eax,%eax,4), %ecx
-; X86-NEXT: .LBB0_32:
; X86-NEXT: leal (%eax,%ecx,2), %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
-; X86-NEXT: .LBB0_34:
-; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .LBB0_14:
+; X86-NEXT: leal (%eax,%eax,8), %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_36:
; X86-NEXT: movl %eax, %ecx
; X86-NEXT: shll $5, %ecx
-; X86-NEXT: jmp .LBB0_38
-; X86-NEXT: .LBB0_35:
+; X86-NEXT: jmp .LBB0_12
+; X86-NEXT: .LBB0_38:
; X86-NEXT: xorl %eax, %eax
-; X86-NEXT: .LBB0_36:
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
+; X86-NEXT: .LBB0_39:
; X86-NEXT: retl
-; X86-NEXT: .LBB0_37:
-; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .LBB0_28:
; X86-NEXT: leal (%eax,%eax,2), %ecx
; X86-NEXT: shll $3, %ecx
-; X86-NEXT: .LBB0_38:
+; X86-NEXT: .LBB0_12:
; X86-NEXT: subl %eax, %ecx
; X86-NEXT: movl %ecx, %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
-; X86-NEXT: .LBB0_39:
-; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .LBB0_25:
; X86-NEXT: shll $2, %eax
-; X86-NEXT: .LBB0_12:
; X86-NEXT: leal (%eax,%eax,4), %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
-; X86-NEXT: .LBB0_40:
-; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .LBB0_29:
; X86-NEXT: shll $3, %eax
-; X86-NEXT: jmp .LBB0_18
-; X86-NEXT: .LBB0_41:
+; X86-NEXT: leal (%eax,%eax,2), %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB0_34:
; X86-NEXT: leal (%eax,%eax,8), %ecx
; X86-NEXT: leal (%ecx,%ecx,2), %ecx
; X86-NEXT: addl %eax, %eax
-; X86-NEXT: .LBB0_9:
; X86-NEXT: addl %ecx, %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
-; X86-NEXT: .LBB0_42:
-; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .LBB0_35:
; X86-NEXT: leal (%eax,%eax), %ecx
; X86-NEXT: shll $5, %eax
-; X86-NEXT: .LBB0_28:
; X86-NEXT: subl %ecx, %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
-; X86-NEXT: .LBB0_43:
-; X86-NEXT: .cfi_def_cfa_offset 8
+; X86-NEXT: .LBB0_32:
; X86-NEXT: leal (%eax,%eax,8), %eax
-; X86-NEXT: .LBB0_18:
; X86-NEXT: leal (%eax,%eax,2), %eax
-; X86-NEXT: popl %esi
-; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl
;
; X64-HSW-LABEL: mult:
; X64-HSW: # %bb.0:
-; X64-HSW-NEXT: # kill: def $edi killed $edi def $rdi
-; X64-HSW-NEXT: cmpl $2, %esi
-; X64-HSW-NEXT: movl $1, %ecx
; X64-HSW-NEXT: movl %esi, %eax
-; X64-HSW-NEXT: cmovgel %ecx, %eax
+; X64-HSW-NEXT: # kill: def $edi killed $edi def $rdi
; X64-HSW-NEXT: testl %esi, %esi
+; X64-HSW-NEXT: movl $1, %ecx
+; X64-HSW-NEXT: cmovgl %ecx, %eax
; X64-HSW-NEXT: cmovel %ecx, %eax
; X64-HSW-NEXT: decl %edi
; X64-HSW-NEXT: cmpl $31, %edi
diff --git a/llvm/test/CodeGen/X86/pr5145.ll b/llvm/test/CodeGen/X86/pr5145.ll
index 5cb0ac9bc9821..3e17f607d3310 100644
--- a/llvm/test/CodeGen/X86/pr5145.ll
+++ b/llvm/test/CodeGen/X86/pr5145.ll
@@ -6,51 +6,55 @@ define void @atomic_maxmin_i8() {
; CHECK-LABEL: atomic_maxmin_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: movzbl sc8(%rip), %eax
+; CHECK-NEXT: movl $5, %ecx
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_1: # %atomicrmw.start14
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpb $6, %al
; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: movl $5, %ecx
-; CHECK-NEXT: cmovgel %eax, %ecx
+; CHECK-NEXT: cmpb $6, %al
+; CHECK-NEXT: movl %eax, %edx
+; CHECK-NEXT: cmovll %ecx, %edx
; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: lock cmpxchgb %cl, sc8(%rip)
+; CHECK-NEXT: lock cmpxchgb %dl, sc8(%rip)
; CHECK-NEXT: jne .LBB0_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end13
; CHECK-NEXT: movzbl sc8(%rip), %eax
+; CHECK-NEXT: movl $6, %ecx
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_3: # %atomicrmw.start8
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpb $7, %al
; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: movl $6, %ecx
-; CHECK-NEXT: cmovll %eax, %ecx
+; CHECK-NEXT: cmpb $6, %al
+; CHECK-NEXT: movl %eax, %edx
+; CHECK-NEXT: cmovgel %ecx, %edx
; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: lock cmpxchgb %cl, sc8(%rip)
+; CHECK-NEXT: lock cmpxchgb %dl, sc8(%rip)
; CHECK-NEXT: jne .LBB0_3
; CHECK-NEXT: # %bb.4: # %atomicrmw.end7
; CHECK-NEXT: movzbl sc8(%rip), %eax
+; CHECK-NEXT: movl $7, %ecx
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_5: # %atomicrmw.start2
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpb $8, %al
; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: movl $7, %ecx
-; CHECK-NEXT: cmovael %eax, %ecx
+; CHECK-NEXT: cmpb $8, %al
+; CHECK-NEXT: movl %eax, %edx
+; CHECK-NEXT: cmovbl %ecx, %edx
; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: lock cmpxchgb %cl, sc8(%rip)
+; CHECK-NEXT: lock cmpxchgb %dl, sc8(%rip)
; CHECK-NEXT: jne .LBB0_5
; CHECK-NEXT: # %bb.6: # %atomicrmw.end1
; CHECK-NEXT: movzbl sc8(%rip), %eax
+; CHECK-NEXT: movl $8, %ecx
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: .LBB0_7: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: cmpb $9, %al
; CHECK-NEXT: movzbl %al, %eax
-; CHECK-NEXT: movl $8, %ecx
-; CHECK-NEXT: cmovbl %eax, %ecx
+; CHECK-NEXT: cmpb $8, %al
+; CHECK-NEXT: movl %eax, %edx
+; CHECK-NEXT: cmovael %ecx, %edx
; CHECK-NEXT: # kill: def $al killed $al killed $eax
-; CHECK-NEXT: lock cmpxchgb %cl, sc8(%rip)
+; CHECK-NEXT: lock cmpxchgb %dl, sc8(%rip)
; CHECK-NEXT: jne .LBB0_7
; CHECK-NEXT: # %bb.8: # %atomicrmw.end
; CHECK-NEXT: retq
diff --git a/llvm/test/CodeGen/X86/sat-add.ll b/llvm/test/CodeGen/X86/sat-add.ll
index 69e6ff7770ebe..97a90adf5968c 100644
--- a/llvm/test/CodeGen/X86/sat-add.ll
+++ b/llvm/test/CodeGen/X86/sat-add.ll
@@ -183,8 +183,8 @@ define i8 @unsigned_sat_variable_i8_using_min(i8 %x, i8 %y) {
; ANY: # %bb.0:
; ANY-NEXT: movl %esi, %eax
; ANY-NEXT: notb %al
-; ANY-NEXT: cmpb %al, %dil
; ANY-NEXT: movzbl %al, %eax
+; ANY-NEXT: cmpb %al, %dil
; ANY-NEXT: cmovbl %edi, %eax
; ANY-NEXT: addb %sil, %al
; ANY-NEXT: # kill: def $al killed $al killed $eax
@@ -363,13 +363,13 @@ define <16 x i8> @unsigned_sat_constant_v16i8_using_min(<16 x i8> %x) {
; SSE-LABEL: unsigned_sat_constant_v16i8_using_min:
; SSE: # %bb.0:
; SSE-NEXT: pminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE-NEXT: paddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]
; SSE-NEXT: retq
;
; AVX-LABEL: unsigned_sat_constant_v16i8_using_min:
; AVX: # %bb.0:
; AVX-NEXT: vpminub {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42]
; AVX-NEXT: retq
%c = icmp ult <16 x i8> %x, <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
%s = select <16 x i1> %c, <16 x i8> %x, <16 x i8> <i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43, i8 -43>
@@ -415,19 +415,19 @@ define <8 x i16> @unsigned_sat_constant_v8i16_using_min(<8 x i16> %x) {
; SSE2-NEXT: movdqa %xmm0, %xmm1
; SSE2-NEXT: psubusw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: psubw %xmm1, %xmm0
-; SSE2-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [42,42,42,42,42,42,42,42]
; SSE2-NEXT: retq
;
; SSE4-LABEL: unsigned_sat_constant_v8i16_using_min:
; SSE4: # %bb.0:
; SSE4-NEXT: pminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE4-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: paddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [42,42,42,42,42,42,42,42]
; SSE4-NEXT: retq
;
; AVX-LABEL: unsigned_sat_constant_v8i16_using_min:
; AVX: # %bb.0:
; AVX-NEXT: vpminuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [42,42,42,42,42,42,42,42]
; AVX-NEXT: retq
%c = icmp ult <8 x i16> %x, <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
%s = select <8 x i1> %c, <8 x i16> %x, <8 x i16> <i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43, i16 -43>
@@ -477,14 +477,14 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_min(<4 x i32> %x) {
; SSE2-NEXT: pandn %xmm0, %xmm2
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
; SSE2-NEXT: por %xmm2, %xmm1
-; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [42,42,42,42]
; SSE2-NEXT: movdqa %xmm1, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: unsigned_sat_constant_v4i32_using_min:
; SSE4: # %bb.0:
; SSE4-NEXT: pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE4-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [42,42,42,42]
; SSE4-NEXT: retq
;
; AVX2-LABEL: unsigned_sat_constant_v4i32_using_min:
@@ -521,7 +521,7 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_sum(<4 x i32> %x) {
; SSE4-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
; SSE4: # %bb.0:
; SSE4-NEXT: pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE4-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [42,42,42,42]
; SSE4-NEXT: retq
;
; AVX2-LABEL: unsigned_sat_constant_v4i32_using_cmp_sum:
@@ -556,7 +556,7 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval(<4 x i32> %x) {
; SSE4-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
; SSE4: # %bb.0:
; SSE4-NEXT: pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE4-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [42,42,42,42]
; SSE4-NEXT: retq
;
; AVX2-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval:
@@ -591,13 +591,13 @@ define <4 x i32> @unsigned_sat_constant_v4i32_using_cmp_notval_nonsplat(<4 x i32
; SSE4-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval_nonsplat:
; SSE4: # %bb.0:
; SSE4-NEXT: pminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
-; SSE4-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE4-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [43,44,45,46]
; SSE4-NEXT: retq
;
; AVX-LABEL: unsigned_sat_constant_v4i32_using_cmp_notval_nonsplat:
; AVX: # %bb.0:
; AVX-NEXT: vpminud {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [43,44,45,46]
; AVX-NEXT: retq
%a = add <4 x i32> %x, <i32 43, i32 44, i32 45, i32 46>
%c = icmp ugt <4 x i32> %x, <i32 -44, i32 -45, i32 -46, i32 -47>
@@ -621,7 +621,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
; SSE2-NEXT: pand %xmm2, %xmm0
; SSE2-NEXT: pandn {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
; SSE2-NEXT: por %xmm2, %xmm0
-; SSE2-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE2-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [42,42]
; SSE2-NEXT: retq
;
; SSE41-LABEL: unsigned_sat_constant_v2i64_using_min:
@@ -639,7 +639,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3]
; SSE41-NEXT: por %xmm5, %xmm0
; SSE41-NEXT: blendvpd %xmm0, %xmm1, %xmm2
-; SSE41-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
+; SSE41-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [42,42]
; SSE41-NEXT: movdqa %xmm2, %xmm0
; SSE41-NEXT: retq
;
@@ -650,7 +650,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
; SSE42-NEXT: pxor %xmm1, %xmm0
; SSE42-NEXT: pcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
; SSE42-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
-; SSE42-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
+; SSE42-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [42,42]
; SSE42-NEXT: movdqa %xmm1, %xmm0
; SSE42-NEXT: retq
;
@@ -659,7 +659,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_min(<2 x i64> %x) {
; AVX2-NEXT: vpxor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpgtq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX2-NEXT: vblendvpd %xmm1, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
-; AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [42,42]
; AVX2-NEXT: retq
;
; AVX512-LABEL: unsigned_sat_constant_v2i64_using_min:
@@ -715,7 +715,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; SSE42-NEXT: movdqa %xmm0, %xmm2
; SSE42-NEXT: pxor %xmm1, %xmm2
-; SSE42-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE42-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [42,42]
; SSE42-NEXT: pxor %xmm0, %xmm1
; SSE42-NEXT: pcmpgtq %xmm1, %xmm2
; SSE42-NEXT: por %xmm2, %xmm0
@@ -725,7 +725,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_sum(<2 x i64> %x) {
; AVX2: # %bb.0:
; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm2
-; AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [42,42]
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm1
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
@@ -774,7 +774,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
; SSE42-NEXT: movdqa {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; SSE42-NEXT: movdqa %xmm0, %xmm2
; SSE42-NEXT: pxor %xmm1, %xmm2
-; SSE42-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
+; SSE42-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # [42,42]
; SSE42-NEXT: pxor %xmm0, %xmm1
; SSE42-NEXT: pcmpgtq %xmm1, %xmm2
; SSE42-NEXT: por %xmm2, %xmm0
@@ -784,7 +784,7 @@ define <2 x i64> @unsigned_sat_constant_v2i64_using_cmp_notval(<2 x i64> %x) {
; AVX2: # %bb.0:
; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm1 = [9223372036854775808,9223372036854775808]
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm2
-; AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
+; AVX2-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 # [42,42]
; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm1
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm2, %xmm1
; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
diff --git a/llvm/test/CodeGen/X86/select.ll b/llvm/test/CodeGen/X86/select.ll
index 1901ba9408e91..956802fa9df83 100644
--- a/llvm/test/CodeGen/X86/select.ll
+++ b/llvm/test/CodeGen/X86/select.ll
@@ -1295,7 +1295,7 @@ define void @clamp_i8(i32 %src, ptr %dst) {
; GENERIC: ## %bb.0:
; GENERIC-NEXT: cmpl $127, %edi
; GENERIC-NEXT: movl $127, %eax
-; GENERIC-NEXT: cmovlel %edi, %eax
+; GENERIC-NEXT: cmovll %edi, %eax
; GENERIC-NEXT: cmpl $-128, %eax
; GENERIC-NEXT: movl $128, %ecx
; GENERIC-NEXT: cmovgel %eax, %ecx
@@ -1307,7 +1307,7 @@ define void @clamp_i8(i32 %src, ptr %dst) {
; ATOM-NEXT: cmpl $127, %edi
; ATOM-NEXT: movl $127, %eax
; ATOM-NEXT: movl $128, %ecx
-; ATOM-NEXT: cmovlel %edi, %eax
+; ATOM-NEXT: cmovll %edi, %eax
; ATOM-NEXT: cmpl $-128, %eax
; ATOM-NEXT: cmovgel %eax, %ecx
; ATOM-NEXT: movb %cl, (%rsi)
@@ -1319,7 +1319,7 @@ define void @clamp_i8(i32 %src, ptr %dst) {
; ATHLON-NEXT: movl {{[0-9]+}}(%esp), %ecx
; ATHLON-NEXT: cmpl $127, %ecx
; ATHLON-NEXT: movl $127, %edx
-; ATHLON-NEXT: cmovlel %ecx, %edx
+; ATHLON-NEXT: cmovll %ecx, %edx
; ATHLON-NEXT: cmpl $-128, %edx
; ATHLON-NEXT: movl $128, %ecx
; ATHLON-NEXT: cmovgel %edx, %ecx
@@ -1329,18 +1329,17 @@ define void @clamp_i8(i32 %src, ptr %dst) {
; MCU-LABEL: clamp_i8:
; MCU: # %bb.0:
; MCU-NEXT: cmpl $127, %eax
-; MCU-NEXT: movl $127, %ecx
-; MCU-NEXT: jg .LBB26_2
+; MCU-NEXT: jl .LBB26_2
; MCU-NEXT: # %bb.1:
-; MCU-NEXT: movl %eax, %ecx
+; MCU-NEXT: movl $127, %eax
; MCU-NEXT: .LBB26_2:
-; MCU-NEXT: cmpl $-128, %ecx
-; MCU-NEXT: movb $-128, %al
+; MCU-NEXT: cmpl $-128, %eax
+; MCU-NEXT: movb $-128, %cl
; MCU-NEXT: jl .LBB26_4
; MCU-NEXT: # %bb.3:
-; MCU-NEXT: movl %ecx, %eax
+; MCU-NEXT: movl %eax, %ecx
; MCU-NEXT: .LBB26_4:
-; MCU-NEXT: movb %al, (%edx)
+; MCU-NEXT: movb %cl, (%edx)
; MCU-NEXT: retl
%cmp = icmp sgt i32 %src, 127
%sel1 = select i1 %cmp, i32 127, i32 %src
@@ -1355,7 +1354,7 @@ define void @clamp_i8(i32 %src, ptr %dst) {
define void @clamp(i32 %src, ptr %dst) {
; GENERIC-LABEL: clamp:
; GENERIC: ## %bb.0:
-; GENERIC-NEXT: cmpl $32768, %edi ## imm = 0x8000
+; GENERIC-NEXT: cmpl $32767, %edi ## imm = 0x7FFF
; GENERIC-NEXT: movl $32767, %eax ## imm = 0x7FFF
; GENERIC-NEXT: cmovll %edi, %eax
; GENERIC-NEXT: cmpl $-32768, %eax ## imm = 0x8000
@@ -1366,7 +1365,7 @@ define void @clamp(i32 %src, ptr %dst) {
;
; ATOM-LABEL: clamp:
; ATOM: ## %bb.0:
-; ATOM-NEXT: cmpl $32768, %edi ## imm = 0x8000
+; ATOM-NEXT: cmpl $32767, %edi ## imm = 0x7FFF
; ATOM-NEXT: movl $32767, %eax ## imm = 0x7FFF
; ATOM-NEXT: movl $32768, %ecx ## imm = 0x8000
; ATOM-NEXT: cmovll %edi, %eax
@@ -1379,7 +1378,7 @@ define void @clamp(i32 %src, ptr %dst) {
; ATHLON: ## %bb.0:
; ATHLON-NEXT: movl {{[0-9]+}}(%esp), %eax
; ATHLON-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; ATHLON-NEXT: cmpl $32768, %ecx ## imm = 0x8000
+; ATHLON-NEXT: cmpl $32767, %ecx ## imm = 0x7FFF
; ATHLON-NEXT: movl $32767, %edx ## imm = 0x7FFF
; ATHLON-NEXT: cmovll %ecx, %edx
; ATHLON-NEXT: cmpl $-32768, %edx ## imm = 0x8000
@@ -1390,19 +1389,18 @@ define void @clamp(i32 %src, ptr %dst) {
;
; MCU-LABEL: clamp:
; MCU: # %bb.0:
-; MCU-NEXT: cmpl $32768, %eax # imm = 0x8000
-; MCU-NEXT: movl $32767, %ecx # imm = 0x7FFF
-; MCU-NEXT: jge .LBB27_2
+; MCU-NEXT: cmpl $32767, %eax # imm = 0x7FFF
+; MCU-NEXT: jl .LBB27_2
; MCU-NEXT: # %bb.1:
-; MCU-NEXT: movl %eax, %ecx
+; MCU-NEXT: movl $32767, %eax # imm = 0x7FFF
; MCU-NEXT: .LBB27_2:
-; MCU-NEXT: cmpl $-32768, %ecx # imm = 0x8000
-; MCU-NEXT: movl $32768, %eax # imm = 0x8000
+; MCU-NEXT: cmpl $-32768, %eax # imm = 0x8000
+; MCU-NEXT: movl $32768, %ecx # imm = 0x8000
; MCU-NEXT: jl .LBB27_4
; MCU-NEXT: # %bb.3:
-; MCU-NEXT: movl %ecx, %eax
+; MCU-NEXT: movl %eax, %ecx
; MCU-NEXT: .LBB27_4:
-; MCU-NEXT: movw %ax, (%edx)
+; MCU-NEXT: movw %cx, (%edx)
; MCU-NEXT: retl
%cmp = icmp sgt i32 %src, 32767
%sel1 = select i1 %cmp, i32 32767, i32 %src
diff --git a/llvm/test/CodeGen/X86/selectcc-to-shiftand.ll b/llvm/test/CodeGen/X86/selectcc-to-shiftand.ll
index 03f4c0f61cdd1..8fb4ced674ba8 100644
--- a/llvm/test/CodeGen/X86/selectcc-to-shiftand.ll
+++ b/llvm/test/CodeGen/X86/selectcc-to-shiftand.ll
@@ -117,7 +117,7 @@ define i32 @not_neg_sel_same_variable(i32 %a) {
; CHECK-NOBMI: # %bb.0:
; CHECK-NOBMI-NEXT: xorl %eax, %eax
; CHECK-NOBMI-NEXT: testl %edi, %edi
-; CHECK-NOBMI-NEXT: cmovnsl %edi, %eax
+; CHECK-NOBMI-NEXT: cmovgl %edi, %eax
; CHECK-NOBMI-NEXT: retq
;
; CHECK-BMI-LABEL: not_neg_sel_same_variable:
@@ -137,9 +137,10 @@ define i32 @not_neg_sel_same_variable(i32 %a) {
define i32 @PR31175(i32 %x, i32 %y) {
; CHECK-NOBMI-LABEL: PR31175:
; CHECK-NOBMI: # %bb.0:
-; CHECK-NOBMI-NEXT: xorl %eax, %eax
; CHECK-NOBMI-NEXT: subl %esi, %edi
-; CHECK-NOBMI-NEXT: cmovnsl %edi, %eax
+; CHECK-NOBMI-NEXT: xorl %eax, %eax
+; CHECK-NOBMI-NEXT: testl %edi, %edi
+; CHECK-NOBMI-NEXT: cmovgl %edi, %eax
; CHECK-NOBMI-NEXT: retq
;
; CHECK-BMI-LABEL: PR31175:
diff --git a/llvm/test/CodeGen/X86/tail-opts.ll b/llvm/test/CodeGen/X86/tail-opts.ll
index d9ab2f7d1f5fb..b4e9960de5660 100644
--- a/llvm/test/CodeGen/X86/tail-opts.ll
+++ b/llvm/test/CodeGen/X86/tail-opts.ll
@@ -695,9 +695,9 @@ return:
define i64 @TESTE(i64 %parami, i64 %paraml) nounwind readnone {
; CHECK-LABEL: TESTE:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: testq %rdi, %rdi
+; CHECK-NEXT: cmpq $2, %rdi
; CHECK-NEXT: movl $1, %eax
-; CHECK-NEXT: cmovgq %rdi, %rax
+; CHECK-NEXT: cmovgeq %rdi, %rax
; CHECK-NEXT: testq %rsi, %rsi
; CHECK-NEXT: jle .LBB11_2
; CHECK-NEXT: # %bb.1: # %bb.nph
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