[llvm] AMDGPU/UniformityAnalysis: MIR Uniformity analysis for INLINEASM (PR #201874)

[Petar Avramovic via llvm-commits]

https://github.com/petar-avramovic created https://github.com/llvm/llvm-project/pull/201874

If any of the defs are divergent, need to report instruction as
NeverUniform so that isUniformReg can calculate uniformity for each def.

>From b3a7e44ee6a7297ec0f9f799ddb80df06839cc9d Mon Sep 17 00:00:00 2001
From: Petar Avramovic <Petar.Avramovic at amd.com>
Date: Fri, 5 Jun 2026 15:51:21 +0200
Subject: [PATCH] AMDGPU/UniformityAnalysis: MIR Uniformity analysis for
 INLINEASM

If any of the defs are divergent, need to report instruction as
NeverUniform so that isUniformReg can calculate uniformity for each def.
---
 llvm/lib/Target/AMDGPU/SIInstrInfo.cpp        | 13 ++++
 .../AMDGPU/MIR/inline-asm.mir                 | 60 +++++++++++++++++++
 2 files changed, 73 insertions(+)
 create mode 100644 llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/inline-asm.mir

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 3b72ba4bd4967..ef9d184555bd6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -11014,6 +11014,19 @@ ValueUniformity SIInstrInfo::getValueUniformity(const MachineInstr &MI) const {
       opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR)
     return ValueUniformity::AlwaysUniform;
 
+  // If any of defs is divergent, report as NeverUniform. isUniformReg will
+  // calculate in more detail for each def from its reg class, if available.
+  if (MI.isInlineAsm()) {
+    for (const MachineOperand &MO : MI.operands()) {
+      if (!MO.isReg() || !MO.isDef())
+        continue;
+      const TargetRegisterClass *RC =
+          MI.getRegClassConstraint(MO.getOperandNo(), this, &RI);
+      if (!RC || !RI.isSGPRClass(RC))
+        return ValueUniformity::NeverUniform;
+    }
+  }
+
   if (isCopyInstr(MI)) {
     const MachineOperand &srcOp = MI.getOperand(1);
     if (srcOp.isReg() && srcOp.getReg().isPhysical()) {
diff --git a/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/inline-asm.mir b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/inline-asm.mir
new file mode 100644
index 0000000000000..e5f450c612444
--- /dev/null
+++ b/llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/inline-asm.mir
@@ -0,0 +1,60 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -passes='print<machine-uniformity>' -filetype=null %s 2>&1 | FileCheck %s
+
+# CHECK-LABEL: MachineUniformityInfo for function:  @inlineasm_s
+# CHECK-LABEL: BLOCK bb.0
+# CHECK-NOT: DIVERGENT: %0: INLINEASM
+---
+name:            inlineasm_s
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    INLINEASM &"s_mov_b32 $0, 7", attdialect, regdef:SReg_32, def %0:sreg_32
+    $sgpr0 = COPY %0
+    SI_RETURN implicit $sgpr0
+...
+
+# CHECK-LABEL: MachineUniformityInfo for function:  @inlineasm_v
+# CHECK-LABEL: BLOCK bb.0
+# CHECK: DIVERGENT: %0: INLINEASM
+---
+name:            inlineasm_v
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    INLINEASM &"v_mov_b32 $0, 8", attdialect, regdef:VGPR_32, def %0:vgpr_32
+    $vgpr0 = COPY %0
+    SI_RETURN implicit $vgpr0
+...
+
+# CHECK-LABEL: MachineUniformityInfo for function:  @inlineasm_sv
+# CHECK-LABEL: BLOCK bb.0
+# CHECK-NOT: DIVERGENT: %0: INLINEASM
+# CHECK: DIVERGENT: %1: INLINEASM
+---
+name:            inlineasm_sv
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    INLINEASM &"s_mov_b32 $0, 7\0Av_mov_b32 $1, 8", attdialect, regdef:SReg_32, def %0:sreg_32, regdef:VGPR_32, def %1:vgpr_32
+    $sgpr0 = COPY %0
+    $vgpr0 = COPY %1
+    SI_RETURN implicit $sgpr0, implicit $vgpr0
+...
+
+# CHECK-LABEL: MachineUniformityInfo for function:  @inlineasm_svs
+# CHECK-LABEL: BLOCK bb.0
+# CHECK-NOT: DIVERGENT: %0: INLINEASM
+# CHECK: DIVERGENT: %1: INLINEASM
+# CHECK-NOT: DIVERGENT: %2: INLINEASM
+---
+name:            inlineasm_svs
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    INLINEASM &"s_mov_b32 $0, 1\0Av_mov_b32 $1, 2\0As_mov_b32 $2, 3", attdialect, regdef:SReg_32, def %0:sreg_32, regdef:VGPR_32, def %1:vgpr_32, regdef:SReg_32, def %2:sreg_32
+    $sgpr0 = COPY %0
+    $vgpr0 = COPY %1
+    $sgpr1 = COPY %2
+    SI_RETURN implicit $sgpr0, implicit $vgpr0, implicit $sgpr1
+...