[llvm] [CodeGen] Remove `--enable-no-signed-zeros-fp-math` flag support (PR #201819)
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Fri Jun 5 05:23:00 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: paperchalice
<details>
<summary>Changes</summary>
Now CodeGen part no longer depends on this flag, remove it, so we can remove `Target::resetTargetOptions` later.
---
Full diff: https://github.com/llvm/llvm-project/pull/201819.diff
8 Files Affected:
- (modified) llvm/include/llvm/CodeGen/CommandFlags.h (-2)
- (modified) llvm/include/llvm/Target/TargetOptions.h (+1-8)
- (modified) llvm/lib/CodeGen/CommandFlags.cpp (-11)
- (modified) llvm/lib/Target/TargetMachine.cpp (+3-5)
- (modified) llvm/test/CodeGen/AMDGPU/fneg-combines.legal.f16.ll (-1)
- (modified) llvm/test/CodeGen/AMDGPU/fneg-combines.si.ll (-1)
- (modified) llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll (+3-6)
- (modified) llvm/test/CodeGen/PowerPC/scalar-min-max-p10.ll (+1-1)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/CommandFlags.h b/llvm/include/llvm/CodeGen/CommandFlags.h
index d10e8732c1562..0af5aa64b29fd 100644
--- a/llvm/include/llvm/CodeGen/CommandFlags.h
+++ b/llvm/include/llvm/CodeGen/CommandFlags.h
@@ -60,8 +60,6 @@ LLVM_ABI CodeGenFileType getFileType();
LLVM_ABI FramePointerKind getFramePointerUsage();
-LLVM_ABI bool getEnableNoSignedZerosFPMath();
-
LLVM_ABI bool getEnableNoTrappingFPMath();
LLVM_ABI DenormalMode::DenormalModeKind getDenormalFPMath();
diff --git a/llvm/include/llvm/Target/TargetOptions.h b/llvm/include/llvm/Target/TargetOptions.h
index 89e29d5f102f6..4b589926615fd 100644
--- a/llvm/include/llvm/Target/TargetOptions.h
+++ b/llvm/include/llvm/Target/TargetOptions.h
@@ -119,8 +119,7 @@ enum CodeObjectVersionKind {
class TargetOptions {
public:
TargetOptions()
- : NoTrappingFPMath(true), NoSignedZerosFPMath(false),
- EnableAIXExtendedAltivecABI(false),
+ : NoTrappingFPMath(true), EnableAIXExtendedAltivecABI(false),
HonorSignDependentRoundingFPMathOption(false), NoZerosInBSS(false),
GuaranteedTailCallOpt(false), StackSymbolOrdering(true),
EnableFastISel(false), EnableGlobalISel(false), UseInitArray(false),
@@ -160,12 +159,6 @@ class TargetOptions {
/// specifies that there are no trap handlers to handle exceptions.
unsigned NoTrappingFPMath : 1;
- /// NoSignedZerosFPMath - This flag is enabled when the
- /// -enable-no-signed-zeros-fp-math is specified on the command line. This
- /// specifies that optimizations are allowed to treat the sign of a zero
- /// argument or result as insignificant.
- unsigned NoSignedZerosFPMath : 1;
-
/// EnableAIXExtendedAltivecABI - This flag returns true when -vec-extabi is
/// specified. The code generator is then able to use both volatile and
/// nonvolitle vector registers. When false, the code generator only uses
diff --git a/llvm/lib/CodeGen/CommandFlags.cpp b/llvm/lib/CodeGen/CommandFlags.cpp
index 403fd49c56984..e7b9b6e194752 100644
--- a/llvm/lib/CodeGen/CommandFlags.cpp
+++ b/llvm/lib/CodeGen/CommandFlags.cpp
@@ -75,7 +75,6 @@ CGOPT_EXP(uint64_t, LargeDataThreshold)
CGOPT(ExceptionHandling, ExceptionModel)
CGOPT_EXP(CodeGenFileType, FileType)
CGOPT(FramePointerKind, FramePointerUsage)
-CGOPT(bool, EnableNoSignedZerosFPMath)
CGOPT(bool, EnableNoTrappingFPMath)
CGOPT(bool, EnableAIXExtendedAltivecABI)
CGOPT(DenormalMode::DenormalModeKind, DenormalFPMath)
@@ -232,13 +231,6 @@ codegen::RegisterCodeGenFlags::RegisterCodeGenFlags() {
"Enable frame pointer elimination")));
CGBINDOPT(FramePointerUsage);
- static cl::opt<bool> EnableNoSignedZerosFPMath(
- "enable-no-signed-zeros-fp-math",
- cl::desc("Enable FP math optimizations that assume "
- "the sign of 0 is insignificant"),
- cl::init(false));
- CGBINDOPT(EnableNoSignedZerosFPMath);
-
static cl::opt<bool> EnableNoTrappingFPMath(
"enable-no-trapping-fp-math",
cl::desc("Enable setting the FP exceptions build "
@@ -592,7 +584,6 @@ TargetOptions
codegen::InitTargetOptionsFromCodeGenFlags(const Triple &TheTriple) {
TargetOptions Options;
Options.AllowFPOpFusion = getFuseFPOps();
- Options.NoSignedZerosFPMath = getEnableNoSignedZerosFPMath();
Options.NoTrappingFPMath = getEnableNoTrappingFPMath();
Options.HonorSignDependentRoundingFPMathOption =
@@ -755,8 +746,6 @@ void codegen::setFunctionAttributes(Function &F, StringRef CPU,
if (getStackRealign())
NewAttrs.addAttribute("stackrealign");
- HANDLE_BOOL_ATTR(EnableNoSignedZerosFPMathView, "no-signed-zeros-fp-math");
-
if ((DenormalFPMathView->getNumOccurrences() > 0 ||
DenormalFP32MathView->getNumOccurrences() > 0) &&
!F.hasFnAttribute(Attribute::DenormalFPEnv)) {
diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp
index 9243cdad43e1e..f22afb831f11d 100644
--- a/llvm/lib/Target/TargetMachine.cpp
+++ b/llvm/lib/Target/TargetMachine.cpp
@@ -153,12 +153,10 @@ bool TargetMachine::isPositionIndependent() const {
// b) these target options should be passed only on the function
// and not on the TargetMachine (via TargetOptions) at all.
void TargetMachine::resetTargetOptions(const Function &F) const {
-#define RESET_OPTION(X, Y) \
- do { \
- Options.X = F.getFnAttribute(Y).getValueAsBool(); \
+#define RESET_OPTION(X, Y) \
+ do { \
+ Options.X = F.getFnAttribute(Y).getValueAsBool(); \
} while (0)
-
- RESET_OPTION(NoSignedZerosFPMath, "no-signed-zeros-fp-math");
}
/// Returns the code generation relocation model. The choices are static, PIC,
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.legal.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.legal.f16.ll
index e50489cdeba54..e946de4b1ee3b 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.legal.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.legal.f16.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-SAFE,VI,VI-SAFE %s
-; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=GCN,GCN-NSZ,VI,VI-NSZ %s
; --------------------------------------------------------------------------------
; rcp tests
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-combines.si.ll b/llvm/test/CodeGen/AMDGPU/fneg-combines.si.ll
index 64af8f6837b71..b3e3718afb3a4 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-combines.si.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-combines.si.ll
@@ -1,5 +1,4 @@
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
-; RUN: llc -enable-no-signed-zeros-fp-math -mtriple=amdgcn -mcpu=tahiti -start-before=amdgpu-unify-divergent-exit-nodes < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; --------------------------------------------------------------------------------
; rcp_legacy tests
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll b/llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll
index 89d11d57c7a9e..fc86c6264d1e9 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll
@@ -1,10 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-no-signed-zeros-fp-math=true < %s | FileCheck %s --check-prefix=GFX9
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-no-signed-zeros-fp-math=false < %s | FileCheck %s --check-prefix=GFX9
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -enable-no-signed-zeros-fp-math=true < %s | FileCheck %s --check-prefix=GFX10
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -enable-no-signed-zeros-fp-math=false < %s | FileCheck %s --check-prefix=GFX10
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -enable-no-signed-zeros-fp-math=true < %s | FileCheck %s --check-prefix=GFX10
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -enable-no-signed-zeros-fp-math=false < %s | FileCheck %s --check-prefix=GFX10
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s --check-prefix=GFX9
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck %s --check-prefix=GFX10
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck %s --check-prefix=GFX10
; no-signed-zeros-fp-math should not increase the number of
; instructions emitted.
diff --git a/llvm/test/CodeGen/PowerPC/scalar-min-max-p10.ll b/llvm/test/CodeGen/PowerPC/scalar-min-max-p10.ll
index 21e240ffb081c..807e64f699a6d 100644
--- a/llvm/test/CodeGen/PowerPC/scalar-min-max-p10.ll
+++ b/llvm/test/CodeGen/PowerPC/scalar-min-max-p10.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mcpu=pwr10 -ppc-asm-full-reg-names \
-; RUN: -verify-machineinstrs --enable-no-signed-zeros-fp-math \
+; RUN: -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
; RUN: llc -mcpu=pwr10 -ppc-asm-full-reg-names -verify-machineinstrs \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
``````````
</details>
https://github.com/llvm/llvm-project/pull/201819
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