[llvm] [X86][GlobalISel] Adding missing Query to G_BUILD_VECTOR legalization (PR #199435)
Evgenii Kudriashov via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 5 04:21:28 PDT 2026
https://github.com/e-kud updated https://github.com/llvm/llvm-project/pull/199435
>From aa75b4beb61463622884b8a4675b841a01110e66 Mon Sep 17 00:00:00 2001
From: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: Sun, 24 May 2026 10:01:22 -0700
Subject: [PATCH 1/2] [X86][GlobalISel] Adding missing Query to G_BUILD_VECTOR
legalization
Once G_BUILD_VECTOR was fixed, legalize-undef-vec-scaling.mir falled
into endless legalization loop as incoming MIR doesn't match correct
lowering of the type.
---
.../lib/Target/X86/GISel/X86LegalizerInfo.cpp | 2 +-
.../GlobalISel/legalize-undef-vec-scaling.mir | 47 ++++++++-----------
2 files changed, 21 insertions(+), 28 deletions(-)
diff --git a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
index ce922538cfdc9..334587b857784 100644
--- a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
@@ -547,7 +547,7 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
return (HasSSE1 && typeInSet(0, {v4s32})(Query)) ||
(HasSSE2 && typeInSet(0, {v2s64, v8s16, v16s8})(Query)) ||
(HasAVX && typeInSet(0, {v4s64, v8s32, v16s16, v32s8})(Query)) ||
- (HasAVX512 && typeInSet(0, {v8s64, v16s32, v32s16, v64s8}));
+ (HasAVX512 && typeInSet(0, {v8s64, v16s32, v32s16, v64s8})(Query));
})
.clampNumElements(0, v16s8, s8MaxVector)
.clampNumElements(0, v8s16, s16MaxVector)
diff --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-undef-vec-scaling.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-undef-vec-scaling.mir
index b996217708a91..5618c15598a76 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-undef-vec-scaling.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-undef-vec-scaling.mir
@@ -30,37 +30,30 @@ name: test_g_implicit_def_cample_size
body: |
bb.1:
; AVX2-LABEL: name: test_g_implicit_def_cample_size
- ; AVX2: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; AVX2-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64)
- ; AVX2-NEXT: [[TRUNC:%[0-9]+]]:_(<5 x s63>) = G_TRUNC [[BUILD_VECTOR]](<5 x s64>)
- ; AVX2-NEXT: RET 0, implicit [[TRUNC]](<5 x s63>)
+ ; AVX2: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
+ ; AVX2-NEXT: [[DEF:%[0-9]+]]:_(<5 x s63>) = G_IMPLICIT_DEF
+ ; AVX2-NEXT: G_STORE [[DEF]](<5 x s63>), [[COPY]](p0) :: (store (<5 x s63>), align 64)
+ ; AVX2-NEXT: $rax = COPY [[COPY]](p0)
+ ; AVX2-NEXT: RET 0, $rax
;
; SSE2-LABEL: name: test_g_implicit_def_cample_size
- ; SSE2: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
- ; SSE2-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64)
- ; SSE2-NEXT: [[TRUNC:%[0-9]+]]:_(<5 x s63>) = G_TRUNC [[BUILD_VECTOR]](<5 x s64>)
- ; SSE2-NEXT: RET 0, implicit [[TRUNC]](<5 x s63>)
+ ; SSE2: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
+ ; SSE2-NEXT: [[DEF:%[0-9]+]]:_(<5 x s63>) = G_IMPLICIT_DEF
+ ; SSE2-NEXT: G_STORE [[DEF]](<5 x s63>), [[COPY]](p0) :: (store (<5 x s63>), align 64)
+ ; SSE2-NEXT: $rax = COPY [[COPY]](p0)
+ ; SSE2-NEXT: RET 0, $rax
;
; AVX512F-LABEL: name: test_g_implicit_def_cample_size
- ; AVX512F: [[CONSTANT_POOL:%[0-9]+]]:_(p0) = G_CONSTANT_POOL %const.0
- ; AVX512F-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[CONSTANT_POOL]](p0) :: (load (s64) from constant-pool, align 64)
- ; AVX512F-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
- ; AVX512F-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[CONSTANT_POOL]], [[C]](s64)
- ; AVX512F-NEXT: [[LOAD1:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD]](p0) :: (load (s64) from constant-pool + 8, basealign 64)
- ; AVX512F-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
- ; AVX512F-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[CONSTANT_POOL]], [[C1]](s64)
- ; AVX512F-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD1]](p0) :: (load (s64) from constant-pool + 16, align 16, basealign 64)
- ; AVX512F-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
- ; AVX512F-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[CONSTANT_POOL]], [[C2]](s64)
- ; AVX512F-NEXT: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD2]](p0) :: (load (s64) from constant-pool + 24, basealign 64)
- ; AVX512F-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
- ; AVX512F-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = nuw inbounds G_PTR_ADD [[CONSTANT_POOL]], [[C3]](s64)
- ; AVX512F-NEXT: [[LOAD4:%[0-9]+]]:_(s64) = G_LOAD [[PTR_ADD3]](p0) :: (load (s64) from constant-pool + 32, align 32, basealign 64)
- ; AVX512F-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<5 x s64>) = G_BUILD_VECTOR [[LOAD]](s64), [[LOAD1]](s64), [[LOAD2]](s64), [[LOAD3]](s64), [[LOAD4]](s64)
- ; AVX512F-NEXT: [[TRUNC:%[0-9]+]]:_(<5 x s63>) = G_TRUNC [[BUILD_VECTOR]](<5 x s64>)
- ; AVX512F-NEXT: RET 0, implicit [[TRUNC]](<5 x s63>)
- %0:_(<5 x s63>) = G_IMPLICIT_DEF
- RET 0, implicit %0
+ ; AVX512F: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
+ ; AVX512F-NEXT: [[DEF:%[0-9]+]]:_(<5 x s63>) = G_IMPLICIT_DEF
+ ; AVX512F-NEXT: G_STORE [[DEF]](<5 x s63>), [[COPY]](p0) :: (store (<5 x s63>), align 64)
+ ; AVX512F-NEXT: $rax = COPY [[COPY]](p0)
+ ; AVX512F-NEXT: RET 0, $rax
+ %0:_(p0) = COPY $rdi
+ %1:_(<5 x s63>) = G_IMPLICIT_DEF
+ G_STORE %1:_(<5 x s63>), %0:_(p0) :: (store (<5 x s63>), align 64)
+ $rax = COPY %0:_(p0)
+ RET 0, $rax
...
>From 94d148e9b22a4be9acbac433da76b7f5601ec748 Mon Sep 17 00:00:00 2001
From: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: Sun, 24 May 2026 10:28:47 -0700
Subject: [PATCH 2/2] Format
---
llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
index 334587b857784..11f330ff49c4c 100644
--- a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
@@ -547,7 +547,8 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
return (HasSSE1 && typeInSet(0, {v4s32})(Query)) ||
(HasSSE2 && typeInSet(0, {v2s64, v8s16, v16s8})(Query)) ||
(HasAVX && typeInSet(0, {v4s64, v8s32, v16s16, v32s8})(Query)) ||
- (HasAVX512 && typeInSet(0, {v8s64, v16s32, v32s16, v64s8})(Query));
+ (HasAVX512 &&
+ typeInSet(0, {v8s64, v16s32, v32s16, v64s8})(Query));
})
.clampNumElements(0, v16s8, s8MaxVector)
.clampNumElements(0, v8s16, s16MaxVector)
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